December 2015 - U-Boot

[U-Boot] [PATCH v3] ARM: mxs: allow boards to select DC-DC switching clock source
by Michael Heimpold 03 Jan '16

03 Jan '16

For some board designs, it might be useful to switch the DC-DC clock source to something else rather the default 24 MHz, e.g. for EMI reasons. For this, override the mxs_power_setup_dcdc_clocksource function in your board support files. Example: void mxs_power_setup_dcdc_clocksource(void) { mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ); } Signed-off-by: Michael Heimpold <mhei(a)heimpold.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes in v3: - fixed and improved kerneldoc - renamed mxs_power_select_dcdc_clocksource to mxs_power_switch_dcdc_clocksource to fit the comment Changes in v2: - use a weak function approach instead of ifdef'ery as suggested by Marek Vasut arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 34 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mxs/sys_proto.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 1972de8..1ec8e2b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -248,6 +248,39 @@ static void mxs_power_setup_5v_detect(void) } /** + * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters + * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock + * + * This function configures and then enables an alternative PLL clock source + * for the DC-DC converters. + */ +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + + /* Select clocksource for DC-DC converters */ + clrsetbits_le32(&power_regs->hw_power_misc, + POWER_MISC_FREQSEL_MASK, + freqsel); + setbits_le32(&power_regs->hw_power_misc, + POWER_MISC_SEL_PLLCLK); +} + +/** + * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters + * + * Normally, there is no need to switch DC-DC clocksource. This is the reason, + * why this function is a stub and does nothing. However, boards can implement + * this function when required and call mxs_power_switch_dcdc_clocksource() to + * switch to an alternative clock source. + */ +__weak void mxs_power_setup_dcdc_clocksource(void) +{ + debug("SPL: Using default DC-DC clocksource\n"); +} + +/** * mxs_src_power_init() - Preconfigure the power block * * This function configures reasonable values for the DC-DC control loop @@ -872,6 +905,7 @@ static void mxs_power_configure_power_source(void) debug("SPL: Configuring power source\n"); + mxs_power_setup_dcdc_clocksource(); mxs_src_power_init(); if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 20ff101..f2b075e 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -25,6 +25,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); + +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); #endif struct mxs_pair { -- 2.5.0

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[U-Boot] [PATCH] cgtqmx6eval: fix pad configuration for SPI bus
by Michael Schanz 03 Jan '16

03 Jan '16

Use the macro SETUP_IOMUX_PAD(...) rather than imx_iomux_v3_setup_multiple_pads(...) in order to setup the pin configuration for ECSPI1. ARRAY_SIZE(pads) provides the wrong size for imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)) in case of MX6QDL. In the particular case, the content of GPR12 is overwritten and the IPG/AHB/ATB/ATP clocks are deactivated. Therefore, the connection to the system via JTAG is not possible anymore. Furthermore, kernel version 3.0.35 hangs during bootprocess in the function etm_init(). Signed-off-by: Michael Schanz <michael.schanz(a)congatec.com> --- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 5fd526d..225de7c 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -404,7 +404,7 @@ static void setup_iomux_uart(void) #ifdef CONFIG_MXC_SPI static void setup_spi(void) { - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + SETUP_IOMUX_PADS(ecspi1_pads); gpio_direction_output(IMX_GPIO_NR(3, 19), 0); } #endif -- 1.9.1

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[U-Boot] [PATCH 1/2] net: fec_mxc: configure MDIO hold time
by Mans Rullgard 03 Jan '16

03 Jan '16

If the host clock frequency is higher than 100 MHz, the MDIO hold time needs to be increased from its current setting of one cycle in order to meet the specified minium of 10 ns. Writing an appropriate value to the HOLDTIME field of the MII_SPEED register achieves this. Comment copied from Linux kernel. Signed-off-by: Mans Rullgard <mans(a)mansr.com> --- drivers/net/fec_mxc.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 79f6737..1250d2a 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -131,13 +131,25 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. + * + * The i.MX28 and i.MX6 types have another filed in the MSCR (aka + * MII_SPEED) register that defines the MDIO output hold time. Earlier + * versions are RAZ there, so just ignore the difference and write the + * register always. + * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. + * HOLDTIME + 1 is the number of clk cycles the fec is holding the + * output. + * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). + * Given that ceil(clkrate / 5000000) <= 64, the calculation for + * holdtime cannot result in a value greater than 3. */ - register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); + u32 pclk = imx_get_fecclk(); + u32 speed = DIV_ROUND_UP(pclk, 5000000); + u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; #ifdef FEC_QUIRK_ENET_MAC speed--; #endif - speed <<= 1; - writel(speed, &eth->mii_speed); + writel(speed << 1 | hold << 8, &eth->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed)); } -- 2.6.3

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[U-Boot] [PATCH] serial_mxc: Fix setup of UARTx_UFCR register
by Maximilian Schwerin 03 Jan '16

03 Jan '16

This patch writes the default values for TXTL and RXTL to UARTx_UFCR. Without this patch some older kernel versions crash as UARTx_UFCR was not always correctly initialized. Signed-off-by: Maximilian Schwerin <maximilian.schwerin(a)tigris.de> --- drivers/serial/serial_mxc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index d6cf1d8..51485c0 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -75,6 +75,7 @@ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -135,6 +136,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define TXTL 2 /* reset default */ +#define RXTL 1 /* reset default */ +#define RFDIV 4 /* divide input clock by 2 */ + static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); @@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) + | (TXTL << UFCR_TXTL_SHF) + | (RXTL << UFCR_RXTL_SHF); __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); -- 1.9.1

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[U-Boot] [PATCH] igep00x0: Do not include config_distro_defaults.h directly
by Ladislav Michl 02 Jan '16

02 Jan '16

File is already included: omap3_igep00x0.h -> ti_omap3_common.h -> ti_armv7_omap.h -> ti_armv7_common.h -> config_distro_defaults.h Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- include/configs/omap3_igep00x0.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index cf2bc3e..a64b38f 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -43,7 +43,7 @@ #else #error "status LED not defined for this machine." #endif -#define RED_LED_DEV 0 +#define RED_LED_DEV 0 #define STATUS_LED_BIT RED_LED_GPIO #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) @@ -56,7 +56,7 @@ #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ /* USB */ -#define CONFIG_USB_MUSB_UDC 1 +#define CONFIG_USB_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 #define CONFIG_TWL4030_USB 1 @@ -81,12 +81,8 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING -/*#undef CONFIG_ENV_IS_NOWHERE*/ - #ifndef CONFIG_SPL_BUILD -#include <config_distro_defaults.h> - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ @@ -138,7 +134,7 @@ #if defined(CONFIG_CMD_NET) #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 +#define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ /* OneNAND boot config */ -- 2.1.4

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[U-Boot] [PATCH v4 1/2] usb: Move determination of TT hub address/port into separate function
by Stefan Brüns 31 Dec '15

31 Dec '15

Start split and complete split tokens need the hub address and the downstream port of the first HS hub (device view). The core of the function was duplicated in both host/ehci_hcd and musb-new/usb-compat.h. Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> Reviewed-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Hans de Goede <hdegoede(a)redhat.com> Tested-by: Hans de Goede <hdegoede(a)redhat.com> --- v2: - renamed function to usb_find_usb2_hub_address_port() - put musb port numbering change into separate patch v3: - do one assignment per line v4: - fix error in musb code (udev => urb->dev) - added Reviewed-by: et al common/usb.c | 56 +++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 50 ++++------------------------------ drivers/usb/musb-new/musb_host.c | 10 ++++--- drivers/usb/musb-new/usb-compat.h | 53 ------------------------------------ include/usb.h | 12 +++++++++ 5 files changed, 80 insertions(+), 101 deletions(-) diff --git a/common/usb.c b/common/usb.c index b177391..9f67cc1 100644 --- a/common/usb.c +++ b/common/usb.c @@ -1214,4 +1214,60 @@ bool usb_device_has_child_on_port(struct usb_device *parent, int port) #endif } +#ifdef CONFIG_DM_USB +void usb_find_usb2_hub_address_port(struct usb_device *udev, + uint8_t *hub_address, uint8_t *hub_port) +{ + struct udevice *parent; + struct usb_device *uparent, *ttdev; + + /* + * When called from usb-uclass.c: usb_scan_device() udev->dev points + * to the parent udevice, not the actual udevice belonging to the + * udev as the device is not instantiated yet. So when searching + * for the first usb-2 parent start with udev->dev not + * udev->dev->parent . + */ + ttdev = udev; + parent = udev->dev; + uparent = dev_get_parent_priv(parent); + + while (uparent->speed != USB_SPEED_HIGH) { + struct udevice *dev = parent; + + if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { + printf("Error: Cannot find high speed parent of usb-1 device\n"); + *hub_address = 0; + *hub_port = 0; + return; + } + + ttdev = dev_get_parent_priv(dev); + parent = dev->parent; + uparent = dev_get_parent_priv(parent); + } + *hub_address = uparent->devnum; + *hub_port = ttdev->portnr; +} +#else +void usb_find_usb2_hub_address_port(struct usb_device *udev, + uint8_t *hub_address, uint8_t *hub_port) +{ + /* Find out the nearest parent which is high speed */ + while (udev->parent->parent != NULL) + if (udev->parent->speed != USB_SPEED_HIGH) { + udev = udev->parent; + } else { + *hub_address = udev->parent->devnum; + *hub_port = udev->portnr; + return; + } + + printf("Error: Cannot find high speed parent of usb-1 device\n"); + *hub_address = 0; + *hub_port = 0; +} +#endif + + /* EOF */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index c85dbce..af025de 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -279,56 +279,16 @@ static inline u8 ehci_encode_speed(enum usb_device_speed speed) static void ehci_update_endpt2_dev_n_port(struct usb_device *udev, struct QH *qh) { - struct usb_device *ttdev; - int parent_devnum; + uint8_t portnr = 0; + uint8_t hubaddr = 0; if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL) return; - /* - * For full / low speed devices we need to get the devnum and portnr of - * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs - * in the tree before that one! - */ -#ifdef CONFIG_DM_USB - /* - * When called from usb-uclass.c: usb_scan_device() udev->dev points - * to the parent udevice, not the actual udevice belonging to the - * udev as the device is not instantiated yet. So when searching - * for the first usb-2 parent start with udev->dev not - * udev->dev->parent . - */ - struct udevice *parent; - struct usb_device *uparent; - - ttdev = udev; - parent = udev->dev; - uparent = dev_get_parent_priv(parent); - - while (uparent->speed != USB_SPEED_HIGH) { - struct udevice *dev = parent; - - if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { - printf("ehci: Error cannot find high-speed parent of usb-1 device\n"); - return; - } - - ttdev = dev_get_parent_priv(dev); - parent = dev->parent; - uparent = dev_get_parent_priv(parent); - } - parent_devnum = uparent->devnum; -#else - ttdev = udev; - while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH) - ttdev = ttdev->parent; - if (!ttdev->parent) - return; - parent_devnum = ttdev->parent->devnum; -#endif + usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr) - qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) | - QH_ENDPT2_HUBADDR(parent_devnum)); + qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) | + QH_ENDPT2_HUBADDR(hubaddr)); } static int diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index 40b9c66..70f8a99 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -2092,9 +2092,13 @@ int musb_urb_enqueue( } #else if (tt_needed(musb, urb->dev)) { - u16 hub_port = find_tt(urb->dev); - qh->h_addr_reg = (u8) (hub_port >> 8); - qh->h_port_reg = (u8) (hub_port & 0xff); + uint8_t portnr = 0; + uint8_t hubaddr = 0; + usb_find_usb2_hub_address_port(urb->dev, + &hubaddr, + &portnr); + qh->h_addr_reg = hubaddr; + qh->h_port_reg = portnr - 1; } #endif } diff --git a/drivers/usb/musb-new/usb-compat.h b/drivers/usb/musb-new/usb-compat.h index 1c41e2a..760bd78 100644 --- a/drivers/usb/musb-new/usb-compat.h +++ b/drivers/usb/musb-new/usb-compat.h @@ -68,38 +68,6 @@ static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, } #ifdef CONFIG_DM_USB -static inline u16 find_tt(struct usb_device *udev) -{ - struct udevice *parent; - struct usb_device *uparent, *ttdev; - - /* - * When called from usb-uclass.c: usb_scan_device() udev->dev points - * to the parent udevice, not the actual udevice belonging to the - * udev as the device is not instantiated yet. So when searching - * for the first usb-2 parent start with udev->dev not - * udev->dev->parent . - */ - ttdev = udev; - parent = udev->dev; - uparent = dev_get_parent_priv(parent); - - while (uparent->speed != USB_SPEED_HIGH) { - struct udevice *dev = parent; - - if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) { - printf("musb: Error cannot find high speed parent of usb-1 device\n"); - return 0; - } - - ttdev = dev_get_parent_priv(dev); - parent = dev->parent; - uparent = dev_get_parent_priv(parent); - } - - return (uparent->devnum << 8) | (ttdev->portnr - 1); -} - static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) { struct udevice *parent = udev->dev->parent; @@ -129,27 +97,6 @@ static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev) return NULL; } #else -static inline u16 find_tt(struct usb_device *dev) -{ - u8 chid; - u8 hub; - - /* Find out the nearest parent which is high speed */ - while (dev->parent->parent != NULL) - if (dev->parent->speed != USB_SPEED_HIGH) - dev = dev->parent; - else - break; - - /* determine the port address at that hub */ - hub = dev->parent->devnum; - for (chid = 0; chid < USB_MAXCHILDREN; chid++) - if (dev->parent->children[chid] == dev) - break; - - return (hub << 8) | chid; -} - static inline struct usb_device *usb_dev_get_parent(struct usb_device *dev) { return dev->parent; diff --git a/include/usb.h b/include/usb.h index 198ecbc..2539364 100644 --- a/include/usb.h +++ b/include/usb.h @@ -875,6 +875,18 @@ int legacy_hub_port_reset(struct usb_device *dev, int port, int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat); +/* + * usb_find_usb2_hub_address_port() - Get hub address and port for TT setting + * + * Searches for the first HS hub above the given device. If a + * HS hub is found, the hub address and the port the device is + * connected to is return, as required for SPLIT transactions + * + * @param: udev full speed or low speed device + */ +void usb_find_usb2_hub_address_port(struct usb_device *udev, + uint8_t *hub_address, uint8_t *hub_port); + /** * usb_alloc_new_device() - Allocate a new device * -- 2.1.4

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[U-Boot] [PATCH v3 10/10] sf: Drop sf_params.c
by Jagan Teki 31 Dec '15

31 Dec '15

sf_params.c is not used anywhere in the code, hence removed the same. Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Mugunthan V N <mugunthanvnm(a)ti.com> Tested-by: Jagan Teki <jteki(a)openedev.com> Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- drivers/mtd/spi/sf_params.c | 146 -------------------------------------------- 1 file changed, 146 deletions(-) delete mode 100644 drivers/mtd/spi/sf_params.c diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c deleted file mode 100644 index 4f37e33..0000000 --- a/drivers/mtd/spi/sf_params.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * SPI flash Params table - * - * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <spi.h> -#include <spi_flash.h> - -#include "sf_internal.h" - -/* SPI/QSPI flash device params structure */ -const struct spi_flash_params spi_flash_params_table[] = { -#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K}, - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, - {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0}, - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0}, -#endif -#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ - {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0}, -#endif -#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0}, - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0}, - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0}, - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0}, - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, - {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, - {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, -#endif -#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0}, - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0}, - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, RD_NORM, 0}, - {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, - {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, - {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, - {"S25FL128S_256K", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL, WR_QPP}, - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP}, - {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, - {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP}, - {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, - {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP}, -#endif -#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0}, - {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0}, - {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, - {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR}, - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR}, - {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR}, -#endif -#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0}, - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0}, - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0}, - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K}, - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, - {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, -#endif - {}, /* Empty entry to terminate the list */ - /* - * Note: - * Below paired flash devices has similar spi_flash params. - * (S25FL129P_64K, S25FL128S_64K) - * (W25Q80BL, W25Q80BV) - * (W25Q16CL, W25Q16DV) - * (W25Q32BV, W25Q32FV_SPI) - * (W25Q64CV, W25Q64FV_SPI) - * (W25Q128BV, W25Q128FV_SPI) - * (W25Q32DW, W25Q32FV_QPI) - * (W25Q64DW, W25Q64FV_QPI) - * (W25Q128FW, W25Q128FV_QPI) - */ -}; -- 1.9.1

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[U-Boot] [PATCH v2 0/8] sf: Add flash_ids inside Core
by Jagan Teki 30 Dec '15

30 Dec '15

This series handle flash_ids stuff inside spi_flash core. Changes for v2: - Remove SECT_4K flag for s25fl128s Jagan Teki (8): sf: Add spi_flash_ids local to core sf: Rename SST_WR to SST_WRITE sf: Remove SPI_NOR_DUAL|QUAD_READ sf: Use sf_params in sandbox sf: Remove SECT_32K sf: Add SECT_4K_PMC sf: Use CONFIG_SPI_FLASH_USE_4K_SECTORS sf: Fix few naming convension for read modes drivers/mtd/spi/Makefile | 4 +- drivers/mtd/spi/sf_internal.h | 5 +- drivers/mtd/spi/spi_flash.c | 446 +++++++++++++++++++++++++++++++++++------- include/linux/err.h | 5 + 4 files changed, 383 insertions(+), 77 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 0/2] Change DM_SEQ_ALIAS to be configurable for SPL
by Nathan Rossi 30 Dec '15

30 Dec '15

Add a config option for SPL_DM_SEQ_ALIAS and enable it for the Zynq targets which require it for SPI flash support in SPL. Nathan Rossi (2): spl: dm: Add SPL_DM_SEQ_ALIAS config option arm: zynq: Enable SPL_DM_SEQ_ALIAS for all Zynq configs configs/zynq_microzed_defconfig | 1 + configs/zynq_picozed_defconfig | 1 + configs/zynq_zc702_defconfig | 1 + configs/zynq_zc706_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm011_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + drivers/core/Kconfig | 9 +++++++++ drivers/core/device.c | 2 +- include/config_uncmd_spl.h | 1 - 13 files changed, 20 insertions(+), 2 deletions(-) -- 2.6.2

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[U-Boot] [PATCH v5 4/5] mips: ath79: add spi driver
by Wills Wang 30 Dec '15

30 Dec '15

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v5: - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation Changes in v4: - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Convert spi driver to driver model - Same code style convertion Changes in v2: - Add a compatible spi driver arch/mips/mach-ath79/Kconfig | 1 + doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++ drivers/spi/Kconfig | 8 ++ drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 210 +++++++++++++++++++++++++++++ 5 files changed, 239 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index 1d92a5b..b5668e9 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -15,6 +15,7 @@ config SOC_AR933X select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_24KC select AR933X_UART + select ATH79_SPI help This supports QCA/Atheros ar933x family SOCs. diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt new file mode 100644 index 0000000..3fd9d67 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-ath79.txt @@ -0,0 +1,19 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cdb110..0ab2741 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,14 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to operate. + please refer to doc/device-tree-bindings/spi/spi-ath79.txt. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..0bedadb --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define SPI_CLK_DIV(x) (((x) >> 1) - 1) + +struct ath79_spi_priv { + void __iomem *regs; +}; + +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + return readl(priv->regs + offset); +} + +static inline void ath79_spi_write(struct udevice *bus, + u32 val, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + writel(val, priv->regs + offset); +} + +static inline void ath79_spi_delay(int max_hz) +{ + uint64_t tick = get_tbclk(); + + do_div(tick, max_hz); + tick = get_ticks() + tick + 1; /* get current timestamp */ + while (get_ticks() < tick) /* loop till event */ + /*NOP*/; +} + +static int ath79_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + uint8_t *rx = din; + const uint8_t *tx = dout; + uint8_t curbyte, curbitlen, restbits; + uint32_t bytes = bitlen / 8; + uint32_t out; + uint32_t in; + + if (flags & SPI_XFER_BEGIN) { + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + } + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes > 0) { + bytes--; + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits && !bytes) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + ath79_spi_delay(slave->max_hz); + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK, + AR71XX_SPI_REG_IOC); + ath79_spi_delay(slave->max_hz); + curbyte <<= 1; + } + + if (!bytes) + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits && !bytes) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) { + ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs), + AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + } + + return 0; +} + + +static int ath79_spi_set_speed(struct udevice *bus, uint speed) +{ + u32 val, div = 0; + + if (speed) + div = get_bus_freq(0) / speed; + + if (div > 63) + div = 63; + + if (div < 5) + div = 5; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL); + val &= ~AR71XX_SPI_CTRL_DIV_MASK; + val |= SPI_CLK_DIV(div); + ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + return 0; +} + +static int ath79_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int ath79_spi_probe(struct udevice *bus) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + fdt_addr_t addr; + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, + AR71XX_SPI_SIZE, + MAP_NOCACHE); + + /* Init SPI Hardware, disable remap, set clock */ + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8), + AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + + return 0; +} + +static int ath79_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0/1/2 */ + if (cs >= 3) + return -ENODEV; + + return 0; +} + +static const struct dm_spi_ops ath79_spi_ops = { + .claim_bus = ath79_spi_claim_bus, + .release_bus = ath79_spi_release_bus, + .xfer = ath79_spi_xfer, + .set_speed = ath79_spi_set_speed, + .set_mode = ath79_spi_set_mode, + .cs_info = ath79_cs_info, +}; + +static const struct udevice_id ath79_spi_ids[] = { + { .compatible = "qca,ar7100-spi" }, + {} +}; + +U_BOOT_DRIVER(ath79_spi) = { + .name = "ath79_spi", + .id = UCLASS_SPI, + .of_match = ath79_spi_ids, + .ops = &ath79_spi_ops, + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv), + .probe = ath79_spi_probe, +}; -- 1.9.1

4 10