December 2015 - U-Boot

[U-Boot] [PATCH v2] net: e1000: use correct helper to do endianness conversion
by Miao Yan 04 Jan '16

04 Jan '16

In struct e1000_rx_desc, field 'length' is declared as uint16_t, so use le16_to_cpu() to do endianness conversion. Also drop conversion on 'status' which is declared as uint8_t. Signed-off-by: Miao Yan <yanmiaobest(a)gmail.com> --- Changes in v2: - fix typos in commit message drivers/net/e1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 2ba03ed..6124bf0 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5165,11 +5165,11 @@ _e1000_poll(struct e1000_hw *hw) inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); invalidate_dcache_range(inval_start, inval_end); - if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) + if (!(rd->status & E1000_RXD_STAT_DD)) return 0; /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ /* Packet received, make sure the data are re-loaded from RAM. */ - len = le32_to_cpu(rd->length); + len = le16_to_cpu(rd->length); invalidate_dcache_range((unsigned long)packet, (unsigned long)packet + roundup(len, ARCH_DMA_MINALIGN)); -- 1.9.1

3 2

[U-Boot] [PATCH] qemu-ppce500: pass 'range_id' around in pci_map_region
by Miao Yan 04 Jan '16

04 Jan '16

In pci_map_region(), pass 'range_id' to fdt_read_range(), otherwise the same address will be mapped again in other calls to pci_map_region() Signed-off-by: Miao Yan <yammiaobest(a)gmail.com> --- board/freescale/qemu-ppce500/qemu-ppce500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c index a0fca0d..6cb5692 100644 --- a/board/freescale/qemu-ppce500/qemu-ppce500.c +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -81,7 +81,7 @@ static int pci_map_region(void *fdt, int pci_node, int range_id, ulong map_addr; int r; - r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size); + r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size); if (r) return r; -- 1.9.1

4 3

[U-Boot] mmc erase fails from U-Boot command line
by Cliff Brust 04 Jan '16

04 Jan '16

I have the need to erase our eMMC from U-Boot on our custom board due to a hard wired boot up configuration. Our design is based on the Freescale i.MX6Q SabreSD Board reference design. The bottom line is the U-Boot command "mmc erase" is failing with the error "Timeout waiting for DAT0 to go high!". Here's a list of the U-Boot commands issued and the result of each so you can see what is going on. ---------------------------------------- => mmc list FSL_SDHC: 0 FSL_SDHC: 1 (SD) FSL_SDHC: 2 (eMMC) => mmc dev 2 switch to partitions #0, OK mmc2(part 0) is current device => mmc info Device: FSL_SDHC Manufacturer ID: 45 OEM: 100 Name: SEM08 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.4.1 High Capacity: Yes Capacity: 7.4 GiB Bus Width: 8-bit Erase Group Size: 512 KiB HC WP Group Size: 16 MiB User Capacity: 7.4 GiB WRREL Boot Capacity: 2 MiB ENH RPMB Capacity: 128 KiB ENH => mmc erase 0 0x400 MMC erase: dev # 2, block # 0, count 1024 ... Timeout waiting for DAT0 to go high! mmc erase failed 0 blocks erased: ERROR ---------------------------------------- Any insight on this issue is greatly appreciated. Thanks, Cliff

7 28

[U-Boot] [PATCH] igep00x0: cleanup ethernet support
by Ladislav Michl 04 Jan '16

04 Jan '16

Move chip reset to separate function, use CONFIG_SMC911X_BASE instead of hardcoded value, remove unneeded local variable from board_eth_init. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- board/isee/igep00x0/igep00x0.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 57b89e0..e2fce50 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -101,6 +101,19 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) #endif #if defined(CONFIG_CMD_NET) + +static void reset_net_chip(int gpio) +{ + if (!gpio_request(gpio, "eth nrst")) { + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + udelay(40); + gpio_set_value(gpio, 1); + mdelay(10); + } +} + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -110,8 +123,8 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); @@ -121,15 +134,7 @@ static void setup_net_chip(void) writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } + reset_net_chip(64); } #else static inline void setup_net_chip(void) {} @@ -200,10 +205,10 @@ void set_muxconf_regs(void) #if defined(CONFIG_CMD_NET) int board_eth_init(bd_t *bis) { - int rc = 0; #ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; #endif - return rc; } #endif -- 2.1.4

2 1

[U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered"
by Fabio Estevam 04 Jan '16

04 Jan '16

This reverts commit 59370f3fcd135089c402c93720a87c688abe600c. This commit breaks ethernet on at least mx6 Riotboard and mx6sxsabresd boards. Reported-by: Catalin Crenguta <catalin.crenguta(a)gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- drivers/net/phy/phy.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d7364ff..9e68f1d 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -771,13 +771,11 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, phy_interface_t interface) { /* Reset the bus */ - if (bus->reset) { + if (bus->reset) bus->reset(bus); - /* Wait 15ms to make sure the PHY has come out of hard reset */ - udelay(15000); - } - + /* Wait 15ms to make sure the PHY has come out of hard reset */ + udelay(15000); return get_phy_device_by_mask(bus, phy_mask, interface); } -- 1.9.1

5 16

[U-Boot] [PATCH 4/4] rapidio: add driver for TI KeyStone RapidIO
by jacquiot.aurelien＠gmail.com 04 Jan '16

04 Jan '16

From: Aurelien Jacquiot <a-jacquiot(a)ti.com> This commit includes the KeyStone device driver for RapidIO allowing to use the RapidIO boot functionality. Today only K2HK devices have RapidIO support. Signed-off-by: Aurelien Jacquiot <a-jacquiot(a)ti.com> --- Makefile | 1 + configs/k2hk_evm_defconfig | 2 + drivers/Kconfig | 2 + drivers/rapidio/Kconfig | 5 + drivers/rapidio/Makefile | 8 + drivers/rapidio/keystone_rio.c | 1374 ++++++++++++++++++++++++++++++++++++++++ drivers/rapidio/keystone_rio.h | 650 +++++++++++++++++++ 7 files changed, 2042 insertions(+), 0 deletions(-) create mode 100644 drivers/rapidio/Kconfig create mode 100644 drivers/rapidio/Makefile create mode 100644 drivers/rapidio/keystone_rio.c create mode 100644 drivers/rapidio/keystone_rio.h diff --git a/Makefile b/Makefile index 3c21f8d..67e6b25 100644 --- a/Makefile +++ b/Makefile @@ -661,6 +661,7 @@ libs-y += drivers/usb/musb/ libs-y += drivers/usb/musb-new/ libs-y += drivers/usb/phy/ libs-y += drivers/usb/ulpi/ +libs-y += drivers/rapidio/ libs-y += common/ libs-$(CONFIG_API) += api/ libs-$(CONFIG_HAS_POST) += post/ diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index d5a4ef2..e350ea4 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="K2HK EVM # " CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_SPI_FLASH=y +CONFIG_CMD_RIO=y +CONFIG_KEYSTONE_RIO=y diff --git a/drivers/Kconfig b/drivers/Kconfig index c481e93..37a37a6 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -70,6 +70,8 @@ source "drivers/video/Kconfig" source "drivers/watchdog/Kconfig" +source "drivers/rapidio/Kconfig" + config PHYS_TO_BUS bool "Custom physical to bus address mapping" help diff --git a/drivers/rapidio/Kconfig b/drivers/rapidio/Kconfig new file mode 100644 index 0000000..2560957 --- /dev/null +++ b/drivers/rapidio/Kconfig @@ -0,0 +1,5 @@ +config KEYSTONE_RIO + bool "Support for TI KeyStone RapidIO" + depends on TARGET_K2HK_EVM + ---help--- + Say Y here if you want to use RapidIO to boot your board. diff --git a/drivers/rapidio/Makefile b/drivers/rapidio/Makefile new file mode 100644 index 0000000..bd7ec50 --- /dev/null +++ b/drivers/rapidio/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2015 +# Texas Instruments Incorporated, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_KEYSTONE_RIO) += keystone_rio.o diff --git a/drivers/rapidio/keystone_rio.c b/drivers/rapidio/keystone_rio.c new file mode 100644 index 0000000..9fe93c3 --- /dev/null +++ b/drivers/rapidio/keystone_rio.c @@ -0,0 +1,1374 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * Authors: Aurelien Jacquiot <a-jacquiot(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/dma-mapping.h> +#include <asm/io.h> +#include <asm/arch/psc_defs.h> +#include <rio.h> + +#include "keystone_rio.h" + +#define DRIVER_VER "v1.1" + +#ifdef CONFIG_SOC_K2HK +#define KEYSTONE_RIO_IS_K2 1 +#else +#define KEYSTONE_RIO_IS_K2 0 +#endif + +#define K2_SERDES(p) ((p)->board_rio_cfg.keystone2_serdes) + +static unsigned int rio_dbg; + +#define debug_rio(fmt, args...) if (rio_dbg) printf(fmt, ##args) + +/* + * Main KeyStone RapidIO driver data + */ +struct keystone_rio_data { + int riohdid; + u32 rio_pe_feat; + + u32 ports_registering; + u32 port_chk_cnt; + + u32 *jtagid_reg; + u32 *serdes_sts_reg; + struct keystone_srio_serdes_regs *serdes_regs; + struct keystone_rio_regs *regs; + + struct keystone_rio_car_csr_regs *car_csr_regs; + struct keystone_rio_serial_port_regs *serial_port_regs; + struct keystone_rio_err_mgmt_regs *err_mgmt_regs; + struct keystone_rio_phy_layer_regs *phy_regs; + struct keystone_rio_transport_layer_regs *transport_regs; + struct keystone_rio_pkt_buf_regs *pkt_buf_regs; + struct keystone_rio_evt_mgmt_regs *evt_mgmt_regs; + struct keystone_rio_port_write_regs *port_write_regs; + struct keystone_rio_link_layer_regs *link_regs; + struct keystone_rio_fabric_regs *fabric_regs; + u32 car_csr_regs_base; + + struct keystone_rio_board_controller_info board_rio_cfg; +} __krio_priv; + +/*--------------------- Maintenance Request Management ---------------------*/ + +static u32 keystone_rio_dio_get_lsu_cc(u32 lsu_id, u8 ltid, u8 *lcb, + struct keystone_rio_data *krio_priv) +{ + u32 idx; + u32 shift; + u32 value; + u32 cc; + /* lSU shadow register status mapping */ + u32 lsu_index[8] = { 0, 9, 15, 20, 24, 33, 39, 44 }; + + /* Compute LSU stat index from LSU id and LTID */ + idx = (lsu_index[lsu_id] + ltid) >> 3; + shift = ((lsu_index[lsu_id] + ltid) & 0x7) << 2; + + /* Get completion code and context */ + value = readl(&(krio_priv->regs->lsu_stat_reg[idx])); + cc = (value >> (shift + 1)) & 0x7; + *lcb = (value >> shift) & 0x1; + + return cc; +} + +/** + * maint_request - Perform a maintenance request + * @port_id: output port ID of transaction + * @dest_id: destination ID of target device + * @hopcount: hopcount for this request + * @offset: offset in the RapidIO configuration space + * @buff: dma address of the data on the host + * @buff_len: length of the data + * @size: 1 for 16bit, 0 for 8bit ID size + * @type: packet type + * + * Returns %0 on success or %-1 on failure. + */ +static inline int keystone_rio_maint_request( + int port_id, + u32 dest_id, + u8 hopcount, + u32 offset, + dma_addr_t buff, + int buff_len, + u16 size, + u16 type, + struct keystone_rio_data *krio_priv) +{ + unsigned int count; + unsigned int status = 0; + unsigned int res = 0; + u8 context; + u8 ltid; + + /* Check is there is space in the LSU shadow reg and that it is free */ + count = 0; + while (1) { + status = readl(&(krio_priv->regs->lsu_reg[0].busy_full)); + if (((status & KEYSTONE_RIO_LSU_FULL_MASK) == 0x0) && + ((status & KEYSTONE_RIO_LSU_BUSY_MASK) == 0x0)) + break; + count++; + + if (count >= KEYSTONE_RIO_TIMEOUT_CNT) { + debug_rio("RIO: no LSU available, status = 0x%x\n", + status); + res = -1; + goto out; + } + udelay(1); + } + + /* Get LCB and LTID, LSU reg 6 is already read */ + context = (status >> 4) & 0x1; + ltid = status & 0xf; + + /* LSU Reg 0 - MSB of RapidIO address */ + writel(0, &(krio_priv->regs->lsu_reg[0].addr_msb)); + + /* LSU Reg 1 - LSB of destination */ + writel(offset, &(krio_priv->regs->lsu_reg[0].addr_lsb_cfg_ofs)); + + /* LSU Reg 2 - source address */ + writel(buff, &(krio_priv->regs->lsu_reg[0].dsp_addr)); + + /* LSU Reg 3 - byte count */ + writel(buff_len, + &(krio_priv->regs->lsu_reg[0].dbell_val_byte_cnt)); + + /* LSU Reg 4 - */ + writel(((port_id << 8) + | (KEYSTONE_RIO_LSU_PRIO << 4) + | (size ? (1 << 10) : 0) + | ((u32) dest_id << 16)), + &(krio_priv->regs->lsu_reg[0].destid)); + + /* LSU Reg 5 */ + writel(((hopcount & 0xff) << 8) | (type & 0xff), + &(krio_priv->regs->lsu_reg[0].dbell_info_fttype)); + + /* Retrieve our completion code */ + count = 0; + res = 0; + while (1) { + u8 lcb; + + status = keystone_rio_dio_get_lsu_cc(0, ltid, &lcb, krio_priv); + if (lcb == context) + break; + count++; + if (count >= KEYSTONE_RIO_TIMEOUT_CNT) { + debug_rio( + "RIO: timeout %d, ltid = %d, context = %d, lcb = %d, cc = %d\n", + count, ltid, context, lcb, status); + res = -2; + break; + } + udelay(1); + } +out: + if (res) + return res; + + if (status) + debug_rio("RIO: transfer error = 0x%x\n", status); + + switch (status) { + case KEYSTONE_RIO_LSU_CC_TIMEOUT: + case KEYSTONE_RIO_LSU_CC_XOFF: + case KEYSTONE_RIO_LSU_CC_ERROR: + case KEYSTONE_RIO_LSU_CC_INVALID: + case KEYSTONE_RIO_LSU_CC_DMA: + return -3; + break; + case KEYSTONE_RIO_LSU_CC_RETRY: + return -4; + break; + case KEYSTONE_RIO_LSU_CC_CANCELED: + return -5; + break; + default: + break; + } + + return 0; +} + +/** + * rio_config_read - Generate a RIO read maintenance transaction + * @portid: Output port ID of transaction + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Location to be read into + * + * Returns %0 on success or %-1 on failure. + */ +int rio_config_read(int portid, + u16 destid, + u8 hopcount, + u32 offset, + int len, + u32 *val) +{ + struct keystone_rio_data *krio_priv = &__krio_priv; + u32 *tbuf; + int res; + dma_addr_t dma; + + tbuf = malloc(len); + if (!tbuf) + return -1; + + memset(tbuf, 0, len); + + dma = dma_map_single(tbuf, len, DMA_FROM_DEVICE); + + res = keystone_rio_maint_request(portid, destid, hopcount, offset, dma, + len, krio_priv->board_rio_cfg.size, + KEYSTONE_RIO_PACKET_TYPE_MAINT_R, + krio_priv); + + dma_unmap_single((void *)tbuf, len, dma); + + /* Taking care of byteswap */ + switch (len) { + case 1: + *val = *((u8 *)tbuf); + break; + case 2: + *val = ntohs(*((u16 *)tbuf)); + break; + default: + *val = ntohl(*((u32 *)tbuf)); + break; + } + + free(tbuf); + + debug_rio( + "RIO: %s portid %d destid %d hopcount %d offset 0x%x len %d val 0x%x res %d\n", + __func__, portid, destid, hopcount, offset, len, *val, + res); + + return res; +} + +/** + * rio_config_write - Generate a RIO write maintenance transaction + * @portid: Output port ID of transaction + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Value to be written + * + * Returns %0 on success or %-1 on failure. + */ +int rio_config_write(int portid, + u16 destid, + u8 hopcount, + u32 offset, + int len, + u32 val) +{ + struct keystone_rio_data *krio_priv = &__krio_priv; + u32 *tbuf; + int res; + dma_addr_t dma; + + tbuf = malloc(len); + if (!tbuf) + return -1; + + memset(tbuf, 0, len); + + /* Taking care of byteswap */ + switch (len) { + case 1: + *tbuf = ((u8) val); + break; + case 2: + *tbuf = htons((u16) val); + break; + default: + *tbuf = htonl((u32) val); + break; + } + + dma = dma_map_single(tbuf, len, DMA_TO_DEVICE); + + res = keystone_rio_maint_request(portid, destid, hopcount, offset, dma, + len, krio_priv->board_rio_cfg.size, + KEYSTONE_RIO_PACKET_TYPE_MAINT_W, + krio_priv); + + dma_unmap_single((void *)tbuf, len, dma); + + debug_rio( + "RIO: %s portid %d destid %d hopcount %d offset 0x%x len %d val 0x%x res %d\n", + __func__, portid, destid, hopcount, offset, len, val, + res); + + free(tbuf); + + return res; +} + +/** + * rio_local_config_read - RIO local config space read + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be read into + * + * Returns %0 on success or %-1 on failure. + */ +int rio_local_config_read(u32 offset, int len, u32 *data) +{ + struct keystone_rio_data *krio_priv = &__krio_priv; + + *data = readl((void *)(krio_priv->car_csr_regs_base + offset)); + + debug_rio("RIO: %s offset 0x%x data 0x%x\n", + __func__, offset, *data); + + return 0; +} + +/** + * rio_local_config_write - RIO local config space write + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be written + * + * Returns %0 on success or %-1 on failure. + */ +int rio_local_config_write(u32 offset, int len, u32 data) +{ + struct keystone_rio_data *krio_priv = &__krio_priv; + + debug_rio("RIO: %s offset 0x%x data 0x%x\n", + __func__, offset, data); + + writel(data, (void *)(krio_priv->car_csr_regs_base + offset)); + + return 0; +} + +/*------------------------- RapidIO hw controller setup ---------------------*/ + +struct keystone_lane_config { + int start; /* lane start number of the port */ + int end; /* lane end number of the port */ +}; + +/* + * Table with the various lanes per port configuration modes: + * path mode 0: 4 ports in 1x + * path mode 1: 3 ports in 2x/1x + * path mode 2: 3 ports in 1x/2x + * path mode 3: 2 ports in 2x + * path mode 4: 1 ports in 4x + */ +static struct keystone_lane_config keystone_lane_configs[5][4] = { + { {0, 1}, {1, 2}, {2, 3}, {3, 4} }, + { {0, 2}, {-1, -1}, {2, 3}, {3, 4} }, + { {0, 1}, {1, 2}, {2, 4}, {-1, -1} }, + { {0, 2}, {-1, -1}, {2, 4}, {-1, -1} }, + { {0, 4}, {-1, -1}, {-1, -1}, {-1, -1} }, +}; + +/* Retrieve the corresponding lanes bitmask from ports bitmask and path_mode */ +static int keystone_rio_get_lane_config(u32 ports, u32 path_mode) +{ + u32 lanes = 0; + + while (ports) { + u32 lane; + u32 port = ffs(ports) - 1; + ports &= ~(1 << port); + + if (keystone_lane_configs[path_mode][port].start == -1) + return -1; + + for (lane = keystone_lane_configs[path_mode][port].start; + lane < keystone_lane_configs[path_mode][port].end; + lane++) { + lanes |= (1 << lane); + } + } + return (int) lanes; +} + +#define reg_fmkr(msb, lsb, val) \ + (((val) & ((1 << ((msb) - (lsb) + 1)) - 1)) << (lsb)) + +#define reg_finsr(addr, msb, lsb, val) \ + writel(((readl(addr) \ + & ~(((1 << ((msb) - (lsb) + 1)) - 1) << (lsb))) \ + | reg_fmkr(msb, lsb, val)), (addr)) + +static void k2_rio_serdes_init_3g(u32 lanes, + struct keystone_rio_data *krio_priv) +{ + void __iomem *reg = (void __iomem *)krio_priv->serdes_regs; + + /* Uses 6G half rate configuration */ + reg_finsr((reg + 0x0000), 31, 24, 0x00); + reg_finsr((reg + 0x0014), 7, 0, 0x82); + reg_finsr((reg + 0x0014), 15, 8, 0x82); + reg_finsr((reg + 0x0060), 7, 0, 0x48); + reg_finsr((reg + 0x0060), 15, 8, 0x2c); + reg_finsr((reg + 0x0060), 23, 16, 0x13); + reg_finsr((reg + 0x0064), 15, 8, 0xc7); + reg_finsr((reg + 0x0064), 23, 16, 0xc3); + reg_finsr((reg + 0x0078), 15, 8, 0xc0); + + /* Setting lane 0 SerDes to 3GHz */ + reg_finsr((reg + 0x0204), 7, 0, 0x80); + reg_finsr((reg + 0x0204), 31, 24, 0x78); + reg_finsr((reg + 0x0208), 7, 0, 0x24); + reg_finsr((reg + 0x020c), 31, 24, 0x02); + reg_finsr((reg + 0x0210), 31, 24, 0x1b); + reg_finsr((reg + 0x0214), 7, 0, 0x7c); + reg_finsr((reg + 0x0214), 15, 8, 0x6e); + reg_finsr((reg + 0x0218), 7, 0, 0xe4); + reg_finsr((reg + 0x0218), 23, 16, 0x80); + reg_finsr((reg + 0x0218), 31, 24, 0x75); + reg_finsr((reg + 0x022c), 15, 8, 0x08); + reg_finsr((reg + 0x022c), 23, 16, 0x20); + reg_finsr((reg + 0x0280), 7, 0, 0x70); + reg_finsr((reg + 0x0280), 23, 16, 0x70); + reg_finsr((reg + 0x0284), 7, 0, 0x85); + reg_finsr((reg + 0x0284), 23, 16, 0x0f); + reg_finsr((reg + 0x0284), 31, 24, 0x1d); + reg_finsr((reg + 0x028c), 15, 8, 0x3b); + + /* Setting lane 1 SerDes to 3GHz */ + reg_finsr((reg + 0x0404), 7, 0, 0x80); + reg_finsr((reg + 0x0404), 31, 24, 0x78); + reg_finsr((reg + 0x0408), 7, 0, 0x24); + reg_finsr((reg + 0x040c), 31, 24, 0x02); + reg_finsr((reg + 0x0410), 31, 24, 0x1b); + reg_finsr((reg + 0x0414), 7, 0, 0x7c); + reg_finsr((reg + 0x0414), 15, 8, 0x6e); + reg_finsr((reg + 0x0418), 7, 0, 0xe4); + reg_finsr((reg + 0x0418), 23, 16, 0x80); + reg_finsr((reg + 0x0418), 31, 24, 0x75); + reg_finsr((reg + 0x042c), 15, 8, 0x08); + reg_finsr((reg + 0x042c), 23, 16, 0x20); + reg_finsr((reg + 0x0480), 7, 0, 0x70); + reg_finsr((reg + 0x0480), 23, 16, 0x70); + reg_finsr((reg + 0x0484), 7, 0, 0x85); + reg_finsr((reg + 0x0484), 23, 16, 0x0f); + reg_finsr((reg + 0x0484), 31, 24, 0x1d); + reg_finsr((reg + 0x048c), 15, 8, 0x3b); + + /* Setting lane 2 SerDes to 3GHz */ + reg_finsr((reg + 0x0604), 7, 0, 0x80); + reg_finsr((reg + 0x0604), 31, 24, 0x78); + reg_finsr((reg + 0x0608), 7, 0, 0x24); + reg_finsr((reg + 0x060c), 31, 24, 0x02); + reg_finsr((reg + 0x0610), 31, 24, 0x1b); + reg_finsr((reg + 0x0614), 7, 0, 0x7c); + reg_finsr((reg + 0x0614), 15, 8, 0x6e); + reg_finsr((reg + 0x0618), 7, 0, 0xe4); + reg_finsr((reg + 0x0618), 23, 16, 0x80); + reg_finsr((reg + 0x0618), 31, 24, 0x75); + reg_finsr((reg + 0x062c), 15, 8, 0x08); + reg_finsr((reg + 0x062c), 23, 16, 0x20); + reg_finsr((reg + 0x0680), 7, 0, 0x70); + reg_finsr((reg + 0x0680), 23, 16, 0x70); + reg_finsr((reg + 0x0684), 7, 0, 0x85); + reg_finsr((reg + 0x0684), 23, 16, 0x0f); + reg_finsr((reg + 0x0684), 31, 24, 0x1d); + reg_finsr((reg + 0x068c), 15, 8, 0x3b); + + /* Setting lane 3 SerDes to 3GHz */ + reg_finsr((reg + 0x0804), 7, 0, 0x80); + reg_finsr((reg + 0x0804), 31, 24, 0x78); + reg_finsr((reg + 0x0808), 7, 0, 0x24); + reg_finsr((reg + 0x080c), 31, 24, 0x02); + reg_finsr((reg + 0x0810), 31, 24, 0x1b); + reg_finsr((reg + 0x0814), 7, 0, 0x7c); + reg_finsr((reg + 0x0814), 15, 8, 0x6e); + reg_finsr((reg + 0x0818), 7, 0, 0xe4); + reg_finsr((reg + 0x0818), 23, 16, 0x80); + reg_finsr((reg + 0x0818), 31, 24, 0x75); + reg_finsr((reg + 0x082c), 15, 8, 0x08); + reg_finsr((reg + 0x082c), 23, 16, 0x20); + reg_finsr((reg + 0x0880), 7, 0, 0x70); + reg_finsr((reg + 0x0880), 23, 16, 0x70); + reg_finsr((reg + 0x0884), 7, 0, 0x85); + reg_finsr((reg + 0x0884), 23, 16, 0x0f); + reg_finsr((reg + 0x0884), 31, 24, 0x1d); + reg_finsr((reg + 0x088c), 15, 8, 0x3b); + + reg_finsr((reg + 0x0a00), 15, 8, 0x08); + reg_finsr((reg + 0x0a08), 23, 16, 0x72); + reg_finsr((reg + 0x0a08), 31, 24, 0x37); + reg_finsr((reg + 0x0a30), 15, 8, 0x77); + reg_finsr((reg + 0x0a30), 23, 16, 0x77); + reg_finsr((reg + 0x0a84), 15, 8, 0x06); + reg_finsr((reg + 0x0a94), 31, 24, 0x10); + reg_finsr((reg + 0x0aa0), 31, 24, 0x81); + reg_finsr((reg + 0x0abc), 31, 24, 0xff); + reg_finsr((reg + 0x0ac0), 7, 0, 0x8b); + reg_finsr((reg + 0x0a48), 15, 8, 0x8c); + reg_finsr((reg + 0x0a48), 23, 16, 0xfd); + reg_finsr((reg + 0x0a54), 7, 0, 0x72); + reg_finsr((reg + 0x0a54), 15, 8, 0xec); + reg_finsr((reg + 0x0a54), 23, 16, 0x2f); + reg_finsr((reg + 0x0a58), 15, 8, 0x21); + reg_finsr((reg + 0x0a58), 23, 16, 0xf9); + reg_finsr((reg + 0x0a58), 31, 24, 0x00); + reg_finsr((reg + 0x0a5c), 7, 0, 0x60); + reg_finsr((reg + 0x0a5c), 15, 8, 0x00); + reg_finsr((reg + 0x0a5c), 23, 16, 0x04); + reg_finsr((reg + 0x0a5c), 31, 24, 0x00); + reg_finsr((reg + 0x0a60), 7, 0, 0x00); + reg_finsr((reg + 0x0a60), 15, 8, 0x80); + reg_finsr((reg + 0x0a60), 23, 16, 0x00); + reg_finsr((reg + 0x0a60), 31, 24, 0x00); + reg_finsr((reg + 0x0a64), 7, 0, 0x20); + reg_finsr((reg + 0x0a64), 15, 8, 0x12); + reg_finsr((reg + 0x0a64), 23, 16, 0x58); + reg_finsr((reg + 0x0a64), 31, 24, 0x0c); + reg_finsr((reg + 0x0a68), 7, 0, 0x02); + reg_finsr((reg + 0x0a68), 15, 8, 0x06); + reg_finsr((reg + 0x0a68), 23, 16, 0x3b); + reg_finsr((reg + 0x0a68), 31, 24, 0xe1); + reg_finsr((reg + 0x0a6c), 7, 0, 0xc1); + reg_finsr((reg + 0x0a6c), 15, 8, 0x4c); + reg_finsr((reg + 0x0a6c), 23, 16, 0x07); + reg_finsr((reg + 0x0a6c), 31, 24, 0xb8); + reg_finsr((reg + 0x0a70), 7, 0, 0x89); + reg_finsr((reg + 0x0a70), 15, 8, 0xe9); + reg_finsr((reg + 0x0a70), 23, 16, 0x02); + reg_finsr((reg + 0x0a70), 31, 24, 0x3f); + reg_finsr((reg + 0x0a74), 7, 0, 0x01); + reg_finsr((reg + 0x0b20), 23, 16, 0x37); + reg_finsr((reg + 0x0b1c), 31, 24, 0x37); + reg_finsr((reg + 0x0b20), 7, 0, 0x5d); + reg_finsr((reg + 0x0000), 7, 0, 0x03); + reg_finsr((reg + 0x0a00), 7, 0, 0x5f); +} + +static void k2_rio_serdes_init_5g(u32 lanes, + struct keystone_rio_data *krio_priv) +{ + void __iomem *reg = (void __iomem *)krio_priv->serdes_regs; + + /* Uses 5Gbps full rate configuration by default */ + reg_finsr((reg + 0x0000), 31, 24, 0x00); + reg_finsr((reg + 0x0014), 7, 0, 0x82); + reg_finsr((reg + 0x0014), 15, 8, 0x82); + reg_finsr((reg + 0x0060), 7, 0, 0x38); + reg_finsr((reg + 0x0060), 15, 8, 0x24); + reg_finsr((reg + 0x0060), 23, 16, 0x14); + reg_finsr((reg + 0x0064), 15, 8, 0xc7); + reg_finsr((reg + 0x0064), 23, 16, 0xc3); + reg_finsr((reg + 0x0078), 15, 8, 0xc0); + + /* Setting lane 0 SerDes to 5GHz */ + reg_finsr((reg + 0x0204), 7, 0, 0x80); + reg_finsr((reg + 0x0204), 31, 24, 0x78); + reg_finsr((reg + 0x0208), 7, 0, 0x26); + reg_finsr((reg + 0x020c), 31, 24, 0x02); + reg_finsr((reg + 0x0214), 7, 0, 0x38); + reg_finsr((reg + 0x0214), 15, 8, 0x6f); + reg_finsr((reg + 0x0218), 7, 0, 0xe4); + reg_finsr((reg + 0x0218), 23, 16, 0x80); + reg_finsr((reg + 0x0218), 31, 24, 0x75); + reg_finsr((reg + 0x022c), 15, 8, 0x08); + reg_finsr((reg + 0x022c), 23, 16, 0x20); + reg_finsr((reg + 0x0280), 7, 0, 0x86); + reg_finsr((reg + 0x0280), 23, 16, 0x86); + reg_finsr((reg + 0x0284), 7, 0, 0x85); + reg_finsr((reg + 0x0284), 23, 16, 0x0f); + reg_finsr((reg + 0x0284), 31, 24, 0x1d); + reg_finsr((reg + 0x028c), 15, 8, 0x2c); + + /* Setting lane 1 SerDes to 5GHz */ + reg_finsr((reg + 0x0404), 7, 0, 0x80); + reg_finsr((reg + 0x0404), 31, 24, 0x78); + reg_finsr((reg + 0x0408), 7, 0, 0x26); + reg_finsr((reg + 0x040c), 31, 24, 0x02); + reg_finsr((reg + 0x0414), 7, 0, 0x38); + reg_finsr((reg + 0x0414), 15, 8, 0x6f); + reg_finsr((reg + 0x0418), 7, 0, 0xe4); + reg_finsr((reg + 0x0418), 23, 16, 0x80); + reg_finsr((reg + 0x0418), 31, 24, 0x75); + reg_finsr((reg + 0x042c), 15, 8, 0x08); + reg_finsr((reg + 0x042c), 23, 16, 0x20); + reg_finsr((reg + 0x0480), 7, 0, 0x86); + reg_finsr((reg + 0x0480), 23, 16, 0x86); + reg_finsr((reg + 0x0484), 7, 0, 0x85); + reg_finsr((reg + 0x0484), 23, 16, 0x0f); + reg_finsr((reg + 0x0484), 31, 24, 0x1d); + reg_finsr((reg + 0x048c), 15, 8, 0x2c); + + /* Setting lane 2 SerDes to 5GHz */ + reg_finsr((reg + 0x0604), 7, 0, 0x80); + reg_finsr((reg + 0x0604), 31, 24, 0x78); + reg_finsr((reg + 0x0608), 7, 0, 0x26); + reg_finsr((reg + 0x060c), 31, 24, 0x02); + reg_finsr((reg + 0x0614), 7, 0, 0x38); + reg_finsr((reg + 0x0614), 15, 8, 0x6f); + reg_finsr((reg + 0x0618), 7, 0, 0xe4); + reg_finsr((reg + 0x0618), 23, 16, 0x80); + reg_finsr((reg + 0x0618), 31, 24, 0x75); + reg_finsr((reg + 0x062c), 15, 8, 0x08); + reg_finsr((reg + 0x062c), 23, 16, 0x20); + reg_finsr((reg + 0x0680), 7, 0, 0x86); + reg_finsr((reg + 0x0680), 23, 16, 0x86); + reg_finsr((reg + 0x0684), 7, 0, 0x85); + reg_finsr((reg + 0x0684), 23, 16, 0x0f); + reg_finsr((reg + 0x0684), 31, 24, 0x1d); + reg_finsr((reg + 0x068c), 15, 8, 0x2c); + + /* Setting lane 3 SerDes to 5GHz */ + reg_finsr((reg + 0x0804), 7, 0, 0x80); + reg_finsr((reg + 0x0804), 31, 24, 0x78); + reg_finsr((reg + 0x0808), 7, 0, 0x26); + reg_finsr((reg + 0x080c), 31, 24, 0x02); + reg_finsr((reg + 0x0814), 7, 0, 0x38); + reg_finsr((reg + 0x0814), 15, 8, 0x6f); + reg_finsr((reg + 0x0818), 7, 0, 0xe4); + reg_finsr((reg + 0x0818), 23, 16, 0x80); + reg_finsr((reg + 0x0818), 31, 24, 0x75); + reg_finsr((reg + 0x082c), 15, 8, 0x08); + reg_finsr((reg + 0x082c), 23, 16, 0x20); + reg_finsr((reg + 0x0880), 7, 0, 0x86); + reg_finsr((reg + 0x0880), 23, 16, 0x86); + reg_finsr((reg + 0x0884), 7, 0, 0x85); + reg_finsr((reg + 0x0884), 23, 16, 0x0f); + reg_finsr((reg + 0x0884), 31, 24, 0x1d); + reg_finsr((reg + 0x088c), 15, 8, 0x2c); + + reg_finsr((reg + 0x0a00), 15, 8, 0x80); + reg_finsr((reg + 0x0a08), 23, 16, 0xd2); + reg_finsr((reg + 0x0a08), 31, 24, 0x38); + reg_finsr((reg + 0x0a30), 15, 8, 0x8d); + reg_finsr((reg + 0x0a30), 23, 16, 0x8d); + reg_finsr((reg + 0x0a84), 15, 8, 0x06); + reg_finsr((reg + 0x0a94), 31, 24, 0x10); + reg_finsr((reg + 0x0aa0), 31, 24, 0x81); + reg_finsr((reg + 0x0abc), 31, 24, 0xff); + reg_finsr((reg + 0x0ac0), 7, 0, 0x8b); + reg_finsr((reg + 0x0a48), 15, 8, 0x8c); + reg_finsr((reg + 0x0a48), 23, 16, 0xfd); + reg_finsr((reg + 0x0a54), 7, 0, 0x72); + reg_finsr((reg + 0x0a54), 15, 8, 0xec); + reg_finsr((reg + 0x0a54), 23, 16, 0x2f); + reg_finsr((reg + 0x0a58), 15, 8, 0x21); + reg_finsr((reg + 0x0a58), 23, 16, 0xf9); + reg_finsr((reg + 0x0a58), 31, 24, 0x00); + reg_finsr((reg + 0x0a5c), 7, 0, 0x60); + reg_finsr((reg + 0x0a5c), 15, 8, 0x00); + reg_finsr((reg + 0x0a5c), 23, 16, 0x04); + reg_finsr((reg + 0x0a5c), 31, 24, 0x00); + reg_finsr((reg + 0x0a60), 7, 0, 0x00); + reg_finsr((reg + 0x0a60), 15, 8, 0x80); + reg_finsr((reg + 0x0a60), 23, 16, 0x00); + reg_finsr((reg + 0x0a60), 31, 24, 0x00); + reg_finsr((reg + 0x0a64), 7, 0, 0x20); + reg_finsr((reg + 0x0a64), 15, 8, 0x12); + reg_finsr((reg + 0x0a64), 23, 16, 0x58); + reg_finsr((reg + 0x0a64), 31, 24, 0x0c); + reg_finsr((reg + 0x0a68), 7, 0, 0x02); + reg_finsr((reg + 0x0a68), 15, 8, 0x06); + reg_finsr((reg + 0x0a68), 23, 16, 0x3b); + reg_finsr((reg + 0x0a68), 31, 24, 0xe1); + reg_finsr((reg + 0x0a6c), 7, 0, 0xc1); + reg_finsr((reg + 0x0a6c), 15, 8, 0x4c); + reg_finsr((reg + 0x0a6c), 23, 16, 0x07); + reg_finsr((reg + 0x0a6c), 31, 24, 0xb8); + reg_finsr((reg + 0x0a70), 7, 0, 0x89); + reg_finsr((reg + 0x0a70), 15, 8, 0xe9); + reg_finsr((reg + 0x0a70), 23, 16, 0x02); + reg_finsr((reg + 0x0a70), 31, 24, 0x3f); + reg_finsr((reg + 0x0a74), 7, 0, 0x01); + reg_finsr((reg + 0x0b20), 23, 16, 0x37); + reg_finsr((reg + 0x0b1c), 31, 24, 0x37); + reg_finsr((reg + 0x0b20), 7, 0, 0x5d); + reg_finsr((reg + 0x0000), 7, 0, 0x03); + reg_finsr((reg + 0x0a00), 7, 0, 0x5f); +} + +static void k2_rio_serdes_lane_enable(u32 lane, u32 rate, + struct keystone_rio_data *krio_priv) +{ + void *regs = (void *)krio_priv->serdes_regs; + u32 val; + + /* Bit 28 Toggled. Bring it out of Reset TX PLL for all lanes */ + val = readl(regs + 0x200 * (lane + 1) + 0x28); + val &= ~BIT(29); + writel(val, regs + 0x200 * (lane + 1) + 0x28); + + /* Set Lane Control Rate */ + switch (rate) { + case KEYSTONE_RIO_FULL_RATE: + writel(0xF0C0F0F0, regs + 0x1fe0 + 4 * lane); + break; + case KEYSTONE_RIO_HALF_RATE: + writel(0xF4C0F4F0, regs + 0x1fe0 + 4 * lane); + break; + case KEYSTONE_RIO_QUARTER_RATE: + writel(0xF8C0F8F0, regs + 0x1fe0 + 4 * lane); + break; + default: + return; + } +} + +static int k2_rio_serdes_config(u32 lanes, u32 baud, + struct keystone_rio_data *krio_priv) +{ + void *regs = (void *)krio_priv->serdes_regs; + u32 rate; + u32 val; + + /* Disable pll before configuring the SerDes registers */ + writel(0x00000000, regs + 0x1ff4); + + switch (baud) { + case KEYSTONE_RIO_BAUD_1_250: + rate = KEYSTONE_RIO_QUARTER_RATE; + k2_rio_serdes_init_5g(lanes, krio_priv); + break; + case KEYSTONE_RIO_BAUD_2_500: + rate = KEYSTONE_RIO_HALF_RATE; + k2_rio_serdes_init_5g(lanes, krio_priv); + break; + case KEYSTONE_RIO_BAUD_5_000: + rate = KEYSTONE_RIO_FULL_RATE; + k2_rio_serdes_init_5g(lanes, krio_priv); + break; + case KEYSTONE_RIO_BAUD_3_125: + rate = KEYSTONE_RIO_HALF_RATE; + k2_rio_serdes_init_3g(lanes, krio_priv); + break; + default: + printf("RIO: unsupported baud rate %d\n", baud); + return -1; + } + + /* Enable serdes for requested lanes */ + while (lanes) { + u32 lane = ffs(lanes) - 1; + lanes &= ~(1 << lane); + + if (lane >= KEYSTONE_RIO_MAX_PORT) + return -1; + + k2_rio_serdes_lane_enable(lane, rate, krio_priv); + } + + /* Enable pll via the pll_ctrl 0x0014 */ + writel(0xe0000000, regs + 0x1ff4); + + /* Wait until CMU_OK bit is set */ + do { + val = readl(regs + 0xbf8); + } while (!(val & BIT(16))); + + return 0; +} + +static int k2_rio_serdes_wait_lock(struct keystone_rio_data *krio_priv, + u32 lanes) +{ + u32 loop; + u32 val; + u32 val_mask; + void *regs = (void *)krio_priv->serdes_regs; + + val_mask = lanes | (lanes << 8); + + /* Wait for the SerDes PLL lock */ + for (loop = 0; loop < 100000; loop++) { + /* read PLL_CTRL */ + val = readl(regs + 0x1ff4); + if ((val & val_mask) == val_mask) + break; + udelay(10); + } + + if (loop == 100000) + return -1; + + return 0; +} + +/** + * keystone_rio_hw_init - Configure a RapidIO controller + * @mode: serdes configuration + * @hostid: device id of the host + */ +static void keystone_rio_hw_init(u32 mode, u32 baud, + struct keystone_rio_data *krio_priv) +{ + u32 val; + u32 block; + struct keystone_serdes_config *serdes_config + = &(krio_priv->board_rio_cfg.serdes_config[mode]); + + /* Set sRIO out of reset */ + writel(0x00000011, &krio_priv->regs->pcr); + + /* Clear BOOT_COMPLETE bit (allowing write) */ + writel(0x00000000, &krio_priv->regs->per_set_cntl); + + /* Enable blocks */ + writel(1, &krio_priv->regs->gbl_en); + for (block = 0; block <= KEYSTONE_RIO_BLK_NUM; block++) + writel(1, &(krio_priv->regs->blk[block].enable)); + + /* Set control register 1 configuration */ + writel(0x00000000, &krio_priv->regs->per_set_cntl1); + + /* Set Control register */ + writel(serdes_config->cfg_cntl, &krio_priv->regs->per_set_cntl); + + if (K2_SERDES(krio_priv)) { + u32 path_mode = krio_priv->board_rio_cfg.path_mode; + u32 ports = krio_priv->board_rio_cfg.ports; + int res; + + /* K2 SerDes main configuration */ + res = keystone_rio_get_lane_config(ports, path_mode); + if (res > 0) { + u32 lanes = (u32) res; + res = k2_rio_serdes_config(lanes, baud, krio_priv); + } + } else { + u32 port; + + /* K1 SerDes main configuration */ + writel(serdes_config->serdes_cfg_pll, + &krio_priv->serdes_regs->pll); + + /* Per-port SerDes configuration */ + for (port = 0; port < KEYSTONE_RIO_MAX_PORT; port++) { + writel(serdes_config->rx_chan_config[port], + &krio_priv->serdes_regs->channel[port].rx); + writel(serdes_config->tx_chan_config[port], + &krio_priv->serdes_regs->channel[port].tx); + } + + /* Check for RIO SerDes PLL lock */ + do { + val = readl(krio_priv->serdes_sts_reg); + } while ((val & 0x1) != 0x1); + } + + /* Set prescalar for ip_clk */ + writel(serdes_config->prescalar_srv_clk, + &krio_priv->link_regs->prescalar_srv_clk); + + /* Peripheral-specific configuration and capabilities */ + writel(KEYSTONE_RIO_DEV_ID_VAL, + &krio_priv->car_csr_regs->dev_id); + writel(KEYSTONE_RIO_DEV_INFO_VAL, + &krio_priv->car_csr_regs->dev_info); + writel(KEYSTONE_RIO_ID_TI, + &krio_priv->car_csr_regs->assembly_id); + writel(KEYSTONE_RIO_EXT_FEAT_PTR, + &krio_priv->car_csr_regs->assembly_info); + + /* Set host device id */ + writel((krio_priv->riohdid & 0xffff) + | ((krio_priv->riohdid & 0xff) << 16), + &krio_priv->car_csr_regs->base_dev_id); + + krio_priv->rio_pe_feat = RIO_PEF_PROCESSOR + | RIO_PEF_CTLS + | KEYSTONE_RIO_PEF_FLOW_CONTROL + | RIO_PEF_EXT_FEATURES + | RIO_PEF_ADDR_34 + | RIO_PEF_STD_RT + | RIO_PEF_INB_DOORBELL + | RIO_PEF_INB_MBOX; + + writel(krio_priv->rio_pe_feat, + &krio_priv->car_csr_regs->pe_feature); + + writel(KEYSTONE_RIO_MAX_PORT << 8, + &krio_priv->car_csr_regs->sw_port); + + writel((RIO_SRC_OPS_READ + | RIO_SRC_OPS_WRITE + | RIO_SRC_OPS_STREAM_WRITE + | RIO_SRC_OPS_WRITE_RESPONSE + | RIO_SRC_OPS_DATA_MSG + | RIO_SRC_OPS_DOORBELL + | RIO_SRC_OPS_ATOMIC_TST_SWP + | RIO_SRC_OPS_ATOMIC_INC + | RIO_SRC_OPS_ATOMIC_DEC + | RIO_SRC_OPS_ATOMIC_SET + | RIO_SRC_OPS_ATOMIC_CLR + | RIO_SRC_OPS_PORT_WRITE), + &krio_priv->car_csr_regs->src_op); + + writel((RIO_DST_OPS_READ + | RIO_DST_OPS_WRITE + | RIO_DST_OPS_STREAM_WRITE + | RIO_DST_OPS_WRITE_RESPONSE + | RIO_DST_OPS_DATA_MSG + | RIO_DST_OPS_DOORBELL + | RIO_DST_OPS_PORT_WRITE), + &krio_priv->car_csr_regs->dest_op); + + writel(RIO_PELL_ADDR_34, + &krio_priv->car_csr_regs->pe_logical_ctl); + + val = (((KEYSTONE_RIO_SP_HDR_NEXT_BLK_PTR & 0xffff) << 16) | + KEYSTONE_RIO_SP_HDR_EP_REC_ID); + writel(val, &krio_priv->serial_port_regs->sp_maint_blk_hdr); + + /* clear high bits of local config space base addr */ + writel(0x00000000, &krio_priv->car_csr_regs->local_cfg_hbar); + + /* set local config space base addr */ + writel(0x00520000, &krio_priv->car_csr_regs->local_cfg_bar); + + /* Enable HOST & MASTER_ENABLE bits */ + writel(0xe0000000, &krio_priv->serial_port_regs->sp_gen_ctl); + + /* set link timeout value */ + writel(0x000FFF00, + &krio_priv->serial_port_regs->sp_link_timeout_ctl); + + /* set response timeout value */ + writel(0x000FFF00, + &krio_priv->serial_port_regs->sp_rsp_timeout_ctl); + + /* allows SELF_RESET and PWDN_PORT resets to clear sticky reg bits */ + writel(0x00000001, &krio_priv->link_regs->reg_rst_ctl); + + /* Set error detection mode */ + /* clear all errors */ + writel(0x00000000, &krio_priv->err_mgmt_regs->err_det); + + /* enable all error detection */ + writel(0x00000000, &krio_priv->err_mgmt_regs->err_en); + + /* set err det block header */ + val = (((KEYSTONE_RIO_ERR_HDR_NEXT_BLK_PTR & 0xffff) << 16) | + KEYSTONE_RIO_ERR_EXT_FEAT_ID); + writel(val, &krio_priv->err_mgmt_regs->err_report_blk_hdr); + + /* clear msb of err catptured addr reg */ + writel(0x00000000, &krio_priv->err_mgmt_regs->h_addr_capt); + + /* clear lsb of err catptured addr reg */ + writel(0x00000000, &krio_priv->err_mgmt_regs->addr_capt); + + /* clear err catptured source and dest devID reg */ + writel(0x00000000, &krio_priv->err_mgmt_regs->id_capt); + + /* clear err catptured packet info */ + writel(0x00000000, &krio_priv->err_mgmt_regs->ctrl_capt); + + /* Force all writes to finish */ + val = readl(&krio_priv->err_mgmt_regs->ctrl_capt); +} + +/** + * keystone_rio_start - Start RapidIO controller + */ +static void keystone_rio_start(struct keystone_rio_data *krio_priv) +{ + u32 val; + + /* set PEREN bit to enable logical layer data flow */ + val = (KEYSTONE_RIO_PER_EN | KEYSTONE_RIO_PER_FREE); + writel(val, &krio_priv->regs->pcr); + + /* set BOOT_COMPLETE bit */ + val = readl(&krio_priv->regs->per_set_cntl); + writel(val | KEYSTONE_RIO_BOOT_COMPLETE, + &krio_priv->regs->per_set_cntl); +} + +/** + * keystone_rio_port_status - Return if the port is OK or not + * @port: index of the port + * + * Return %0 if the port is ready or %-EIO on failure. + */ +static int keystone_rio_port_status(int port, + struct keystone_rio_data *krio_priv) +{ + unsigned int count, value; + int solid_ok = 0; + + if (port >= KEYSTONE_RIO_MAX_PORT) + return -1; + + /* Check port status */ + for (count = 0; count < 300; count++) { + value = readl( + &(krio_priv->serial_port_regs->sp[port].err_stat)); + + if (value & RIO_PORT_N_ERR_STS_PORT_OK) { + solid_ok++; + if (solid_ok == 100) + break; + } else { + if (solid_ok) { + debug_rio( + "RIO: unstable port %d (solid_ok = %d)\n", + port, solid_ok); + return -2; + } + solid_ok = 0; + } + udelay(20); + } + + return 0; +} + +/** + * keystone_rio_port_disable - Disable a RapidIO port + * @port: index of the port to configure + */ +static void keystone_rio_port_disable(u32 port, + struct keystone_rio_data *krio_priv) +{ + /* Disable port */ + writel(0x800000, &(krio_priv->serial_port_regs->sp[port].ctl)); +} + +/** + * keystone_rio_port_init - Configure a RapidIO port + * @port: index of the port to configure + * @mode: serdes configuration + */ +static int keystone_rio_port_init(u32 port, u32 path_mode, + struct keystone_rio_data *krio_priv) +{ + if (port >= KEYSTONE_RIO_MAX_PORT) + return -1; + + /* Disable packet forwarding */ + writel(0xffffffff, &(krio_priv->regs->pkt_fwd_cntl[port].pf_16b)); + writel(0x0003ffff, &(krio_priv->regs->pkt_fwd_cntl[port].pf_8b)); + + /* Silence and discovery timers */ + if ((port == 0) || (port == 2)) { + writel(0x20000000, + &(krio_priv->phy_regs->phy_sp[port].silence_timer)); + writel(0x20000000, + &(krio_priv->phy_regs->phy_sp[port].discovery_timer)); + } + + /* Enable port in input and output */ + writel(0x600000, &(krio_priv->serial_port_regs->sp[port].ctl)); + + /* Program channel allocation to ports (1x, 2x or 4x) */ + writel(path_mode, &(krio_priv->phy_regs->phy_sp[port].path_ctl)); + + return 0; +} + +/** + * keystone_rio_port_activate - Start using a RapidIO port + * @port: index of the port to configure + */ +static int keystone_rio_port_activate(u32 port, + struct keystone_rio_data *krio_priv) +{ + /* Cleanup port error status */ + writel(KEYSTONE_RIO_PORT_ERROR_MASK, + &(krio_priv->serial_port_regs->sp[port].err_stat)); + writel(0, &(krio_priv->err_mgmt_regs->sp_err[port].det)); + + /* Enable promiscuous */ + writel(0x00309000, + &(krio_priv->transport_regs->transport_sp[port].control)); + + return 0; +} + +/*------------------------ Main driver functions -----------------------*/ + +static void keystone_rio_get_controller_defaults( + struct keystone_rio_data *krio_priv, + int riosize, + u32 rioports, + int riopmode, + int riobaudrate) +{ + struct keystone_rio_board_controller_info *c + = &krio_priv->board_rio_cfg; + int i; + + c->keystone2_serdes = KEYSTONE_RIO_IS_K2; + + if (K2_SERDES(krio_priv)) { + /* K2 configuration */ + c->rio_regs_base = 0x2900000; + c->rio_regs_size = 0x40000; + c->boot_cfg_regs_base = 0x2620000; + c->boot_cfg_regs_size = 0x1000; + c->serdes_cfg_regs_base = 0x232c000; + c->serdes_cfg_regs_size = 0x1000; + } else { + /* K1 configuration */ + c->rio_regs_base = 0x2900000; + c->rio_regs_size = 0x21000; + c->boot_cfg_regs_base = 0x2620000; + c->boot_cfg_regs_size = 0x3b0; + c->serdes_cfg_regs_base = 0x2900360; + c->serdes_cfg_regs_size = 0x1000; + } + + /* dev-id-size */ + c->size = riosize; + + /* ports to use */ + c->ports = rioports; + + /* SerDes config */ + c->serdes_config_num = 1; /* total number of serdes_config[] entries */ + c->mode = 0; /* default serdes_config[] entry to use */ + c->path_mode = riopmode; + + if (K2_SERDES(krio_priv)) { + /* + * K2 sRIO config 0 + */ + c->serdes_config[0].prescalar_srv_clk = 0x001f; + c->serdes_baudrate = riobaudrate; + } else { + /* + * K1 sRIO config 0: MPY = 5x, div rate = half, + * link rate = 3.125 Gbps, mode 1x + */ + + /* setting control register config */ + c->serdes_config[0].cfg_cntl = 0x0c053860; + + /* SerDes PLL configuration */ + c->serdes_config[0].serdes_cfg_pll = 0x0229; + + /* prescalar_srv_clk */ + c->serdes_config[0].prescalar_srv_clk = 0x001e; + + /* serdes rx_chan_config */ + for (i = 0; i < KEYSTONE_RIO_MAX_PORT; i++) + c->serdes_config[0].rx_chan_config[i] = 0x00440495; + + /* serdes tx_chan_config */ + for (i = 0; i < KEYSTONE_RIO_MAX_PORT; i++) + c->serdes_config[0].tx_chan_config[i] = 0x00180795; + } +} + +/* + * Platform configuration setup + */ +static int keystone_rio_setup_controller(struct keystone_rio_data *krio_priv) +{ + u32 ports; + u32 p; + u32 mode; + u32 baud; + u32 path_mode; + u32 size = 0; + int res = 0; + char str[8]; + + size = krio_priv->board_rio_cfg.size; + ports = krio_priv->board_rio_cfg.ports; + mode = krio_priv->board_rio_cfg.mode; + baud = krio_priv->board_rio_cfg.serdes_baudrate; + path_mode = krio_priv->board_rio_cfg.path_mode; + + debug_rio( + "RIO: size = %d, ports = 0x%x, mode = %d, baud = %d, path_mode = %d\n", + size, ports, mode, baud, path_mode); + + if (mode >= krio_priv->board_rio_cfg.serdes_config_num) { + mode = 0; + printf("RIO: invalid port mode, forcing it to %d\n", mode); + } + + if (baud > KEYSTONE_RIO_BAUD_5_000) { + baud = KEYSTONE_RIO_BAUD_5_000; + printf("RIO: invalid baud rate, forcing it to 5Gbps\n"); + } + + switch (baud) { + case KEYSTONE_RIO_BAUD_1_250: + snprintf(str, sizeof(str), "1.25"); + break; + case KEYSTONE_RIO_BAUD_2_500: + snprintf(str, sizeof(str), "2.50"); + break; + case KEYSTONE_RIO_BAUD_3_125: + snprintf(str, sizeof(str), "3.125"); + break; + case KEYSTONE_RIO_BAUD_5_000: + snprintf(str, sizeof(str), "5.00"); + break; + default: + return -1; + } + + printf("RIO: initializing %s Gbps interface with port configuration %d\n", + str, path_mode); + + /* Hardware set up of the controller */ + keystone_rio_hw_init(mode, baud, krio_priv); + + /* Disable all ports */ + for (p = 0; p < KEYSTONE_RIO_MAX_PORT; p++) + keystone_rio_port_disable(p, krio_priv); + + /* Start the controller */ + keystone_rio_start(krio_priv); + + /* Try to lock K2 SerDes*/ + if (K2_SERDES(krio_priv)) { + int lanes = keystone_rio_get_lane_config(ports, path_mode); + if (lanes > 0) { + res = k2_rio_serdes_wait_lock(krio_priv, (u32) lanes); + if (res < 0) + debug_rio( + "SerDes for lane mask 0x%x on %s Gbps not locked\n", + lanes, str); + } + } + + /* Use and check ports status (but only the requested ones) */ + krio_priv->ports_registering = ports; + while (ports) { + int status; + u32 port = ffs(ports) - 1; + if (port > 32) + return 0; + ports &= ~(1 << port); + + res = keystone_rio_port_init(port, path_mode, krio_priv); + if (res < 0) { + printf("RIO: initialization of port %d failed\n", p); + return res; + } + + /* Start the port */ + keystone_rio_port_activate(port, krio_priv); + + /* Check the port status */ + status = keystone_rio_port_status(port, krio_priv); + if (status == 0) { + krio_priv->ports_registering &= ~(1 << port); + printf("RIO: port RIO%d ready\n", port); + } else { + printf("RIO: port %d not ready (status %d)\n", + port, status); + } + } + + if (krio_priv->ports_registering != 0) + return -1; + + return res; +} + +/** + * rio_init - Initialize RapidIO subsystem + * @riohdid: RapidIO host device ID + * @riosize: RapidIO device ID size + * @rioports: bitmask of ports to configure + * @riopmode: path mode (lanes to ports mapping) + * @riobaudrate: link baudrate + * + * Returns riohandle on success or %NULL on failure. + */ +void *rio_init(int riohdid, + int riosize, + u32 rioports, + int riopmode, + int riobaudrate) +{ + struct keystone_rio_data *krio_priv = &__krio_priv; + int res = 0; + void *regs; + + keystone_rio_get_controller_defaults(krio_priv, + riosize, + rioports, + riopmode, + riobaudrate); + + regs = (void *)krio_priv->board_rio_cfg.boot_cfg_regs_base; + krio_priv->jtagid_reg = regs + 0x0018; + krio_priv->serdes_sts_reg = regs + 0x0154; + + regs = (void *)krio_priv->board_rio_cfg.serdes_cfg_regs_base; + krio_priv->serdes_regs = regs; + + regs = (void *)krio_priv->board_rio_cfg.rio_regs_base; + krio_priv->regs = regs; + krio_priv->car_csr_regs = regs + 0x0b000; + krio_priv->serial_port_regs = regs + 0x0b100; + krio_priv->err_mgmt_regs = regs + 0x0c000; + krio_priv->phy_regs = regs + 0x1b000; + krio_priv->transport_regs = regs + 0x1b300; + krio_priv->pkt_buf_regs = regs + 0x1b600; + krio_priv->evt_mgmt_regs = regs + 0x1b900; + krio_priv->port_write_regs = regs + 0x1ba00; + krio_priv->link_regs = regs + 0x1bd00; + krio_priv->fabric_regs = regs + 0x1be00; + krio_priv->car_csr_regs_base = (u32) regs + 0xb000; + + krio_priv->riohdid = riohdid; + + /* Enable srio clock */ + psc_enable_module(KS2_LPSC_SRIO); + + printf("KeyStone RapidIO driver %s, hdid=%d\n", DRIVER_VER, riohdid); + + /* Setup the sRIO controller */ + res = keystone_rio_setup_controller(krio_priv); + if (res < 0) + return NULL; + + return (void *)krio_priv; +} + +/** + * rio_shutdown - Shutdown RapidIO subsystem + * @riohandle: RapidIO handle (returned by rio_init) + * + * Returns %0 on success or %-1 on failure. + */ +int rio_shutdown(void *riohandle) +{ + if (riohandle != &__krio_priv) + return -1; + + /* Power off */ + psc_disable_module(KS2_LPSC_SRIO); + + return 0; +} diff --git a/drivers/rapidio/keystone_rio.h b/drivers/rapidio/keystone_rio.h new file mode 100644 index 0000000..92547ae --- /dev/null +++ b/drivers/rapidio/keystone_rio.h @@ -0,0 +1,650 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * Authors: Aurelien Jacquiot <a-jacquiot(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef KEYSTONE_RIO_H +#define KEYSTONE_RIO_H + +#include <asm/setup.h> +#include <asm/cache.h> +#include <asm/io.h> + +#define BIT(x) (1 << (x)) + +#define KEYSTONE_RIO_MAP_FLAG_SEGMENT BIT(0) +#define KEYSTONE_RIO_MAP_FLAG_SRC_PROMISC BIT(1) +#define KEYSTONE_RIO_MAP_FLAG_TT_16 BIT(13) +#define KEYSTONE_RIO_MAP_FLAG_DST_PROMISC BIT(15) +#define KEYSTONE_RIO_DESC_FLAG_TT_16 BIT(9) + +#define KEYSTONE_RIO_BOOT_COMPLETE BIT(24) +#define KEYSTONE_RIO_PER_EN BIT(2) +#define KEYSTONE_RIO_PER_FREE BIT(0) +#define KEYSTONE_RIO_PEF_FLOW_CONTROL BIT(7) + +/* + * Packet types + */ +#define KEYSTONE_RIO_PACKET_TYPE_NREAD 0x24 +#define KEYSTONE_RIO_PACKET_TYPE_NWRITE 0x54 +#define KEYSTONE_RIO_PACKET_TYPE_NWRITE_R 0x55 +#define KEYSTONE_RIO_PACKET_TYPE_SWRITE 0x60 +#define KEYSTONE_RIO_PACKET_TYPE_DBELL 0xa0 +#define KEYSTONE_RIO_PACKET_TYPE_MAINT_R 0x80 +#define KEYSTONE_RIO_PACKET_TYPE_MAINT_W 0x81 +#define KEYSTONE_RIO_PACKET_TYPE_MAINT_RR 0x82 +#define KEYSTONE_RIO_PACKET_TYPE_MAINT_WR 0x83 +#define KEYSTONE_RIO_PACKET_TYPE_MAINT_PW 0x84 + +/* + * LSU defines + */ +#define KEYSTONE_RIO_LSU_PRIO 0 + +#define KEYSTONE_RIO_LSU_BUSY_MASK BIT(31) +#define KEYSTONE_RIO_LSU_FULL_MASK BIT(30) + +#define KEYSTONE_RIO_LSU_CC_MASK 0x0f +#define KEYSTONE_RIO_LSU_CC_TIMEOUT 0x01 +#define KEYSTONE_RIO_LSU_CC_XOFF 0x02 +#define KEYSTONE_RIO_LSU_CC_ERROR 0x03 +#define KEYSTONE_RIO_LSU_CC_INVALID 0x04 +#define KEYSTONE_RIO_LSU_CC_DMA 0x05 +#define KEYSTONE_RIO_LSU_CC_RETRY 0x06 +#define KEYSTONE_RIO_LSU_CC_CANCELED 0x07 + +/* Mask for receiving both error and good completion LSU interrupts */ +#define KEYSTONE_RIO_ICSR_LSU0(src_id) ((0x10001) << (src_id)) + +/* Keystone2 supported baud rates */ +#define KEYSTONE_RIO_BAUD_1_250 0 +#define KEYSTONE_RIO_BAUD_2_500 1 +#define KEYSTONE_RIO_BAUD_3_125 2 +#define KEYSTONE_RIO_BAUD_5_000 3 + +#define KEYSTONE_RIO_FULL_RATE 0 +#define KEYSTONE_RIO_HALF_RATE 1 +#define KEYSTONE_RIO_QUARTER_RATE 2 + +/* Max ports configuration per path modes */ +#define KEYSTONE_MAX_PORTS_PATH_MODE_0 0xf /* 4 ports */ +#define KEYSTONE_MAX_PORTS_PATH_MODE_1 0xd /* 3 ports */ +#define KEYSTONE_MAX_PORTS_PATH_MODE_2 0x7 /* 3 ports */ +#define KEYSTONE_MAX_PORTS_PATH_MODE_3 0x5 /* 2 ports */ +#define KEYSTONE_MAX_PORTS_PATH_MODE_4 0x1 /* 1 ports */ + +#define SERDES_LANE(lane_num) (0x01 << lane_num) +#define IS_SERDES_LANE_USED(lanes, lane_num) (lanes & SERDES_LANE(lane_num)) + +/* + * Various RIO defines + */ +#define KEYSTONE_RIO_TIMEOUT_CNT 1000 + +/* + * RIO error, reset and special event interrupt defines + */ +#define KEYSTONE_RIO_PORT_ERROR_OUT_PKT_DROP BIT(26) +#define KEYSTONE_RIO_PORT_ERROR_OUT_FAILED BIT(25) +#define KEYSTONE_RIO_PORT_ERROR_OUT_DEGRADED BIT(24) +#define KEYSTONE_RIO_PORT_ERROR_OUT_RETRY BIT(20) +#define KEYSTONE_RIO_PORT_ERROR_OUT_ERROR BIT(17) +#define KEYSTONE_RIO_PORT_ERROR_IN_ERROR BIT(9) +#define KEYSTONE_RIO_PORT_ERROR_PW_PENDING BIT(4) +#define KEYSTONE_RIO_PORT_ERROR_PORT_ERR BIT(2) + +#define KEYSTONE_RIO_PORT_ERROR_MASK \ + (KEYSTONE_RIO_PORT_ERROR_OUT_PKT_DROP |\ + KEYSTONE_RIO_PORT_ERROR_OUT_FAILED |\ + KEYSTONE_RIO_PORT_ERROR_OUT_DEGRADED |\ + KEYSTONE_RIO_PORT_ERROR_OUT_RETRY |\ + KEYSTONE_RIO_PORT_ERROR_OUT_ERROR |\ + KEYSTONE_RIO_PORT_ERROR_IN_ERROR |\ + KEYSTONE_RIO_PORT_ERROR_PW_PENDING |\ + KEYSTONE_RIO_PORT_ERROR_PORT_ERR) + + +#define KEYSTONE_RIO_SP_HDR_NEXT_BLK_PTR 0x1000 +#define KEYSTONE_RIO_SP_HDR_EP_REC_ID 0x0002 +#define KEYSTONE_RIO_ERR_HDR_NEXT_BLK_PTR 0x3000 +#define KEYSTONE_RIO_ERR_EXT_FEAT_ID 0x0007 + +/* + * RapidIO global definitions + */ +#define KEYSTONE_RIO_MAX_PORT 4 +#define KEYSTONE_RIO_BLK_NUM 9 +#define KEYSTONE_RIO_MAINT_BUF_SIZE 64 + +/* + * Dev Id and dev revision + */ +#define KEYSTONE_RIO_DEV_ID_VAL \ + ((((__raw_readl(krio_priv->jtagid_reg)) << 4) & 0xffff0000) | 0x30) + +#define KEYSTONE_RIO_DEV_INFO_VAL \ + (((__raw_readl(krio_priv->jtagid_reg)) >> 28) & 0xf) + +#define KEYSTONE_RIO_ID_TI (0x00000030) +#define KEYSTONE_RIO_EXT_FEAT_PTR (0x00000100) + +/* + * SerDes configurations + */ +struct keystone_serdes_config { + u32 cfg_cntl; /* setting control register config */ + u16 serdes_cfg_pll; /* SerDes PLL configuration */ + u16 prescalar_srv_clk; /* prescalar fo ip_clk */ + + /* SerDes receive channel configuration (per-port) */ + u32 rx_chan_config[KEYSTONE_RIO_MAX_PORT]; + + /* SerDes transmit channel configuration (per-port) */ + u32 tx_chan_config[KEYSTONE_RIO_MAX_PORT]; +}; + +/* + * Per board RIO devices controller configuration + */ +struct keystone_rio_board_controller_info { + u32 rio_regs_base; + u32 rio_regs_size; + + u32 boot_cfg_regs_base; + u32 boot_cfg_regs_size; + + u32 serdes_cfg_regs_base; + u32 serdes_cfg_regs_size; + + u16 ports; /* bitfield of port(s) to probe on this controller */ + u16 mode; /* hw mode (default serdes config). + index into serdes_config[] */ + u16 id; /* host id */ + u16 size; /* RapidIO common transport system size. + * 0 - Small size. 256 devices. + * 1 - Large size, 65536 devices. */ + u16 keystone2_serdes; + u16 serdes_config_num; + u32 serdes_baudrate; + u32 path_mode; + + struct keystone_serdes_config serdes_config[4]; +}; + +struct keystone_rio_data; + +/* + * RapidIO Registers + */ + +struct keystone_srio_serdes_regs { + u32 pll; + + struct { + u32 rx; + u32 tx; + } channel[4]; +}; + +/* RIO Registers 0000 - 2fff */ +struct keystone_rio_regs { +/* Required Peripheral Registers */ + u32 pid; /* 0000 */ + u32 pcr; /* 0004 */ + u32 __rsvd0[3]; /* 0008 - 0010 */ + +/* Peripheral Settting Control Registers */ + u32 per_set_cntl; /* 0014 */ + u32 per_set_cntl1; /* 0018 */ + + u32 __rsvd1[2]; /* 001c - 0020 */ + + u32 gbl_en; /* 0024 */ + u32 gbl_en_stat; /* 0028 */ + + struct { + u32 enable; /* 002c */ + u32 status; /* 0030 */ + } blk[10]; /* 002c - 0078 */ + + /* ID Registers */ + u32 __rsvd2[17]; /* 007c - 00bc */ + u32 multiid_reg[8]; /* 00c0 - 00dc */ + +/* Hardware Packet Forwarding Registers */ + struct { + u32 pf_16b; + u32 pf_8b; + } pkt_fwd_cntl[8]; /* 00e0 - 011c */ + + u32 __rsvd3[24]; /* 0120 - 017c */ + +/* Interrupt Registers */ + struct { + u32 status; + u32 __rsvd0; + u32 clear; + u32 __rsvd1; + } doorbell_int[4]; /* 0180 - 01bc */ + + struct { + u32 status; + u32 __rsvd0; + u32 clear; + u32 __rsvd1; + } lsu_int[2]; /* 01c0 - 01dc */ + + u32 err_rst_evnt_int_stat; /* 01e0 */ + u32 __rsvd4; + u32 err_rst_evnt_int_clear; /* 01e8 */ + u32 __rsvd5; + + u32 __rsvd6[4]; /* 01f0 - 01fc */ + + struct { + u32 route; /* 0200 */ + u32 route2; /* 0204 */ + u32 __rsvd; /* 0208 */ + } doorbell_int_route[4]; /* 0200 - 022c */ + + u32 lsu0_int_route[4]; /* 0230 - 023c */ + u32 lsu1_int_route1; /* 0240 */ + + u32 __rsvd7[3]; /* 0244 - 024c */ + + u32 err_rst_evnt_int_route[3]; /* 0250 - 0258 */ + + u32 __rsvd8[2]; /* 025c - 0260 */ + + u32 interupt_ctl; /* 0264 */ + + u32 __rsvd9[26]; /* 0268, 026c, 0270 - 02cc */ + + u32 intdst_rate_cntl[16]; /* 02d0 - 030c */ + u32 intdst_rate_disable; /* 0310 */ + + u32 __rsvd10[59]; /* 0314 - 03fc */ + +/* RXU Registers */ + struct { + u32 ltr_mbox_src; + u32 dest_prom_seg; + u32 flow_qid; + } rxu_map[64]; /* 0400 - 06fc */ + + struct { + u32 cos_src; + u32 dest_prom; + u32 stream; + } rxu_type9_map[64]; /* 0700 - 09fc */ + + u32 __rsvd11[192]; /* 0a00 - 0cfc */ + +/* LSU/MAU Registers */ + struct { + u32 addr_msb; /* 0d00 */ + u32 addr_lsb_cfg_ofs; /* 0d04 */ + u32 dsp_addr; /* 0d08 */ + u32 dbell_val_byte_cnt; /* 0d0c */ + u32 destid; /* 0d10 */ + u32 dbell_info_fttype; /* 0d14 */ + u32 busy_full; /* 0d18 */ + } lsu_reg[8]; /* 0d00 - 0ddc */ + + u32 lsu_setup_reg[2]; /* 0de0 - 0de4 */ + u32 lsu_stat_reg[6]; /* 0de8 - 0dfc */ + u32 lsu_flow_masks[4]; /* 0e00 - 0e0c */ + + u32 __rsvd12[16]; /* 0e10 - 0e4c */ + +/* Flow Control Registers */ + u32 flow_cntl[16]; /* 0e50 - 0e8c */ + u32 __rsvd13[8]; /* 0e90 - 0eac */ + +/* TXU Registers 0eb0 - 0efc */ + u32 tx_cppi_flow_masks[8]; /* 0eb0 - 0ecc */ + u32 tx_queue_sch_info[4]; /* 0ed0 - 0edc */ + u32 garbage_coll_qid[3]; /* 0ee0 - 0ee8 */ + + u32 __rsvd14[69]; /* 0eec, 0ef0 - 0ffc */ + +}; + +/* CDMAHP Registers 1000 - 2ffc */ +struct keystone_rio_pktdma_regs { + u32 __rsvd[2048]; /* 1000 - 2ffc */ +}; + +/* CSR/CAR Registers b000+ */ +struct keystone_rio_car_csr_regs { + u32 dev_id; /* b000 */ + u32 dev_info; /* b004 */ + u32 assembly_id; /* b008 */ + u32 assembly_info; /* b00c */ + u32 pe_feature; /* b010 */ + + u32 sw_port; /* b014 */ + + u32 src_op; /* b018 */ + u32 dest_op; /* b01c */ + + u32 __rsvd1[7]; /* b020 - b038 */ + + u32 data_stm_info; /* b03c */ + + u32 __rsvd2[2]; /* b040 - b044 */ + + u32 data_stm_logical_ctl; /* b048 */ + u32 pe_logical_ctl; /* b04c */ + + u32 __rsvd3[2]; /* b050 - b054 */ + + u32 local_cfg_hbar; /* b058 */ + u32 local_cfg_bar; /* b05c */ + + u32 base_dev_id; /* b060 */ + u32 __rsvd4; + u32 host_base_id_lock; /* b068 */ + u32 component_tag; /* b06c */ + /* b070 - b0fc */ +}; + +struct keystone_rio_serial_port_regs { + u32 sp_maint_blk_hdr; /* b100 */ + u32 __rsvd6[7]; /* b104 - b11c */ + + u32 sp_link_timeout_ctl; /* b120 */ + u32 sp_rsp_timeout_ctl; /* b124 */ + u32 __rsvd7[5]; /* b128 - b138 */ + u32 sp_gen_ctl; /* b13c */ + + struct { + u32 link_maint_req; /* b140 */ + u32 link_maint_resp;/* b144 */ + u32 ackid_stat; /* b148 */ + u32 __rsvd[2]; /* b14c - b150 */ + u32 ctl2; /* b154 */ + u32 err_stat; /* b158 */ + u32 ctl; /* b15c */ + } sp[4]; /* b140 - b1bc */ + + /* b1c0 - bffc */ +}; + +struct keystone_rio_err_mgmt_regs { + u32 err_report_blk_hdr; /* c000 */ + u32 __rsvd9; + u32 err_det; /* c008 */ + u32 err_en; /* c00c */ + u32 h_addr_capt; /* c010 */ + u32 addr_capt; /* c014 */ + u32 id_capt; /* c018 */ + u32 ctrl_capt; /* c01c */ + u32 __rsvd10[2]; /* c020 - c024 */ + u32 port_write_tgt_id; /* c028 */ + u32 __rsvd11[5]; /* c02c - c03c */ + + struct { + u32 det; /* c040 */ + u32 rate_en; /* c044 */ + u32 attr_capt_dbg0; /* c048 */ + u32 capt_0_dbg1; /* c04c */ + u32 capt_1_dbg2; /* c050 */ + u32 capt_2_dbg3; /* c054 */ + u32 capt_3_dbg4; /* c058 */ + u32 __rsvd0[3]; /* c05c - c064 */ + u32 rate; /* c068 */ + u32 thresh; /* c06c */ + u32 __rsvd1[4]; /* c070 - c07c */ + } sp_err[4]; /* c040 - c13c */ + + u32 __rsvd12[1972]; /* c140 - e00c */ + + struct { + u32 stat0; /* e010 */ + u32 stat1; /* e014 */ + u32 __rsvd[6]; /* e018 - e02c */ + } lane_stat[4]; /* e010 - e08c */ + + /* e090 - 1affc */ +}; + +struct keystone_rio_phy_layer_regs { + u32 phy_blk_hdr; /* 1b000 */ + u32 __rsvd14[31]; /* 1b004 - 1b07c */ + struct { + u32 imp_spec_ctl; /* 1b080 */ + u32 pwdn_ctl; /* 1b084 */ + u32 __rsvd0[2]; + + u32 status; /* 1b090 */ + u32 int_enable; /* 1b094 */ + u32 port_wr_enable; /* 1b098 */ + u32 event_gen; /* 1b09c */ + + u32 all_int_en; /* 1b0a0 */ + u32 all_port_wr_en; /* 1b0a4 */ + u32 __rsvd1[2]; + + u32 path_ctl; /* 1b0b0 */ + u32 discovery_timer;/* 1b0b4 */ + u32 silence_timer; /* 1b0b8 */ + u32 vmin_exp; /* 1b0bc */ + + u32 pol_ctl; /* 1b0c0 */ + u32 __rsvd2; + u32 denial_ctl; /* 1b0c8 */ + u32 __rsvd3; + + u32 rcvd_mecs; /* 1b0d0 */ + u32 __rsvd4; + u32 mecs_fwd; /* 1b0d8 */ + u32 __rsvd5; + + u32 long_cs_tx1; /* 1b0e0 */ + u32 long_cs_tx2; /* 1b0e4 */ + u32 __rsvd[6]; /* 1b0e8, 1b0ec, 1b0f0 - 1b0fc */ + } phy_sp[4]; /* 1b080 - 1b27c */ + + /* 1b280 - 1b2fc */ +}; + +struct keystone_rio_transport_layer_regs { + u32 transport_blk_hdr; /* 1b300 */ + u32 __rsvd16[31]; /* 1b304 - 1b37c */ + + struct { + u32 control; /*1b380 */ + u32 __rsvd0[3]; + + u32 status; /* 1b390 */ + u32 int_enable; /* 1b394 */ + u32 port_wr_enable; /* 1b398 */ + u32 event_gen; /* 1b39c */ + + struct { + u32 ctl; /* 1b3a0 */ + u32 pattern_match; /* 1b3a4 */ + u32 __rsvd[2]; /* 1b3a8 - 1b3ac */ + } base_route[4]; /* 1b3a0 - 1b3dc */ + + u32 __rsvd1[8]; /* 1b3e0 - 1b3fc */ + + } transport_sp[4]; /* 1b380 - 1b57c */ + + /* 1b580 - 1b5fc */ +}; + +struct keystone_rio_pkt_buf_regs { + u32 pkt_buf_blk_hdr; /* 1b600 */ + u32 __rsvd18[31]; /* 1b604 - 1b67c */ + + struct { + u32 control; /* 1b680 */ + u32 __rsvd0[3]; + + u32 status; /* 1b690 */ + u32 int_enable; /* 1b694 */ + u32 port_wr_enable; /* 1b698 */ + u32 event_gen; /* 1b69c */ + + u32 ingress_rsc; /* 1b6a0 */ + u32 egress_rsc; /* 1b6a4 */ + u32 __rsvd1[2]; + + u32 ingress_watermark[4]; /* 1b6b0 - 1b6bc */ + u32 __rsvd2[16]; /* 1b6c0 - 1b6fc */ + + } pkt_buf_sp[4]; /* 1b680 - 1b87c */ + + /* 1b880 - 1b8fc */ +}; + +struct keystone_rio_evt_mgmt_regs { + u32 evt_mgmt_blk_hdr; /* 1b900 */ + u32 __rsvd20[3]; + + u32 evt_mgmt_int_stat; /* 1b910 */ + u32 evt_mgmt_int_enable; /* 1b914 */ + u32 evt_mgmt_int_port_stat; /* 1b918 */ + u32 __rsvd21; + + u32 evt_mgmt_port_wr_stat; /* 1b920 */ + u32 evt_mgmt_port_wr_enable;/* 1b924 */ + u32 evt_mgmt_port_wr_port_stat; /* 1b928 */ + u32 __rsvd22; + + u32 evt_mgmt_dev_int_en; /* 1b930 */ + u32 evt_mgmt_dev_port_wr_en; /* 1b934 */ + u32 __rsvd23; + u32 evt_mgmt_mecs_stat; /* 1b93c */ + + u32 evt_mgmt_mecs_int_en; /* 1b940 */ + u32 evt_mgmt_mecs_cap_en; /* 1b944 */ + u32 evt_mgmt_mecs_trig_en; /* 1b948 */ + u32 evt_mgmt_mecs_req; /* 1b94c */ + + u32 evt_mgmt_mecs_port_stat;/* 1b950 */ + u32 __rsvd24[2]; + u32 evt_mgmt_mecs_event_gen;/* 1b95c */ + + u32 evt_mgmt_rst_port_stat; /* 1b960 */ + u32 __rsvd25; + u32 evt_mgmt_rst_int_en; /* 1b968 */ + u32 __rsvd26; + + u32 evt_mgmt_rst_port_wr_en;/* 1b970 */ + /* 1b974 - 1b9fc */ +}; + +struct keystone_rio_port_write_regs { + u32 port_wr_blk_hdr; /* 1ba00 */ + u32 port_wr_ctl; /* 1ba04 */ + u32 port_wr_route; /* 1ba08 */ + u32 __rsvd28; + + u32 port_wr_rx_stat; /* 1ba10 */ + u32 port_wr_rx_event_gen; /* 1ba14 */ + u32 __rsvd29[2]; + + u32 port_wr_rx_capt[4]; /* 1ba20 - 1ba2c */ + /* 1ba30 - 1bcfc */ +}; + +struct keystone_rio_link_layer_regs { + u32 link_blk_hdr; /* 1bd00 */ + u32 __rsvd31[8]; /* 1bd04 - 1bd20 */ + u32 whiteboard; /* 1bd24 */ + u32 port_number; /* 1bd28 */ + + u32 __rsvd32; /* 1bd2c */ + + u32 prescalar_srv_clk; /* 1bd30 */ + u32 reg_rst_ctl; /* 1bd34 */ + u32 __rsvd33[4]; /* 1bd38, 1bd3c, 1bd40, 1bd44 */ + u32 local_err_det; /* 1bd48 */ + u32 local_err_en; /* 1bd4c */ + + u32 local_h_addr_capt; /* 1bd50 */ + u32 local_addr_capt; /* 1bd54 */ + u32 local_id_capt; /* 1bd58 */ + u32 local_ctrl_capt; /* 1bd5c */ + + /* 1bd60 - 1bdfc */ +}; + +struct keystone_rio_fabric_regs { + u32 fabric_hdr; /* 1be00 */ + u32 __rsvd35[3]; /* 1be04 - 1be0c */ + + u32 fabric_csr; /* 1be10 */ + u32 __rsvd36[11]; /* 1be14 - 1be3c */ + + u32 sp_fabric_status[4]; /* 1be40 - 1be4c */ +}; + +/** + * keystone_rio_config_read - Generate a KeyStone read maintenance transaction + * @portid: Output port ID of transaction + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Location to be read into + * + * Generates a KeyStone read maintenance transaction. Returns %0 on + * success or %-1 on failure. + */ +int keystone_rio_config_read(int portid, + u16 destid, + u8 hopcount, + u32 offset, + int len, + u32 *val); + +/** + * keystone_rio_config_write - Generate a KeyStone write maintenance transaction + * @portid: Output port ID of transaction + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Value to be written + * + * Generates an KeyStone write maintenance transaction. Returns %0 on + * success or %-1 on failure. + */ +int keystone_rio_config_write(int portid, + u16 destid, + u8 hopcount, + u32 offset, + int len, + u32 val); + +/** + * keystone_local_config_read - Generate a KeyStone local config space read + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be read into + * + * Generates a KeyStone local configuration space read. Returns %0 on + * success or %-1 on failure. + */ +int keystone_local_config_read(u32 offset, int len, u32 *data); + +/** + * keystone_local_config_write - Generate a KeyStone local config space write + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be written + * + * Generates a KeyStone local configuration space write. Returns %0 on + * success or %-EINVAL on failure. + */ +int keystone_local_config_write(u32 offset, int len, u32 data); + +#endif /* KEYSTONE_RIO_H */ -- 1.6.2.1

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[U-Boot] [PATCH 3/4] rapidio: add documentation for RapidIO boot
by jacquiot.aurelien＠gmail.com 04 Jan '16

04 Jan '16

From: Aurelien Jacquiot <a-jacquiot(a)ti.com> This commit adds the RapidIO boot functionality documentation. Its explains what RapidIO boot feature does, how to use it and the basic API that must be provided by a RapidIO hw controller driver. Signed-off-by: Aurelien Jacquiot <a-jacquiot(a)ti.com> --- doc/README.rapidio | 158 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 158 insertions(+), 0 deletions(-) create mode 100644 doc/README.rapidio diff --git a/doc/README.rapidio b/doc/README.rapidio new file mode 100644 index 0000000..e360a7f --- /dev/null +++ b/doc/README.rapidio @@ -0,0 +1,158 @@ + RapidIO support for TI KeyStone devices + ======================================= + + +This feature allows to boot a device through RapidIO using DirectI/O (DIO). +A new set of commands is added to U-Boot for this purpose. + +This feature is today designed to work with Texas Instruments KeyStone devices +but may be easily extended to be used on different architectures. + +How it works +------------ + +This booting mechanism uses the DirectI/O functionality which allows a +remote devices to directly read and write into the device address space +(so basically here into the DDR or any mapped memory such as MSM). + +The boot sequence is pretty simple. The RIO boot initializes the RapidIO +controller then the link partner needs to push the various images (kernel, +fdt, ...). When images are loaded into their respective locations by the peer, +U-Boot can start the images normally like with any other boot mechanismes. + +It is the link partner responsability to push the various images in the device +memory then signaling U-Boot that images have been loaded. + +for that purpose, the simpler way is to use the 'mwait' U-Boot command which +allows to wait a defined value in memory. The link partner has only to write +the expected value at a given address when it has pushed all images. + +Basically the sequence should be the following (A is the device to be booted, B +is the link partner device which pushes the images to boot): + + [B]: board is up and booted, RapidIO controller is initialized but not the link + [A]: board is powered on, entering U-Boot + [A]: the 'rio init' command is called + [A]: U-Boot configures the local RapidIO controller and hardware waits the link + establishement + [B]: Linux kernel starts the RapidIO link configuration and eventually the + RapidIO enumeration/discovery process (see Linux kernel RapidIO subsytem + driver for more information) + [AB]: RapidIO link is now established between the both link partners + [A]: the 'mwait 0x80000000 0xbadface' command is called + [A]: U-Boot reads the first word at beginning of the DDR in loop and waits + until it is set to 0xbadface + [B]: system pushes the kernel image using DIO + [B]: system pushes the dtb image using DIO + [B]: system pushes the skern image using DIO + [B]: system set the 0xbadface value at the first word of the remote DDR + [A]: U-Boot detects that first DDR word has changed to 0xbadface and exits the + mwait command + [A]: skern, fdt and kernel can be installed and started normally with the + 'mon_install' and 'bootm' U-Boot commands + +RapidIO subsystem commands +-------------------------- + + - rio init [dev_id] [id_size] [port_mask] [pathmode] [baudrate]: + This command is used to initialize the RapidIO controller. Optional + parameters are used to define the RapidIO configuration. + Note that environment variables can be instead of parameters. + + 1) dev_id ('riohdid' environment variable) to set the host device Id. + By default if not specified it is set to -1. + + 2) id_size ('riosize' environment variable) to indicate the Ids size + (0 for small, 1 for big). By default it is set to 0 (small Ids). + + 3) port_mask ('rioports' environment variable) is a bitmask of ports to use. + By default it is set to 0x1 (port 0). + + 4) pathmode ('riopathmode' environment variable) defines the port path mode + (mapping of ports over lanes). The default mode is 0 (4 independent ports + in 1x). + + 5) baudrate ('riobaudrate' environment variable) defines the port speed: + 0 for 1.25Gbps, 1 for 2.5Gbps, 2 for 3.125Gbps, 3 for 5Gbps and 4 for + 6.25Gpbs (if supported). It is set by default to 2 (2.5Gbps). + + - rio shutdown: It disables the RapidIO controller. + + - rio r port dev_id hopcount offset: This command allows to read the remote + RapidIO configuration space by performing a maintenance read request. + + - rio w port dev_id hopcount offset value: This command allows to write into + the remote RapidIO configuration space by performing a maintenance write + request. + + - rio lr offset: This performs a local RapidIO configuration space read. + + - rio lw offset value: This performs a local RapidIO configuration space write. + +Device support +-------------- + +The RapidIO controller of the KeyStone devices is supported through the +drivers/rapidio/keystone_rio.c device driver. + +The RapidIO driver must export the following functions (see include/rio.h for +full prototypes). + + - rio_init() : initialize RapidIO controller + - rio_shutdown(): shutdown RapidIO controller + - rio_config_read(): perform a RapidIO maintenance read transaction + - rio_config_write(): perform a RapidIO maintenance read transaction + - rio_local_config_read(): local configuration space read + - rio_local_config_write(): local configuration space write + +Booting with RapidIO +-------------------- + +Example of RapidIO booting with U-Boot: + +K2HK EVM # rio init -1 0 0x1 4 3 +rioboot: waiting for link up ... +KeyStone RapidIO driver v1.1, hdid=-1 +RIO: initializing 5.00 Gbps interface with port configuration 4 +RIO: port RIO0 ready +K2HK EVM # mwait 0x80000000 0xbadface +waiting 0xbadface at 0x80000000... +K2HK EVM # mon_install ${addr_mon} +## installed monitor, freq [200000000], status 0 +K2HK EVM # bootm ${addr_kern} ${addr_uninitrd} ${addr_fdt} +## Booting kernel from Legacy Image at 88000000 ... + Image Name: Linux-3.8.4 + Created: 2014-01-27 17:48:10 UTC + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 3990680 Bytes = 3.8 MiB + Load Address: 80008000 + Entry Point: 80008000 + Verifying Checksum ... OK + +----- + +Here is an example under Linux using the riodio utility and the riodev feature +of the booting of a remote device which uses U-Boot RapidIO booting mechanism +(like the example above): + +# riodio -f uImage /dev/rio0.1 0x88000000 +# riodio -f k2hk-evm.dtb /dev/rio0.1 0x87000000 +# riodio -f skern-keystone-evm.bin /dev/rio0.1 0xc5f0000 +# riodio -v 0xbadface /dev/rio0.1 0x80000000 + +This will push the various images and notify U-Boot. + +----- + +Example of (local and remote) read/write commands: + +K2HK EVM # rio r 0 -1 1 0x0 +00000000: b9810030 0... +K2HK EVM # rio r 0 -1 1 0x4 +00000004: 00000000 .... +K2HK EVM # rio r 0 -1 1 0x8 +00000008: 00000030 0... +K2HK EVM # rio lr 0 +00000000: b9810030 0... +K2HK EVM # rio lr 8 +00000008: 00000030 0... -- 1.6.2.1

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[U-Boot] [PATCH 2/4] rapidio: add support for RapidIO boot
by jacquiot.aurelien＠gmail.com 04 Jan '16

04 Jan '16

From: Aurelien Jacquiot <a-jacquiot(a)ti.com> RapidIO is a high-performance packet-switched interconnect technology (www.rapidio.org) that can be used for messaging or memory transfers like Ethernet or PCIe. This commit adds the RapidIO boot functionality for slave mode (i.e. U-Boot does not fetch the images, images are pushed by a peer device/board). A new 'rio' command group allows to initialize and perform basic RapidIO operations. This feature has been firstly designed for TI KeyStone architecture but can used by any device that has hardware RapidIO support and corresponding driver. For more information, read the doc/README.rapidio documentation. Signed-off-by: Aurelien Jacquiot <a-jacquiot(a)ti.com> --- common/Kconfig | 7 +- common/Makefile | 1 + common/cmd_rio.c | 260 +++++++++++++++++++++++++++++++++++++ include/rio.h | 382 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 649 insertions(+), 1 deletions(-) create mode 100644 common/cmd_rio.c create mode 100644 include/rio.h diff --git a/common/Kconfig b/common/Kconfig index 0388a6c..2a3dbd2 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -355,8 +355,13 @@ config CMD_REMOTEPROC depends on REMOTEPROC help Support for Remote Processor control -endmenu +config CMD_RIO + bool "rapidio" + help + RapidIO support. + +endmenu menu "Shell scripting commands" diff --git a/common/Makefile b/common/Makefile index d986cde..7380958 100644 --- a/common/Makefile +++ b/common/Makefile @@ -195,6 +195,7 @@ obj-$(CONFIG_YAFFS2) += cmd_yaffs2.o obj-$(CONFIG_CMD_SPL) += cmd_spl.o obj-$(CONFIG_CMD_ZIP) += cmd_zip.o obj-$(CONFIG_CMD_ZFS) += cmd_zfs.o +obj-$(CONFIG_CMD_RIO) += cmd_rio.o # others obj-$(CONFIG_BOOTSTAGE) += bootstage.o diff --git a/common/cmd_rio.c b/common/cmd_rio.c new file mode 100644 index 0000000..72db7d1 --- /dev/null +++ b/common/cmd_rio.c @@ -0,0 +1,260 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * Authors: Aurelien Jacquiot <a-jacquiot(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * RapidIO support + */ +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <watchdog.h> +#include <rio.h> + +static void *rio_handle; + +static int rio_cmd_init(int argc, char * const argv[]) +{ + int riohdid = -1; /* none */ + int riosize = 0; /* small Ids */ + u32 rioports = 0x1; /* port 0 */ + int riopmode = 0; /* 4 ports in 1x */ + int riobaudrate = 1; /* 2.5Gbps */ + char *s; + + if (rio_handle) { + printf("RapidIO device already initialized!\n"); + return CMD_RET_FAILURE; + } + + /* hostid */ + if (argc >= 2) { + riohdid = simple_strtol(argv[2], NULL, 10); + } else { + s = getenv("riohdid"); + if (s != NULL) + riohdid = simple_strtol(s, NULL, 10); + goto call_init; + } + + /* dev-id size */ + if (argc >= 3) { + riosize = simple_strtol(argv[3], NULL, 10); + } else { + s = getenv("riosize"); + if (s != NULL) + riosize = simple_strtol(s, NULL, 10); + goto call_init; + } + + /* port bitmask */ + if (argc >= 4) { + rioports = simple_strtoul(argv[4], NULL, 16); + } else { + s = getenv("rioports"); + if (s != NULL) + rioports = simple_strtoul(s, NULL, 16); + goto call_init; + } + + /* port path mode */ + if (argc >= 5) { + riopmode = simple_strtol(argv[5], NULL, 10); + } else { + s = getenv("riopathmode"); + if (s != NULL) + riopmode = simple_strtol(s, NULL, 10); + goto call_init; + } + + /* baudrate */ + if (argc >= 6) { + riobaudrate = simple_strtol(argv[6], NULL, 10); + } else { + s = getenv("riobaudrate"); + if (s != NULL) + riobaudrate = simple_strtol(s, NULL, 10); + } + +call_init: + printf("rioboot: waiting for link up ...\n"); + + /* Initialize RIO */ + rio_handle = rio_init(riohdid, riosize, rioports, riopmode, + riobaudrate); + if (!rio_handle) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int rio_cmd(int argc, char * const argv[]) +{ + char *cmd; + + if (argc == 1) + return CMD_RET_USAGE; + + if (!rio_handle) { + printf("RapidIO device not initialized!\n"); + return CMD_RET_FAILURE; + } + + cmd = argv[1]; + + if ((strncmp(cmd, "r", 1) == 0) || (strncmp(cmd, "w", 1) == 0)) { + int portid; + u16 destid; + u8 hopcount; + u32 offset; + + if (argc < 5) + return CMD_RET_USAGE; + + portid = simple_strtol(argv[2], NULL, 10); + destid = simple_strtol(argv[3], NULL, 10) & 0xffff; + hopcount = simple_strtoul(argv[4], NULL, 10) & 0xff; + offset = simple_strtoul(argv[5], NULL, 16); + + if (strncmp(cmd, "r", 1) == 0) { + int res; + u32 val; + + /* Do maintenance read */ + res = rio_config_read(portid, + destid, + hopcount, + offset, + sizeof(val), + &val); + + if (res) { + printf("cannot perform maintenance read\n"); + return CMD_RET_FAILURE; + } + + /* Display value */ + print_buffer(offset, (const void *)&val, sizeof(val), + 1, 0); + } + + if (strncmp(cmd, "w", 1) == 0) { + int res; + u32 val; + + if (argc < 6) + return CMD_RET_USAGE; + + val = simple_strtoul(argv[6], NULL, 16); + + /* Do maintenance write */ + res = rio_config_write(portid, + destid, + hopcount, + offset, + sizeof(val), + val); + + if (res) { + printf("cannot perform maintenance write\n"); + return CMD_RET_FAILURE; + } + } + + return CMD_RET_SUCCESS; + } + + if ((strncmp(cmd, "lr", 2) == 0) || (strncmp(cmd, "lw", 2) == 0)) { + u32 offset; + + if (argc < 2) + return CMD_RET_USAGE; + + offset = simple_strtoul(argv[2], NULL, 16); + + if (strncmp(cmd, "lr", 2) == 0) { + int res; + u32 val; + + /* Do local read */ + res = rio_local_config_read(offset, + sizeof(val), + &val); + + if (res) { + printf("cannot perform local read\n"); + return CMD_RET_FAILURE; + } + + /* Display value */ + print_buffer(offset, (const void *)&val, sizeof(val), + 1, 0); + } + + if (strncmp(cmd, "lw", 2) == 0) { + int res; + u32 val; + + if (argc < 3) + return CMD_RET_USAGE; + + val = simple_strtoul(argv[3], NULL, 16); + + /* Do local write */ + res = rio_local_config_write(offset, + sizeof(val), + val); + + if (res) { + printf("cannot perform local write\n"); + return CMD_RET_FAILURE; + } + } + + return CMD_RET_SUCCESS; + } + + return CMD_RET_USAGE; +} + +static int do_rio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd = argv[1]; + int ret; + + if (strncmp(cmd, "init", 4) == 0) + return rio_cmd_init(argc, argv); + + if (strncmp(cmd, "shutdown", 8) == 0) { + if (rio_handle) { + rio_shutdown(rio_handle); + rio_handle = NULL; + return CMD_RET_SUCCESS; + } else { + printf("RapidIO device not initialized!\n"); + return CMD_RET_FAILURE; + } + } + + ret = rio_cmd(argc, argv); + + if (ret == CMD_RET_USAGE) + return cmd_usage(cmdtp); + + return ret; +} + +U_BOOT_CMD(rio, CONFIG_SYS_MAXARGS, 1, do_rio, + "RapidIO sub-system", + "init [dev_id] [id_size] [port_mask] [pathmode] [baudrate]\n" + " - initialized RapidIO device\n" + "rio shutdown - shutdown RapidIO device\n" + "rio r port dev_id hopcount offset - perform config read\n" + "rio w port dev_id hopcount offset value - perform config write\n" + "rio lr offset - perform local config read\n" + "rio lw offset value - perform local config write\n" +); diff --git a/include/rio.h b/include/rio.h new file mode 100644 index 0000000..6b9341d --- /dev/null +++ b/include/rio.h @@ -0,0 +1,382 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * Authors: Aurelien Jacquiot <a-jacquiot(a)ti.com> + * + * Part of this file is borrowed from Linux rio_regs.h. + * (C) Copyright 2005 MontaVista Software, Inc. + * Matt Porter <mporter(a)kernel.crashing.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RIO_H_ +#define _RIO_H_ + +/* + * In RapidIO, each device has a 16MB configuration space that is + * accessed via maintenance transactions. Portions of configuration + * space are standardized and/or reserved. + */ +#define RIO_DEV_ID_CAR 0x00 +#define RIO_DEV_INFO_CAR 0x04 +#define RIO_ASM_ID_CAR 0x08 +#define RIO_ASM_ID_MASK 0xffff0000 +#define RIO_ASM_VEN_ID_MASK 0x0000ffff + +#define RIO_ASM_INFO_CAR 0x0c +#define RIO_ASM_REV_MASK 0xffff0000 +#define RIO_EXT_FTR_PTR_MASK 0x0000ffff + +#define RIO_PEF_CAR 0x10 +#define RIO_PEF_BRIDGE 0x80000000 +#define RIO_PEF_MEMORY 0x40000000 +#define RIO_PEF_PROCESSOR 0x20000000 +#define RIO_PEF_SWITCH 0x10000000 +#define RIO_PEF_INB_MBOX 0x00f00000 +#define RIO_PEF_INB_MBOX0 0x00800000 +#define RIO_PEF_INB_MBOX1 0x00400000 +#define RIO_PEF_INB_MBOX2 0x00200000 +#define RIO_PEF_INB_MBOX3 0x00100000 +#define RIO_PEF_INB_DOORBELL 0x00080000 +#define RIO_PEF_EXT_RT 0x00000200 +#define RIO_PEF_STD_RT 0x00000100 +#define RIO_PEF_CTLS 0x00000010 +#define RIO_PEF_FLOW_CONTROL 0x00000080 +#define RIO_PEF_EXT_FEATURES 0x00000008 +#define RIO_PEF_ADDR_66 0x00000004 +#define RIO_PEF_ADDR_50 0x00000002 +#define RIO_PEF_ADDR_34 0x00000001 + +#define RIO_SWP_INFO_CAR 0x14 +#define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00 +#define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff + +#define RIO_SRC_OPS_CAR 0x18 +#define RIO_SRC_OPS_READ 0x00008000 +#define RIO_SRC_OPS_WRITE 0x00004000 +#define RIO_SRC_OPS_STREAM_WRITE 0x00002000 +#define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000 +#define RIO_SRC_OPS_DATA_MSG 0x00000800 +#define RIO_SRC_OPS_DOORBELL 0x00000400 +#define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100 +#define RIO_SRC_OPS_ATOMIC_INC 0x00000080 +#define RIO_SRC_OPS_ATOMIC_DEC 0x00000040 +#define RIO_SRC_OPS_ATOMIC_SET 0x00000020 +#define RIO_SRC_OPS_ATOMIC_CLR 0x00000010 +#define RIO_SRC_OPS_PORT_WRITE 0x00000004 + +#define RIO_DST_OPS_CAR 0x1c +#define RIO_DST_OPS_READ 0x00008000 +#define RIO_DST_OPS_WRITE 0x00004000 +#define RIO_DST_OPS_STREAM_WRITE 0x00002000 +#define RIO_DST_OPS_WRITE_RESPONSE 0x00001000 +#define RIO_DST_OPS_DATA_MSG 0x00000800 +#define RIO_DST_OPS_DOORBELL 0x00000400 +#define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100 +#define RIO_DST_OPS_ATOMIC_INC 0x00000080 +#define RIO_DST_OPS_ATOMIC_DEC 0x00000040 +#define RIO_DST_OPS_ATOMIC_SET 0x00000020 +#define RIO_DST_OPS_ATOMIC_CLR 0x00000010 +#define RIO_DST_OPS_PORT_WRITE 0x00000004 + +#define RIO_OPS_READ 0x00008000 +#define RIO_OPS_WRITE 0x00004000 +#define RIO_OPS_STREAM_WRITE 0x00002000 +#define RIO_OPS_WRITE_RESPONSE 0x00001000 +#define RIO_OPS_DATA_MSG 0x00000800 +#define RIO_OPS_DOORBELL 0x00000400 +#define RIO_OPS_ATOMIC_TST_SWP 0x00000100 +#define RIO_OPS_ATOMIC_INC 0x00000080 +#define RIO_OPS_ATOMIC_DEC 0x00000040 +#define RIO_OPS_ATOMIC_SET 0x00000020 +#define RIO_OPS_ATOMIC_CLR 0x00000010 +#define RIO_OPS_PORT_WRITE 0x00000004 + + /* 0x20-0x30 *//* Reserved */ + +#define RIO_SWITCH_RT_LIMIT 0x34 +#define RIO_RT_MAX_DESTID 0x0000ffff + +#define RIO_MBOX_CSR 0x40 +#define RIO_MBOX0_AVAIL 0x80000000 +#define RIO_MBOX0_FULL 0x40000000 +#define RIO_MBOX0_EMPTY 0x20000000 +#define RIO_MBOX0_BUSY 0x10000000 +#define RIO_MBOX0_FAIL 0x08000000 +#define RIO_MBOX0_ERROR 0x04000000 +#define RIO_MBOX1_AVAIL 0x00800000 +#define RIO_MBOX1_FULL 0x00200000 +#define RIO_MBOX1_EMPTY 0x00200000 +#define RIO_MBOX1_BUSY 0x00100000 +#define RIO_MBOX1_FAIL 0x00080000 +#define RIO_MBOX1_ERROR 0x00040000 +#define RIO_MBOX2_AVAIL 0x00008000 +#define RIO_MBOX2_FULL 0x00004000 +#define RIO_MBOX2_EMPTY 0x00002000 +#define RIO_MBOX2_BUSY 0x00001000 +#define RIO_MBOX2_FAIL 0x00000800 +#define RIO_MBOX2_ERROR 0x00000400 +#define RIO_MBOX3_AVAIL 0x00000080 +#define RIO_MBOX3_FULL 0x00000040 +#define RIO_MBOX3_EMPTY 0x00000020 +#define RIO_MBOX3_BUSY 0x00000010 +#define RIO_MBOX3_FAIL 0x00000008 +#define RIO_MBOX3_ERROR 0x00000004 + +#define RIO_WRITE_PORT_CSR 0x44 +#define RIO_DOORBELL_CSR 0x44 +#define RIO_DOORBELL_AVAIL 0x80000000 +#define RIO_DOORBELL_FULL 0x40000000 +#define RIO_DOORBELL_EMPTY 0x20000000 +#define RIO_DOORBELL_BUSY 0x10000000 +#define RIO_DOORBELL_FAILED 0x08000000 +#define RIO_DOORBELL_ERROR 0x04000000 +#define RIO_WRITE_PORT_AVAILABLE 0x00000080 +#define RIO_WRITE_PORT_FULL 0x00000040 +#define RIO_WRITE_PORT_EMPTY 0x00000020 +#define RIO_WRITE_PORT_BUSY 0x00000010 +#define RIO_WRITE_PORT_FAILED 0x00000008 +#define RIO_WRITE_PORT_ERROR 0x00000004 + + /* 0x48 *//* Reserved */ + +#define RIO_PELL_CTRL_CSR 0x4c +#define RIO_PELL_ADDR_66 0x00000004 +#define RIO_PELL_ADDR_50 0x00000002 +#define RIO_PELL_ADDR_34 0x00000001 + + /* 0x50-0x54 *//* Reserved */ + +#define RIO_LCSH_BA 0x58 +#define RIO_LCSL_BA 0x5c + +#define RIO_DID_CSR 0x60 + + /* 0x64 *//* Reserved */ + +#define RIO_HOST_DID_LOCK_CSR 0x68 +#define RIO_COMPONENT_TAG_CSR 0x6c + +#define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70 +#define RIO_STD_RTE_CONF_PORT_SEL_CSR 0x74 +#define RIO_STD_RTE_DEFAULT_PORT 0x78 + + /* 0x7c-0xf8 *//* Reserved */ + /* 0x100-0xfff8 *//* [I] Extended Features Space */ + +#define RIO_PORT_LINK_MAINT_REQ_CSR 0x140 +#define RIO_PORT_LINK_MAINT_RESP_CSR 0x144 +#define RIO_PORT_LOCAL_ACKID_CSR 0x148 +#define RIO_PORT_ERR_STAT_CSR 0x158 +#define RIO_PORT_CTRL_CSR 0x15c + +#define RIO_PORT_OFFSET 0x20 + +#define RIO_PORT_CTRL_TYPE_SERIAL 0x00000001 +#define RIO_PORT_CTRL_ENUM_BOUNDARY 0x00020000 +#define RIO_PORT_CTRL_MCAST_EVT_PART 0x00080000 +#define RIO_PORT_CTRL_ERR_CHECK_DIS 0x00100000 +#define RIO_PORT_CTRL_INPUT_PORT_EN 0x00200000 +#define RIO_PORT_CTRL_OUTPUT_PORT_EN 0x00400000 +#define RIO_PORT_CTRL_PORT_DIS 0x00800000 + + /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */ + +/* + * Extended Features Space is a configuration space area where + * functionality is mapped into extended feature blocks via a + * singly linked list of extended feature pointers (EFT_PTR). + * + * Each extended feature block can be identified/located in + * Extended Features Space by walking the extended feature + * list starting with the Extended Feature Pointer located + * in the Assembly Information CAR. + * + * Extended Feature Blocks (EFBs) are identified with an assigned + * EFB ID. Extended feature block offsets in the definitions are + * relative to the offset of the EFB within the Extended Features + * Space. + */ + +/* Helper macros to parse the Extended Feature Block header */ +#define RIO_EFB_PTR_MASK 0xffff0000 +#define RIO_EFB_ID_MASK 0x0000ffff +#define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16) +#define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK) + +/* Extended Feature Block IDs */ +#define RIO_EFB_PAR_EP_ID 0x0001 +#define RIO_EFB_PAR_EP_REC_ID 0x0002 +#define RIO_EFB_PAR_EP_FREE_ID 0x0003 +#define RIO_EFB_SER_EP_ID_V13P 0x0001 +#define RIO_EFB_SER_EP_REC_ID_V13P 0x0002 +#define RIO_EFB_SER_EP_FREE_ID_V13P 0x0003 +#define RIO_EFB_SER_EP_ID 0x0004 +#define RIO_EFB_SER_EP_REC_ID 0x0005 +#define RIO_EFB_SER_EP_FREE_ID 0x0006 +#define RIO_EFB_SER_EP_FREC_ID 0x0009 +#define RIO_EFB_ERR_MGMNT 0x0007 + +/* + * Physical 8/16 LP-LVDS + * ID=0x0001, Generic End Point Devices + * ID=0x0002, Generic End Point Devices, software assisted recovery option + * ID=0x0003, Generic End Point Free Devices + * + * Physical LP-Serial + * ID=0x0004, Generic End Point Devices + * ID=0x0005, Generic End Point Devices, software assisted recovery option + * ID=0x0006, Generic End Point Free Devices + */ +#define RIO_PORT_MNT_HEADER 0x0000 +#define RIO_PORT_REQ_CTL_CSR 0x0020 +#define RIO_PORT_RSP_CTL_CSR 0x0024 /* 0x0001/0x0002 */ +#define RIO_PORT_LINKTO_CTL_CSR 0x0020 /* Serial */ +#define RIO_PORT_RSPTO_CTL_CSR 0x0024 /* Serial */ +#define RIO_PORT_GEN_CTL_CSR 0x003c +#define RIO_PORT_GEN_HOST 0x80000000 +#define RIO_PORT_GEN_MASTER 0x40000000 +#define RIO_PORT_GEN_DISCOVERED 0x20000000 +#define RIO_PORT_N_MNT_REQ_CSR(x) (0x0040 + x*0x20) +#define RIO_PORT_N_MNT_RSP_CSR(x) (0x0044 + x*0x20) +#define RIO_PORT_N_MNT_RSP_RVAL 0x80000000 +#define RIO_PORT_N_MNT_RSP_ASTAT 0x000003e0 +#define RIO_PORT_N_MNT_RSP_LSTAT 0x0000001f +#define RIO_PORT_N_ACK_STS_CSR(x) (0x0048 + x*0x20) +#define RIO_PORT_N_ACK_CLEAR 0x80000000 +#define RIO_PORT_N_ACK_INBOUND 0x1f000000 +#define RIO_PORT_N_ACK_OUTSTAND 0x00001f00 +#define RIO_PORT_N_ACK_OUTBOUND 0x0000001f +#define RIO_PORT_N_ERR_STS_CSR(x) (0x0058 + x*0x20) +#define RIO_PORT_N_ERR_STS_PW_OUT_ES 0x00010000 /* Output Error-stopped */ +#define RIO_PORT_N_ERR_STS_PW_INP_ES 0x00000100 /* Input Error-stopped */ +#define RIO_PORT_N_ERR_STS_PW_PEND 0x00000010 /* Port-Write Pending */ +#define RIO_PORT_N_ERR_STS_PORT_ERR 0x00000004 +#define RIO_PORT_N_ERR_STS_PORT_OK 0x00000002 +#define RIO_PORT_N_ERR_STS_PORT_UNINIT 0x00000001 +#define RIO_PORT_N_ERR_STS_CLR_MASK 0x07120204 +#define RIO_PORT_N_CTL_CSR(x) (0x005c + x*0x20) +#define RIO_PORT_N_CTL_PWIDTH 0xc0000000 +#define RIO_PORT_N_CTL_PWIDTH_1 0x00000000 +#define RIO_PORT_N_CTL_PWIDTH_4 0x40000000 +#define RIO_PORT_N_CTL_P_TYP_SER 0x00000001 +#define RIO_PORT_N_CTL_LOCKOUT 0x00000002 +#define RIO_PORT_N_CTL_EN_RX_SER 0x00200000 +#define RIO_PORT_N_CTL_EN_TX_SER 0x00400000 +#define RIO_PORT_N_CTL_EN_RX_PAR 0x08000000 +#define RIO_PORT_N_CTL_EN_TX_PAR 0x40000000 + +/* + * Error Management Extensions (RapidIO 1.3+, Part 8) + * + * Extended Features Block ID=0x0007 + */ + +/* General EM Registers (Common for all Ports) */ + +#define RIO_EM_EFB_HEADER 0x000 +#define RIO_EM_LTL_ERR_DETECT 0x008 +#define RIO_EM_LTL_ERR_EN 0x00c +#define RIO_EM_LTL_HIADDR_CAP 0x010 +#define RIO_EM_LTL_ADDR_CAP 0x014 +#define RIO_EM_LTL_DEVID_CAP 0x018 +#define RIO_EM_LTL_CTRL_CAP 0x01c +#define RIO_EM_PW_TGT_DEVID 0x028 +#define RIO_EM_PKT_TTL 0x02c + +/* Per-Port EM Registers */ + +#define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40) +#define REM_PED_IMPL_SPEC 0x80000000 +#define REM_PED_LINK_TO 0x00000001 +#define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) +#define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40) +#define RIO_EM_PN_PKT_CAP_0(x) (0x04c + x*0x40) +#define RIO_EM_PN_PKT_CAP_1(x) (0x050 + x*0x40) +#define RIO_EM_PN_PKT_CAP_2(x) (0x054 + x*0x40) +#define RIO_EM_PN_PKT_CAP_3(x) (0x058 + x*0x40) +#define RIO_EM_PN_ERRRATE(x) (0x068 + x*0x40) +#define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) + +/** + * rio_init - Initialize RapidIO subsystem + * @riohdid: RapidIO host device ID + * @riosize: RapidIO device ID size + * @rioports: bitmask of ports to configure + * @riopmode: path mode (lanes to ports mapping) + * @riobaudrate: link baudrate + * + * Returns riohandle on success or %NULL on failure. + */ +void *rio_init(int riohdid, + int riosize, + u32 rioports, + int riopmode, + int riobaudrate); + +/** + * rio_shutdown - Shutdown RapidIO subsystem + * @riohandle: RapidIO handle (returned by rio_init) + * + * Returns %0 on success or %-1 on failure. + */ +int rio_shutdown(void *riohandle); + +/** + * rio_config_read - Generate a RIO read maintenance transaction + * @portid: Output port ID of transaction + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Location to be read into + * + * Returns %0 on success or %-1 on failure. + */ +int rio_config_read(int portid, + u16 destid, + u8 hopcount, + u32 offset, + int len, + u32 *val); + +/** + * rio_config_write - Generate a RIO write maintenance transaction + * @portid: Output port ID of transaction + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Value to be written + * + * Returns %0 on success or %-1 on failure. + */ +int rio_config_write(int portid, + u16 destid, + u8 hopcount, + u32 offset, + int len, + u32 val); + +/** + * rio_local_config_read - RIO local config space read + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be read into + * + * Returns %0 on success or %-1 on failure. + */ +int rio_local_config_read(u32 offset, int len, u32 *data); + +/** + * rio_local_config_write - RIO local config space write + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be written + * + * Returns %0 on success or %-1 on failure. + */ +int rio_local_config_write(u32 offset, int len, u32 data); + +#endif /* _RIO_H_ */ -- 1.6.2.1

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[U-Boot] [PATCH 1/4] cmd_mem.c: add a memory wait (mwait) command
by jacquiot.aurelien＠gmail.com 04 Jan '16

04 Jan '16

From: Aurelien Jacquiot <a-jacquiot(a)ti.com> This new memory command allows to wait a given value in memory. It can be useful when U-Boot is used in a slave mode (another device is pushing images to the local memory) such as RapidIO or any RDMA kind of transport. We can then be notified that images have been loaded to our memory before booting. Usage is: mwait[.b, .w, .l, .q] address value Signed-off-by: Aurelien Jacquiot <a-jacquiot(a)ti.com> --- common/cmd_mem.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 69 insertions(+), 0 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 43c3fb6..af6e39d 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1238,6 +1238,65 @@ static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif +static int +do_mem_mwait(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr; +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + u64 val, readval; +#else + ulong val, readval; +#endif + int size; + + if (argc != 3) + return CMD_RET_USAGE; + + /* check for size specification */ + size = cmd_get_data_size(argv[0], 4); + if (size < 1) + return 1; + + /* first arg: address */ + addr = simple_strtoul(argv[1], NULL, 16); + + /* second arg: expected value */ +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + val = simple_strtoull(argv[2], NULL, 16); + printf("waiting 0x%llx at 0x%lx...\n", val, addr); +#else + val = simple_strtoul(argv[2], NULL, 16); + printf("waiting 0x%lx at 0x%lx...\n", val, addr); +#endif + + for (;;) { + if (size == 4) + readval = *((u32 *)addr); +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + else if (size == 8) + readval = *((u64 *)addr); +#endif + else if (size == 2) + readval = *((u16 *)addr); + else + readval = *((u8 *)addr); + + if (readval == val) + return 0; + + /* check for ctrl-c to abort... */ + if (ctrlc()) { + puts("Abort\n"); + return 0; + } + + WATCHDOG_RESET(); + udelay(1000); + } + + return 0; +} + /**************************************************/ U_BOOT_CMD( md, 3, 1, do_mem_md, @@ -1399,6 +1458,16 @@ U_BOOT_CMD( ); #endif /* CONFIG_MX_CYCLIC */ +U_BOOT_CMD( + mwait, 3, 1, do_mem_mwait, + "memory wait for value", +#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA + "[.b, .w, .l, .q] address value\n" +#else + "[.b, .w, .l] address value\n" +#endif +); + #ifdef CONFIG_CMD_MEMINFO U_BOOT_CMD( meminfo, 3, 1, do_mem_info, -- 1.6.2.1

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 04 Jan '16

04 Jan '16

The following changes since commit 78680314c53a95c0bb25e942662979843b60d7b9: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-12-27 09:15:57 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to f3643fe7d0dcd8a799fe8882db0903b3477e6338: usb: musb: Fix hub port setting for SPLIT transactions (2015-12-31 10:05:32 +0100) ---------------------------------------------------------------- Stefan Brüns (4): usb: Alloc buffer for USB descriptor dynamically usb: dwc2: avoid out of bounds access usb: Move determination of TT hub address/port into separate function usb: musb: Fix hub port setting for SPLIT transactions common/usb.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------- drivers/usb/host/dwc2.c | 7 ++++--- drivers/usb/host/ehci-hcd.c | 50 +++++--------------------------------------------- drivers/usb/musb-new/musb_host.c | 10 +++++++--- drivers/usb/musb-new/usb-compat.h | 53 ----------------------------------------------------- include/usb.h | 17 +++++++++++++++-- 6 files changed, 115 insertions(+), 120 deletions(-)

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