December 2015 - U-Boot

[U-Boot] [PATCH 1/2] nios2: rename board nios2-generic to 3c120_devboard
by Thomas Chou 06 Jan '16

06 Jan '16

Rename board nios2-generic to 3c120_devboard. Since nios2 is converted to driver model and device tree control of u-boot, the nios2-generic board directory is removed. We can rename the board back to a real board name. Now the boards maintained in u-boot mainline are the same as Linux kernel, namely 3c120 and 10m50. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- configs/3c120_defconfig | 27 ++++++++++ configs/nios2-generic_defconfig | 27 ---------- doc/README.nios2 | 8 +-- include/configs/3c120_devboard.h | 107 +++++++++++++++++++++++++++++++++++++++ include/configs/nios2-generic.h | 107 --------------------------------------- 5 files changed, 138 insertions(+), 138 deletions(-) create mode 100644 configs/3c120_defconfig delete mode 100644 configs/nios2-generic_defconfig create mode 100644 include/configs/3c120_devboard.h delete mode 100644 include/configs/nios2-generic.h diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig new file mode 100644 index 0000000..736119e --- /dev/null +++ b/configs/3c120_defconfig @@ -0,0 +1,27 @@ +CONFIG_NIOS2=y +CONFIG_SYS_CONFIG_NAME="3c120_devboard" +CONFIG_DM_SERIAL=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_ITEST is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ALTERA_PIO=y +CONFIG_MISC=y +CONFIG_ALTERA_SYSID=y +CONFIG_MTD=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_ALTERA_TSE=y +CONFIG_ALTERA_JTAG_UART=y +CONFIG_ALTERA_JTAG_UART_BYPASS=y +CONFIG_TIMER=y +CONFIG_ALTERA_TIMER=y diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig deleted file mode 100644 index 0a6de6f..0000000 --- a/configs/nios2-generic_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_NIOS2=y -CONFIG_SYS_CONFIG_NAME="nios2-generic" -CONFIG_DM_SERIAL=y -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" -CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ITEST is not set -CONFIG_CMD_DHCP=y -# CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_ALTERA_PIO=y -CONFIG_MISC=y -CONFIG_ALTERA_SYSID=y -CONFIG_MTD=y -CONFIG_CFI_FLASH=y -CONFIG_DM_ETH=y -CONFIG_ALTERA_TSE=y -CONFIG_ALTERA_JTAG_UART=y -CONFIG_ALTERA_JTAG_UART_BYPASS=y -CONFIG_TIMER=y -CONFIG_ALTERA_TIMER=y diff --git a/doc/README.nios2 b/doc/README.nios2 index 2dab7d1..a33c4e8 100644 --- a/doc/README.nios2 +++ b/doc/README.nios2 @@ -45,9 +45,9 @@ the sequence of these devices, like this, }; Next, you will need a default config file. You may start with -nios2-generic_defconfig, modify the options and save it. +3c120_defconfig, modify the options and save it. -$ make nios2-generic_defconfig +$ make 3c120_defconfig $ make menuconfig $ make savedefconfig $ cp defconfig configs/mysystem_defconfig @@ -72,9 +72,9 @@ copies all the u-boot-dtb.bin, not just u-boot.bin. binary. This is handy for development, eg, using gdb or nios2-download. The last thing, legacy board header file describes those config options -not covered in Kconfig yet. You may copy it from nios2-generic.h. +not covered in Kconfig yet. You may copy it from 3c120_devboard.h. -$ cp include/configs/nios2-generic.h include/configs/mysystem.h +$ cp include/configs/3c120_devboard.h include/configs/mysystem.h Please change the SDRAM base and size to match your board. The base should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h new file mode 100644 index 0000000..856c836 --- /dev/null +++ b/include/configs/3c120_devboard.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * SERIAL + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ + +/* + * CFI Flash + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* + * NET options + */ +#define CONFIG_SYS_RX_ETH_BUFFER 0 +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHY_MARVELL + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * FDT options + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR 0xe2840000 + +/* + * MEMORY ORGANIZATION + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). + */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN 0x20000 + +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ + CONFIG_ENV_SIZE - \ + CONFIG_SYS_MALLOC_LEN - \ + 0x10000) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_GPIO + +#endif /* __CONFIG_H */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h deleted file mode 100644 index 856c836..0000000 --- a/include/configs/nios2-generic.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * BOARD/CPU - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO_LATE - -/* - * SERIAL - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ - -/* - * CFI Flash - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * NET options - */ -#define CONFIG_SYS_RX_ETH_BUFFER 0 -#define CONFIG_CMD_MII -#define CONFIG_PHY_GIGE -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_PHY_MARVELL - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * FDT options - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_LMB - -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ -#define CONFIG_ENV_IS_IN_FLASH - -#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR 0xe2840000 - -/* - * MEMORY ORGANIZATION - * -Monitor at top of sdram. - * -The heap is placed below the monitor - * -The stack is placed below the heap (&grows down). - */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 - -/* - * MISC - */ -#define CONFIG_SYS_LONGHELP /* Provide extended help */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + \ - 16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_ENV_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - 0x10000) -#define CONFIG_CMDLINE_EDITING -#define CONFIG_CMD_GPIO - -#endif /* __CONFIG_H */ -- 2.5.0

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[U-Boot] Pull request: u-boot-spi/next
by Jagan Teki 06 Jan '16

06 Jan '16

Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 312db9f75f50b339310474d72c8524cef2bd7931: armv7: omap-common: Rework SPL board_mmc_init() (2015-12-14 13:42:54 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 25aade812e40f2e869575199c64e35ebcdf5554b: defconfig: am437x_sk_evm: enable spi driver model (2015-12-29 13:27:46 +0530) ---------------------------------------------------------------- Jagan Teki (24): sf: Get spi locally from spi_flash spi: make mode visible to both dm and non-dm spi: Use mode instead of op_mode_tx spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUAD sf: Move spi_read_cmds_array locally sf: Rename spi_flash_set_* functions sf: Rename bank_end to bar_end in read_bar sf: Remove spi_flash_remove sf: Minor cleanup sf: Use BIT macro sf: Fix quad bit set for micron devices sf: Read back and check once spansion quad bit set sf: Read back and check once macronix quad bit set sf: Write quad bit along with read status spi: Remove SPI_OPM_RX_EXTN spi: Remove SPI_OPM_RX_DIO|QIOF spi: Rename SPI_OPM_RX_* to SPI_RX_* spi: Rename op_mode_rx to mode_rx spi: Move flags macro's to spi_slave{} members spi: Fix bit assignment with flags spi: Use BIT macro spi: Minor cleanup sf: Make IO modes at last in read modes spi: Add SPI_TX_DUAL mode Mugunthan V N (17): drivers: spi: ti_qspi: do not hard code chip select for memory map configuration drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion drivers: spi: ti_qspi: prepare driver for DM conversion dm: core: Add a new api to get indexed device address spi: Add support for dual and quad mode dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl dts: dra7: add spi alias for qspi drivers: spi: ti_qspi: convert driver to adopt device driver model arm: dts: dra7: add qspi register maps for memory map and control module arm: dts: am437x-gp-evm: add spi-flash comaptible for flash arm: dts: dra7-evm: add spi-flash comaptible for flash arm: dts: dra72-evm: add spi-flash comaptible for flash defconfig: dra72_evm: enable spi driver model defconfig: dra74_evm: enable spi driver model am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl arm: dts: am4372: add qspi register maps for memory map defconfig: am437x_sk_evm: enable spi driver model arch/arm/dts/am4372.dtsi | 5 +- arch/arm/dts/am437x-sk-evm.dts | 2 +- arch/arm/dts/dra7-evm.dts | 2 +- arch/arm/dts/dra7.dtsi | 8 +- arch/arm/dts/dra72-evm.dts | 2 +- configs/am437x_sk_evm_defconfig | 3 + configs/dra72_evm_defconfig | 2 + configs/dra74_evm_defconfig | 2 + drivers/core/device.c | 31 ++- drivers/mtd/spi/sf-uclass.c | 7 +- drivers/mtd/spi/sf_internal.h | 55 +++-- drivers/mtd/spi/sf_probe.c | 2 +- drivers/mtd/spi/spi_flash.c | 185 +++++++++----- drivers/spi/ich.c | 4 +- drivers/spi/spi-uclass.c | 38 ++- drivers/spi/ti_qspi.c | 524 ++++++++++++++++++++++++++++------------ include/configs/am43xx_evm.h | 2 + include/configs/dra7xx_evm.h | 5 + include/dm/device.h | 11 + include/spi.h | 75 +++--- include/spi_flash.h | 2 - 21 files changed, 667 insertions(+), 300 deletions(-)

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[U-Boot] [PATCH v2 0/6] add dma uclass implementation and adopt ti-edma3 to it
by Mugunthan V N 06 Jan '16

06 Jan '16

this patch series enables adds support for dma driver model and to adopt driver model. this has been tested on am437x-sk evms (logs [1]). also pushed a branch for testing [2] [1]: http://pastebin.ubuntu.com/14167595/ [2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-dma-v2 changes from initial->v2: * changed config_dm_dma to config_dma. * removed un-wanted enums. * added dma_get_device(). * removed post_bind in uclass driver and added device_probe in dma_get_device() Mugunthan V N (6): dm: implement a DMA uclass dma: Kconfig: Add TI_EDMA3 entry sf: spi_flash: use dma to copy data from mmap region if platform supports spi: ti_qspi: compile out spi_flash_copy_mmap when CONFIG_DMA is defined drivers: dma: ti-edma3: convert driver to adopt driver model defconfig: am437x_sk_evm: enable dma driver model configs/am437x_sk_evm_defconfig | 1 + drivers/dma/Kconfig | 22 +++++++++++ drivers/dma/Makefile | 2 + drivers/dma/dma-uclass.c | 78 +++++++++++++++++++++++++++++++++++++++ drivers/dma/ti-edma3.c | 74 ++++++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi_flash.c | 9 +++++ drivers/spi/ti_qspi.c | 2 +- include/dm/uclass-id.h | 1 + include/dma.h | 81 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 267 insertions(+), 3 deletions(-) create mode 100644 drivers/dma/dma-uclass.c create mode 100644 include/dma.h -- 2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC
by Wills Wang 06 Jan '16

06 Jan '16

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v3: None Changes in v2: None drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 274 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 275 insertions(+) create mode 100644 drivers/serial/serial_ar933x.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..9a7ad89 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c new file mode 100644 index 0000000..6c0d726 --- /dev/null +++ b/drivers/serial/serial_ar933x.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <serial.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> +#include <asm/arch/ar933x_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct ar933x_serial_baudrate{ + u32 baudrate; + u32 scale; + u32 step; +}; + +const struct ar933x_serial_baudrate baudrate_table_40mhz[] = { +/* baudrate, scale, step */ + {600, 255, 503}, + {1200, 249, 983}, + {2400, 167, 1321}, + {4800, 87, 1384}, + {9600, 45, 1447}, + {14400, 53, 2548}, + {19200, 22, 1447}, + {28800, 26, 2548}, + {38400, 28, 3649}, + {56000, 7, 1468}, + {57600, 34, 6606}, + {115200, 28, 10947}, + {128000, 6, 2936}, + {153600, 18, 9563}, + {230400, 16, 12834}, + {250000, 4, 4096}, + {256000, 6, 5872}, + {460800, 7, 12079}, + {576000, 4, 9437}, + {921600, 3, 12079}, + {1000000, 2, 9830}, + {1152000, 2, 11324}, + {1500000, 0, 4915}, + {2000000, 0, 6553}, + }; + +const struct ar933x_serial_baudrate baudrate_table_25mhz[] = { +/* baudrate, scale, step */ + {600, 255, 805}, + {1200, 209, 1321}, + {2400, 104, 1321}, + {4800, 54, 1384}, + {9600, 78, 3976}, + {14400, 98, 7474}, + {19200, 55, 5637}, + {28800, 77, 11777}, + {38400, 36, 7449}, + {56000, 4, 1468}, + {57600, 35, 10871}, + {115200, 20, 12683}, + {128000, 11, 8053}, + {153600, 9, 8053}, + {230400, 9, 12079}, + {250000, 6, 9175}, + {256000, 5, 8053}, + {460800, 4, 12079}, + {576000, 3, 12079}, + {921600, 1, 9663}, + {1000000, 1, 10485}, + {1152000, 1, 12079}, + {1500000, 0, 7864}, + {2000000, 0, 10485}, +}; + +static inline u32 ar933x_read(u32 base, u32 offset) +{ + return readl(KSEG1ADDR(base + offset)); +} + +static inline void ar933x_write(u32 base, u32 offset, u32 val) +{ + writel(val, KSEG1ADDR(base + offset)); +} + +static int ar933x_serial_init(void) +{ + u32 val; + + /* + * Set GPIO10 (UART_SO) as output and enable UART, + * BIT(15) in GPIO_FUNCTION_1 register must be written with 1 + */ + val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE); + val |= BIT(10); + ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val); + + val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC); + val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15)); + ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val); + + /* + * UART controller configuration: + * - no DMA + * - no interrupt + * - DCE mode + * - no flow control + * - set RX ready oride + * - set TX ready oride + */ + val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE + | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S); + ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val); + return 0; +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_setbrg(struct udevice *dev, int baudrate) +{ +#else +static void ar933x_serial_setbrg(void) +{ + int baudrate = gd->baudrate; +#endif + u32 val, scale, step; + const struct ar933x_serial_baudrate *baudrate_table; + int i, baudrate_table_size; + + val = ar933x_read(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP); + if (val & AR933X_BOOTSTRAP_REF_CLK_40) { + baudrate_table = baudrate_table_40mhz; + baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz); + scale = (40000000 / (16 * baudrate)) - 1; + step = 8192; + } else { + baudrate_table = baudrate_table_25mhz; + baudrate_table_size = ARRAY_SIZE(baudrate_table_25mhz); + scale = (25000000 / (16 * baudrate)) - 1; + step = 8192; + } + + for (i = 0; i < baudrate_table_size; i++) { + if (baudrate_table[i].baudrate == gd->baudrate) { + scale = baudrate_table[i].scale; + step = baudrate_table[i].step; + } + } + + val = ((scale & AR933X_UART_CLOCK_SCALE_M) + << AR933X_UART_CLOCK_SCALE_S); + val |= ((step & AR933X_UART_CLOCK_STEP_M) + << AR933X_UART_CLOCK_STEP_S); + ar933x_write(AR933X_UART_BASE, AR933X_UART_CLOCK_REG, val); +#ifdef CONFIG_DM_SERIAL + return 0; +#endif +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_putc(struct udevice *dev, const char c) +#else +static void ar933x_serial_putc(const char c) +#endif +{ + u32 data; + + if (c == '\n') +#ifdef CONFIG_DM_SERIAL + ar933x_serial_putc(dev, '\r'); +#else + ar933x_serial_putc('\r'); +#endif + do { + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_TX_CSR)); + + data = (u32)c | AR933X_UART_DATA_TX_CSR; + ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, data); +#ifdef CONFIG_DM_SERIAL + return 0; +#endif +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_getc(struct udevice *dev) +#else +static int ar933x_serial_getc(void) +#endif +{ + u32 data; + + do { + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_RX_CSR)); + + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR); + return data & AR933X_UART_DATA_TX_RX_MASK; +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_pending(struct udevice *dev, bool input) +{ + u32 data; + + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + if (input) + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; + else + return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1; +} + +static int ar933x_serial_probe(struct udevice *dev) +{ + ar933x_serial_init(); + return 0; +} + +static const struct dm_serial_ops ar933x_serial_ops = { + .putc = ar933x_serial_putc, + .pending = ar933x_serial_pending, + .getc = ar933x_serial_getc, + .setbrg = ar933x_serial_setbrg, +}; + +static const struct udevice_id ar933x_serial_ids[] = { + { .compatible = "ath79,ar933x-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_ar933x) = { + .name = "serial_ar933x", + .id = UCLASS_SERIAL, + .of_match = ar933x_serial_ids, + .probe = ar933x_serial_probe, + .ops = &ar933x_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#else +static int ar933x_serial_tstc(void) +{ + u32 data; + + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; +} + +static struct serial_device ar933x_serial_drv = { + .name = "ar933x_serial", + .start = ar933x_serial_init, + .stop = NULL, + .setbrg = ar933x_serial_setbrg, + .putc = ar933x_serial_putc, + .puts = default_serial_puts, + .getc = ar933x_serial_getc, + .tstc = ar933x_serial_tstc, +}; + +void ar933x_serial_initialize(void) +{ + serial_register(&ar933x_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &ar933x_serial_drv; +} +#endif -- 1.9.1

3 6

[U-Boot] [PATCH] powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC
by Bryan Hundven 05 Jan '16

05 Jan '16

As I work to re-add p1_p2_rdb, CONFIG_P2020RDB conflicts with p1_p2_rdb's CONFIG_P2020RDB. Rename p1_p2_rdb_pc's CONFIG_P2020RDB to CONFIG_P2020RDB_PC. Signed-off-by: Bryan Hundven <bryanhundven(a)gmail.com> Cc: Andy Fleming <afleming(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- board/freescale/p1_p2_rdb_pc/ddr.c | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 2 +- configs/P2020RDB-PC_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_defconfig | 2 +- include/configs/p1_p2_rdb_pc.h | 8 ++++---- 10 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 946d503..ef59b58 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -49,7 +49,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P2020RDB) +#elif defined(CONFIG_P2020RDB_PC) /* Micron MT41J128M16_15E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 578bfc5..c7bb971 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -3,7 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,NAND" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 19c795a..c79399e 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SDCARD" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index bdc5e43..898993f 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b9d4a47..16af720 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index ea9f830..19ec9d2 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -3,7 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,NAND" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 997887d..ee0fd33 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SDCARD" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index e547ea4..40190c4 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SPIFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index fdad880..6629285 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 60bedaa..e64805a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -154,7 +154,7 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_P2020RDB_PC) #define CONFIG_BOARDNAME "P2020RDB-PCA" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P2020 @@ -323,7 +323,7 @@ #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_P2020RDB_PC) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -382,7 +382,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_P2020RDB_PC #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -618,7 +618,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_P2020RDB_PC) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) -- 2.5.0

4 7

[U-Boot] [PATCH V3] usb:ci_udc: Remove ULPI setting for i.MX OTG controller
by Peng Fan 05 Jan '16

05 Jan '16

From: "Ye.Li" <B37916(a)freescale.com> All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface. Set to ULPI is not correct, even the controller will reject this setting in PORTSC register. Signed-off-by: Ye.Li <B37916(a)freescale.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- Hi Marek, In V2: https://patchwork.ozlabs.org/patch/541663/ The reason still use DBG, but not change to debug, is that the driver use DBG for debugging and error handling usage. So In this patch, I still keep DBG. If you think, it better to switch to use function debug, I can write another patch to convert all the DBGs to debug for ci_udc driver. Regards, Peng. Changes since v2: - Correct code indent. Changes since v1: - Add error handling for udc probe drivers/usb/gadget/ci_udc.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 1ba5054..d36bcf6 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -1018,18 +1018,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) return ret; ret = ci_udc_probe(); -#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) - /* - * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all - * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection - */ - if (!ret) { - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + if (ret) { + DBG("udc probe failed, returned %d\n", ret); + return ret; } -#endif ret = driver->bind(&controller.gadget); if (ret) { -- 2.6.2

3 4

[U-Boot] [RFC PATCH 1/2] common: Add new clk command
by Michal Simek 05 Jan '16

05 Jan '16

Command provides just dump subcommand for showing clock frequencies in a soc. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- README | 1 + common/Makefile | 1 + common/cmd_clk.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++ include/clk.h | 6 ++++++ include/config_cmd_all.h | 1 + 5 files changed, 60 insertions(+) create mode 100644 common/cmd_clk.c create mode 100644 include/clk.h diff --git a/README b/README index aea82be..0087649 100644 --- a/README +++ b/README @@ -887,6 +887,7 @@ The following options need to be configured: CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... diff --git a/common/Makefile b/common/Makefile index d12cba5..a000e7d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff --git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644 index 0000000..6d3d46a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <clk.h> + +int __weak soc_clk_dump(void) +{ + puts("Not implemented\n"); + return 1; +} + +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + return soc_clk_dump(); +} + +static cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""), +}; + +static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return CMD_RET_USAGE; + + /* Strip off leading 'clk' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +#ifdef CONFIG_SYS_LONGHELP +static char clk_help_text[] = + "dump - Print clock frequencies"; +#endif + +U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text); diff --git a/include/clk.h b/include/clk.h new file mode 100644 index 0000000..df4570c --- /dev/null +++ b/include/clk.h @@ -0,0 +1,6 @@ +#ifndef _CLK_H_ +#define _CLK_H_ + +int soc_clk_dump(void); + +#endif /* _CLK_H_ */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d847069..3e8983f 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CLK /* Clock support */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ -- 1.8.2.3

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[U-Boot] [PATCH V2] common: nvedit: use snprintf instead of sprintf
by Peng Fan 04 Jan '16

04 Jan '16

From: Peng Fan <peng.fan(a)nxp.com> Use snprintf to replace sprintf. Coverity log: " Unbounded source buffer (STRING_SIZE) string_size: Passing string init_val of unknown size to sprintf. " Reported-by: Coverity Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger(a)ni.com> --- common/cmd_nvedit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index f4c2523..3d295d1 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -594,7 +594,7 @@ static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, /* Set read buffer to initial value or empty sting */ init_val = getenv(argv[1]); if (init_val) - sprintf(buffer, "%s", init_val); + snprintf(buffer, CONFIG_SYS_CBSIZE, "%s", init_val); else buffer[0] = '\0'; -- 2.6.2

2 1

[U-Boot] [PATCH V2] common: env: initialize scalar variable
by Peng Fan 04 Jan '16

04 Jan '16

From: Peng Fan <peng.fan(a)nxp.com> Before calling hsearch_r, initialize callback entry to NULL. Coverity log: " Uninitialized scalar variable (UNINIT) uninit_use_in_call: Using uninitialized value e. Field e.callback is uninitialized when calling hsearch_r. " Reported-by: Coverity Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- common/env_callback.c | 1 + common/env_flags.c | 1 + 2 files changed, 2 insertions(+) diff --git a/common/env_callback.c b/common/env_callback.c index f4d3dbd..1957cc1 100644 --- a/common/env_callback.c +++ b/common/env_callback.c @@ -97,6 +97,7 @@ static int set_callback(const char *name, const char *value, void *priv) e.key = name; e.data = NULL; + e.callback = NULL; hsearch_r(e, FIND, &ep, &env_htab, 0); /* does the env variable actually exist? */ diff --git a/common/env_flags.c b/common/env_flags.c index e682d85..7719355 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -455,6 +455,7 @@ static int set_flags(const char *name, const char *value, void *priv) e.key = name; e.data = NULL; + e.callback = NULL; hsearch_r(e, FIND, &ep, &env_htab, 0); /* does the env variable actually exist? */ -- 2.6.2

2 1

[U-Boot] [PATCH 1/1] common: cli: avoid memory leak
by Peng Fan 04 Jan '16

04 Jan '16

From: Peng Fan <peng.fan(a)nxp.com> Whether CONFIG_SYS_HUSH_PARSER is defined or not, should always check to free 'buff' to avoid memory leak. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Simon Glass <sjg(a)chromium.org> --- common/cli.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cli.c b/common/cli.c index fbcd339..119d282 100644 --- a/common/cli.c +++ b/common/cli.c @@ -103,9 +103,9 @@ int run_command_list(const char *cmd, int len, int flag) * is pretty rare. */ rcode = cli_simple_run_command_list(buff, flag); +#endif if (need_buff) free(buff); -#endif return rcode; } -- 2.6.2

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