December 2015 - U-Boot

[U-Boot] [PATCH V2] arm: novena: Switch novena to config_distro_bootcmd
by Marek Vasut 29 Dec '15

29 Dec '15

From: Vagrant Cascadian <vagrant(a)aikidev.net> Switch Novena to distro bootcmd, so it can be used with debian easily. Signed-off-by: Vagrant Cascadian <vagrant(a)aikidev.net> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Sean Cross <xobs(a)kosagi.com> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/novena.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) V2: Add fdtfile to specify the device tree blob. Fix fdt_addr_r to point past kernel address. diff --git a/include/configs/novena.h b/include/configs/novena.h index 718989f..fc953f6 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -16,6 +16,7 @@ #define CONFIG_FIT #define CONFIG_KEYBOARD +#include <config_distro_defaults.h> #include "mx6_common.h" /* U-Boot Commands */ @@ -58,7 +59,7 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttymxc1,115200 " -#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run net_nfs" #define CONFIG_HOSTNAME novena /* Physical Memory Map */ @@ -190,6 +191,7 @@ #endif /* Extra U-Boot environment. */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -199,6 +201,11 @@ "rootdev=/dev/mmcblk0p2\0" \ "netdev=eth0\0" \ "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "ramdisk_addr_r=0x28000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdtfile=imx6q-novena.dtb\0" \ "addcons=" \ "setenv bootargs ${bootargs} " \ "console=${consdev},${baudrate}\0" \ @@ -242,5 +249,19 @@ "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ "fi ; " \ "fi\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(SATA, sata, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#else +#define CONFIG_EXTRA_ENV_SETTINGS +#endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_H */ -- 2.1.4

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[U-Boot] [PATCH v5 0/5] add support for atheros ath79 based SOCs
by Wills Wang 29 Dec '15

29 Dec '15

These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x chip. Changes in v5: - Add independent Kconfig - Use SRAM for initial stack - Move DDR initialization into board_early_init_f - Convert DDR tap tunning code to C - Save SOC's version into arch_global_data - remove ar933x_serial_platdata - Import document "qca,ar9330-uart.txt" from kernel - Add support for debug UART - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation - Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk - Remove useless README file - Remove useless checkboard function Changes in v4: - Use global_data to save CPU/DDR/AHB clock - Use arch_global_data to save SOC's type, revison and id - Auto calculate baudrate for serial driver - Move pinctrl code in serial driver into arch/mips/mach-ath79 - Use get_serial_clock to serial clock source - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Move SoC specific header files into arch/mips/mach-ath79/include/mach - Optimize assembly code - Same code style convertion - Convert serial driver to driver model - Same code style convertion - Convert spi driver to driver model - Same code style convertion - Add support for device tree Changes in v2: - Move all SoC specific header files into arch/mips/include/asm/arch-ath79 - Check SOC type and extract common code into arch/mips/mach-ath79 - Move serial driver code into drivers/serial - Add a compatible spi driver - Add a reference board implemention Wills Wang (5): mips: implement to access the KSEG0/1 memory range in map_physmem mips: add support for QCA/Atheros ath79 SOCs mips: ath79: add serial driver for ar933x SOC mips: ath79: add spi driver mips: ath79: add AP121 reference board arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/dts/Makefile | 2 +- arch/mips/dts/ap121.dts | 37 + arch/mips/dts/ar933x.dtsi | 64 ++ arch/mips/include/asm/global_data.h | 6 + arch/mips/include/asm/io.h | 7 +- arch/mips/mach-ath79/Kconfig | 22 + arch/mips/mach-ath79/Makefile | 9 + arch/mips/mach-ath79/ar933x/Makefile | 8 + arch/mips/mach-ath79/ar933x/board.c | 42 + arch/mips/mach-ath79/ar933x/clk.c | 86 ++ arch/mips/mach-ath79/ar933x/ddr.c | 215 ++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 286 +++++ arch/mips/mach-ath79/cpu.c | 173 +++ arch/mips/mach-ath79/dram.c | 17 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1136 ++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 14 + arch/mips/mach-ath79/reset.c | 46 + board/ath79/ap121/Kconfig | 9 + board/ath79/ap121/MAINTAINERS | 6 + board/ath79/ap121/Makefile | 8 + board/ath79/ap121/ap121.c | 6 + configs/ap121_defconfig | 40 + .../serial/qca,ar9330-uart.txt | 24 + doc/device-tree-bindings/spi/spi-ath79.txt | 19 + drivers/serial/Kconfig | 17 + drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 259 +++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 210 ++++ include/configs/ap121.h | 86 ++ 34 files changed, 3011 insertions(+), 3 deletions(-) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 arch/mips/mach-ath79/Kconfig create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/board.c create mode 100644 arch/mips/mach-ath79/ar933x/clk.c create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/reset.c create mode 100644 board/ath79/ap121/Kconfig create mode 100644 board/ath79/ap121/MAINTAINERS create mode 100644 board/ath79/ap121/Makefile create mode 100644 board/ath79/ap121/ap121.c create mode 100644 configs/ap121_defconfig create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/serial/serial_ar933x.c create mode 100644 drivers/spi/ath79_spi.c create mode 100644 include/configs/ap121.h -- 1.9.1

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[U-Boot] [PATCH v2 0/8] x86: qemu: add fw_cfg interface support for qemu-x86 targets
by Miao Yan 29 Dec '15

29 Dec '15

The fw_cfg interface provided by QEMU allow guests to retrieve various information about the system, e.g. cpu number, variaous firmware data, kernel setup, etc. The fw_cfg interface can be accessed through 3 IO ports (on x86), using x86 in/out instructions. - 0x510: select configuration items to access - 0x511: reading this port will return data selected in 0x510 - 0x514: this can be used to detect if DMA interface is available If fw_cfg DMA interface is available, it can be used to accelerate accesses. This patchset adds the following supports for qemu-x86 targets: + the fw_cfg driver itself + add a U-Boot command 'fw' to support direct accessing kernel informtion from fw_cfg interface, this saves the time of loading them from hard disk or network again, through emulated devices. + use fw_cfg to get cpu number at runtime, so smp boot no longer relies on the cpu node hard-coded in dts files. Changes in v2: - rebase to u-boot-x86/next - various cleanups Miao Yan (8): x86: qemu: add fw_cfg support x86: qemu: add a cpu uclass driver for qemu target x86: fix a typo in function name x86: use actual CPU number for allocating memory x86: qemu: add qemu_fwcfg_fdt_fixup() x86: qemu: fix up cpu node in device tree x86: reserve more spaces for dtb x86: qemu: add documentaion for the fw_cfg interface arch/x86/cpu/mp_init.c | 12 +- arch/x86/cpu/qemu/Makefile | 2 +- arch/x86/cpu/qemu/cpu.c | 57 ++++++++ arch/x86/cpu/qemu/fw_cfg.c | 306 +++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/qemu/fw_cfg.h | 108 ++++++++++++++ arch/x86/cpu/qemu/qemu.c | 7 + arch/x86/dts/Makefile | 2 +- arch/x86/dts/qemu-x86_i440fx.dts | 19 +-- arch/x86/dts/qemu-x86_q35.dts | 19 +-- doc/README.x86 | 36 ++++- 10 files changed, 521 insertions(+), 47 deletions(-) create mode 100644 arch/x86/cpu/qemu/cpu.c create mode 100644 arch/x86/cpu/qemu/fw_cfg.c create mode 100644 arch/x86/cpu/qemu/fw_cfg.h -- 1.9.1

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Re: [U-Boot] [PATCH 2/3] armv8/ls1043aqds: add QSPI support in SD boot
by Scott Wood 29 Dec '15

29 Dec '15

On Thu, 2015-12-24 at 16:40 +0800, Gong Qianyu wrote: > From: Gong Qianyu <Qianyu.Gong(a)freescale.com> > > QSPI and IFC are pin-multiplexed on LS1043A. So we use > ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and > ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot. If > QSPI is enabled, IFC should be disabled in kernel as well. > > Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> > Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> > --- > arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 5 +++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +++ > arch/arm/dts/fsl-ls1043a-qds.dts | 14 +++++++++++++ > arch/arm/dts/fsl-ls1043a.dtsi | 11 +++++++++++ > board/freescale/ls1043aqds/MAINTAINERS | 1 + > .../ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg | 8 ++++++++ > configs/ls1043aqds_sdcard_qspi_defconfig | 10 ++++++++++ > include/configs/ls1043a_common.h | 13 ++++++++++++ > include/configs/ls1043aqds.h | 23 > ++++++++++++++++++++++ > 9 files changed, 88 insertions(+) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c > b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c > index eafdd71..a247510 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c > @@ -201,4 +201,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) > #ifdef CONFIG_FSL_LSCH3 > fdt_fixup_smmu(blob); > #endif > + > +#ifdef CONFIG_FSL_QSPI > + do_fixup_by_compat(blob, "fsl,ifc", > + "status", "disabled", 8 + 1, 1); > +#endif This needs to only happen on LS1043A (and any other chips that have the same muxing). > } > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > index 23d6b73..4b1f792 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > @@ -219,6 +219,9 @@ void fsl_lsch2_early_init_f(void) > init_early_memctl_regs(); /* tighten IFC timing */ > #endif > > +#ifdef CONFIG_FSL_QSPI > + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); > +#endif Likewise. -Scott

2 1

[U-Boot] [PATCH] net: gem: Build warning fixes for 64-bit
by Michal Simek 29 Dec '15

29 Dec '15

Cast pointers to unsigned long instead of a sized 32-bit type to avoid pointer to integer cast size mismatch warnings. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 045954a7b059..ee2c6b1f4579 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -347,13 +347,13 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) for (i = 0; i < RX_BUF; i++) { priv->rx_bd[i].status = 0xF0000000; priv->rx_bd[i].addr = - ((u32)(priv->rxbuffers) + + ((unsigned long)(priv->rxbuffers) + (i * PKTSIZE_ALIGN)); } /* WRAP bit to last BD */ priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; /* Write RxBDs to IP */ - writel((u32)priv->rx_bd, &regs->rxqbase); + writel((unsigned long)priv->rx_bd, &regs->rxqbase); /* Setup for DMA Configuration register */ writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr); @@ -378,8 +378,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + sizeof(dummy_rx_bd)); - writel((u32)dummy_tx_bd, &regs->transmit_q1_ptr); - writel((u32)dummy_rx_bd, &regs->receive_q1_ptr); + writel((unsigned long)dummy_tx_bd, &regs->transmit_q1_ptr); + writel((unsigned long)dummy_rx_bd, &regs->receive_q1_ptr); priv->init++; } @@ -458,7 +458,7 @@ static inline int wait_for_bit(const char *func, u32 *reg, const u32 mask, static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) { - u32 addr, size; + unsigned long addr, size; struct zynq_gem_priv *priv = dev->priv; struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; struct emac_bd *current_bd = &priv->tx_bd[1]; @@ -466,7 +466,7 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) /* Setup Tx BD */ memset(priv->tx_bd, 0, sizeof(struct emac_bd)); - priv->tx_bd->addr = (u32)ptr; + priv->tx_bd->addr = (unsigned long)ptr; priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | ZYNQ_GEM_TXBUF_LAST_MASK; /* Dummy descriptor to mark it as the last in descriptor chain */ @@ -476,14 +476,14 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) ZYNQ_GEM_TXBUF_USED_MASK; /* setup BD */ - writel((u32)priv->tx_bd, &regs->txqbase); + writel((unsigned long)priv->tx_bd, &regs->txqbase); - addr = (u32) ptr; + addr = (unsigned long)ptr; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); - addr = (u32)priv->rxbuffers; + addr = (unsigned long)priv->rxbuffers; addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); @@ -519,7 +519,7 @@ static int zynq_gem_recv(struct eth_device *dev) frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; if (frame_len) { - u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + unsigned long addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; addr &= ~(ARCH_DMA_MINALIGN - 1); net_process_received_packet((u8 *)addr, frame_len); @@ -601,7 +601,8 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; - priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); + priv->rx_bd = (struct emac_bd *)((unsigned long)bd_space + + BD_SEPRN_SPACE); priv->phyaddr = phy_addr; priv->emio = emio; -- 2.5.0

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[U-Boot] [PATCH 0/7] add fw_cfg interface support for qemu-x86 targets
by Miao Yan 29 Dec '15

29 Dec '15

The fw_cfg interface provided by QEMU allow guests to retrieve various information about the system, e.g. cpu number, variaous firmware data, kernel setup, etc. The fw_cfg interface can be accessed through 3 IO ports (on x86), using x86 in/out instructions. - 0x510: select configuration items to access - 0x511: reading this port will return data selected in 0x510 - 0x514: this can be used to detect if DMA interface is available If fw_cfg DMA interface is available, it can be used to accelerate accesses. This patchset adds the following supports for qemu-x86 targets: + the fw_cfg driver itself + add a U-Boot command 'fw' to support direct accessing kernel informtion from fw_cfg interface, this saves the time of loading them from hard disk or network again, through emulated devices. + use fw_cfg to get cpu number at runtime, so smp boot no longer relies on the cpu node hard-coded in dts files. Miao Yan (7): x86: qemu: add fw_cfg support x86: qemu: add a cpu uclass driver for qemu target x86: fix a typo in function name x86: qemu: use actual CPU number for allocating memory x86: qemu: add qemu_fwcfg_fdt_fixup() x86: qemu: fixup cpu node in device tree qemu-x86: add documentaion for the fw_cfg interface arch/x86/cpu/mp_init.c | 12 +- arch/x86/cpu/qemu/Makefile | 2 +- arch/x86/cpu/qemu/cpu.c | 58 ++++++++ arch/x86/cpu/qemu/fw_cfg.c | 281 +++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/qemu/fw_cfg.h | 85 ++++++++++++ arch/x86/cpu/qemu/qemu.c | 7 + arch/x86/dts/qemu-x86_i440fx.dts | 18 +-- arch/x86/dts/qemu-x86_q35.dts | 19 +-- doc/README.x86 | 36 ++++- 9 files changed, 473 insertions(+), 45 deletions(-) create mode 100644 arch/x86/cpu/qemu/cpu.c create mode 100644 arch/x86/cpu/qemu/fw_cfg.c create mode 100644 arch/x86/cpu/qemu/fw_cfg.h -- 1.9.1

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[U-Boot] [PATCH v2 00/10] spi: Cleanup set
by Jagan Teki 29 Dec '15

29 Dec '15

Cleanup set on spi_slave{} Changes for v2: - Replaced mode, mode_rx out-of structure members position - Added SPI_TX_DUAL patch Jagan Teki (10): spi: Remove SPI_OPM_RX_EXTN spi: Remove SPI_OPM_RX_DIO|QIOF spi: Rename SPI_OPM_RX_* to SPI_RX_* spi: Rename op_mode_rx to mode_rx spi: Move flags macro's to spi_slave{} members spi: Fix bit assignment with flags spi: Use BIT macro spi: Minor cleanup sf: Make IO modes at last in read modes spi: Add SPI_TX_DUAL mode drivers/mtd/spi/sf_internal.h | 4 +-- drivers/mtd/spi/spi_flash.c | 4 +-- drivers/spi/ich.c | 2 +- drivers/spi/ti_qspi.c | 2 +- include/spi.h | 65 ++++++++++++++++++++----------------------- 5 files changed, 36 insertions(+), 41 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] sf: Make IO modes at last in read modes
by Jagan Teki 29 Dec '15

29 Dec '15

SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Tested-by: Jagan Teki <jteki(a)openedev.com> Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- drivers/mtd/spi/sf_internal.h | 4 ++-- drivers/mtd/spi/spi_flash.c | 2 +- include/spi.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 55ba81e..007a5a0 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -25,8 +25,8 @@ enum spi_read_cmds { ARRAY_SLOW = BIT(0), ARRAY_FAST = BIT(1), DUAL_OUTPUT_FAST = BIT(2), - DUAL_IO_FAST = BIT(3), - QUAD_OUTPUT_FAST = BIT(4), + QUAD_OUTPUT_FAST = BIT(3), + DUAL_IO_FAST = BIT(4), QUAD_IO_FAST = BIT(5), }; diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 691be1a..e92f729 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -975,8 +975,8 @@ int spi_flash_scan(struct spi_flash *flash) CMD_READ_ARRAY_SLOW, CMD_READ_ARRAY_FAST, CMD_READ_DUAL_OUTPUT_FAST, - CMD_READ_DUAL_IO_FAST, CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, CMD_READ_QUAD_IO_FAST }; /* Read the ID codes */ diff --git a/include/spi.h b/include/spi.h index 803fb40..d09c901 100644 --- a/include/spi.h +++ b/include/spi.h @@ -105,7 +105,7 @@ struct spi_slave { #define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */ #define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */ #define SPI_RX_DUAL BIT(2) /* receive with 2 wires */ -#define SPI_RX_QUAD BIT(4) /* receive with 4 wires */ +#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */ unsigned int wordlen; unsigned int max_write_size; -- 1.9.1

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[U-Boot] [PATCH v1 07/18] board: Add Microchip PIC32MZ[DA] Starter Kit board.
by Purna Chandra Mandal 29 Dec '15

29 Dec '15

This adds support for Microchip PIC32MZ[DA] Starter Kit board based on a PIC32MZ[DA] family of microcontrollers. Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- arch/mips/dts/Makefile | 2 +- arch/mips/dts/pic32mzda_sk.dts | 38 ++++ arch/mips/mach-pic32/Kconfig | 7 + board/microchip/pic32mzda/Kconfig | 13 ++ board/microchip/pic32mzda/MAINTAINERS | 6 + board/microchip/pic32mzda/Makefile | 7 + board/microchip/pic32mzda/README | 22 ++ board/microchip/pic32mzda/config.mk | 4 + board/microchip/pic32mzda/ddr.c | 389 ++++++++++++++++++++++++++++++++++ board/microchip/pic32mzda/ddr.h | 46 ++++ board/microchip/pic32mzda/pic32mzda.c | 41 ++++ configs/pic32mzdask_defconfig | 22 ++ include/configs/pic32mzdask.h | 110 ++++++++++ 13 files changed, 706 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/pic32mzda_sk.dts create mode 100644 board/microchip/pic32mzda/Kconfig create mode 100644 board/microchip/pic32mzda/MAINTAINERS create mode 100644 board/microchip/pic32mzda/Makefile create mode 100644 board/microchip/pic32mzda/README create mode 100644 board/microchip/pic32mzda/config.mk create mode 100644 board/microchip/pic32mzda/ddr.c create mode 100644 board/microchip/pic32mzda/ddr.h create mode 100644 board/microchip/pic32mzda/pic32mzda.c create mode 100644 configs/pic32mzdask_defconfig create mode 100644 include/configs/pic32mzdask.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 724b5d2..b513918 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#dtb-$(CONFIG_XXX) += xxx.dtb +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts new file mode 100644 index 0000000..99e7f64 --- /dev/null +++ b/arch/mips/dts/pic32mzda_sk.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Purna Chandra Mandal, purna.mandal(a)microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "pic32mzda.dtsi" + +/ { + model = "Microchip PIC32MZDASK"; + compatible = "microchip,pic32mzdask", "microchip,pic32mzda"; + + aliases { + console = &uart2; + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clock { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig index 9983131..f82df37 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -24,6 +24,12 @@ endchoice choice prompt "Board select" +config TARGET_PIC32MZDASK + bool "Microchip PIC32MZ[DA] Starter Kit" + depends on SOC_PIC32MZDA + help + This supports Microchip PIC32MZ[DA] Starter Kit. + endchoice config PIC32_SUPPORTS_FDT_BOOT @@ -31,4 +37,5 @@ config PIC32_SUPPORTS_FDT_BOOT select MIPS_BOOT_FDT select MIPS_BOOT_CMDLINE_LEGACY +source "board/microchip/pic32mzda/Kconfig" endmenu diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig new file mode 100644 index 0000000..8acb393 --- /dev/null +++ b/board/microchip/pic32mzda/Kconfig @@ -0,0 +1,13 @@ + +if TARGET_PIC32MZDASK + +config SYS_BOARD + default "pic32mzda" + +config SYS_VENDOR + default "microchip" + +config SYS_CONFIG_NAME + default "pic32mzdask" + +endif diff --git a/board/microchip/pic32mzda/MAINTAINERS b/board/microchip/pic32mzda/MAINTAINERS new file mode 100644 index 0000000..c934f1a --- /dev/null +++ b/board/microchip/pic32mzda/MAINTAINERS @@ -0,0 +1,6 @@ +PIC32MZDASK BOARD +M: Purna Chandra Mandal <purna.mandal(a)microchip.com> +S: Maintained +F: board/microchip/pic32mzda/ +F: include/configs/pic32mzdask.h +F: configs/pic32mzdask_defconfig diff --git a/board/microchip/pic32mzda/Makefile b/board/microchip/pic32mzda/Makefile new file mode 100644 index 0000000..93733b4 --- /dev/null +++ b/board/microchip/pic32mzda/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal(a)microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := pic32mzda.o ddr.o diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README new file mode 100644 index 0000000..ccf6dcb --- /dev/null +++ b/board/microchip/pic32mzda/README @@ -0,0 +1,22 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + */ + +PIC32MZ[DA] Starter-Kit +---------------------------------------- +PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller. +This family is powered by MIPS M14KEC 32bit general purpose core with advanced +microcontroller features and peripherals. + +This processor boots with proprietary stage1 bootloader running from on-chip +boot-flash. Stage1 bootloader locates and jumps to U-Boot programmed on +another onchip program flash. Finally U-Boot locates and loads OS image +(along with other required files for booting) from either uSD card, or +ethernet, or from USB storage connected on-chip USB controller. + +To boot Linux following three files are mandatory - uEnv.txt (custom U-Boot +environment file), uImage, *.dtb (platform device-tree-blob file). + +U-Boot jumps to Linux using UHI specification. + +Visit http://microchip.com for details. diff --git a/board/microchip/pic32mzda/config.mk b/board/microchip/pic32mzda/config.mk new file mode 100644 index 0000000..a12e712 --- /dev/null +++ b/board/microchip/pic32mzda/config.mk @@ -0,0 +1,4 @@ +# +# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU) +# +CONFIG_SYS_TEXT_BASE = 0x9d004000 diff --git a/board/microchip/pic32mzda/ddr.c b/board/microchip/pic32mzda/ddr.c new file mode 100644 index 0000000..31a44fa --- /dev/null +++ b/board/microchip/pic32mzda/ddr.c @@ -0,0 +1,389 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <asm/io.h> +#include <stdint.h> +#include <config.h> +#include <linux/kernel.h> +#include <asm/mipsregs.h> +#include <asm/arch-pic32/pic32.h> + +#include "ddr.h" + +/* macros */ +#define hc_clk_dly(dly) \ + (max_t(u32, (DIV_ROUND_UP((dly), CLK_PERIOD)), 2) - 2) + +/* Host Commands */ +#define IDLE_NOP 0x00FFFFFF +#define PRECH_ALL_CMD 0x00FFF401 +#define REF_CMD 0x00FFF801 +#define LOAD_MODE_CMD 0x00FFF001 +#define CKE_LOW 0x00FFEFFE + +#define NUM_HOST_CMDS 12 + +/* DDR address decoding */ +#define COL_HI_RSHFT 0 +#define COL_HI_MASK 0 +#define COL_LO_MASK ((1 << COL_BITS) - 1) + +#define BA_RSHFT COL_BITS +#define BANK_ADDR_MASK ((1 << BA_BITS) - 1) + +#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) +#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) + +#define CS_ADDR_RSHIFT 0 +#define CS_ADDR_MASK 0 + +/* MPLL freq is 400MHz */ +#define CLK_PERIOD 2500 /* 2500 psec */ +#define CTRL_CLK_PERIOD (CLK_PERIOD * 2) + +/* Arbiter */ +#define NUM_AGENTS 5 +#define MIN_LIM_WIDTH 5 +#define RQST_PERIOD_WIDTH 8 +#define MIN_CMDACPT_WIDTH 8 + +#define EN_AUTO_PRECH 0 +#define SB_PRI 1 +#define BIG_ENDIAN 0 +#define HALF_RATE_MODE 1 + +/*****************************************************************************/ +/* DDR definitions */ +/*****************************************************************************/ + +/* DDR Address Mapping: CS, ROW, BA, COL */ +#define COL_BITS 10 +#define ROW_BITS 13 +#define BA_BITS 3 +#define CS_BITS 1 + +/* DDR constants */ +#define BL 2 /* Burst length in cycles */ + +/* default CAS latency for all speed grades */ +#define RL 5 + +/* default write latency for all speed grades = CL-1 */ +#define WL 4 + +#define MAX_BURST 3 + +/* NOTE: DDR data from Micron MT47H64M16HR-3 data sheet */ +#define tRFC_MIN 127500 /* psec */ +#define tWR 15000 /* psec */ +#define tRP 12500 /* psec */ +#define tRCD 12500 /* psec */ +#define tRRD 7500 /* psec */ + +/* tRRD_TCK is a minimum of 2 clk periods, regardless of clk freq */ +#define tRRD_TCK 2 +#define tWTR 7500 /* psec */ + +/* tWTR_TCK is a minimum of 2 clk periods, regardless of clk freq */ +#define tWTR_TCK 2 +#define tRTP 7500 /* psec */ +#define tRTP_TCK (BL / 2) +#define tXP_TCK 2 /* clocks */ +#define tCKE_TCK 3 /* clocks */ +#define tXSNR (tRFC_MIN + 10000) /* psec */ +#define tDLLK 200 /* clocks */ +#define tRAS_MIN 45000 /* psec */ +#define tRC 57500 /* psec */ +#define tFAW 35000 /* psec */ +#define tMRD 2 /* clocks */ +#define tRFI 7800000 /* psec */ + +/* Refresh Config */ +#define MAX_PEND_REF 7 + +/* Power Config */ +#define PRECH_PWR_DN_ONLY 0 +#define SELF_REF_DLY 17 +#define PWR_DN_DLY 8 +#define EN_AUTO_SELF_REF 0 +#define EN_AUTO_PWR_DN 0 +#define ERR_CORR_EN 0 +#define ECC_EN 0 + +/* PHY PAD CONTROL */ +#define ODT_SEL 1 +#define ODT_EN 1 +#define DRIVE_SEL 0 +#define ODT_PD 2 +#define ODT_PU 3 +#define EXTRA_OEN_CLK 0 +#define NOEXT_DLL 1 +#define HALF_RATE 1 +#define DLR_DFI_WRCMD 1 +#define DRVSTR_PFET 0xE +#define DRVSTR_NFET 0xE +#define RCVR_EN 1 +#define PREAMBLE_DLY 2 + +/* PHY DLL RECALIBRATE */ +#define RECALIB_CNT 0x10 +#define DELAY_START_VAL 3 + +/* SCL CONFIG */ +#define SCL_BURST8 1 +#define SCL_DDR2_CONNECTED 1 +#define SCL_ODTCSWW 1 +#define SCL_CSEN 1 +#define SCL_CAPCLKDLY 3 +#define SCL_DDRCLKDLY 4 + +/* SCL START */ +#define SCL_START 0x10000000 +#define SCL_EN 0x04000000 +#define SCL_LUBPASS 3 + +void ddr_pmd_unlock(void) +{ + writel(0, PMD7); +} + +/* init DDR2 Phy */ +void ddr_phy_init(void) +{ + u32 phy_pad_ctl; + + /* Enable DDR peripheral (disabled by default) */ + ddr_pmd_unlock(); + + /* PHY_DLL_RECALIB */ + writel((DELAY_START_VAL << 28) | (RECALIB_CNT << 8), DDR2PHYDLLR); + + phy_pad_ctl = (ODT_SEL | (ODT_EN << 1) | (DRIVE_SEL << 2) | + (ODT_PD << 4) | (ODT_PU << 6) | + (EXTRA_OEN_CLK << 8) | (NOEXT_DLL << 9) | + (DLR_DFI_WRCMD << 13) | (HALF_RATE << 14) | + (DRVSTR_PFET << 16) | (DRVSTR_NFET << 20) | + (RCVR_EN << 28) | (PREAMBLE_DLY << 29)); + + /* PHY_PAD_CTRL */ + writel(phy_pad_ctl, DDR2PHYPADCON); + + /* SCL_CONFIG_0 */ + writel(SCL_BURST8 | (SCL_DDR2_CONNECTED << 1) | (RL << 4) | + (SCL_ODTCSWW << 24), DDR2SCLCFG0); + + /* SCL_CONFIG_1 */ + writel(SCL_CSEN | (WL << 8), DDR2SCLCFG1); + + /* SCLLAT */ + writel(SCL_CAPCLKDLY | (SCL_DDRCLKDLY << 4), DDR2SCLLAT); +} + +/* init DDR2 Controller */ +void ddr_init(void) +{ + u32 v; + u32 wr2prech, rd2prech, wr2rd, wr2rd_csc; + u32 ras2ras, ras2cas, prech2ras; + u32 ba_field, ma_field; + + /* MEM_WIDTH */ + writel(HALF_RATE_MODE << 3, DDR2MEMWIDTH); + + /* Set arbiter configuration per target */ + writel(0 * MIN_LIM_WIDTH, DDR2TSEL); + writel(0x1f, DDR2MINLIM); + writel(0 * RQST_PERIOD_WIDTH, DDR2TSEL); + writel(0xff, DDR2REQPRD); + writel(0 * MIN_CMDACPT_WIDTH, DDR2TSEL); + writel(0x04, DDR2MINCMD); + + writel(1 * MIN_LIM_WIDTH, DDR2TSEL); + writel(0x1f, DDR2MINLIM); + writel(1 * RQST_PERIOD_WIDTH, DDR2TSEL); + writel(0xff, DDR2REQPRD); + writel(1 * MIN_CMDACPT_WIDTH, DDR2TSEL); + writel(0x10, DDR2MINCMD); + + writel(2 * MIN_LIM_WIDTH, DDR2TSEL); + writel(0x1f, DDR2MINLIM); + writel(2 * RQST_PERIOD_WIDTH, DDR2TSEL); + writel(0xff, DDR2REQPRD); + writel(2 * MIN_CMDACPT_WIDTH, DDR2TSEL); + writel(0x10, DDR2MINCMD); + + writel(3 * MIN_LIM_WIDTH, DDR2TSEL); + writel(0x04, DDR2MINLIM); + writel(3 * RQST_PERIOD_WIDTH, DDR2TSEL); + writel(0xff, DDR2REQPRD); + writel(3 * MIN_CMDACPT_WIDTH, DDR2TSEL); + writel(0x04, DDR2MINCMD); + + writel(4 * MIN_LIM_WIDTH, DDR2TSEL); + writel(0x04, DDR2MINLIM); + writel(4 * RQST_PERIOD_WIDTH, DDR2TSEL); + writel(0xff, DDR2REQPRD); + writel(4 * MIN_CMDACPT_WIDTH, DDR2TSEL); + writel(0x04, DDR2MINCMD); + + /* Address Configuration */ + writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) | + (COL_HI_RSHFT << 24) | (SB_PRI << 29) | + (EN_AUTO_PRECH << 30)), DDR2MEMCFG0); + writel(ROW_ADDR_MASK, DDR2MEMCFG1); + writel(COL_HI_MASK, DDR2MEMCFG2); + writel(COL_LO_MASK, DDR2MEMCFG3); + writel((BANK_ADDR_MASK | (CS_ADDR_MASK << 8)), DDR2MEMCFG4); + + /* Refresh Config */ + writel((DIV_ROUND_UP(tRFI, CTRL_CLK_PERIOD) - 2) | + ((DIV_ROUND_UP(tRFC_MIN, CTRL_CLK_PERIOD) - 2) << 16) | + (MAX_PEND_REF << 24), DDR2REFCFG); + + /* Power Config */ + writel((ECC_EN | (ERR_CORR_EN << 1) | (EN_AUTO_PWR_DN << 2) | + (EN_AUTO_SELF_REF << 3) | (PWR_DN_DLY << 4) | + (SELF_REF_DLY << 12) | (PRECH_PWR_DN_ONLY << 22)), + DDR2PWRCFG); + + /* Delay Config */ + wr2rd = max_t(u32, DIV_ROUND_UP(tWTR, CTRL_CLK_PERIOD), + DIV_ROUND_UP(tWTR_TCK, 2)) + WL + BL; + wr2rd_csc = max_t(u32, wr2rd - 1, 3); + wr2prech = DIV_ROUND_UP(tWR, CTRL_CLK_PERIOD) + (WL + BL); + rd2prech = max_t(u32, DIV_ROUND_UP(tRTP, CTRL_CLK_PERIOD), + DIV_ROUND_UP(tRTP_TCK, 2)) + BL - 2; + ras2ras = max_t(u32, DIV_ROUND_UP(tRRD, CTRL_CLK_PERIOD), + DIV_ROUND_UP(tRRD_TCK, 2)) - 1; + ras2cas = DIV_ROUND_UP(tRCD, CTRL_CLK_PERIOD) - 1; + prech2ras = DIV_ROUND_UP(tRP, CTRL_CLK_PERIOD) - 1; + + writel(((wr2rd & 0x0F) | ((wr2rd_csc & 0x0F) << 4) | + ((BL - 1) << 8) | (BL << 12) | ((BL - 1) << 16) | + ((BL - 1) << 20) | ((BL + 2) << 24) | + ((RL - WL + 3) << 28)), DDR2DLYCFG0); + + writel(((tCKE_TCK - 1) | (((DIV_ROUND_UP(tDLLK, 2) - 2) & 0xFF) << 8) | + ((tCKE_TCK - 1) << 16) | + ((max_t(u32, tXP_TCK, tCKE_TCK) - 1) << 20) | + ((wr2prech >> 4) << 26) | ((wr2rd >> 4) << 27) | + ((wr2rd_csc >> 4) << 28) | (((RL + 5) >> 4) << 29) | + ((DIV_ROUND_UP(tDLLK, 2) >> 8) << 30)), DDR2DLYCFG1); + + writel((DIV_ROUND_UP(tRP, CTRL_CLK_PERIOD) | (rd2prech << 8) | + ((wr2prech & 0x0F) << 12) | (ras2ras << 16) | (ras2cas << 20) | + (prech2ras << 24) | ((RL + 3) << 28)), DDR2DLYCFG2); + + writel(((DIV_ROUND_UP(tRAS_MIN, CTRL_CLK_PERIOD) - 1) | + ((DIV_ROUND_UP(tRC, CTRL_CLK_PERIOD) - 1) << 8) | + ((DIV_ROUND_UP(tFAW, CTRL_CLK_PERIOD) - 1) << 16)), + DDR2DLYCFG3); + + /* ODT Config */ + writel(0x00000000, DDR2ODTCFG); + writel(0x00010000, DDR2ODTENCFG);/* WREN on CS */ + + writel(((RL - 3) << 8) | ((WL - 3) << 12) | (2 << 16) | (3 << 20), + DDR2ODTCFG); + + /* TODO: resolve differences in NXTDATRQDLY, NXDATAVDLY and RDATENDLY */ + writel(/*(WL - 1)*/2 | (/*((RL + 1) & 0x0F)*/4 << 4) | + (/*(RL - 1)*/2 << 16) | + (MAX_BURST << 24) | (7 << 28) | (BIG_ENDIAN << 31), + DDR2XFERCFG); + + /* DRAM Initialization */ + /* bring CKE high after reset and wait 400 nsec */ + writel(IDLE_NOP, DDR2CMD10); + writel((0x00 | (0x00 << 8) | (hc_clk_dly(400000) << 11)), + DDR2CMD20); + + /* issue precharge all command */ + writel(PRECH_ALL_CMD, DDR2CMD10 + 0x04); + writel((0x04 | (0x00 << 8) | (hc_clk_dly(tRP + CLK_PERIOD) << 11)), + DDR2CMD20 + 0x04); + + /* initialize EMR2 */ + writel(LOAD_MODE_CMD, DDR2CMD10 + 0x08); + writel((0x00 | (0x02 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), + DDR2CMD20 + 0x08); + + /* initialize EMR3 */ + writel(LOAD_MODE_CMD, DDR2CMD10 + 0x0C); + writel((0x00 | (0x03 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), + DDR2CMD20 + 0x0C); + + /* + * RDQS disable, DQSB enable, OCD exit, 150 ohm termination, + * AL=0, DLL enable + */ + writel((LOAD_MODE_CMD | (0x40 << 24)), DDR2CMD10 + 0x10); + writel((0x00 | (0x01 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), + DDR2CMD20 + 0x10); + + v = ((DIV_ROUND_UP(tWR, CLK_PERIOD) - 1) << 1) | 1; + ma_field = v & 0xFF; + ba_field = (v >> 8) & 0x03; + + /* + * PD fast exit, WR REC = tWR in clocks -1, + * DLL reset, CAS = RL, burst = 4 + */ + writel((LOAD_MODE_CMD | (((RL << 4) | 2) << 24)), DDR2CMD10 + 0x14); + writel((ma_field | (ba_field << 8) | + (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), DDR2CMD20 + 0x14); + + /* issue precharge all command */ + writel(PRECH_ALL_CMD, DDR2CMD10 + 0x18); + writel((0x04 | (0x00 << 8) | (hc_clk_dly(tRP + CLK_PERIOD) << 11)), + DDR2CMD20 + 0x18); + + /* issue refresh command */ + writel(REF_CMD, DDR2CMD10 + 0x1C); + writel((0x00 | (0x00 << 8) | (hc_clk_dly(tRFC_MIN) << 11)), + DDR2CMD20 + 0x1C); + + /* issue refresh command */ + writel(REF_CMD, DDR2CMD10 + 0x20); + writel((0x00 | (0x00 << 8) | (hc_clk_dly(tRFC_MIN) << 11)), + DDR2CMD20 + 0x20); + + /* Mode register programming as before without DLL reset */ + writel((((RL << 4) | 3) << 24) | LOAD_MODE_CMD, DDR2CMD10 + 0x24); + + v = ((DIV_ROUND_UP(tWR, CLK_PERIOD) - 1) << 1); + ma_field = v & 0xFF; + ba_field = (v >> 8) & 0x03; + + writel((ma_field | (ba_field << 8) | + (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), DDR2CMD20 + 0x24); + + /* extended mode register same as before with OCD default */ + writel((LOAD_MODE_CMD | (0xC0 << 24)), DDR2CMD10 + 0x28); + writel((0x03 | (0x01 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), + DDR2CMD20 + 0x28); + + /* extended mode register same as before with OCD exit */ + writel((LOAD_MODE_CMD | (0x40 << 24)), DDR2CMD10 + 0x2C); + writel((0x00 | (0x01 << 8) | (hc_clk_dly(140 * CLK_PERIOD) << 11)), + DDR2CMD20 + 0x2C); + + writel(0x1B, DDR2CMDISSUE); + writel(0x01, DDR2MEMCON); + + while (readl(DDR2CMDISSUE) & 0x10) + ; + + writel(0x03, DDR2MEMCON); + + /* SCL Start */ + writel(SCL_START | SCL_EN, DDR2SCLSTART); + + /* Wait for SCL byte to pass */ + while ((readl(DDR2SCLSTART) & SCL_LUBPASS) != SCL_LUBPASS) + ; +} diff --git a/board/microchip/pic32mzda/ddr.h b/board/microchip/pic32mzda/ddr.h new file mode 100644 index 0000000..7828169 --- /dev/null +++ b/board/microchip/pic32mzda/ddr.h @@ -0,0 +1,46 @@ +/* + * (c) 2015 Purna Chandra Mandal purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __PIC32MZDA_DDR_H +#define __PIC32MZDA_DDR_H + +#define DDR2TSEL (PIC32_DDR2C_BASE + 0x00) /* ARB_AGENT_SEL */ +#define DDR2MINLIM (PIC32_DDR2C_BASE + 0x04) /* MIN_LIMIT */ +#define DDR2REQPRD (PIC32_DDR2C_BASE + 0x08) /* RQST_PERIOD */ +#define DDR2MINCMD (PIC32_DDR2C_BASE + 0x0c) /* MIN_CMD_ACPT */ +#define DDR2MEMCON (PIC32_DDR2C_BASE + 0x10) /* MEM_START */ +#define DDR2MEMCFG0 (PIC32_DDR2C_BASE + 0x14) /* MEM_CONFIG_1 */ +#define DDR2MEMCFG1 (PIC32_DDR2C_BASE + 0x18) /* MEM_CONFIG_2 */ +#define DDR2MEMCFG2 (PIC32_DDR2C_BASE + 0x1c) /* MEM_CONFIG_3 */ +#define DDR2MEMCFG3 (PIC32_DDR2C_BASE + 0x20) /* MEM_CONFIG_4 */ +#define DDR2MEMCFG4 (PIC32_DDR2C_BASE + 0x24) /* MEM_CONFIG_5 */ +#define DDR2REFCFG (PIC32_DDR2C_BASE + 0x28) /* REF_CONFIG */ +#define DDR2PWRCFG (PIC32_DDR2C_BASE + 0x2c) /* PWR_SAVE_ECC_CONFIG */ +#define DDR2DLYCFG0 (PIC32_DDR2C_BASE + 0x30) /* DLY_CONFIG1 */ +#define DDR2DLYCFG1 (PIC32_DDR2C_BASE + 0x34) /* DLY_CONFIG2 */ +#define DDR2DLYCFG2 (PIC32_DDR2C_BASE + 0x38) /* DLY_CONFIG3 */ +#define DDR2DLYCFG3 (PIC32_DDR2C_BASE + 0x3c) /* DLY_CONFIG4 */ +#define DDR2ODTCFG (PIC32_DDR2C_BASE + 0x40) /* ODT_CONFIG */ +#define DDR2XFERCFG (PIC32_DDR2C_BASE + 0x44) /* DATA_XFR_CONFIG */ +#define DDR2CMDISSUE (PIC32_DDR2C_BASE + 0x48) /* HOST_CMD_ISSUE */ +#define DDR2ODTENCFG (PIC32_DDR2C_BASE + 0x4c) /* ODT_EN_CONFIG */ +#define DDR2MEMWIDTH (PIC32_DDR2C_BASE + 0x50) /* MEM_WIDTH */ +#define DDR2CMD10 (PIC32_DDR2C_BASE + 0x80) /* HOST_CMD1 */ +#define DDR2CMD20 (PIC32_DDR2C_BASE + 0xc0) /* HOST_CMD2 */ + +/* DDR PHY */ +#define DDR2SCLSTART (PIC32_DDR2P_BASE + 0x00) /* SCL_START */ +#define DDR2SCLLAT (PIC32_DDR2P_BASE + 0x0c) /* PHY_SCLLAAT */ +#define DDR2SCLCFG0 (PIC32_DDR2P_BASE + 0x18) /* SCL_CONFIG_1 */ +#define DDR2SCLCFG1 (PIC32_DDR2P_BASE + 0x1c) /* SCL_CONFIG_2 */ +#define DDR2PHYPADCON (PIC32_DDR2P_BASE + 0x20) /* PHY_PAD_CTRL */ +#define DDR2PHYDLLR (PIC32_DDR2P_BASE + 0x24) /* PHY_DLL_RECALIB */ + +void ddr_phy_init(void); +void ddr_init(void); + +#endif /* __PIC32MZDA_DDR_H */ diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c new file mode 100644 index 0000000..ad312b2 --- /dev/null +++ b/board/microchip/pic32mzda/pic32mzda.c @@ -0,0 +1,41 @@ +/* + * Microchip PIC32MZ[DA] Starter Kit board + * + * Copyright (C) 2015, Microchip Technology Inc. + * Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <asm/arch-pic32/pic32.h> + +#include "ddr.h" + +/* initialize the DDR and PHY */ +phys_size_t initdram(int board_type) +{ + ddr_phy_init(); + ddr_init(); + return CONFIG_SYS_MEM_SIZE; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + ulong rate = 0; + struct udevice *dev; + + printf("Core: %s\n", get_core_name()); + + if (!uclass_get_device(UCLASS_CLK, 0, &dev)) { + rate = clk_get_rate(dev); + printf("CPU Speed: %lu MHz\n", rate / 1000000); + } + + return 0; +} +#endif diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig new file mode 100644 index 0000000..df06f8b --- /dev/null +++ b/configs/pic32mzdask_defconfig @@ -0,0 +1,22 @@ +CONFIG_MIPS=y +CONFIG_MACH_PIC32=y +CONFIG_SOC_PIC32MZDA=y +CONFIG_TARGET_PIC32MZDASK=y +CONFIG_PIC32_SUPPORTS_FDT_BOOT=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_HUSH_PARSER=y +CONFIG_SYS_PROMPT="dask # " +CONFIG_CMD_TIME=y +# CONFIG_CMD_IMLS is not set +CONFIG_SUPPORT_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_DM_SERIAL=y +CONFIG_PIC32_SERIAL=y +CONFIG_CLK=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_PIC32_PINCTRL=y diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h new file mode 100644 index 0000000..9f867ed --- /dev/null +++ b/include/configs/pic32mzdask.h @@ -0,0 +1,110 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Microchip PIC32MZ[DA] StarterKit. + */ + +#ifndef __PIC32MZDASK_CONFIG_H +#define __PIC32MZDASK_CONFIG_H + +/* System Configuration */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_BOARDINFO + +/*-------------------------------------------- + * CPU configuration + */ +#define CONFIG_MIPS 1 +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ + +/* CPU Timer rate */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_ICACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*---------------------------------------------------------------------- + * Memory Layout + */ +#define CONFIG_SYS_SRAM_BASE 0x80000000 +#define CONFIG_SYS_SRAM_SIZE 0x00080000 /* 512K in PIC32MZSK */ + +/* Initial RAM for temporary stack, global data */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* SDRAM Configuration (for final code, data, stack, heap) */ +#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CONFIG_SYS_MEM_SIZE (128 << 20) /* 128M */ + +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) +#define CONFIG_STACKSIZE (4 << 10) /* regular stack */ +#define CONFIG_SYS_EXCEPTION_ADDR 0xA000100 /* EBASE ADDR */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 << 10) + +#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ +#define CONFIG_SYS_ENV_ADDR 0x88300000 + +/* Memory Test */ +#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x88080000 + +/*---------------------------------------------------------------------- + * Commands + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMD_CLK +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_MEMINFO + +/*------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_SYS_NO_FLASH + +/*------------------------------------------------------------ + * Console Configuration + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Handover flattened device tree (dtb file) to Linux kernel + */ +#define CONFIG_OF_LIBFDT 1 + +/* ------------------------------------------------- + * Environment + */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x4000 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_BOOTDELAY 5 /* autoboot after X seconds */ +#undef CONFIG_BOOTARGS + +#define CONFIG_MEMSIZE_IN_BYTES /* pass 'memsize=' in bytes */ +#endif /* __PIC32MZDASK_CONFIG_H */ -- 1.8.3.1

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[U-Boot] [PULL] Please pull u-boot-nios/master
by Thomas Chou 29 Dec '15

29 Dec '15

The following changes since commit 78680314c53a95c0bb25e942662979843b60d7b9: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-12-27 09:15:57 -0500) are available in the git repository at: git://git.denx.de/u-boot-nios.git master for you to fetch changes up to 8e8106dcd540e4c735da6a0b71919747c15ce93a: altera_qspi: allow ctrl-c to abort the erase ops (2015-12-28 09:32:43 +0800) ---------------------------------------------------------------- Thomas Chou (5): altera_qspi: call callback even if the erase failed altera_qspi: set fail_addr for erase ops altera_qspi: skip erase if the sector is blank altera_qspi: show erase progress altera_qspi: allow ctrl-c to abort the erase ops drivers/mtd/altera_qspi.c | 56 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 46 insertions(+), 10 deletions(-)

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