December 2015 - U-Boot

[U-Boot] [PATCH v2 1/4] sf: Fix quad bit set for micron devices
by Jagan Teki 23 Dec '15

23 Dec '15

Setting up quad bit for micron devices need to do the same way as other flash devices like spansion, winbond etc does using enhanced volatile config register so this patch adds this support instead of printing "QEB is volatile" Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Peter Pan <peterpandong(a)micron.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v2: - none drivers/mtd/spi/sf_internal.h | 3 +++ drivers/mtd/spi/spi_flash.c | 62 +++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 561abc3..55ba81e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,6 +77,7 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -90,6 +91,7 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -104,6 +106,7 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) +#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6fe8c9d..8e8b89f 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -111,6 +111,37 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int read_evcr(struct spi_flash *flash, u8 *evcr) +{ + int ret; + const u8 cmd = CMD_READ_EVCR; + + ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); + if (ret < 0) { + debug("SF: error reading EVCR\n"); + return ret; + } + + return 0; +} + +static int write_evcr(struct spi_flash *flash, u8 evcr) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_EVCR; + ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); + if (ret < 0) { + debug("SF: error while writing EVCR register\n"); + return ret; + } + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) { @@ -843,6 +874,34 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int micron_quad_enable(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (!(qeb_status & STATUS_QEB_MICRON)) + return 0; + + ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); + if (ret < 0) + return ret; + + /* read EVCR and check it */ + ret = read_evcr(flash, &qeb_status); + if (!(ret > 0 && !(qeb_status & STATUS_QEB_MICRON))) { + printf("SF: Micron EVCR Quad bit not clear\n"); + return -EINVAL; + } + + return ret; +} +#endif + static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { @@ -857,8 +916,7 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); -- 1.9.1

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[U-Boot] [PATCH] arm: socfpga: Fix USB doesn't work on socdk board
by shengjiangwu 23 Dec '15

23 Dec '15

Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 06783dc..7819ad0 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -9,19 +9,19 @@ const u8 sys_mgr_init_table[] = { 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ 0, /* EMACIO14 */ 0, /* EMACIO15 */ 0, /* EMACIO16 */ -- 1.7.9.5

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
by 圣江吴 23 Dec '15

23 Dec '15

> From: Marek Vasut > Date: 2015-12-23 10:07 > To: ShengjiangWu > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote: > > > -----Original Message----- > > > From: Marek Vasut [mailto:marex@denx.de] > > > Sent: Wednesday, December 23, 2015 9:25 AM > > > To: 圣江吴 > > > Cc: u-boot(a)lists.denx.de; clsee(a)altera.com; > > > dinguyen(a)opensource.altera.com; dinh.linux(a)gmail.com; pavel(a)denx.de; > > > sr(a)denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on > > > socdk board > > > > > > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江吴 wrote: > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex(a)denx.de> wrote: > > > > > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote: > > > > > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote: > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI. > > > > > Updated QSPI clock. > > > > > > > > > > Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> > > > > > Cc: Chin Liang See <clsee(a)altera.com> > > > > > Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> > > > > > Cc: Dinh Nguyen <dinh.linux(a)gmail.com> > > > > > Cc: Pavel Machek <pavel(a)denx.de> > > > > > Cc: Marek Vasut <marex(a)denx.de> > > > > > Cc: Stefan Roese <sr(a)denx.de> > > > > > > > > Applied, thanks. > > > > > > > > I will push your patches to [1] in a few hours, can you try and see if > > > > the CV SOCDK works fine for you? Thanks > > > > > > > > [1] http://git.denx.de/?p=u-boot/u-boot- > > > > socfpga.git;a=shortlog;h=refs/heads/master > > > > > > > > Pushed. Please let me know how SoCDK works for you now and if there > > > > are still some problems. > > > > > > > > > > > > Best regards, > > > > Marek Vasut > > > > > > > > > > > > Hi Marek, > > > > > > > > Thank you for your help, I tested the master branch, emac1 and QSPI > > > > works. Below is log. > > > > > > Good! so we're happy ? Can you give USB a spin too? I think it might have > > > some issues and I don't have the necessary cable here. > > > > > > [...] > > > > > > Best regards, > > > Marek Vasut > > > > Hi Marek, > > > > Yes, emac1 and qspi are working now. I'm afraid USB is not working, > > > > => usb reset > > resetting USB... > > USB0: Core Release: 2.93a > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > dwc_otg_core_host_init: Timeout! > > scanning bus 0 for devices... 1 USB Device(s) found > > => usb tree > > USB device tree: > > 1 Hub (480 Mb/s, 0mA) > > U-Boot Root Hub > > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts . Hi Marek, Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb works, => usb start starting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 98mA) Generic USB Storage 000000000272 => Best Regards, ShengjiangWu

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[U-Boot] [PATCH v3 01/17] arm: socfpga: Enable ubi and ubifs support
by Chin Liang See 23 Dec '15

23 Dec '15

When QSPI and NAND is enabled, the ubi and ubifs support will be enabled too. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- Changes for v2 - move CONFIG_SPI_FLASH_USE_4K_SECTORS to Kconfig --- include/configs/socfpga_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f7c0eb5..dfc3ed5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -300,6 +300,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "-@1536k(UBI)\0" #endif +/* UBI and UBIFS support */ +#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif + /* * SPL * -- 1.9.2.468.g3f0c02a

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
by 圣江吴 23 Dec '15

23 Dec '15

On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex(a)denx.de> wrote: On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote: On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote: > Updated pinmux group MIXED1IO[15-20] for QSPI. > Updated QSPI clock. > > Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> > Cc: Chin Liang See <clsee(a)altera.com> > Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> > Cc: Dinh Nguyen <dinh.linux(a)gmail.com> > Cc: Pavel Machek <pavel(a)denx.de> > Cc: Marek Vasut <marex(a)denx.de> > Cc: Stefan Roese <sr(a)denx.de> Applied, thanks. I will push your patches to [1] in a few hours, can you try and see if the CV SOCDK works fine for you? Thanks [1] http://git.denx.de/?p=u-boot/u-boot- socfpga.git;a=shortlog;h=refs/heads/master Pushed. Please let me know how SoCDK works for you now and if there are still some problems. Best regards, Marek Vasut Hi Marek, Thank you for your help, I tested the master branch, emac1 and QSPI works. Below is log. Best Regards, ShengjiangWu => reset resetting ... U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: Error: ethernet@ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 => env default -a ## Resetting to default environment => setenv netmask 255.255.254.0 => setenv gatewayip 128.224.98.1 => setenv ipaddr 128.224.98.85 => setenv serverip 128.224.99.137 => setenv ethaddr 00:04:9f:13:57:b4 => saveenv Saving Environment to MMC... Writing to MMC(0)... done => reset resetting ... U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC External Transceiver (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: eth0: ethernet@ff702000 Hit any key to stop autoboot: 0 => tftp 0x8000000 /tftpboot/altera/uVxWorks Speed: 100, full duplex Using ethernet@ff702000 device TFTP from server 128.224.99.137; our IP address is 128.224.98.85 Filename '/tftpboot/altera/uVxWorks'. Load address: 0x8000000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################ 3.3 MiB/s done Bytes transferred = 6418496 (61f040 hex) => sf probe SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total 128 MiB => sf read 0x7000000 0 0x60000 device 0 offset 0x0, size 0x60000 SF: 393216 bytes @ 0x0 Read: OK => md 0x7000000 07000000: ea00001a e59ff014 e59ff014 e59ff014 ................ 07000010: e59ff014 e59ff014 e59ff014 e59ff014 ................ 07000020: ffff0020 ffff0024 ffff0028 ffff002c ...$...(...,... 07000030: ffff0030 ffff0100 ffff0038 12345678 0.......8...xV4. 07000040: 31305341 2e160000 01390000 ea000007 AS01......9..... 07000050: 01000040 0000b854 0000b854 0000b900 @...T...T....... 07000060: 0000b854 0badc0de 0badc0de 0badc0de T............... 07000070: eb000040 e10f0000 e3c0001f e38000d3 @............... 07000080: e129f000 ee110f10 e3c00a02 ee010f10 ..)............. 07000090: e59f00a8 ee0c0f10 eb000008 eb000015 ................ 070000a0: eb000690 ee070f15 ee070f9a ee070f95 ................ 070000b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ........../.../. 070000c0: e3a00000 ee080f17 ee070f15 ee070fd5 ................ 070000d0: ee070f9a ee070f95 ee110f10 e3c00a02 ................ 070000e0: e3c00007 e3800002 e3800b02 e3800a01 ................ 070000f0: ee010f10 e1a0f00e ea000018 e320f000 .............. . =>

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
by Marek Vasut 23 Dec '15

23 Dec '15

On Wednesday, December 23, 2015 at 02:25:29 AM, 圣江吴 wrote: > On Dec 22, 2015, at 05:22 PM, 圣江吴 <shengjiangwu(a)icloud.com> wrote: > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut <marex(a)denx.de> wrote: > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote: > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote: > > Updated pinmux group MIXED1IO[15-20] for QSPI. > > Updated QSPI clock. > > > > Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> > > Cc: Chin Liang See <clsee(a)altera.com> > > Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> > > Cc: Dinh Nguyen <dinh.linux(a)gmail.com> > > Cc: Pavel Machek <pavel(a)denx.de> > > Cc: Marek Vasut <marex(a)denx.de> > > Cc: Stefan Roese <sr(a)denx.de> > > Applied, thanks. > > I will push your patches to [1] in a few hours, can you try and see if the > CV SOCDK works fine for you? Thanks > > [1] http://git.denx.de/?p=u-boot/u-boot- > socfpga.git;a=shortlog;h=refs/heads/master > > Pushed. Please let me know how SoCDK works for you now and if there are > still some problems. > > > Best regards, > Marek Vasut > > > Hi Marek, > > Thank you for your help, I tested the master branch, emac1 and QSPI > works. Below is log. > > Best Regards, > ShengjiangWu > > => reset > resetting ... > > U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52) > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED > drivers/ddr/altera/sequencer.c: Calibration complete > Trying to boot from MMC > > > U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800) > > CPU: Altera SoCFPGA Platform > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > BOOT: SD/MMC External Transceiver (1.8V) > Watchdog enabled > I2C: ready > DRAM: 1 GiB > MMC: dwmmc0@ff704000: 0 > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Model: Altera SOCFPGA Cyclone V SoC Development Kit > Net: > Error: ethernet@ff702000 address not set. > No ethernet found. > Hit any key to stop autoboot: 0 > => env default -a > ## Resetting to default environment > => setenv netmask 255.255.254.0 > => setenv gatewayip 128.224.98.1 > => setenv ipaddr 128.224.98.85 > => setenv serverip 128.224.99.137 > => setenv ethaddr 00:04:9f:13:57:b4 > => saveenv > Saving Environment to MMC... > Writing to MMC(0)... done > => reset > resetting ... > > U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52) > drivers/ddr/altera/sequencer.c: Preparing to start memory calibration > drivers/ddr/altera/sequencer.c: CALIBRATION PASSED > drivers/ddr/altera/sequencer.c: Calibration complete > Trying to boot from MMC > > > U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800) > > CPU: Altera SoCFPGA Platform > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 > BOOT: SD/MMC External Transceiver (1.8V) > Watchdog enabled > I2C: ready > DRAM: 1 GiB > MMC: dwmmc0@ff704000: 0 > In: serial > Out: serial > Err: serial > Model: Altera SOCFPGA Cyclone V SoC Development Kit > Net: eth0: ethernet@ff702000 > Hit any key to stop autoboot: 0 > => tftp 0x8000000 /tftpboot/altera/uVxWorks > Speed: 100, full duplex > Using ethernet@ff702000 device > TFTP from server 128.224.99.137; our IP address is 128.224.98.85 > Filename '/tftpboot/altera/uVxWorks'. > Load address: 0x8000000 > Loading: ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################ > 3.3 MiB/s > done > Bytes transferred = 6418496 (61f040 hex) > => sf probe > SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total > 128 MiB => sf read 0x7000000 0 0x60000 > device 0 offset 0x0, size 0x60000 > SF: 393216 bytes @ 0x0 Read: OK > => md 0x7000000 > 07000000: ea00001a e59ff014 e59ff014 e59ff014 ................ > 07000010: e59ff014 e59ff014 e59ff014 e59ff014 ................ > 07000020: ffff0020 ffff0024 ffff0028 ffff002c ...$...(...,... > 07000030: ffff0030 ffff0100 ffff0038 12345678 0.......8...xV4. > 07000040: 31305341 2e160000 01390000 ea000007 AS01......9..... > 07000050: 01000040 0000b854 0000b854 0000b900 @...T...T....... > 07000060: 0000b854 0badc0de 0badc0de 0badc0de T............... > 07000070: eb000040 e10f0000 e3c0001f e38000d3 @............... > 07000080: e129f000 ee110f10 e3c00a02 ee010f10 ..)............. > 07000090: e59f00a8 ee0c0f10 eb000008 eb000015 ................ > 070000a0: eb000690 ee070f15 ee070f9a ee070f95 ................ > 070000b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ........../.../. > 070000c0: e3a00000 ee080f17 ee070f15 ee070fd5 ................ > 070000d0: ee070f9a ee070f95 ee110f10 e3c00a02 ................ > 070000e0: e3c00007 e3800002 e3800b02 e3800a01 ................ > 070000f0: ee010f10 e1a0f00e ea000018 e320f000 .............. . > => > > BTW, I tested on master branch of u-boot-socfpga, not SoCDK. Oh yeah, CV socdk is the abbreviation for "cyclone v soc development kit". btw can you please fix your mailer so it adds ">" before the quoted text?

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[U-Boot] [PATCH 1/6] arm: socfpga: Define NAND reset bit
by Marek Vasut 23 Dec '15

23 Dec '15

Define the NAND reset bit and fix the ordering of the macros. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index e50fbd8..2f070f2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -65,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) -- 2.1.4

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Re: [U-Boot] [PATCH] net: lpc32xx: Fix MDIO busy wait
by MESSIER, ALEXANDRE 22 Dec '15

22 Dec '15

Hello Vladimir, > Hi Alexandre, > > On 16.12.2015 20:37, amessier.tyco(a)gmail.com wrote: > > From: Alexandre Messier <amessier(a)tycoint.com> > > > > The MDIO read function waits on the busy flag after issuing the read > > command, > > that's correct, after issuing the read command and before register read. > > > while the MDIO write function waits on the busy flag before > > issuing the write command. > > and that is not correct, I believe. > > From the spec (MII Mgmt Indicators Register): > > For PHY Write if scan is not used: > 1. Write 0 to MCMD > 2. Write PHY address and register address to MADR > 3. Write data to MWTD > --> 4. Wait for busy bit to be cleared in MIND > > For PHY Read if scan is not used: > 1. Write 1 to MCMD > 2. Write PHY address and register address to MADR > --> 3. Wait for busy bit to be cleared in MIND > 4. Write 0 to MCMD > 5. Read data from MRDD > > Could you please test/review an alternative fix? I believe it adds proper > serialization of all command sequences (read/read, read/write, write/read > and write/write). Thank you in advance. Yes, this approach is fine too. I tested it and it fixes the issue. If you want to submit it as a new patch: Tested-by: Alexandre Messier <amessier(a)tycoint.com> > > diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c > index e76e9bc..3ba5b4b 100644 > --- a/drivers/net/lpc32xx_eth.c > +++ b/drivers/net/lpc32xx_eth.c > @@ -304,6 +304,13 @@ static int mii_reg_write(const char *devname, u8 > phy_adr, u8 reg_ofs, u16 data) > return -EFAULT; > } > > + /* write the phy and reg addressse into the MII address reg */ > + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << > MADR_REG_OFFSET), > + &regs->madr); > + > + /* write data to the MII write register */ > + writel(data, &regs->mwtd); > + > /* wait till the MII is not busy */ > timeout = MII_TIMEOUT; > do { > @@ -319,13 +326,6 @@ static int mii_reg_write(const char *devname, u8 > phy_adr, u8 reg_ofs, u16 data) > return -EFAULT; > } > > - /* write the phy and reg addressse into the MII address reg */ > - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << > MADR_REG_OFFSET), > - &regs->madr); > - > - /* write data to the MII write register */ > - writel(data, &regs->mwtd); > - > /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, > reg_ofs, data);*/ > > > > This causes an issue when writing then immediately reading. As the MDIO > > module is still busy, the read command is not processed. The wait on > > busy flag in the read command passes because the previous write > command > > finishes. In the end, the value returned by the read function is > > whatever was present in the MDIO data register. > > > > Fix the issue by making sure the busy flag is cleared before issuing a > > read command. This way, it is still possible to issue a write command > > and continue executing u-boot code while the command is processed by > > the hardware. Any following MDIO read/write commands after a write > > command will wait for a cleared busy flag. > > -- > With best wishes, > Vladimir > > ________________________________ This e-mail contains privileged and confidential information intended for the use of the addressees named above. If you are not the intended recipient of this e-mail, you are hereby notified that you must not disseminate, copy or take any action in respect of any information contained in it. If you have received this e-mail in error, please notify the sender immediately by e-mail and immediately destroy this e-mail and its attachments.

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[U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
by shengjiangwu 22 Dec '15

22 Dec '15

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------ board/altera/cyclone5-socdk/qts/pll_config.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0..06783dc 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 9e336e3..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -- 1.7.9.5

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[U-Boot] [PATCH 1/2] arm: socfpga: Make /soc available in pre-reloc
by Marek Vasut 22 Dec '15

22 Dec '15

This node must be available before relocation, otherwise the board will not find mmc and will thus not boot. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 224928f..a202709 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -34,6 +34,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { -- 2.1.4

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