January 2015 - U-Boot

[U-Boot] [PATCH] edminiv2: fix PCIE IO base address typo
by Albert ARIBAUD 25 Feb '15

25 Feb '15

Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/include/asm/arch-orion5x/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 08a450f..092dbd6 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -86,7 +86,7 @@ enum orion5x_cpu_attrib { #endif #if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) -#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000 #endif #if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) -- 2.1.0

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[U-Boot] [PATCH] edminiv2: switch to generic board support
by Albert ARIBAUD 25 Feb '15

25 Feb '15

Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- board/LaCie/edminiv2/config.mk | 12 ------------ include/configs/edminiv2.h | 4 ++++ 2 files changed, 4 insertions(+), 12 deletions(-) delete mode 100644 board/LaCie/edminiv2/config.mk diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk deleted file mode 100644 index dfa84f0..0000000 --- a/board/LaCie/edminiv2/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot(a)aribaud.net> -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TEXT_BASE must equal the intended FLASH location of u-boot. -CONFIG_SYS_TEXT_BASE = 0xfff90000 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 70a698a..47da4a9 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -12,6 +12,10 @@ #ifndef _CONFIG_EDMINIV2_H #define _CONFIG_EDMINIV2_H +/* general settings */ +#define CONFIG_SYS_TEXT_BASE 0xfff90000 +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ -- 2.1.0

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[U-Boot] [PATCH 0/1] fix ARM DCC support for ARMv7 based cores (e.g. CortexA)
by Alexander Merkle 25 Feb '15

25 Feb '15

arm_dcc.c supported ARMv4 (ARM7) to ARMv6 (ARM11) correctly. All recent CortexA/ARMv7 based cores share the mrc/mcr coprocessor calls of ARMv6. Due to the missing #ifdef the ARM7/ARMv4 calls are used as soon as CONFIG_CPU_V7 is defined. This results in an undefined instruction exception. Alexander Merkle (1): fix ARM DCC support for ARMv7 based cores (e.g. CortexA) drivers/serial/arm_dcc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.1.4

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[U-Boot] [PATCH] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
by Aneesh Bansal 25 Feb '15

25 Feb '15

Secure Boot Target is added for NAND for P3041 Changes: In PowerPC, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e 0x0 - 0xDFFFFFFF In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on this SRAM at location 0xBFF40000 with entry point as 0xBFFFFFFC. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Makefile | 4 ++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 15 +++++++++++++++ board/freescale/common/p_corenet/tlb.c | 18 +++++++++++++++++- configs/P3041DS_NAND_SECURE_BOOT_defconfig | 4 ++++ include/configs/corenet_ds.h | 6 ++++++ 5 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig diff --git a/Makefile b/Makefile index 36a9a28..ca98b3e 100644 --- a/Makefile +++ b/Makefile @@ -714,8 +714,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin else +ifneq ($(CONFIG_SECURE_BOOT), y) +# For Secure Boot The Image needs to be signed and Header must also +# be included. So The image has to be built explicitly ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl endif +endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 85d32fc..2da99a1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -851,6 +851,21 @@ int cpu_init_r(void) setup_mp(); #endif +#ifdef CONFIG_SECURE_BOOT + /* Disable the TLB Created for L3 and create the TLB required for + * PCIE (CONFIG_SYS_PCIE1_MEM_VIRT) which was not created earlier. + */ + int tlb_index; + tlb_index = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); + if (tlb_index != -1) + disable_tlb(tlb_index); + + set_tlb(1, CONFIG_SYS_PCIE1_MEM_VIRT, + CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, tlb_index, BOOKE_PAGESZ_1G, 1); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 { if (SVR_MAJ(svr) < 3) { diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46..1b60cfb 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -42,7 +42,9 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* In Case of Secure RAM Boot L3 address is defined at 0xbff00000 */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -76,11 +78,25 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + defined(CONFIG_SECURE_BOOT) + /* In case of Secure Boot, L3 is used as 1M SRAM + * and the address of the SRAM is at 0xbff00000. + * The PCIE TLB entry conflicts with the above entry. + * So, the entry for PCIE is not created at this point of time. + * It will be created later on in cpu_init_r() + * when U-Boot has relocated to DDR + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1), +#else /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), +#endif /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig new file mode 100644 index 0000000..e810b1c --- /dev/null +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xBFF40000" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_P3041DS=y diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 225ffdd..8fba5ec 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -16,6 +16,11 @@ #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xbffffffc +#define CONFIG_BPTR_VIRT_ADDR 0xbffff000 +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg @@ -29,6 +34,7 @@ #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -- 1.8.1.4

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[U-Boot] [RFC] m68k: generic board
by Angelo Dureghello 24 Feb '15

24 Feb '15

Dear all, i would like to post a patch with the m68k generic board support, tested and working here, but of course not tested for all the other m68k boards except mine. My coldfire board is the "amcore" board not yet accepted. http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/193661 http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/193660 I need some suggestions on how to proceed now. I already modified my board config to work with generic board support. So my thought is to post 2 separate patches: 1 - add generic board (1/1). Each board maintainer should then test it and report for feedbacks. 2 Re-post a 2/2 patch (v8) of amcore using generic board: - amcore board (1), - mcf5307 support (2), This amcore board is the coldfire base i use here for all the general m68k tests. With your help commenting on this patch until it is conformant to the last recent coding guidelines could help me and Alison to know what has to be purged / changed, (eventually, if needed) in all other m68k boards code. What do you think ? Best regards, Angelo Dureghello

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[U-Boot] [PATCH] configs: LS1012XA: Modify CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS for LS102XA
by Nikhil Badola 24 Feb '15

24 Feb '15

Change CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS value to 2 for LS102XAQDS and LS102XATWR. The XHCI controller has 2 ports; one for 2.0 and the other for 3.0 USB transactions Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- Depends on patch https://patchwork.ozlabs.org/patch/401448/ and https://patchwork.ozlabs.org/patch/401449/ include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1389b00..3cd4a9f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -298,7 +298,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 2b23cc9..4098214 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -46,7 +46,7 @@ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) -- 1.7.11.7

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[U-Boot] [PATCHv1 00/22] Add SPL support for SoCFGPA
by dinguyen＠opensource.altera.com 24 Feb '15

24 Feb '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Hello, This patchset adds all the SPL code that is necessary to support the SoCFPGA platform. With this patch series, one should be able to configure the SDRAM controller and run u-boot. I have pushed a branch to git://git.rocketboards.org/u-boot-socfpga-next.git socfpga_for_next_spl_v1 for testing and reviewing. Thanks, Dinh Dinh Nguyen (22): arm: socfpga: spl: Add main sdram code arm: socfpga: enable saveenv to mmc partition arm: socfpga: Add sdram initialization code arm: socfpga: spl: Add SRAM section arm: socfpga: spl: put SPL in sram arm: socfpga: add functions to bring sdram, timer, and uart out of reset arm: socfpga: spl: enable sdram, timer and uart arm: socfpga: spl: Add call to timer_init arm: socfpga: spl: allow bootrom to enable IOs after warm reset arm: socfpga: spl: add sdram init and calibration arm: socfpga: spl: printout sdram size arm: socfpga: spl: Use common lowlevel_init arm: socfpga: spl: Add s_init arm: socfpga: spl: update lowlevel_init arm: socfpga: spl: add relocate_stack_to_sdram to lowlevel_init.S arm: socfpga: spl: add the stack in OCRAM arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h arm: socfpga: add sdram stack to SPL arm: socfpga: spl: set SPL_MALLOC_SIZE arm: socfpga: spl: add a malloc section in sram arm: socfpga: spl: Add SDRAM check arm: socfpga: spl: update pll_config for dev kit arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/Makefile | 4 +- arch/arm/cpu/armv7/socfpga/config.mk | 3 +- arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 89 +- arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 + arch/arm/cpu/armv7/socfpga/s_init.c | 49 + arch/arm/cpu/armv7/socfpga/sdram.c | 1311 ++++ arch/arm/cpu/armv7/socfpga/spl.c | 33 + arch/arm/cpu/armv7/socfpga/system_manager.c | 9 + arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 29 +- arch/arm/include/asm/arch-socfpga/reset_manager.h | 37 + arch/arm/include/asm/arch-socfpga/sdram.h | 434 ++ arch/arm/include/asm/arch-socfpga/system_manager.h | 20 +- board/altera/socfpga/Makefile | 1 + board/altera/socfpga/pll_config.h | 8 +- board/altera/socfpga/sdram/Makefile | 12 + board/altera/socfpga/sdram/sdram_config.h | 100 + board/altera/socfpga/sdram/sdram_io.h | 44 + board/altera/socfpga/sdram/sequencer.c | 7993 ++++++++++++++++++++ board/altera/socfpga/sdram/sequencer.h | 504 ++ board/altera/socfpga/sdram/sequencer_auto.h | 216 + .../altera/socfpga/sdram/sequencer_auto_ac_init.c | 88 + .../socfpga/sdram/sequencer_auto_inst_init.c | 273 + board/altera/socfpga/sdram/sequencer_defines.h | 154 + board/altera/socfpga/sdram/system.h | 15 + include/configs/socfpga_common.h | 16 +- include/configs/socfpga_cyclone5.h | 1 + 27 files changed, 11422 insertions(+), 47 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/s_init.c create mode 100644 arch/arm/cpu/armv7/socfpga/sdram.c create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h create mode 100644 board/altera/socfpga/sdram/Makefile create mode 100644 board/altera/socfpga/sdram/sdram_config.h create mode 100644 board/altera/socfpga/sdram/sdram_io.h create mode 100644 board/altera/socfpga/sdram/sequencer.c create mode 100644 board/altera/socfpga/sdram/sequencer.h create mode 100644 board/altera/socfpga/sdram/sequencer_auto.h create mode 100644 board/altera/socfpga/sdram/sequencer_auto_ac_init.c create mode 100644 board/altera/socfpga/sdram/sequencer_auto_inst_init.c create mode 100644 board/altera/socfpga/sdram/sequencer_defines.h create mode 100644 board/altera/socfpga/sdram/system.h -- 2.2.1

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[U-Boot] [PATCH 00/12] imx:mx6 add ldo bypass
by Peng Fan 24 Feb '15

24 Feb '15

This patch set is based on these three patches: https://patchwork.ozlabs.org/patch/426621/ https://patchwork.ozlabs.org/patch/426623/ https://patchwork.ozlabs.org/patch/426622/ If want to test this patch set, please first apply the up 3 patches. This patch set is mainly to add ldo bypass support. Since pmic related function is not readly in previous patch, patch 1/12, patch 2/12, patch 3/12 is first to add pmic related support, such as power_init_board, related iomux/pad settings and configuration in header file. Then ldo bypass function can be implemented. patch 4/12 is to update mxc_ccm_regs with more registers, since ldo setting will use them. patch 5/12 is to update fuse_bank0_regs, since ldo setting will check it. patch 6/12 is to add a macro for setting voltage easily. patch 7/12 is to add ldo bypass related common function. patch 8/12, patch 9/12, patch 10/12, patch 11/12 is to implement ldo_mode_set in different boards' file. patch 12/12 is to invoke ldo_mode_set in arch_preboot_os. Future work will integrate Device tree for i.MX6 U-Boot. Then we can move it to power_init_board. More detailed info can see each patch's commit log. Peng Fan (12): imx:mx6slevk add pmic and i2c configuration imx:mx6sl add I2c pad settings imx:mx6slevk implement power init board imx:mx6 update mxc_ccm_reg imx:mx6 update fuse_bank0_regs pmic:pfuze add macro for setting voltage imx:mx6 Support LDO bypass imx:mx6slevk add ldo mode set function imx:mx6sabresd Add ldo_mode_set function imx:mx6sxsabresd add ldo mode set function imx:mx6qsabreauto add ldo mode init ARM:imx call ldo_mode_set in arch_preboot_os arch/arm/cpu/armv7/mx6/soc.c | 141 ++++++++++++++++++++++++++ arch/arm/imx-common/cpu.c | 4 + arch/arm/include/asm/arch-mx6/crm_regs.h | 87 ++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 12 ++- arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 + arch/arm/include/asm/arch-mx6/sys_proto.h | 9 ++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 31 ++++++ board/freescale/mx6sabresd/mx6sabresd.c | 85 ++++++++++++++++ board/freescale/mx6slevk/mx6slevk.c | 100 ++++++++++++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 50 +++++++++ include/configs/mx6qsabreauto.h | 2 + include/configs/mx6sabresd.h | 2 + include/configs/mx6slevk.h | 14 +++ include/configs/mx6sxsabresd.h | 2 + include/power/pfuze100_pmic.h | 2 + 15 files changed, 542 insertions(+), 4 deletions(-) -- 1.8.4

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[U-Boot] [PATCH] fastboot: Add USB cable detect check
by Rob Herring 24 Feb '15

24 Feb '15

Add a check for USB cable attached and only enter fastboot when a cable is attached. Signed-off-by: Rob Herring <robh(a)kernel.org> --- common/cmd_fastboot.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c index b72f4f3..346ab80 100644 --- a/common/cmd_fastboot.c +++ b/common/cmd_fastboot.c @@ -20,6 +20,12 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) if (ret) return ret; + if (!g_dnl_board_usb_cable_connected()) { + puts("\rUSB cable not detected.\n" \ + "Command exit.\n"); + return CMD_RET_FAILURE; + } + while (1) { if (g_dnl_detach()) break; -- 2.1.0

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[U-Boot] [PATCH] mmc: dw_mmc: fixed the wrong bit control
by Jaehoon Chung 23 Feb '15

23 Feb '15

If mode is not DDR-mode, then it needs to clear it. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index b18c75d..76fa0b0 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -321,7 +321,7 @@ static void dwmci_set_ios(struct mmc *mmc) if (mmc->ddr_mode) regs |= DWMCI_DDR_MODE; else - regs &= DWMCI_DDR_MODE; + regs &= ~DWMCI_DDR_MODE; dwmci_writel(host, DWMCI_UHS_REG, regs); -- 1.9.1

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