January 2015 - U-Boot

[U-Boot] [PATCH] board: tbs2910: Gate clock when switching async clock muxes
by Soeren Moch 23 Feb '15

23 Feb '15

According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch <smoch(a)web.de> -- Cc: Stefano Babic <sbabic(a)denx.de> --- board/tbs/tbs2910/tbs2910.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index dfa430e..42b166d 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -326,21 +326,25 @@ static void setup_display(void) reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); - /* select video pll for ldb_di0_clk */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); - writel(reg, &ccm->cs2cdr); + /* gate ipu1_di0_clk */ + reg = readl(&ccm->CCGR3); + reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &ccm->CCGR3); - /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */ - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */ + /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | + (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | + (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); + + /* enable ipu1_di0_clk */ + reg = readl(&ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &ccm->CCGR3); } #endif /* CONFIG_VIDEO_IPUV3 */ -- 1.9.1

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[U-Boot] [PATCH v3 00/13] ARMv7: add PSCI support to u-boot
by Marc Zyngier 19 Feb '15

19 Feb '15

PSCI is an ARM standard that provides a generic interface that supervisory software can use to manage power in the following situations: - Core idle management - CPU hotplug - big.LITTLE migration models - System shutdown and reset It basically allows the kernel to offload these tasks to the firmware, and rely on common kernel side code. More importantly, it gives a way to ensure that CPUs enter the kernel at the appropriate exception level (ie HYP mode, to allow the use of the virtualization extensions), even across events like CPUs being powered off/on or suspended. The main idea here is to turn some of the existing u-boot code into a separate section that can live in secure RAM (or a reserved page of memory), containing a secure monitor that will implement the PSCI operations. This code will still be alive when u-boot is long gone, hence the need for a piece of memory that will not be touched by the OS. This patch series contains 4 parts: - the first four patches are just bug fixes - the next two refactor the HYP/non-secure code to allow relocation in secure memory - the next four contain the generic PSCI code and DT infrastructure - the last three implement the CPU_ON method of the Allwinner A20 (aka sun7i). I realize the A20 u-boot code is not upstream yet (BTW is anyone actively working on that?), but hopefully that should give a good idea of how things are structured so far. The patches are against the mainline u-boot tree as of today, merged with the sunxi u-boot tree of the day and the first 10 patches will directly apply to mainline u-boot. As for using this code, it goes like this: sun7i# ext2load mmc 0:1 0x40008000 zImage ; ext2load mmc 0:1 0x60000000 sun7i-a20-cubietruck.dtb 2270120 bytes read in 117 ms (18.5 MiB/s) 9138 bytes read in 3 ms (2.9 MiB/s) sun7i# fdt addr 0x60000000 ; fdt resize ; fdt set ethernet0 mac-address "[5a fe b0 07 b0 07]" sun7i# setenv bootargs console=ttyS0,115200 earlyprintk ip=dhcp root=/dev/nfs nfsroot=/backup/a20_root,tcp sun7i# bootz 0x40008000 - 0x60000000 The kernel now boots in HYP mode, finds its secondary CPU without any SMP code present in the kernel, and runs KVM out of the box. I've been told the Xen/ARM guys managed to do the same fairly easily. This code has also been tested on a VExpress TC2, running KVM with all 5 CPUs, in order to make sure there was no obvious regression. I'm wildly cross-posting this patch series, including to lists I'm not subscribed to. Please keep me on Cc for any comment you may have. The code is also available at: git://git.kernel.org/pub/scm/linux/kernel/git/maz/u-boot.git wip/psci Cheers, M. Ma Haijun (1): ARM: convert arch_fixup_memory_node to a generic FDT fixup function Marc Zyngier (12): ARM: HYP/non-sec: move switch to non-sec to the last boot phase ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 ARM: non-sec: reset CNTVOFF to zero ARM: add missing HYP mode constant ARM: HYP/non-sec: add separate section for secure code ARM: HYP/non-sec: allow relocation to secure RAM ARM: HYP/non-sec: add generic ARMv7 PSCI code ARM: HYP/non-sec: add the option for a second-stage monitor ARM: HYP/non-sec/PSCI: emit DT nodes sunxi: fix SRAM_B/SRAM_D memory map sunxi: HYP/non-sec: add sun7i PSCI backend sunxi: HYP/non-sec: configure CNTFRQ on all CPUs arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/Makefile | 5 + arch/arm/cpu/armv7/nonsec_virt.S | 168 +++++++++++++++++--------------- arch/arm/cpu/armv7/psci.S | 105 ++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/Makefile | 3 + arch/arm/cpu/armv7/sunxi/psci.S | 162 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-dt.c | 100 +++++++++++++++++++ arch/arm/cpu/armv7/virt-v7.c | 59 ++++------- arch/arm/cpu/u-boot.lds | 30 ++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 4 +- arch/arm/include/asm/armv7.h | 11 ++- arch/arm/include/asm/proc-armv/ptrace.h | 2 + arch/arm/include/asm/psci.h | 35 +++++++ arch/arm/include/asm/secure.h | 26 +++++ arch/arm/lib/bootm-fdt.c | 13 ++- arch/arm/lib/bootm.c | 27 +++-- arch/arm/lib/interrupts.c | 2 +- arch/arm/lib/sections.c | 2 + common/image-fdt.c | 7 +- include/common.h | 6 +- include/configs/sun7i.h | 7 ++ 21 files changed, 627 insertions(+), 149 deletions(-) create mode 100644 arch/arm/cpu/armv7/psci.S create mode 100644 arch/arm/cpu/armv7/sunxi/psci.S create mode 100644 arch/arm/cpu/armv7/virt-dt.c create mode 100644 arch/arm/include/asm/psci.h create mode 100644 arch/arm/include/asm/secure.h -- 1.8.5.1

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[U-Boot] [PATCH v2 0/3] Add generic early debug UART feature
by Simon Glass 19 Feb '15

19 Feb '15

This series adds debug UART infrastructure which can in principle be used on any architecture. It works best with those that don't need a stack to call functions (e.g. ARM, PowerPC). This came up in a discussion on the mailing list here: https://patchwork.ozlabs.org/patch/384613/ My concerns at the time were: - it doesn't need to be written in assembler - it doesn't need to be ARM-specific - it only supports one serial driver This potentially creates a problem where to support n architectures and m serial drivers we need n * m lots of assembler-coded functions. For example, in Linux for ARM we have: ../plat-spear/include/plat/debug-macro.S ../mach-s5pc100/include/mach/debug-macro.S ../mach-shark/include/mach/debug-macro.S ../mach-spear3xx/include/mach/debug-macro.S ../mach-sa1100/include/mach/debug-macro.S ../mach-l7200/include/mach/debug-macro.S ../mach-mv78xx0/include/mach/debug-macro.S ../mach-realview/include/mach/debug-macro.S ../mach-mmp/include/mach/debug-macro.S ../mach-s3c64xx/include/mach/debug-macro.S ../mach-s5pv210/include/mach/debug-macro.S ../mach-clps711x/include/mach/debug-macro.S ../mach-versatile/include/mach/debug-macro.S ../mach-iop32x/include/mach/debug-macro.S ../mach-ebsa110/include/mach/debug-macro.S ../mach-ux500/include/mach/debug-macro.S ../mach-orion5x/include/mach/debug-macro.S ../mach-lpc32xx/include/mach/debug-macro.S ../mach-vt8500/include/mach/debug-macro.S ../mach-rpc/include/mach/debug-macro.S ../mach-kirkwood/include/mach/debug-macro.S ../mach-spear6xx/include/mach/debug-macro.S ../mach-footbridge/include/mach/debug-macro.S ../mach-davinci/include/mach/debug-macro.S ../plat-samsung/include/plat/debug-macro.S ../mach-spear13xx/include/mach/debug-macro.S ../mach-exynos/include/mach/debug-macro.S ../mach-exynos/include/mach/regs-debug.h ../mach-dove/include/mach/debug-macro.S ../mach-omap1/include/mach/debug-macro.S ../mach-u300/include/mach/debug-macro.S ../mach-bcm2835/include/mach/debug-macro.S ../mach-h720x/include/mach/debug-macro.S ../mach-ep93xx/include/mach/debug-macro.S ../mach-gemini/include/mach/debug-macro.S ../mach-s3c24xx/include/mach/debug-macro.S ../mach-at91/include/mach/debug-macro.S ../mach-ixp4xx/include/mach/debug-macro.S ../mach-nomadik/include/mach/debug-macro.S ../mach-cns3xxx/include/mach/debug-macro.S ../mach-mxs/include/mach/debug-macro.S ../mach-iop33x/include/mach/debug-macro.S ../mach-ks8695/include/mach/debug-macro.S ../mach-netx/include/mach/debug-macro.S ../mach-iop13xx/include/mach/debug-macro.S ../mach-integrator/include/mach/debug-macro.S ../mach-msm/include/mach/debug-macro.S ../mach-pxa/include/mach/debug-macro.S ../mach-s5p64x0/include/mach/debug-macro.S ../mach-prima2/include/mach/debug-macro.S ../mach-omap2/include/mach/debug-macro.S This series provides a possible alternative. It works by allowing any serial driver to export one init function and provide a putc() function. These can be used to output debug data before the real serial driver is available. Only one debug UART can be used at a time, and its address and serial clock must be provided statically in Kconfig. This implementation does not depend on driver model being set up, and it is possible for it to operate without a stack on some architectures (e.g. PowerPC, ARM). It provides the same features as the ARM-specific debug.S but with more UART and architecture support. As an example, here is the code generated for printch() by gcc 4.8 on ARM using the ns16550 driver (Tegra Seaboard): 0013b3b0 <printch>: 13b3b0: e59f201c ldr r2, [pc, #28] ; 13b3d4 <printch+0x24> 13b3b4: e5d23305 ldrb r3, [r2, #773] ; 0x305 13b3b8: e6ef3073 uxtb r3, r3 13b3bc: e3130020 tst r3, #32 13b3c0: 0afffffb beq 13b3b4 <printch+0x4> 13b3c4: e6ef0070 uxtb r0, r0 13b3c8: e59f3004 ldr r3, [pc, #4] ; 13b3d4 <printch+0x24> 13b3cc: e5c30300 strb r0, [r3, #768] ; 0x300 13b3d0: e12fff1e bx lr 13b3d4: 70006000 .word 0x70006000 The PowerPC 4xx code (ELDK-5.3) for printhex8() is this: 0102db44 <printhex8>: 102db44: 3c c0 ef 60 lis r6,-4256 102db48: 3c e0 ef 60 lis r7,-4256 102db4c: 39 20 00 1c li r9,28 102db50: 60 c6 03 05 ori r6,r6,773 102db54: 60 e7 03 00 ori r7,r7,768 102db58: 7c 6a 4c 30 srw r10,r3,r9 102db5c: 55 4a 07 3e clrlwi r10,r10,28 102db60: 2b 8a 00 09 cmplwi cr7,r10,9 102db64: 39 0a 00 30 addi r8,r10,48 102db68: 40 9d 00 08 ble- cr7,102db70 <printhex8+0x2c> 102db6c: 39 0a 00 57 addi r8,r10,87 102db70: 7c 00 04 ac sync 102db74: 89 46 00 00 lbz r10,0(r6) 102db78: 0c 0a 00 00 twi 0,r10,0 102db7c: 4c 00 01 2c isync 102db80: 55 4a 06 b4 rlwinm r10,r10,0,26,26 102db84: 71 45 00 ff andi. r5,r10,255 102db88: 41 82 ff e8 beq+ 102db70 <printhex8+0x2c> 102db8c: 55 08 06 3e clrlwi r8,r8,24 102db90: 7c 00 04 ac sync 102db94: 99 07 00 00 stb r8,0(r7) 102db98: 2f 89 00 00 cmpwi cr7,r9,0 102db9c: 39 29 ff fc addi r9,r9,-4 102dba0: 40 9e ff b8 bne+ cr7,102db58 <printhex8+0x14> 102dba4: 4e 80 00 20 blr However this is somewhat toolchain-dependent. For example, some toolchains may spill over the available registers and use the stack. It would be nice to have a way to tell gcc not to do that. This is not offered as a catch-all solution, but I believe it has value for many use cases. Changes in v2: - Add asmlinkage to exported functions - Split series out on its own - Add x86 support (asmlinkage, so it still needs a stack at present) - Add better cover letter Simon Glass (3): serial: Support an early UART for debugging serial: ns16550: Add access functions that don't need platdata serial: ns16550: Support debug UART drivers/serial/Kconfig | 59 ++++++++++++++++++++ drivers/serial/ns16550.c | 98 ++++++++++++++++++++++++++------- include/debug_uart.h | 139 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 276 insertions(+), 20 deletions(-) create mode 100644 include/debug_uart.h -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH v1 0/4] Jetson-TK1 support for PSCI
by Ian Campbell 19 Feb '15

19 Feb '15

Hi Thierry, I needed to boot my Jetson in NS mode (in order to boot Xen) and was investigating the possibility of PSCI support when I discovered that you had already started on it[0]. Hurrah! I cherry-picked the relevant commit onto u-boot-tegra#master and added a few more patches and now it boots correctly for me, both running Xen (some Xen side patches are needed too) and native Linux. The main things which was needed was to rebase for some recent Kconfig changes relating to virt and nonsec mode and to arrange for the RAM used by the secure code to be reserved in the FDT. I also reserved the RAM using the hardware MC_SECURITY_CFG registers for good measure. I also pushed my tree to gitorious: https://gitorious.org/ijc/u-boot jetson-psci-v1 I would Ack your patch, but I don't think you've posted it and it has no S-o-b so that would seem a bit premature/rude of me. For the same reason I've not actually included it in the series posted (but it is in the gitorious branch). FWIW I think you could drop your stub versions of psci_cpu_off and psci_cpu_suspend (assuming you don't want to implement them) since the common code has stubs. Albert, I've CCd you on a couple of patches which touch common ARM code. Nothing too major I think. Cheers, Ian. [0] https://github.com/thierryreding/u-boot/commit/5996d2b0dea2953ae8881f40b7f8…

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[U-Boot] [PATCH 1/3] ARM: imx fix register base address for i.MX6SX
by Peng Fan 17 Feb '15

17 Feb '15

Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- arch/arm/include/asm/arch-mx6/imx-regs.h | 50 ++++++++++++++++---------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5314298..44e31c9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -277,31 +277,31 @@ #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #ifdef CONFIG_MX6SX -#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) -#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) -#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) -#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) -#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) -#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) -#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) -#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) -#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) -#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) -#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) -#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) -#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) -#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) -#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) -#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) -#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) -#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#define GIS_BASE_ADDR (AIPS3_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_BASE_ADDR + 0x1C000) +#define LCDIF1_BASE_ADDR (AIPS3_BASE_ADDR + 0x20000) +#define LCDIF2_BASE_ADDR (AIPS3_BASE_ADDR + 0x24000) +#define VADC_BASE_ADDR (AIPS3_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_BASE_ADDR + 0x84000) +#define WDOG3_BASE_ADDR (AIPS3_BASE_ADDR + 0x88000) +#define ECSPI5_BASE_ADDR (AIPS3_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_BASE_ADDR + 0xB0000) #endif #define CHIP_REV_1_0 0x10 -- 1.8.4

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[U-Boot] [PATCH v2 0/11] Add full DDR init for Marvell Armada-XP MV78xx0 (AXP)
by Stefan Roese 17 Feb '15

17 Feb '15

This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the AXP boot image. Not linked with the main U-Boot. With this code addition and the also included SERDES / PHY setup code, the Armada-XP support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Hopefully other MVEBU SoC's will follow here. Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and on a custom fixed DDR configuration board (maxbcm with MV78460). Thanks, Stefan Changes in v2: - Patch added to patch series (removal of dummy binary.0 files) - Rebased on current master (2015.01, git ID ab77f241) Stefan Roese (11): arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr arm: mvebu: Add Serdes PHY config code arm: armada-xp: Add SPL support used to include the DDR training code scripts/Makefile.spl: Add MVEBU DDR code to SPL tools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS Makefile: Add another kwb build target used on Marvell Armada-XP (AXP) arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot arm: maxbcm: Enable SPL to include DDR training code into U-Boot arm: mvebu: Placeholder bin_hdr file can now be removed arm: armada-xp: Change built target to include the SPL binary as bin_hdr Makefile | 6 + arch/arm/Kconfig | 2 + arch/arm/cpu/armv7/armada-xp/Makefile | 2 + arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S | 62 + arch/arm/cpu/armv7/armada-xp/spl.c | 38 + arch/arm/include/asm/arch-armada-xp/config.h | 4 + arch/arm/include/asm/arch-armada-xp/cpu.h | 16 + arch/arm/mvebu-common/Makefile | 2 + arch/arm/mvebu-common/serdes/Makefile | 6 + arch/arm/mvebu-common/serdes/board_env_spec.h | 262 ++++ arch/arm/mvebu-common/serdes/high_speed_env_lib.c | 1572 +++++++++++++++++++ arch/arm/mvebu-common/serdes/high_speed_env_spec.c | 185 +++ arch/arm/mvebu-common/serdes/high_speed_env_spec.h | 87 ++ arch/arm/mvebu-common/u-boot-spl.lds | 57 + board/Marvell/db-mv784mp-gp/binary.0 | 17 - board/Marvell/db-mv784mp-gp/kwbimage.cfg | 2 +- board/maxbcm/binary.0 | 17 - board/maxbcm/kwbimage.cfg | 2 +- board/maxbcm/maxbcm.c | 85 +- configs/db-mv784mp-gp_defconfig | 5 +- configs/maxbcm_defconfig | 5 +- drivers/ddr/mvebu/Makefile | 14 + drivers/ddr/mvebu/ddr3_axp.h | 510 +++++++ drivers/ddr/mvebu/ddr3_axp_config.h | 146 ++ drivers/ddr/mvebu/ddr3_axp_mc_static.h | 284 ++++ drivers/ddr/mvebu/ddr3_axp_training_static.h | 770 ++++++++++ drivers/ddr/mvebu/ddr3_axp_vars.h | 226 +++ drivers/ddr/mvebu/ddr3_dfs.c | 1552 +++++++++++++++++++ drivers/ddr/mvebu/ddr3_dqs.c | 1374 +++++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.c | 1115 ++++++++++++++ drivers/ddr/mvebu/ddr3_hw_training.h | 392 +++++ drivers/ddr/mvebu/ddr3_init.c | 1219 +++++++++++++++ drivers/ddr/mvebu/ddr3_init.h | 143 ++ drivers/ddr/mvebu/ddr3_patterns_64bit.h | 924 ++++++++++++ drivers/ddr/mvebu/ddr3_pbs.c | 1592 ++++++++++++++++++++ drivers/ddr/mvebu/ddr3_read_leveling.c | 1214 +++++++++++++++ drivers/ddr/mvebu/ddr3_sdram.c | 669 ++++++++ drivers/ddr/mvebu/ddr3_spd.c | 1300 ++++++++++++++++ drivers/ddr/mvebu/ddr3_write_leveling.c | 1366 +++++++++++++++++ drivers/ddr/mvebu/xor.c | 436 ++++++ drivers/ddr/mvebu/xor.h | 70 + drivers/ddr/mvebu/xor_regs.h | 103 ++ include/configs/db-mv784mp-gp.h | 49 + include/configs/maxbcm.h | 49 + scripts/Makefile.spl | 1 + tools/kwbimage.c | 11 + 46 files changed, 17919 insertions(+), 44 deletions(-) create mode 100644 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S create mode 100644 arch/arm/cpu/armv7/armada-xp/spl.c create mode 100644 arch/arm/mvebu-common/serdes/Makefile create mode 100644 arch/arm/mvebu-common/serdes/board_env_spec.h create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_lib.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.c create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.h create mode 100644 arch/arm/mvebu-common/u-boot-spl.lds delete mode 100644 board/Marvell/db-mv784mp-gp/binary.0 delete mode 100644 board/maxbcm/binary.0 create mode 100644 drivers/ddr/mvebu/Makefile create mode 100644 drivers/ddr/mvebu/ddr3_axp.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_config.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_mc_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_training_static.h create mode 100644 drivers/ddr/mvebu/ddr3_axp_vars.h create mode 100644 drivers/ddr/mvebu/ddr3_dfs.c create mode 100644 drivers/ddr/mvebu/ddr3_dqs.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.c create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.h create mode 100644 drivers/ddr/mvebu/ddr3_init.c create mode 100644 drivers/ddr/mvebu/ddr3_init.h create mode 100644 drivers/ddr/mvebu/ddr3_patterns_64bit.h create mode 100644 drivers/ddr/mvebu/ddr3_pbs.c create mode 100644 drivers/ddr/mvebu/ddr3_read_leveling.c create mode 100644 drivers/ddr/mvebu/ddr3_sdram.c create mode 100644 drivers/ddr/mvebu/ddr3_spd.c create mode 100644 drivers/ddr/mvebu/ddr3_write_leveling.c create mode 100644 drivers/ddr/mvebu/xor.c create mode 100644 drivers/ddr/mvebu/xor.h create mode 100644 drivers/ddr/mvebu/xor_regs.h -- 2.2.2

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[U-Boot] [PATCH] spi: davinci: Remove duplicate code to set bus and cs for slave
by Axel Lin 17 Feb '15

17 Feb '15

It's done in spi_alloc_slave(). Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/davinci_spi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ec5b9d..bf18362 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -32,9 +32,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!ds) return NULL; - ds->slave.bus = bus; - ds->slave.cs = cs; - switch (bus) { case SPI0_BUS: ds->regs = (struct davinci_spi_regs *)SPI0_BASE; -- 1.9.1

2 1

[U-Boot] [PATCH] spi: cf_qspi: Fixup to_cf_qspi_slave macro
by Axel Lin 17 Feb '15

17 Feb '15

The third parameter of container_of is the name of the member within the struct. Current code only works if the parameter passed to to_cf_qspi_slave named slave. Fix it. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/cf_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c index 6b85633..834c5bd 100644 --- a/drivers/spi/cf_qspi.c +++ b/drivers/spi/cf_qspi.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define clamp(x, low, high) (min(max(low, x), high)) -#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s) +#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave) struct cf_qspi_slave { struct spi_slave slave; /* Specific bus:cs ID for each device */ -- 1.9.1

2 1

[U-Boot] [PATCH] buildman: allow multiple toolchains in a single path
by Albert ARIBAUD 15 Feb '15

15 Feb '15

When buildman scans a toolchain path, it stops at the first toolchain found. However, a single path can contains several toolchains, each with its own prefix. This patch lets buildman scan all toolchains in the path. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- tools/buildman/toolchain.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index d4c5d4a..537797a 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -197,13 +197,14 @@ class Toolchains: Returns: Filename of C compiler if found, else None """ + fnames = [] for subdir in ['.', 'bin', 'usr/bin']: dirname = os.path.join(path, subdir) if verbose: print " - looking in '%s'" % dirname for fname in glob.glob(dirname + '/*gcc'): if verbose: print " - found '%s'" % fname - return fname - return None + fnames.append(fname) + return fnames def Scan(self, verbose): @@ -219,8 +220,8 @@ class Toolchains: if verbose: print 'Scanning for tool chains' for path in self.paths: if verbose: print " - scanning path '%s'" % path - fname = self.ScanPath(path, verbose) - if fname: + fnames = self.ScanPath(path, verbose) + for fname in fnames: self.Add(fname, True, verbose) def List(self): -- 2.1.0

2 2

[U-Boot] [PATCH 1/2] buildman: Fix incorrect arguemnt in GetUpstream()
by Simon Glass 15 Feb '15

15 Feb '15

This causes an error when trying to build a local branch which has a local branch as its upstream. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reported-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- tools/patman/gitutil.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index cc5a55a..9a40f68 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -129,7 +129,7 @@ def GetUpstream(git_dir, branch): return upstream, msg if remote == '.': - return merge + return merge, None elif remote and merge: leaf = merge.split('/')[-1] return '%s/%s' % (remote, leaf), None -- 2.2.0.rc0.207.ga3a616c

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