January 2015 - U-Boot

[U-Boot] [PATCH 0/5] peach_pi: Add support for FIMD and DP
by Ajay Kumar 02 Mar '15

02 Mar '15

Add support for the eDP panel supported on peach_pi. Sjoerd Simons(1): [PATCH 1/5] Exynos5800: The Peach-Pi board does not have a Parade video bridge Ajay Kumar (4): [PATCH 2/5] arm: exynos: add display clocks for Exynos5800 [PATCH 3/5] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi [PATCH 5/5] peach_pi: dts: Add lcd poweron delay arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 +- arch/arm/dts/exynos5800-peach-pi.dts | 6 +-- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ board/samsung/smdk5420/smdk5420.c | 32 +++++++----- 5 files changed, 88 insertions(+), 20 deletions(-) -- 1.7.9.5

6 18

[U-Boot] [PATCH v2 0/3] Clean out SPL ready for driver model
by Simon Glass 26 Feb '15

26 Feb '15

This series includes a few more patches aimed at getting rid of gdata, the parallel global_data structure introduced on some ARM boards. This series relies on this patch: https://patchwork.ozlabs.org/patch/423789/ Changes in v2: - Remove gdata definition from ARM spl header file also Simon Glass (3): ti: davinci: Remove unnecessary stack and global_data fiddles Revert "Revert "ARM: SPL: do not set gd again"" arm: spl: Avoid setting up a duplicate global data structure arch/arm/cpu/arm926ejs/davinci/spl.c | 6 +----- arch/arm/include/asm/spl.h | 2 -- arch/arm/lib/spl.c | 12 ------------ 3 files changed, 1 insertion(+), 19 deletions(-) -- 2.2.0.rc0.207.ga3a616c

3 13

[U-Boot] [PATCH 0/2] Invoke board specific board_usb_cleanup function
by Inha Song 26 Feb '15

26 Feb '15

This patches invoke board-specific usb cleanup interface (board_usb_cleanup) After USB initalization. Inha Song (2): usb: common: provide a _weak board_usb_cleanup() function usb: invoke board specific USB cleanup interface common/cmd_dfu.c | 1 + common/cmd_thordown.c | 1 + common/cmd_usb_mass_storage.c | 1 + common/usb.c | 6 ++++++ 4 files changed, 9 insertions(+) -- 2.0.0.390.gcb682f8

5 15

Re: [U-Boot] Odroid XU3 - exynos5422 - SPL - iRAM/sRAM address
by Sjoerd Simons 26 Feb '15

26 Feb '15

(Corrected the u-boot list address in the cc of this thread and added Kevin hilman who is also quite interested in this topic) On Tue, 2015-01-20 at 10:36 +0100, Sjoerd Simons wrote: > Hey Suriyan, > > I just noticed the patchset Akshay Saraswat sent (Add support for > booting multiple cores), which would hopefully fix some issues wrt. > booting secondary cores we've seen on the XU3 thusfar. Unfortunately, > those fixes need to be applied in the SPL stage, hence coming back to > the BL2 story :). Any updates you can share? > > Separately i do wonder if getting a (very basic?) signed BL2 to > chainload an unsigned SPL might not be the best way forward here. Would > allow us to fix SPL issues in u-boot without having to ask hardkernel to > sign every time ? :/ > > > On Fri, 2014-12-19 at 15:45 -0800, Suriyan Ramasami wrote: > > Just to close the loop. > > > > For the XU3, scanning memory, I found the signed BL2 loaded at address > > 0x02027000. > > Regards > > - Suriyan > > > > PS: Any pointers with regards to mem_ctrl_init() is appreciated. > > > > On Fri, Dec 19, 2014 at 12:43 PM, Suriyan Ramasami <suriyan.r(a)gmail.com> wrote: > > > Hello All, > > > Greetings! > > > > > > I have been dabbling with trying to get mainline SPL working on > > > the Odroid XU3. The issue that I am facing is that currently I do not > > > know what address the BL1 loads and passes control to the SPL (signed > > > BL2). > > > Of course, I could get another SPL signed from Hard kernel and > > > have the address written out in some memory address, but I thought if > > > someone has access to the documents it might be faster to get this > > > information. > > > > > > As an update ... > > > So far, I have successfully gotten an Hardkernel based SPL to > > > chain load an unsigned SPL from mainline. I am hitting some issues in > > > mem_ctrl_init() or so I think. I was wondering if the issues were > > > cause of it being initialized twice (one from the signed BL2) and the > > > other from the mainline SPL that is chain loaded. > > > > > > Thanks > > > - Suriyan > >

4 16

[U-Boot] [PATCH v2] arm: ls1021x: Add support for initializing CAAM's stream id
by Alison Wang 25 Feb '15

25 Feb '15

There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo(a)freescale.com> Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- Changes in v2: - Move changing CCSR macros to a separated patch. arch/arm/include/asm/arch-ls102xa/config.h | 1 + .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 57 ++++++++++++++++++++++ board/freescale/common/ls102xa_stream_id.c | 15 ++++++ board/freescale/ls1021aqds/ls1021aqds.c | 21 ++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 21 ++++++++ 5 files changed, 115 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da..f200bc8 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -36,6 +36,7 @@ #define CONFIG_SYS_LS102XA_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index abd70fc..fa571b3 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -7,11 +7,68 @@ #ifndef __FSL_LS102XA_STREAM_ID_H_ #define __FSL_LS102XA_STREAM_ID_H_ +#include <fsl_sec.h> + +#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ + { .compat = name, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ + { .compat = name, \ + .id = { idA, idB }, .num_ids = 2, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ +#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum) + +/* This is a bit evil since we treat rtic param as both a string & hex value */ +#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ + SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + +#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ + SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ + offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, 0) + +struct liodn_id_table { + const char *compat; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + struct smmu_stream_id { uint16_t offset; uint16_t stream_id; char dev_name[32]; }; +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size); void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); #endif diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index 6154c9c..f434269 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -16,3 +16,18 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) for (i = 0; i < num; i++) out_be32(scfg + id[i].offset, id[i].stream_id); } + +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) +{ + int i; + u32 liodn; + + for (i = 0; i < size; i++) { + if (tbl[i].num_ids == 2) + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + else + liodn = tbl[i].id[0]; + + out_le32((uint32_t *)(tbl[i].reg_offset), liodn); + } +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index f08e54f..a578ba7 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -450,6 +450,25 @@ static struct csu_ns_dev ns_dev[] = { }; #endif +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), + SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), +}; + struct smmu_stream_id dev_stream_id[] = { { 0x100, 0x01, "ETSEC MAC1" }, { 0x104, 0x02, "ETSEC MAC2" }, @@ -489,6 +508,8 @@ int board_init(void) config_serdes_mux(); #endif + ls1021x_config_caam_stream_id(sec_liodn_tbl, + ARRAY_SIZE(sec_liodn_tbl)); ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8ab229d..8b73172 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -389,6 +389,25 @@ static struct csu_ns_dev ns_dev[] = { }; #endif +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), + SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), +}; + struct smmu_stream_id dev_stream_id[] = { { 0x100, 0x01, "ETSEC MAC1" }, { 0x104, 0x02, "ETSEC MAC2" }, @@ -425,6 +444,8 @@ int board_init(void) #endif #endif + ls1021x_config_caam_stream_id(sec_liodn_tbl, + ARRAY_SIZE(sec_liodn_tbl)); ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] arm: ls102xa: workaround for cache coherency problem
by Chenhui Zhao 25 Feb '15

25 Feb '15

The RCPM FSM may not be reset after power-on, for example, in the cases of cold boot and wakeup from deep sleep. It causes cache coherency problem and may block deep sleep. Therefore, reset them if they are not be reset. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/cpu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce2d92f..a61f6d1 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -14,6 +14,13 @@ #include "fsl_epu.h" +#define DCSR_RCPM2_BLOCK_OFFSET 0x223000 +#define DCSR_RCPM2_CPMFSMCR0 0x400 +#define DCSR_RCPM2_CPMFSMSR0 0x404 +#define DCSR_RCPM2_CPMFSMCR1 0x414 +#define DCSR_RCPM2_CPMFSMSR1 0x418 +#define CPMFSMSR_FSM_STATE_MASK 0x7f + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -107,6 +114,27 @@ int cpu_eth_init(bd_t *bis) int arch_cpu_init(void) { void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *rcpm2_base = + (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + u32 state; + + /* + * The RCPM FSM state may not be reset after power-on. + * So, reset them. + */ + state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) & + CPMFSMSR_FSM_STATE_MASK; + if (state != 0) { + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80); + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0); + } + + state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) & + CPMFSMSR_FSM_STATE_MASK; + if (state != 0) { + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80); + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0); + } /* * After wakeup from deep sleep, Clear EPU registers -- 1.9.1

2 1

[U-Boot] [PATCH 1/4] arm/ls102xa: create TLB to map PCIe region
by Minghuan Lian 25 Feb '15

25 Feb '15

LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/cpu.c | 203 +++++++++++++++++++++++++++-- arch/arm/include/asm/arch-ls102xa/config.h | 14 ++ 2 files changed, 207 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce2d92f..18665a3 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -8,6 +8,8 @@ #include <asm/arch/clock.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> +#include <asm/cache.h> +#include <asm/system.h> #include <tsec.h> #include <netdev.h> #include <fsl_esdhc.h> @@ -16,6 +18,197 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_DCACHE_OFF + +/* + * Bit[1] of the descriptor indicates the descriptor type, + * and bit[0] indicates whether the descriptor is valid. + */ +#define PMD_TYPE_TABLE 0x3 +#define PMD_TYPE_SECT 0x1 + +/* AttrIndx[2:0] */ +#define PMD_ATTRINDX(t) ((t) << 2) + +/* Section */ +#define PMD_SECT_AF (1 << 10) + +#define BLOCK_SIZE_L1 (1UL << 30) +#define BLOCK_SIZE_L2 (1UL << 21) + +/* TTBCR flags */ +#define TTBCR_EAE (1 << 31) +#define TTBCR_T0SZ(x) ((x) << 0) +#define TTBCR_T1SZ(x) ((x) << 16) +#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) +#define TTBCR_IRGN0_NC (0 << 8) +#define TTBCR_IRGN0_WBWA (1 << 8) +#define TTBCR_IRGN0_WT (2 << 8) +#define TTBCR_IRGN0_WBNWA (3 << 8) +#define TTBCR_IRGN0_MASK (3 << 8) +#define TTBCR_ORGN0_NC (0 << 10) +#define TTBCR_ORGN0_WBWA (1 << 10) +#define TTBCR_ORGN0_WT (2 << 10) +#define TTBCR_ORGN0_WBNWA (3 << 10) +#define TTBCR_ORGN0_MASK (3 << 10) +#define TTBCR_SHARED_NON (0 << 12) +#define TTBCR_SHARED_OUTER (2 << 12) +#define TTBCR_SHARED_INNER (3 << 12) +#define TTBCR_EPD0 (0 << 7) +#define TTBCR (TTBCR_SHARED_NON | \ + TTBCR_ORGN0_NC | \ + TTBCR_IRGN0_NC | \ + TTBCR_USING_TTBR0 | \ + TTBCR_EAE) + +/* + * Memory region attributes for LPAE (defined in pgtable): + * + * n = AttrIndx[2:0] + * + * n MAIR + * UNCACHED 000 00000000 + * BUFFERABLE 001 01000100 + * DEV_WC 001 01000100 + * WRITETHROUGH 010 10101010 + * WRITEBACK 011 11101110 + * DEV_CACHED 011 11101110 + * DEV_SHARED 100 00000100 + * DEV_NONSHARED 100 00000100 + * unused 101 + * unused 110 + * WRITEALLOC 111 11111111 + */ +#define MT_MAIR0 0xeeaa4400 +#define MT_MAIR1 0xff000004 +#define MT_STRONLY_ORDER 0 +#define MT_NORMAL_NC 1 +#define MT_DEVICE_MEM 4 +#define MT_NORMAL 7 + +/* The phy_addr must be aligned to 4KB */ +static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr) +{ + u32 value = phy_addr | PMD_TYPE_TABLE; + + page_table[2 * index] = value; + page_table[2 * index + 1] = 0; +} + +/* The phy_addr must be aligned to 4KB */ +static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, + u32 memory_type) +{ + u64 value; + + value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF; + value |= PMD_ATTRINDX(memory_type); + page_table[2 * index] = value & 0xFFFFFFFF; + page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF; +} + +/* + * Start MMU after DDR is available, we create MMU table in DRAM. + * The base address of TTLB is gd->arch.tlb_addr. We use two + * levels of translation tables here to cover 40-bit address space. + * + * The TTLBs are located at PHY 2G~4G. + * + * VA mapping: + * + * ------- <---- 0GB + * | | + * | | + * |-------| <---- 0x24000000 + * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 + * |-------| <---- 0x300000000 + * | | + * |-------| <---- 0x34000000 + * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 + * |-------| <---- 0x40000000 + * | | + * |-------| <---- 0x80000000 DDR0 space start + * |\\\\\\\| + *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space + * |\\\\\\\| + * ------- <---- 4GB DDR0 space end + */ +static void mmu_setup(void) +{ + u32 *level0_table = (u32 *)gd->arch.tlb_addr; + u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000); + u64 va_start = 0; + u32 reg; + int i; + + /* Level 0 Table 2-3 are used to map DDR */ + set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); + set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); + /* Level 0 Table 1 is used to map device */ + set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); + /* Level 0 Table 0 is used to map device including PCIe MEM */ + set_pgtable(level0_table, 0, (u32)level1_table); + + /* Level 1 has 512 entries */ + for (i = 0; i < 512; i++) { + /* Mapping for PCIe 1 */ + if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && + va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + + CONFIG_SYS_PCIE_MMAP_SIZE)) + set_pgsection(level1_table, i, + CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + MT_DEVICE_MEM); + /* Mapping for PCIe 2 */ + else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && + va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + + CONFIG_SYS_PCIE_MMAP_SIZE)) + set_pgsection(level1_table, i, + CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + MT_DEVICE_MEM); + else + set_pgsection(level1_table, i, + va_start, + MT_DEVICE_MEM); + va_start += BLOCK_SIZE_L2; + } + + asm volatile("dsb sy;isb"); + asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */ + : : "r" (TTBCR) : "memory"); + asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */ + : : "r" ((u32)level0_table), "r" (0) : "memory"); + asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */ + : : "r" (MT_MAIR0) : "memory"); + asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */ + : : "r" (MT_MAIR1) : "memory"); + + /* Set the access control to all-supervisor */ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + : : "r" (~0)); + + /* Enable the mmu */ + reg = get_cr(); + set_cr(reg | CR_M); +} + +/* + * This function is called from lib/board.c. It recreates MMU + * table in main memory. MMU and i/d-cache are enabled here. + */ +void enable_caches(void) +{ + /* Invalidate all TLB */ + mmu_page_table_flush(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + /* Set up and enable mmu */ + mmu_setup(); + + /* Invalidate & Enable d-cache */ + invalidate_dcache_all(); + set_cr(get_cr() | CR_C); +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -78,16 +271,6 @@ int print_cpuinfo(void) } #endif -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - #ifdef CONFIG_FSL_ESDHC int cpu_mmc_init(bd_t *bis) { diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 5e934da..1c32f2e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -61,6 +61,20 @@ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +/* + * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) + * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. + */ +#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ + CONFIG_SYS_PCIE1_VIRT_ADDR) +#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ + CONFIG_SYS_PCIE2_VIRT_ADDR) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM -- 1.9.1

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[U-Boot] [PATCH] arm: ls102xa: Define default values for some CCSR macros
by Alison Wang 25 Feb '15

25 Feb '15

This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 697d4ca..a29c041 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -37,6 +37,43 @@ #define DCFG_DCSR_PORCR1 0 +/* + * Define default values for some CCSR macros to make header files cleaner + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v1 0/24] Update ARMv8 LS2085a emulator and simulator boards
by York Sun 25 Feb '15

25 Feb '15

This set update LS2085a for both emulator and simulator "boards". There are also changes to DDR driver to accomodate new features and bug fix. U-boot still runs at EL3. This will change when we have the security monitor in place later. lowlevel.S will be trimmed down once both security monitor and PSCI are in place. Flushing L3 cache (Dickens) code will also be moved into security monitor. U-boot will eventually run at EL2. Arnab Basu (2): ARMv8/fsl-lsch3: Patch cpu node properties in DT for online cores ARMv8/ls2085a: Switch to passing earlycon to kernel Bhupesh Sharma (3): fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodes ls2085/configs: Ensure right banners are printed for EMU and SIMU J. German Rivera (1): drivers/mc: Migrated MC Flibs to 0.5.2 Kuldip Giroh (1): ARMv8/LS2085A: HugeTLB support is required by default in LS NADK Stuart Yoder (1): ARMv8/ls2085a: Move kernel image load address York Sun (16): armv8/fsl-lsch3: Change normal memory shareability armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack armv8/ls2085a: Enable cluster timebase for all clusters driver/ddr/fsl: Adjust CAS to preamble override for emulator driver/ddr/fsl: Add bit operation accessors driver/ddr/fsl: Add workaround for A008336 driver/ddr/fsl: Add workround for erratumn A008514 armv8/fsl-lsch3: Add support for second DDR clock driver/ddr/fsl: Add support for multiple DDR clocks ARMv8/LS2085A: Enable auto precharge for DP-DDR driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation ARMv8/LS2085A: Adjust system clock and DDR clock driver/ddr/fsl: Add sync of refresh armv8/fsl-lsch3: Enable workaround for A008336 armv8/fsl-lsch3: Enable erratum workround for A008514 armv8/ls2085a_emu: Enable sync of refresh README | 3 + arch/arm/cpu/armv8/cache.S | 6 + arch/arm/cpu/armv8/cache_v8.c | 18 +- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 62 +----- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 28 ++- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 132 +++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/mp.c | 8 + arch/arm/cpu/armv8/fsl-lsch3/mp.h | 1 + arch/arm/cpu/armv8/fsl-lsch3/speed.c | 16 +- arch/arm/include/asm/arch-fsl-lsch3/config.h | 38 ++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 3 + arch/arm/include/asm/armv8/mmu.h | 3 +- arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/system.h | 1 + arch/arm/lib/bootm.c | 2 +- board/freescale/ls2085a/ddr.c | 1 + board/freescale/ls2085a/ls2085a.c | 29 ++- doc/README.fsl-trustzone-components | 25 +++ drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/ctrl_regs.c | 216 ++++++++++++--------- drivers/ddr/fsl/ddr1_dimm_params.c | 18 +- drivers/ddr/fsl/ddr2_dimm_params.c | 12 +- drivers/ddr/fsl/ddr3_dimm_params.c | 8 +- drivers/ddr/fsl/ddr4_dimm_params.c | 8 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 36 +++- drivers/ddr/fsl/lc_common_dimm_params.c | 27 +-- drivers/ddr/fsl/main.c | 29 +-- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 4 +- drivers/ddr/fsl/options.c | 6 +- drivers/ddr/fsl/util.c | 67 ++++++- drivers/net/Makefile | 2 +- drivers/net/{fsl_mc => fsl-mc}/Makefile | 4 +- drivers/net/fsl-mc/dpmng.c | 91 +++++++++ drivers/net/fsl-mc/fsl_dpmng_cmd.h | 49 +++++ drivers/net/{fsl_mc => fsl-mc}/mc.c | 132 ++++++++----- drivers/net/fsl-mc/mc_sys.c | 63 ++++++ include/configs/ls2085a_common.h | 19 +- include/configs/ls2085a_emu.h | 4 + include/configs/ls2085a_simu.h | 3 + include/fsl-mc/fsl_dpmng.h | 121 ++++++++++++ include/{ => fsl-mc}/fsl_mc.h | 0 include/fsl-mc/fsl_mc_cmd.h | 132 +++++++++++++ include/fsl-mc/fsl_mc_sys.h | 26 +++ include/fsl_ddr.h | 23 ++- include/fsl_ddr_dimm_params.h | 2 +- 45 files changed, 1185 insertions(+), 298 deletions(-) create mode 100644 doc/README.fsl-trustzone-components rename drivers/net/{fsl_mc => fsl-mc}/Makefile (75%) create mode 100644 drivers/net/fsl-mc/dpmng.c create mode 100644 drivers/net/fsl-mc/fsl_dpmng_cmd.h rename drivers/net/{fsl_mc => fsl-mc}/mc.c (67%) create mode 100644 drivers/net/fsl-mc/mc_sys.c create mode 100644 include/fsl-mc/fsl_dpmng.h rename include/{ => fsl-mc}/fsl_mc.h (100%) create mode 100644 include/fsl-mc/fsl_mc_cmd.h create mode 100644 include/fsl-mc/fsl_mc_sys.h -- 1.7.9.5

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[U-Boot] [PATCH] edminiv2: switch to SPL
by Albert ARIBAUD 25 Feb '15

25 Feb '15

ED Mini V2 is based on Orion 5x which boots at fixed address 0xFFFF0000 in NOR Flash. Place SPL there, and switch U-Boot from .bin to .img format, stored in NOR Flash at 0xFFF90000. Note: this patch was tested on HW and works, i.e. it boots U-Boot properly, but SPL console output currently does not appear, due to GD being trashed by arch/arm/lib/spl.c. This trashing is soon to be removed, and then ED Mini V2 SPL console output will become visible. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/cpu/arm926ejs/orion5x/Kconfig | 1 + arch/arm/cpu/arm926ejs/orion5x/cpu.c | 2 + arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 14 +++++- arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds | 61 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-orion5x/spl.h | 10 +++++ board/LaCie/edminiv2/edminiv2.c | 20 +++++++++ configs/edminiv2_defconfig | 7 +-- include/configs/edminiv2.h | 23 +++++++++- 8 files changed, 132 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-orion5x/spl.h diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig index 5a54262..291c511 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig +++ b/arch/arm/cpu/arm926ejs/orion5x/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_EDMINIV2 bool "LaCie Ethernet Disk mini V2" + select SUPPORT_SPL endchoice diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index f88db3b..2ecd385 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -234,7 +234,9 @@ int arch_cpu_init(void) /* Enable and invalidate L2 cache in write through mode */ invalidate_l2_cache(); +#ifdef CONFIG_SPL_BUILD orion5x_config_adr_windows(); +#endif return 0; } diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S index 4dacc29..51a8b3c 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S @@ -62,14 +62,16 @@ /* * Low-level init happens right after start.S has switched to SVC32, * flushed and disabled caches and disabled MMU. We're still running - * from the boot chip select, so the first thing we should do is set - * up RAM for us to relocate into. + * from the boot chip select, so the first thing SPL should do is to + * set up the RAM to copy U-Boot into. */ .globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SPL_BUILD + /* Use 'r4 as the base for internal register accesses */ ldr r4, =ORION5X_REGS_PHY_BASE @@ -273,5 +275,13 @@ lowlevel_init: orr r2, r2, r6 str r2, [r3, #0x484] + /* enable for 2 GB DDR; detection should find out real amount */ + sub r6, r6, r6 + str r6, [r3, #0x500] + ldr r6, =0x7fff0001 + str r6, [r3, #0x504] + +#endif /* CONFIG_SPL_BUILD */ + /* Return to U-boot via saved link register */ mov pc, lr diff --git a/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds new file mode 100644 index 0000000..6f7fca0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/orion5x/u-boot-spl.lds @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot(a)aribaud.net> + * + * Based on: + * + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh(a)ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .nor : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .bss : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + CPUDIR/start.o (.text) + *(.text*) + } > .nor + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .nor + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .bss +} diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h new file mode 100644 index 0000000..23745bc --- /dev/null +++ b/arch/arm/include/asm/arch-orion5x/spl.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot(a)aribaud.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NOR 1 diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 80ec7fa..2983201 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -12,6 +12,8 @@ #include <miiphy.h> #include <asm/arch/orion5x.h> #include "../common/common.h" +#include <spl.h> +#include <ns16550.h> DECLARE_GLOBAL_DATA_PTR; @@ -83,3 +85,21 @@ void reset_phy(void) mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ + +/* + * SPL serial setup and NOR boot device selection + */ + +#ifdef CONFIG_SPL_BUILD + +void spl_board_init(void) +{ + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NOR; +} + +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index 3b1a6c1..20c1c65 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -1,3 +1,4 @@ -CONFIG_ARM=y -CONFIG_ORION5X=y -CONFIG_TARGET_EDMINIV2=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ORION5X=y ++S:CONFIG_TARGET_EDMINIV2=y diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 47da4a9..ee5f76b 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -13,10 +13,31 @@ #define _CONFIG_EDMINIV2_H /* general settings */ -#define CONFIG_SYS_TEXT_BASE 0xfff90000 #define CONFIG_SYS_GENERIC_BOARD /* + * SPL + */ + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NOR_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0xffff0000 +#define CONFIG_SPL_MAX_SIZE 0x0000fff0 +#define CONFIG_SPL_STACK 0x00020000 +#define CONFIG_SPL_BSS_START_ADDR 0x00020000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff +#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_UBOOT_BASE 0xfff90000 +#define CONFIG_SYS_UBOOT_START 0x00800000 +#define CONFIG_SYS_TEXT_BASE 0x00800000 + +/* * Version number information */ -- 2.1.0

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