January 2015 - U-Boot

[U-Boot] [PATCH] patman: Make dry-run output match real functionality
by Peter Tyser 15 Feb '15

15 Feb '15

When run with the --dry-run argument patman prints out information showing what it would do. This information currently doesn't line up with what patman/git send-email really do. Some basic examples: - If an email address is addressed via "Series-cc" and "Patch-cc" patman shows that email address would be CC-ed two times. - If an email address is addressed via "Series-to" and "Patch-cc" patman shows that email address would be sent TO and CC-ed. - If an email address is addressed from a combination of tag aliases, get_maintainer.pl output, "Series-cc", "Patch-cc", etc patman shows that the email address would be CC-ed multiple times. Patman currently does try to send duplicate emails like the --dry-run output shows, but "git send-email" intelligently removes duplicate addresses so this patch shouldn't change the non-dry-run functionality. Change patman's output and email addressing to line up with the "git send-email" logic. This trims down patman's dry-run output and prevents confusion about what patman will do when emails are actually sent. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- tools/patman/gitutil.py | 3 ++- tools/patman/series.py | 21 ++++++++------------- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index cc5a55a..c593070 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -392,7 +392,8 @@ def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, "Or do something like this\n" "git config sendemail.to u-boot(a)lists.denx.de") return - cc = BuildEmailList(series.get('cc'), '--cc', alias, raise_on_error) + cc = BuildEmailList(list(set(series.get('cc')) - set(series.get('to'))), + '--cc', alias, raise_on_error) if self_only: to = BuildEmailList([os.getenv('USER')], '--to', alias, raise_on_error) cc = [] diff --git a/tools/patman/series.py b/tools/patman/series.py index b67f870..60ebc76 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -94,6 +94,9 @@ class Series(dict): cmd: The git command we would have run process_tags: Process tags as if they were aliases """ + to_set = set(gitutil.BuildEmailList(self.to)); + cc_set = set(gitutil.BuildEmailList(self.cc)); + col = terminal.Color() print 'Dry run, so not doing much. But I would do this:' print @@ -106,24 +109,16 @@ class Series(dict): commit = self.commits[upto] print col.Color(col.GREEN, ' %s' % args[upto]) cc_list = list(self._generated_cc[commit.patch]) - - # Skip items in To list - if 'to' in self: - try: - map(cc_list.remove, gitutil.BuildEmailList(self.to)) - except ValueError: - pass - - for email in cc_list: + for email in set(cc_list) - to_set - cc_set: if email == None: email = col.Color(col.YELLOW, "<alias '%s' not found>" % tag) if email: print ' Cc: ',email print - for item in gitutil.BuildEmailList(self.get('to', '<none>')): + for item in to_set: print 'To:\t ', item - for item in gitutil.BuildEmailList(self.cc): + for item in cc_set - to_set: print 'Cc:\t ', item print 'Version: ', self.get('version') print 'Prefix:\t ', self.get('prefix') @@ -131,7 +126,7 @@ class Series(dict): print 'Cover: %d lines' % len(self.cover) cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) all_ccs = itertools.chain(cover_cc, *self._generated_cc.values()) - for email in set(all_ccs): + for email in set(all_ccs) - to_set - cc_set: print ' Cc: ',email if cmd: print 'Git command: %s' % cmd @@ -230,7 +225,7 @@ class Series(dict): if add_maintainers: list += get_maintainer.GetMaintainer(commit.patch) all_ccs += list - print >>fd, commit.patch, ', '.join(list) + print >>fd, commit.patch, ', '.join(set(list)) self._generated_cc[commit.patch] = list if cover_fname: -- 1.9.1

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[U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting
by Ye.Li 15 Feb '15

15 Feb '15

The I2C SDA and SCL require the IOMUX SION bit set to get input signal. Signed-off-by: Ye.Li <B37916(a)freescale.com> --- arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index 7c6c1e8..da8c698 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -420,7 +420,7 @@ enum { MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0), MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0), - MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0), + MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0), MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0), MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0), MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0), @@ -467,7 +467,7 @@ enum { MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0), - MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0), + MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0), MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0), MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0), MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0), -- 1.7.4.1

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[U-Boot] [PATCH 0/3] arm: reduce .bss section clear time
by Przemyslaw Marczak 13 Feb '15

13 Feb '15

This patchset reduces the boot time for ARM architecture, Exynos boards, and boards with DFU enabled(ARM). For tested Trats2 device, this was done in three steps. First was enable the arch memcpy and memset. The second step was enable memset for .bss clear. The third step for reduce this operation is to keep .bss section small as possible. The .bss section will grow if we have a lot of static variables. This section is cleared before jump to the relocated U-Boot, and it's done word by word. To reduce the time for this step, we can enable arch memset, which uses multiple ARM registers. For configs with DFU enabled, we can find the dfu buffer in this section, which has at least 8MB (32MB for trats2). This is a lot of useless data, which is not required for standard boot. So this buffer should be dynamic allocated. Przemyslaw Marczak (3): exynos: config: enable arch memcpy and arch memset arm: relocation: clear .bss section with arch memset if defined dfu: mmc: file buffer: remove static allocation arch/arm/lib/crt0.S | 10 +++++++++- drivers/dfu/dfu_mmc.c | 25 ++++++++++++++++++++++--- include/configs/exynos-common.h | 3 +++ 3 files changed, 34 insertions(+), 4 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] arm: exynos: fix the div value for set_mmc_clk
by Jaehoon Chung 13 Feb '15

13 Feb '15

The most exynos used the "Ratio + 1" as div value. And value at register is "Ratio". So if want to set exact value, it needs to subtract one. Value at register ("Ratio") = div - 1 Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b31c13b..3110bb0 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1656,6 +1656,10 @@ unsigned long get_mmc_clk(int dev_index) void set_mmc_clk(int dev_index, unsigned int div) { + /* If want to set correct value, it needs to substract one from div.*/ + if (div > 0) + div -= 1; + if (cpu_is_exynos5()) { if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); -- 1.9.1

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[U-Boot] [PATCH v2 0/3] Support eMMC reset using DT for some exynos boards
by Joonyoung Shim 13 Feb '15

13 Feb '15

This patchset is to support eMMC reset using DT for some exynos boards e.g. Odroid X2/U3/XU3. It needs to reset eMMC memory to perform complete reboot, so we should handle nRESET_OUT line specially. nRESET_OUT line is connected to gpio and it can have different gpio by boards, so we will get gpio from DT. This patchset is based on http://git.denx.de/u-boot-dm.git gpio-working branch. Thanks. Changes from v1: - s/SD4_nRESET_OUT/nRESET_OUT - Remove codes for non DT case - Add comments about eMMC reset delay time Joonyoung Shim (3): samsung: board: support eMMC reset using DT Odroid: Add eMMC-reset node on DT Odroid-XU3: Add eMMC-reset node on DT arch/arm/dts/exynos4412-odroid.dts | 5 +++++ arch/arm/dts/exynos5422-odroidxu3.dts | 5 +++++ board/samsung/common/board.c | 28 ++++++++++++++++++++++++++++ board/samsung/odroid/odroid.c | 8 -------- doc/device-tree-bindings/exynos/emmc-reset.txt | 15 +++++++++++++++ 5 files changed, 53 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/exynos/emmc-reset.txt

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[U-Boot] [PATCH] odroid: fix g2d sclk rate
by Joonyoung Shim 13 Feb '15

13 Feb '15

G2D core should be provided 200MHz clock rate. Signed-off-by: Joonyoung Shim <jy0922.shim(a)samsung.com> --- board/samsung/odroid/odroid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index b7d2381..1554b9d 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -248,12 +248,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); -- 1.9.1

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[U-Boot] [PATCH] EXYNOS5: Add function to enable exynos5420 usbdev phy ctrl
by Joonyoung Shim 13 Feb '15

13 Feb '15

Exynos5420 has different registers with other exynos5 SoCs to control usb device phy, so need separated function to enable exynos5420 usb device phy. Signed-off-by: Joonyoung Shim <jy0922.shim(a)samsung.com> --- I used "usbdev" instead of "usbdrd" on function name because registers name prefix is usbdev_. arch/arm/cpu/armv7/exynos/power.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 1520d64..1b12051 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -102,10 +102,34 @@ static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) } } +static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable) +{ + struct exynos5420_power *power = + (struct exynos5420_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBDEV_PHY */ + setbits_le32(&power->usbdev_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + setbits_le32(&power->usbdev1_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } else { + /* Disabling USBDEV_PHY */ + clrbits_le32(&power->usbdev_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + clrbits_le32(&power->usbdev1_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } +} + void set_usbdrd_phy_ctrl(unsigned int enable) { - if (cpu_is_exynos5()) - exynos5_set_usbdrd_phy_ctrl(enable); + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + exynos5420_set_usbdev_phy_ctrl(enable); + else + exynos5_set_usbdrd_phy_ctrl(enable); + } } static void exynos5_dp_phy_control(unsigned int enable) -- 1.9.1

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[U-Boot] [PATCH 01/10] arm: socfpga: Minor coding style fix
by Marek Vasut 12 Feb '15

12 Feb '15

Replace multiple spaces with a single tab. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> Acked-by: Pavel Machek <pavel(a)denx.de> Reviewed-by: Stefan Roese <sr(a)denx.de> Cc: Vince Bridgers <vbridger(a)opensource.altera.com> --- board/altera/socfpga/iocsr_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h index 490f109..4a7ed46 100644 --- a/board/altera/socfpga/iocsr_config.h +++ b/board/altera/socfpga/iocsr_config.h @@ -9,9 +9,9 @@ #ifndef _PRELOADER_IOCSR_CONFIG_H_ #define _PRELOADER_IOCSR_CONFIG_H_ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) #endif /*_PRELOADER_IOCSR_CONFIG_H_*/ -- 2.1.3

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[U-Boot] [PATCH 0/2] Fastboot OEM commands
by Rob Herring 12 Feb '15

12 Feb '15

This series adds fastboot oem sub-command infrastructure and support for "oem format" command which partitions and formats the storage device. The partition layout is set within the u-boot env and is implemented using the "gpt write" command. Rob Michael Scott (1): fastboot: add "fastboot oem" command support Rob Herring (1): fastboot: add support for "oem format" command drivers/usb/gadget/f_fastboot.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.1.0

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[U-Boot] [PATCH v3 0/12] Add support for caching Memory Reference Code data
by Simon Glass 11 Feb '15

11 Feb '15

Since the memory reference code is so slow on x86, add a feature to bypass this, storing the previous parameters in SPI flash. This saves around 500ms on each boot. Also enable a SPI flash environment. Changes in v3: - Add new patch to move checksum to its own file in net/ - Adjust net/ code to use the new checksum functions - Use checksum code that is now in net/checksum.c - Adjust functions to remain compatible with other RTC drivers - Drop accidental creation of link.dts due to bad rebase - Use checksum code from net/checksum.c - Add misc_init_r() call for link now that it is shared with chromebook_link Changes in v2: - Use intel,ich-spi as the compatible string - Refactor IP checksum patches - Adjust the mc146818 driver instead of adding a new cmos.h header - Make changes to chromebook_link.dts since link.dts is gone - Use intel,ich-spi as the compatible string - Update for the new CMOS RAM access functions in the RTC - Add a comment about why both CMOS RAM and SPI flash are used for the cache Simon Glass (12): x86: dts: Add compatible string for Intel ICH9 SPI controller net: Add a separate file for IP checksumming net: Use new checksum functions x86: Use ipchecksum from net/ x86: rtc: mc146818: Add helpers to read/write CMOS RAM x86: spi: Add device tree support Allow architecture-specific memory reservation x86: dts: Add SPI flash MRC details for chromebook_link x86: Implement a cache for Memory Reference Code parameters x86: config: Enable hook for saving MRC configuration x86: ivybridge: Drop the Kconfig MRC cache information x86: config: chromebook_link: Enable environment arch/x86/cpu/coreboot/Makefile | 1 - arch/x86/cpu/coreboot/coreboot.c | 5 + arch/x86/cpu/coreboot/ipchecksum.c | 55 ------ arch/x86/cpu/coreboot/tables.c | 8 +- arch/x86/cpu/ivybridge/Kconfig | 28 --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/mrccache.c | 156 +++++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 253 ++++++++++++++++++++++++ arch/x86/dts/chromebook_link.dts | 15 +- arch/x86/include/asm/arch-coreboot/ipchecksum.h | 37 ---- arch/x86/include/asm/arch-ivybridge/mrccache.h | 51 +++++ arch/x86/include/asm/global_data.h | 3 + common/board_f.c | 7 + drivers/rtc/mc146818.c | 121 +++++++----- drivers/spi/ich.c | 7 + include/configs/chromebook_link.h | 8 + include/configs/x86-common.h | 1 + include/fdtdec.h | 1 + include/net.h | 32 ++- include/rtc.h | 32 +++ lib/fdtdec.c | 1 + net/Makefile | 1 + net/checksum.c | 60 ++++++ net/net.c | 25 +-- net/ping.c | 10 +- 25 files changed, 713 insertions(+), 206 deletions(-) delete mode 100644 arch/x86/cpu/coreboot/ipchecksum.c create mode 100644 arch/x86/cpu/ivybridge/mrccache.c delete mode 100644 arch/x86/include/asm/arch-coreboot/ipchecksum.h create mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h create mode 100644 net/checksum.c -- 2.2.0.rc0.207.ga3a616c

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