January 2015 - U-Boot

[U-Boot] please pull u-boot-arc master
by Alexey Brodkin 10 Apr '15

10 Apr '15

Dear Tom, The following changes since commit b188067f39627d977bb1db67c8456e9aaab90743: arm: vf610: fix boot from SD-card (2015-01-09 10:27:51 -0500) are available in the git repository at: git://git.denx.de/u-boot-arc.git for you to fetch changes up to 4c8c485ad9249e1ca1822474954b78799ca937e9: arc: introduce "mdbtrick" target (2015-01-09 23:59:54 +0300) ---------------------------------------------------------------- Alexey Brodkin (1): arc: introduce "mdbtrick" target arch/arc/Makefile | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- Best regards, Alexey

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Re: [U-Boot] Regarding patch: http://patchwork.ozlabs.org/patch/373593/
by Marek Vasut 07 Apr '15

07 Apr '15

On Thursday, December 18, 2014 at 09:32:56 AM, Ramneek Mehresh wrote: > Hi Marex, > > Following u-boot patch is pending for your review for some time. Please let > me know if you have any concerns. fsl/usb: Add USB XHCI support: > http://patchwork.ozlabs.org/patch/373593/ I missed the patch completely, sorry. Next time, please keep me on CC when submitting the patches, that helps a lot. As for the board_usb_init, you can drop the inline and the __board_usb_init() and do: __weak int board_usb_init(int index, enum usb_init_type init) { return 0; } The static void fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) must shut down the controller, which I don't see happening. Why? Thanks! Best regards, Marek Vasut

3 13

[U-Boot] [RFC PATCH] ARM: Merge v7 and v8 outer cache operations
by fenghua＠phytium.com.cn 02 Apr '15

02 Apr '15

From: David Feng <fenghua(a)phytium.com.cn> Armv7 and Armv8 allow outer cache exist, it is outside of the architecture defined cache hierarchy and can not be manipulated by architecture defined instructions. It's processor specific. This patch merge v7_outer_cache_* and v8 l3_cache_*. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- arch/arm/cpu/armv7/cache_v7.c | 22 +++++++++++----------- arch/arm/cpu/armv7/cpu.c | 2 +- arch/arm/cpu/armv7/exynos/soc.c | 2 +- arch/arm/cpu/armv7/mx6/soc.c | 4 ++-- arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/cpu/armv7/s5pc1xx/cache.c | 4 ++-- arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 14 +++++++------- arch/arm/cpu/armv8/cache_v8.c | 21 ++++++++++++++++----- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 2 +- arch/arm/include/asm/armv7.h | 7 ------- arch/arm/include/asm/cache.h | 7 +++++++ arch/arm/include/asm/system.h | 2 -- arch/arm/lib/cache-pl310.c | 12 ++++++------ 14 files changed, 57 insertions(+), 48 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 0f9d837..7d4d5d3 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -237,7 +237,7 @@ void invalidate_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - v7_outer_cache_inval_all(); + outer_cache_inval_all(); } /* @@ -248,7 +248,7 @@ void flush_dcache_all(void) { v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL); - v7_outer_cache_flush_all(); + outer_cache_flush_all(); } /* @@ -259,7 +259,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) { v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - v7_outer_cache_inval_range(start, stop); + outer_cache_inval_range(start, stop); } /* @@ -271,12 +271,12 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); - v7_outer_cache_flush_range(start, stop); + outer_cache_flush_range(start, stop); } void arm_init_before_mmu(void) { - v7_outer_cache_enable(); + outer_cache_enable(); invalidate_dcache_all(); v7_inval_tlb(); } @@ -355,9 +355,9 @@ void invalidate_icache_all(void) #endif /* Stub implementations for outer cache operations */ -__weak void v7_outer_cache_enable(void) {} -__weak void v7_outer_cache_disable(void) {} -__weak void v7_outer_cache_flush_all(void) {} -__weak void v7_outer_cache_inval_all(void) {} -__weak void v7_outer_cache_flush_range(u32 start, u32 end) {} -__weak void v7_outer_cache_inval_range(u32 start, u32 end) {} +__weak void outer_cache_enable(void) {} +__weak void outer_cache_disable(void) {} +__weak void outer_cache_flush_all(void) {} +__weak void outer_cache_inval_all(void) {} +__weak void outer_cache_flush_range(unsigned long start, unsigned long end) {} +__weak void outer_cache_inval_range(unsigned long start, unsigned long end) {} diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 01cdb7e..07ad549 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -47,7 +47,7 @@ int cleanup_before_linux(void) * dcache_disable() in turn flushes the d-cache and disables MMU */ dcache_disable(); - v7_outer_cache_disable(); + outer_cache_disable(); /* * After D-cache is flushed and before it is disabled there may diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index 8c7d7d8..3813c6c 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -50,7 +50,7 @@ static void exynos5_set_l2cache_params(void) /* * Sets L2 cache related parameters before enabling data cache */ -void v7_outer_cache_enable(void) +void outer_cache_enable(void) { if (cpu_is_exynos5()) exynos5_set_l2cache_params(); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5f5f497..e3f0fdd 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -472,7 +472,7 @@ void imx_setup_hdmi(void) #ifndef CONFIG_SYS_L2CACHE_OFF #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 -void v7_outer_cache_enable(void) +void outer_cache_enable(void) { struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; unsigned int val; @@ -521,7 +521,7 @@ void v7_outer_cache_enable(void) setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } -void v7_outer_cache_disable(void) +void outer_cache_disable(void) { struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 90d6ae7..d5e215d 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -470,7 +470,7 @@ static void omap3_invalidate_l2_cache_secure(void) } } -void v7_outer_cache_enable(void) +void outer_cache_enable(void) { /* Set L2EN */ omap3_update_aux_cr_secure(0x2, 0); diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index db16548..9841aaa 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -157,12 +157,12 @@ void init_omap_revision(void) } #ifndef CONFIG_SYS_L2CACHE_OFF -void v7_outer_cache_enable(void) +void outer_cache_enable(void) { set_pl310_ctrl_reg(1); } -void v7_outer_cache_disable(void) +void outer_cache_disable(void) { set_pl310_ctrl_reg(0); } diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c index 51af299..de6f08d 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.c +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c @@ -23,7 +23,7 @@ void disable_caches(void) #endif #ifndef CONFIG_SYS_L2CACHE_OFF -void v7_outer_cache_enable(void) +void outer_cache_enable(void) { __asm( "push {r0, r1, r2, lr}\n\t" @@ -34,7 +34,7 @@ void v7_outer_cache_enable(void) ); } -void v7_outer_cache_disable(void) +void outer_cache_disable(void) { __asm( "push {r0, r1, r2, lr}\n\t" diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c index e47f977..76487cb 100644 --- a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c +++ b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c @@ -29,12 +29,12 @@ static void uniphier_cache_maint_all(u32 operation) readl(SSCOPE); /* need a read back to confirm */ } -void v7_outer_cache_flush_all(void) +void outer_cache_flush_all(void) { uniphier_cache_maint_all(SSCOQM_CM_WB_INV); } -void v7_outer_cache_inval_all(void) +void outer_cache_inval_all(void) { uniphier_cache_maint_all(SSCOQM_CM_INV); } @@ -92,17 +92,17 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) readl(SSCOPE); /* need a read back to confirm */ } -void v7_outer_cache_flush_range(u32 start, u32 end) +void outer_cache_flush_range(u32 start, u32 end) { uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV); } -void v7_outer_cache_inval_range(u32 start, u32 end) +void outer_cache_inval_range(u32 start, u32 end) { uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); } -void v7_outer_cache_enable(void) +void outer_cache_enable(void) { u32 tmp; tmp = readl(SSCC); @@ -111,7 +111,7 @@ void v7_outer_cache_enable(void) } #endif -void v7_outer_cache_disable(void) +void outer_cache_disable(void) { u32 tmp; tmp = readl(SSCC); @@ -141,7 +141,7 @@ void enable_caches(void) */ /* L2 disable */ - v7_outer_cache_disable(); + outer_cache_disable(); /* L1 disable */ reg = get_cr(); diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 9dbcdf2..e4415e8 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -11,6 +11,16 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Stubs for outer cache operations + */ +__weak void outer_cache_enable(void) {} +__weak void outer_cache_disable(void) {} +__weak void outer_cache_flush_all(void) {} +__weak void outer_cache_inval_all(void) {} +__weak void outer_cache_flush_range(unsigned long start, unsigned long end) {} +__weak void outer_cache_inval_range(unsigned long start, unsigned long end) {} + #ifndef CONFIG_SYS_DCACHE_OFF void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type) @@ -71,10 +81,7 @@ static void mmu_setup(void) void invalidate_dcache_all(void) { __asm_invalidate_dcache_all(); -} - -void __weak flush_l3_cache(void) -{ + outer_cache_inval_all(); } /* @@ -83,7 +90,7 @@ void __weak flush_l3_cache(void) void flush_dcache_all(void) { __asm_flush_dcache_all(); - flush_l3_cache(); + outer_cache_flush_all(); } /* @@ -92,6 +99,7 @@ void flush_dcache_all(void) void invalidate_dcache_range(unsigned long start, unsigned long stop) { __asm_flush_dcache_range(start, stop); + outer_cache_inval_range(start, stop); } /* @@ -100,12 +108,14 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) void flush_dcache_range(unsigned long start, unsigned long stop) { __asm_flush_dcache_range(start, stop); + outer_cache_flush_range(start, stop); } void dcache_enable(void) { /* The data cache is not active unless the mmu is enabled */ if (!(get_sctlr() & CR_M)) { + outer_cache_enable(); invalidate_dcache_all(); __asm_invalidate_tlb_all(); mmu_setup(); @@ -128,6 +138,7 @@ void dcache_disable(void) flush_dcache_all(); __asm_invalidate_tlb_all(); + outer_cache_disable(); } int dcache_status(void) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 47b947f..1f36f7e 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -275,7 +275,7 @@ static void hnf_pstate_req(u64 *ptr, u64 state) } } -void flush_l3_cache(void) +void outer_cache_flush_all(void) { hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY); hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY); diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23..004434f 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -69,13 +69,6 @@ #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) -void v7_outer_cache_enable(void); -void v7_outer_cache_disable(void); -void v7_outer_cache_flush_all(void); -void v7_outer_cache_inval_all(void); -void v7_outer_cache_flush_range(u32 start, u32 end); -void v7_outer_cache_inval_range(u32 start, u32 end); - #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) int armv7_init_nonsec(void); diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index a836e9f..5a4ac2f 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -36,6 +36,13 @@ void dram_bank_mmu_setup(int bank); #endif +void outer_cache_enable(void); +void outer_cache_disable(void); +void outer_cache_flush_all(void); +void outer_cache_inval_all(void); +void outer_cache_flush_range(unsigned long start, unsigned long end); +void outer_cache_inval_range(unsigned long start, unsigned long end); + /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 89f2294..3b0fd0d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -78,8 +78,6 @@ void gic_send_sgi(unsigned long sgino); void wait_for_wakeup(void); void smp_kick_all_cpus(void); -void flush_l3_cache(void); - #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 1ad1f8a..4735407 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -39,18 +39,18 @@ static void pl310_background_op_all_ways(u32 *op_reg) pl310_cache_sync(); } -void v7_outer_cache_inval_all(void) +void outer_cache_inval_all(void) { pl310_background_op_all_ways(&pl310->pl310_inv_way); } -void v7_outer_cache_flush_all(void) +void outer_cache_flush_all(void) { pl310_background_op_all_ways(&pl310->pl310_clean_inv_way); } /* Flush(clean invalidate) memory from start to stop-1 */ -void v7_outer_cache_flush_range(u32 start, u32 stop) +void outer_cache_flush_range(unsigned long start, unsigned long stop) { /* PL310 currently supports only 32 bytes cache line */ u32 pa, line_size = 32; @@ -68,7 +68,7 @@ void v7_outer_cache_flush_range(u32 start, u32 stop) } /* invalidate memory from start to stop-1 */ -void v7_outer_cache_inval_range(u32 start, u32 stop) +void outer_cache_inval_range(unsigned long start, unsigned long stop) { /* PL310 currently supports only 32 bytes cache line */ u32 pa, line_size = 32; @@ -78,7 +78,7 @@ void v7_outer_cache_inval_range(u32 start, u32 stop) * invalidate the first cache-line */ if (start & (line_size - 1)) { - printf("ERROR: %s - start address is not aligned - 0x%08x\n", + printf("ERROR: %s - start address is not aligned - 0x%lx\n", __func__, start); /* move to next cache line */ start = (start + line_size - 1) & ~(line_size - 1); @@ -89,7 +89,7 @@ void v7_outer_cache_inval_range(u32 start, u32 stop) * invalidate the last cache-line */ if (stop & (line_size - 1)) { - printf("ERROR: %s - stop address is not aligned - 0x%08x\n", + printf("ERROR: %s - stop address is not aligned - 0x%lx\n", __func__, stop); /* align to the beginning of this cache line */ stop &= ~(line_size - 1); -- 1.7.9.5

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[U-Boot] [PATCH 0/6] ARM: at91: SAMA5: extract the common sama5 chip configurations to a common header
by Josh Wu 30 Mar '15

30 Mar '15

This patch series reorganized the configurations for SAMA5 chips. Make the common part into one file. That way we don't need to have many copy of the same configurations. Josh Wu (6): ARM: at91: sama5d3_xplained: spl: enable PMECC header generation ARM: at91: sama5: move the common part of configurations to at91-sama5_common.h ARM: at91: sama5d3_xplained: set ENV_FAT_DEVICE_AND_PART intead of using number ARM: at91: sama5d3: mmc: save enviroment as a fat file (uboot.env) ARM: at91: sama5: move the bootcmd definition to the common header ARM: at91: at91sam9x5: mmc: save environment as a file in FAT partition. include/configs/at91-sama5_common.h | 126 ++++++++++++++++++++++++++++++++++++ include/configs/at91sam9x5ek.h | 12 ++-- include/configs/sama5d3_xplained.h | 100 ++-------------------------- include/configs/sama5d3xek.h | 114 ++------------------------------ include/configs/sama5d4_xplained.h | 116 ++------------------------------- include/configs/sama5d4ek.h | 116 ++------------------------------- 6 files changed, 153 insertions(+), 431 deletions(-) create mode 100644 include/configs/at91-sama5_common.h -- 1.9.1

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[U-Boot] [PATCH] ARMv8: bug fix of mmu setup and code optimization
by fenghua＠phytium.com.cn 27 Mar '15

27 Mar '15

From: David Feng <fenghua(a)phytium.com.cn> 1. Fix a bug of mmu_setup that variable i and j should be type long instead of int. 2. Give mmu_setup weak attribute so that other implementation can redfine it. 3. A more common set_pgtable_section(). 4. Give device memory PXN and UXN attribute. CPU may speculatively prefetch instructions from device memory, but the IO subsystem of some implementation may not support this operation. The two attributes prevent this behavior. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- arch/arm/cpu/armv8/cache_v8.c | 73 +++++++++++++++++++++++------------- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 22 +++++------ arch/arm/include/asm/armv8/mmu.h | 71 +++++++++++++++++++---------------- 3 files changed, 95 insertions(+), 71 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index e4415e8..023dd23 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -22,55 +22,74 @@ __weak void outer_cache_flush_range(unsigned long start, unsigned long end) {} __weak void outer_cache_inval_range(unsigned long start, unsigned long end) {} #ifndef CONFIG_SYS_DCACHE_OFF -void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type) -{ - u64 value; - value = section | PMD_TYPE_SECT | PMD_SECT_AF; - value |= PMD_ATTRINDX(memory_type); - page_table[index] = value; +/* 42 bits virtual address */ +#define VA_BITS (42) + +/* 42 bits physical address */ +#define TCR_EL1_IPS_BITS TCR_EL1_IPS_BITS_42 +#define TCR_EL2_IPS_BITS TCR_EL2_IPS_BITS_42 +#define TCR_EL3_IPS_BITS TCR_EL3_IPS_BITS_42 + +/* PTWs cacheable, inner/outer WBWA and inner-shareable */ +#define TCR_FLAGS (TCR_TG0_64K | \ + TCR_SHARED_INNER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(VA_BITS)) + +void set_pgtable_section(u64 *page_table, u64 index, u64 output_address, + u64 memory_type, u64 extra_flags) +{ + page_table[index] = output_address | PMD_TYPE_SECT | PMD_SECT_AF | + PMD_SECT_SHARED_INNER | PMD_ATTRINDX(memory_type) | + extra_flags; } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +void __weak mmu_setup(void) { - int i, j, el; + int el; + u64 i, j, tcr; bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr; /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, + PMD_SECT_PXN | PMD_SECT_UXN); + } - /* Setup an identity-mapping for all RAM space */ + /* + * Setup an identity-mapping for all RAM space. + * The secure or non-secure memory access make sense + * when u-boot running at el3 and is mostly implementation + * specific. + */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ulong start = bd->bi_dram[i].start; - ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; + u64 start = bd->bi_dram[i].start; + u64 end = bd->bi_dram[i].start + bd->bi_dram[i].size; for (j = start >> SECTION_SHIFT; j < end >> SECTION_SHIFT; j++) { set_pgtable_section(page_table, j, j << SECTION_SHIFT, - MT_NORMAL); + MT_NORMAL, PMD_SECT_NS); } } /* load TTBR0 */ + tcr = TCR_FLAGS; el = current_el(); - if (el == 1) { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL1_IPS_BITS, - MEMORY_ATTRIBUTES); - } else if (el == 2) { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL2_IPS_BITS, - MEMORY_ATTRIBUTES); - } else { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL3_IPS_BITS, - MEMORY_ATTRIBUTES); - } + if (el == 1) + tcr |= TCR_EL1_IPS_BITS; + else if (el == 2) + tcr |= TCR_EL2_IPS_BITS; + else + tcr |= TCR_EL3_IPS_BITS; + + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, tcr, MEMORY_ATTRIBUTES); + /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 1f36f7e..bcd2cf2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -82,11 +82,11 @@ static inline void early_mmu_setup(void) section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); + MT_NORMAL, 0); set_pgtable_section(level2_table, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; section_l2 += BLOCK_SIZE_L2; @@ -108,13 +108,13 @@ static inline void early_mmu_setup(void) set_pgtable_section(level2_table, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + MT_NORMAL, 0); for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) >> SECTION_SHIFT_L2; i++) { section_l2 = i << SECTION_SHIFT_L2; set_pgtable_section(level2_table, i, - section_l2, MT_NORMAL); + section_l2, MT_NORMAL, 0); } el = current_el(); @@ -154,11 +154,11 @@ static inline void final_mmu_setup(void) section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); + MT_NORMAL, 0); set_pgtable_section(level2_table_0, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; section_l2 += BLOCK_SIZE_L2; @@ -177,7 +177,7 @@ static inline void final_mmu_setup(void) set_pgtable_section(level2_table_0, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + MT_NORMAL, 0); /* * Fill in other part of tables if cache is needed @@ -190,7 +190,7 @@ static inline void final_mmu_setup(void) section_l2 = section_base; for (i = 0; i < 512; i++) { set_pgtable_section(level2_table_1, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l2 += BLOCK_SIZE_L2; } tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); @@ -200,7 +200,7 @@ static inline void final_mmu_setup(void) i < tbl_limit >> SECTION_SHIFT_L2; i++) { section_l2 = section_base + (i << SECTION_SHIFT_L2); set_pgtable_section(level2_table_1, i, - section_l2, MT_NORMAL); + section_l2, MT_NORMAL, 0); } /* flush new MMU table */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b7b67b..2ae5ab6 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -16,27 +16,6 @@ #define UL(x) _AC(x, UL) -/***************************************************************/ -/* - * The following definitions are related each other, shoud be - * calculated specifically. - */ -#define VA_BITS (42) /* 42 bits virtual address */ - -/* PAGE_SHIFT determines the page size */ -#undef PAGE_SIZE -#define PAGE_SHIFT 16 -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -/* - * section address mask and size definitions. - */ -#define SECTION_SHIFT 29 -#define SECTION_SIZE (UL(1) << SECTION_SHIFT) -#define SECTION_MASK (~(SECTION_SIZE-1)) -/***************************************************************/ - /* * Memory types */ @@ -65,7 +44,10 @@ /* * Section */ -#define PMD_SECT_S (3 << 8) +#define PMD_SECT_NS (1 << 5) +#define PMD_SECT_SHARED_NON (0 << 8) +#define PMD_SECT_SHARED_OUTER (2 << 8) +#define PMD_SECT_SHARED_INNER (3 << 8) #define PMD_SECT_AF (1 << 10) #define PMD_SECT_NG (1 << 11) #define PMD_SECT_PXN (UL(1) << 53) @@ -97,20 +79,42 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) -#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ -#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ -#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#define TCR_EL1_IPS_BITS_32 (UL(0) << 32) /* 32 bits physical address */ +#define TCR_EL1_IPS_BITS_36 (UL(1) << 32) /* 36 bits physical address */ +#define TCR_EL1_IPS_BITS_40 (UL(2) << 32) /* 40 bits physical address */ +#define TCR_EL1_IPS_BITS_42 (UL(3) << 32) /* 42 bits physical address */ +#define TCR_EL1_IPS_BITS_44 (UL(4) << 32) /* 44 bits physical address */ +#define TCR_EL1_IPS_BITS_48 (UL(5) << 32) /* 48 bits physical address */ +#define TCR_EL2_IPS_BITS_32 (0 << 16) /* 32 bits physical address */ +#define TCR_EL2_IPS_BITS_36 (1 << 16) /* 36 bits physical address */ +#define TCR_EL2_IPS_BITS_40 (2 << 16) /* 40 bits physical address */ +#define TCR_EL2_IPS_BITS_42 (3 << 16) /* 42 bits physical address */ +#define TCR_EL2_IPS_BITS_44 (4 << 16) /* 44 bits physical address */ +#define TCR_EL2_IPS_BITS_48 (5 << 16) /* 48 bits physical address */ +#define TCR_EL3_IPS_BITS_32 TCR_EL2_IPS_BITS_32 +#define TCR_EL3_IPS_BITS_36 TCR_EL2_IPS_BITS_36 +#define TCR_EL3_IPS_BITS_40 TCR_EL2_IPS_BITS_40 +#define TCR_EL3_IPS_BITS_42 TCR_EL2_IPS_BITS_42 +#define TCR_EL3_IPS_BITS_44 TCR_EL2_IPS_BITS_44 +#define TCR_EL3_IPS_BITS_48 TCR_EL2_IPS_BITS_48 -/* PTWs cacheable, inner/outer WBWA and non-shareable */ -#define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(VA_BITS)) +/***************************************************************/ +/* PAGE_SHIFT determines the page size */ +#undef PAGE_SIZE +#define PAGE_SHIFT 16 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +/* Section address mask and size definitions */ +#define SECTION_SHIFT 29 +#define SECTION_SIZE (UL(1) << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) +/***************************************************************/ #ifndef __ASSEMBLY__ -void set_pgtable_section(u64 *page_table, u64 index, - u64 section, u64 memory_type); +void set_pgtable_section(u64 *page_table, u64 index, u64 output_address, + u64 memory_type, u64 extra_flags); + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -132,4 +136,5 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) asm volatile("isb"); } #endif + #endif /* _ASM_ARMV8_MMU_H_ */ -- 1.7.9.5

2 1

[U-Boot] [RFC PATCH 0/7] Add Driver Model support to network stack
by Joe Hershberger 23 Mar '15

23 Mar '15

For now this simply addresses the MAC part of the network hardware. The next part to implement is the PHY children. I wanted to get early feedback on what I have so far to make sure I'm going in the direction that Simon envisioned. Joe Hershberger (7): net: Provide a function to get the current MAC address net: Rename helper function to be more clear net: Remove unneeded "extern" in net.h net: Refactor in preparation for driver model net: Add basic driver model support to Ethernet stack net: Add network support to sandbox net: Add ARP and PING response to sandbox driver arch/mips/cpu/mips32/au1x00/au1x00_eth.c | 2 +- arch/powerpc/cpu/mpc8260/ether_fcc.c | 2 +- arch/powerpc/cpu/mpc85xx/ether_fcc.c | 2 +- arch/powerpc/cpu/mpc8xx/scc.c | 2 +- arch/sandbox/dts/sandbox.dts | 4 + common/board_r.c | 4 +- common/cmd_bdinfo.c | 2 + drivers/net/Makefile | 2 + drivers/net/sandbox.c | 166 +++++++++++++ include/configs/sandbox.h | 14 +- include/dm/uclass-id.h | 1 + include/net.h | 158 +++++++----- net/eth.c | 408 +++++++++++++++++++++++++++---- net/net.c | 2 +- 14 files changed, 649 insertions(+), 120 deletions(-) create mode 100644 drivers/net/sandbox.c -- 1.7.11.5

4 280

[U-Boot] How do I use AM335x eth1 rather than eth0 ?
by Mark Jackson 17 Mar '15

17 Mar '15

We have a dual Ethernet board (based on the BeagelBone) but with both Ethernet ports connected. I'm wanting to use eth1 (rather than eth0), so in my board.c file, I changed:- static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_id = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_id = 1, }, }; ... to ... static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_id = 1, }, { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_id = 0, }, }; ... assuming that eth0 would now be ignored (as only 1 slave is configured). But (eg) dhcp still only responds on eth0 !?! What else do I have to change ? Cheers Mark J.

4 5

[U-Boot] [PATCH v2] mmc: fsl_esdhc: Add support for DDR mode
by Volodymyr Riazantsev 12 Mar '15

12 Mar '15

Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Change-Id: Ie27a945c9fe79d044cc886e269b60747f1744116 Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev(a)globallogic.com> --- drivers/mmc/fsl_esdhc.c | 8 ++++++-- include/configs/mx6_common.h | 2 ++ include/fsl_esdhc.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c55eb28..f5d2ccb 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) esdhc_write32(&regs->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) esdhc_write32(&regs->mixctrl, - (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) + | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(&regs->xfertyp, xfertyp); @@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) if ((sdhc_clk / (div * pre_div)) <= clock) break; - pre_div >>= 1; + pre_div >>= mmc->ddr_mode ? 2 : 1; div -= 1; clk = (pre_div << 8) | (div << 4); @@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) } cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; +#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; +#endif if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce..29b72b2 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_MP #define CONFIG_MXC_GPT_HCLK diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648..313fa1e 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -108,6 +108,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001 -- 2.2.0

4 8

[U-Boot] [RFC PATCH 0/7] RFC: dm: Add USB support
by Simon Glass 09 Mar '15

09 Mar '15

This series adds basic driver model support to USB. The intent is to permit the various subsystems (OHCI, EHCI, XHCI) to co-exist and allow any number of USB ports of different types. So far the absolute limit on the number of USB devices is only slightly relaxed. Only USB controllers have a real driver model device. USB devices (including the hub in the controller) are not modelled as driver model devices. This is for two reasons: - it is easier since we don't need to bind a whole lot of devices when scanning - the two main USB devices (block devices and Ethernet) don't have driver mode support yet anyway, so it would be pointless. However the recent network RFC has encouraged me to send this. The basic approach is to set up the driver model structures in parallel to what already exists rather than to replace them. This allows both driver model and legacy to be used for USB, although not with the same board. So far only XHCI is supported. As an example the Exynos XHCI driver is converted to driver model. I would appreciate comments before going further. Caveats: - sandbox code is incomplete and there are no tests - 'usb stop' does not remove existing devices (I have not yet settled on the best approach) - the usb.h changes need to be split correctly into the patches once they are final This series is available at u-boot-dm/usb-working. Simon Glass (7): dm: usb: Add a uclass for USB controllers dm: usb: Support driver model in exynos XHCI dm: usb: Adjust users of the USB stack to work with driver model dm: usb: WIP sandbox USB implementation dm: core: Add a function to get the uclass data for a device arm: Show relocated PC/LR in the register dump dm: exynos: Enable driver model for snow XHCI Makefile | 1 + arch/arm/lib/interrupts.c | 13 +- arch/sandbox/dts/sandbox.dts | 20 +++ arch/sandbox/include/asm/processor.h | 0 common/cmd_usb.c | 74 ++++++++--- common/usb.c | 28 +++-- common/usb_hub.c | 13 +- common/usb_storage.c | 148 +++++++++++++--------- drivers/core/device.c | 10 ++ drivers/usb/dev/Makefile | 10 ++ drivers/usb/dev/sandbox-flash.c | 95 +++++++++++++++ drivers/usb/dev/sandbox-hub.c | 116 ++++++++++++++++++ drivers/usb/dev/usb-emul-uclass.c | 16 +++ drivers/usb/eth/usb_ether.c | 46 +++++-- drivers/usb/host/Makefile | 5 + drivers/usb/host/usb-sandbox.c | 151 +++++++++++++++++++++++ drivers/usb/host/usb-uclass.c | 227 ++++++++++++++++++++++++++++++++++ drivers/usb/host/xhci-exynos5.c | 115 +++++++++++++++++- drivers/usb/host/xhci.c | 229 ++++++++++++++++++++++++++++------- drivers/usb/host/xhci.h | 24 ++++ include/configs/sandbox.h | 3 + include/configs/snow.h | 1 + include/dm/device.h | 10 ++ include/dm/uclass-id.h | 2 + include/usb.h | 76 +++++++++++- include/usb_defs.h | 14 ++- 26 files changed, 1294 insertions(+), 153 deletions(-) create mode 100644 arch/sandbox/include/asm/processor.h create mode 100644 drivers/usb/dev/Makefile create mode 100644 drivers/usb/dev/sandbox-flash.c create mode 100644 drivers/usb/dev/sandbox-hub.c create mode 100644 drivers/usb/dev/usb-emul-uclass.c create mode 100644 drivers/usb/host/usb-sandbox.c create mode 100644 drivers/usb/host/usb-uclass.c -- 2.2.0.rc0.207.ga3a616c

4 20

[U-Boot] [PATCH] lib: div64: syncronize to current kernel version
by Nishanth Menon 06 Mar '15

06 Mar '15

Synchronize with the implementation from v3.18 tag. This allows us to use a standardized 64 bit ops on architectures that do not natively support 64 bit (example: 32bit ARM) Signed-off-by: Nishanth Menon <nm(a)ti.com> --- include/linux/math64.h | 81 ++++++++++++++++++++++++++++++ lib/div64.c | 132 +++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 209 insertions(+), 4 deletions(-) diff --git a/include/linux/math64.h b/include/linux/math64.h index 6d760d7..a10ccbb 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -2,9 +2,13 @@ #define _LINUX_MATH64_H #include <linux/types.h> +#include <div64.h> #if BITS_PER_LONG == 64 +#define div64_long(x, y) div64_s64((x), (y)) +#define div64_ul(x, y) div64_u64((x), (y)) + /** * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder * @@ -27,6 +31,15 @@ static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) } /** + * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder + */ +static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +/** * div64_u64 - unsigned 64bit divide with 64bit divisor */ static inline u64 div64_u64(u64 dividend, u64 divisor) @@ -34,8 +47,19 @@ static inline u64 div64_u64(u64 dividend, u64 divisor) return dividend / divisor; } +/** + * div64_s64 - signed 64bit divide with 64bit divisor + */ +static inline s64 div64_s64(s64 dividend, s64 divisor) +{ + return dividend / divisor; +} + #elif BITS_PER_LONG == 32 +#define div64_long(x, y) div_s64((x), (y)) +#define div64_ul(x, y) div_u64((x), (y)) + #ifndef div_u64_rem static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) { @@ -48,10 +72,18 @@ static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder); #endif +#ifndef div64_u64_rem +extern u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder); +#endif + #ifndef div64_u64 extern u64 div64_u64(u64 dividend, u64 divisor); #endif +#ifndef div64_s64 +extern s64 div64_s64(s64 dividend, s64 divisor); +#endif + #endif /* BITS_PER_LONG */ /** @@ -82,4 +114,53 @@ static inline s64 div_s64(s64 dividend, s32 divisor) u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder); +static __always_inline u32 +__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) +{ + u32 ret = 0; + + while (dividend >= divisor) { + /* The following asm() prevents the compiler from + optimising this loop into a modulo operation. */ + asm("" : "+rm"(dividend)); + + dividend -= divisor; + ret++; + } + + *remainder = dividend; + + return ret; +} + +#if defined(CONFIG_ARCH_SUPPORTS_INT128) && defined(__SIZEOF_INT128__) + +#ifndef mul_u64_u32_shr +static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) +{ + return (u64)(((unsigned __int128)a * mul) >> shift); +} +#endif /* mul_u64_u32_shr */ + +#else + +#ifndef mul_u64_u32_shr +static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift) +{ + u32 ah, al; + u64 ret; + + al = a; + ah = a >> 32; + + ret = ((u64)al * mul) >> shift; + if (ah) + ret += ((u64)ah * mul) << (32 - shift); + + return ret; +} +#endif /* mul_u64_u32_shr */ + +#endif + #endif /* _LINUX_MATH64_H */ diff --git a/lib/div64.c b/lib/div64.c index 795ef0e..9b53faf 100644 --- a/lib/div64.c +++ b/lib/div64.c @@ -9,17 +9,21 @@ * Generic C version of 64bit/32bit division and modulo, with * 64bit result and 32bit remainder. * - * The fast case for (n>>32 == 0) is handled inline by do_div(). + * The fast case for (n>>32 == 0) is handled inline by do_div(). * * Code generated for this function might be very inefficient * for some CPUs. __div64_32() can be overridden by linking arch-specific - * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S. + * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S. */ +#include <common.h> #include <div64.h> -#include <linux/types.h> +#include <linux/math64.h> -uint32_t __div64_32(uint64_t *n, uint32_t base) +/* Not needed on 64bit architectures */ +#if BITS_PER_LONG == 32 + +uint32_t __attribute__((weak)) __div64_32(uint64_t *n, uint32_t base) { uint64_t rem = *n; uint64_t b = base; @@ -51,3 +55,123 @@ uint32_t __div64_32(uint64_t *n, uint32_t base) *n = res; return rem; } + + +#ifndef div_s64_rem +s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) +{ + u64 quotient; + + if (dividend < 0) { + quotient = div_u64_rem(-dividend, abs(divisor), (u32 *)remainder); + *remainder = -*remainder; + if (divisor > 0) + quotient = -quotient; + } else { + quotient = div_u64_rem(dividend, abs(divisor), (u32 *)remainder); + if (divisor < 0) + quotient = -quotient; + } + return quotient; +} +#endif + +/** + * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder + * @dividend: 64bit dividend + * @divisor: 64bit divisor + * @remainder: 64bit remainder + * + * This implementation is a comparable to algorithm used by div64_u64. + * But this operation, which includes math for calculating the remainder, + * is kept distinct to avoid slowing down the div64_u64 operation on 32bit + * systems. + */ +#ifndef div64_u64_rem +u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder) +{ + u32 high = divisor >> 32; + u64 quot; + + if (high == 0) { + u32 rem32; + quot = div_u64_rem(dividend, divisor, &rem32); + *remainder = rem32; + } else { + int n = 1 + fls(high); + quot = div_u64(dividend >> n, divisor >> n); + + if (quot != 0) + quot--; + + *remainder = dividend - quot * divisor; + if (*remainder >= divisor) { + quot++; + *remainder -= divisor; + } + } + + return quot; +} +#endif + +/** + * div64_u64 - unsigned 64bit divide with 64bit divisor + * @dividend: 64bit dividend + * @divisor: 64bit divisor + * + * This implementation is a modified version of the algorithm proposed + * by the book 'Hacker's Delight'. The original source and full proof + * can be found here and is available for use without restriction. + * + * 'http://www.hackersdelight.org/HDcode/newCode/divDouble.c.txt' + */ +#ifndef div64_u64 +u64 div64_u64(u64 dividend, u64 divisor) +{ + u32 high = divisor >> 32; + u64 quot; + + if (high == 0) { + quot = div_u64(dividend, divisor); + } else { + int n = 1 + fls(high); + quot = div_u64(dividend >> n, divisor >> n); + + if (quot != 0) + quot--; + if ((dividend - quot * divisor) >= divisor) + quot++; + } + + return quot; +} +#endif + +/** + * div64_s64 - signed 64bit divide with 64bit divisor + * @dividend: 64bit dividend + * @divisor: 64bit divisor + */ +#ifndef div64_s64 +s64 div64_s64(s64 dividend, s64 divisor) +{ + s64 quot, t; + + quot = div64_u64(abs64(dividend), abs64(divisor)); + t = (dividend ^ divisor) >> 63; + + return (quot ^ t) - t; +} +#endif + +#endif /* BITS_PER_LONG == 32 */ + +/* + * Iterative div/mod for use when dividend is not expected to be much + * bigger than divisor. + */ +u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) +{ + return __iter_div_u64_rem(dividend, divisor, remainder); +} -- 1.9.1

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