November 2014 - U-Boot

[U-Boot] [PATCH] ARM: remove unused CPU directory
by Masahiro Yamada 13 Nov '14

13 Nov '14

There is no board with CPU "arm_intcm". Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- arch/arm/cpu/arm_intcm/Makefile | 9 ----- arch/arm/cpu/arm_intcm/config.mk | 8 ---- arch/arm/cpu/arm_intcm/cpu.c | 36 ------------------ arch/arm/cpu/arm_intcm/start.S | 79 ---------------------------------------- 4 files changed, 132 deletions(-) delete mode 100644 arch/arm/cpu/arm_intcm/Makefile delete mode 100644 arch/arm/cpu/arm_intcm/config.mk delete mode 100644 arch/arm/cpu/arm_intcm/cpu.c delete mode 100644 arch/arm/cpu/arm_intcm/start.S diff --git a/arch/arm/cpu/arm_intcm/Makefile b/arch/arm/cpu/arm_intcm/Makefile deleted file mode 100644 index 3279f12..0000000 --- a/arch/arm/cpu/arm_intcm/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk deleted file mode 100644 index 438668d..0000000 --- a/arch/arm/cpu/arm_intcm/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/arm_intcm/cpu.c b/arch/arm/cpu/arm_intcm/cpu.c deleted file mode 100644 index 0d00e4b..0000000 --- a/arch/arm/cpu/arm_intcm/cpu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code for an unknown cpu - * - hence fairly empty...... - */ - -#include <common.h> -#include <command.h> - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* Since the CM has unknown processor we do not support - * cache operations - */ - - return (0); -} diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S deleted file mode 100644 index c0c07b6..0000000 --- a/arch/arm/cpu/arm_intcm/start.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> - * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <version.h> - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - - .globl reset - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - mov pc, lr - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* arm_int_generic assumes the ARM boot monitor, or user software, - * has initialized the platform - */ - mov pc, lr /* back to my caller */ -#endif -- 1.9.1

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[U-Boot] [PATCH v7 0/3] Adds support for Exynos5422 odroid xu3 board
by Hyungwon Hwang 13 Nov '14

13 Nov '14

This is v7 of the patchset adding support Odroud XU3 board. link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ v5: https://patchwork.ozlabs.org/patch/407941/ v6: https://patchwork.ozlabs.org/patch/408647/ This patchset fixes GPIO information of Exynos5420 which is needed to support Exynos5422 Odroid XU3 board. On the base of the fixes, this patchset adds support for Exynos5422 Odroid XU3 board. I have done this work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1: 26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat. link: https://patchwork.ozlabs.org/patch/405246/ (updated) How to test this patch: 1. git clone http://git.denx.de/u-boot-samsung.git 2. git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370 3. Get and apply the patchset of Akshay Saraswat https://patchwork.ozlabs.org/patch/405246/ https://patchwork.ozlabs.org/patch/405247/ https://patchwork.ozlabs.org/patch/405248/ https://patchwork.ozlabs.org/patch/405249/ https://patchwork.ozlabs.org/patch/405250/ https://patchwork.ozlabs.org/patch/405251/ https://patchwork.ozlabs.org/patch/405252/ 4. Apply this patchset 5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config 6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8 7. Now you can use u-boot-dtb.bin for your downloading Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SECURE_BL1_ONLY diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ + "if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ + "elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ + "elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ + "mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ Changes for v2: - Add a patch to add new common setup header file for Odroid X2/U3 and Odroid XU3 Changes for v3: - Remove the patch which adds new common setup header file from v2 - Remove the wrong patch to fix GPIO information of Exynos 5800 - Remove unnecessary node from DT file - Remove unnecessary features from config file - Fix some trivial typos in comments Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file Changes for v5: - Add the specific build instruction - Update the information of patchset by Akshay Saraswat - Convert /include/ to #include in DT file Changes for v6: - Separate out the documentation to new commit - Remove unnecessary header file inclusuib from the board-specific setup file - Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined Changes for v7: - Fix several errata in the documentation - Remove OF_CONTROL dependency from !SPL_BUILD Hyungwon Hwang (3): exynos5: fix GPIO information of exynos5420 Odroid-XU3: Add support for Odroid-XU3 Odroid-XU3: Add documentation for Odroid-XU3 arch/arm/cpu/armv7/exynos/Kconfig | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 60 +++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- board/samsung/odroid-xu3/Kconfig | 12 ++ board/samsung/odroid-xu3/MAINTAINERS | 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 +++++++++++++ configs/odroid-xu3_defconfig | 4 + doc/README.odroid-xu3 | 134 ++++++++++++++++++ include/configs/odroid_xu3.h | 144 ++++++++++++++++++++ 13 files changed, 708 insertions(+), 127 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 doc/README.odroid-xu3 create mode 100644 include/configs/odroid_xu3.h -- 1.8.3.2

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[U-Boot] [PATCH] km_arm: convert the km_arm boards to the generic board support
by Valentin Longchamp 13 Nov '14

13 Nov '14

This implies that all the km_kirkwood boards and their variants now are using the generic board init sequence. Signed-off-by: Valentin Longchamp <valentin.longchamp(a)keymile.com> --- include/configs/km/km_arm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index d31e674..f780f8b 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -20,6 +20,8 @@ #ifndef _CONFIG_KM_ARM_H #define _CONFIG_KM_ARM_H +#define CONFIG_SYS_GENERIC_BOARD + /* We got removed from Linux mach-types.h */ #define MACH_TYPE_KM_KIRKWOOD 2255 -- 1.8.0.1

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[U-Boot] [PATCH v2 0/33] x86: Add support for running on bare hardware
by Simon Glass 13 Nov '14

13 Nov '14

At present U-Boot's x86 support requires Coreboot to run first, starting up the CPU and then setting up SDRAM and video among other tasks. U-Boot then runs as a payload. Notably U-Boot does not handle the ACPI fun on x86 where the kernel can call back into the 'BIOS' to perform certain tasks. This Coreboot + U-Boot method is used for link (Chromebook Pixel) and it works fairly well. However this does not remove the need for all x86-specific init in U-Boot. For each generation of chipset we need to adjust U-Boot to make it work, albeit sometimes not a lot. In any case this work has not been done so the x86 port risks being stranded. There are also a few disadvantages to using two separate boot loaders. When Coreboot decides not set to up the video card, it is not possible for U-Boot to go back and do this. Building an image which has both boot loaders in itis a little tricky, particularly with the binary blobs that are required. After some experimentation prompted by a discussion at ELCE, it was found that while x86 is somewhat different to most of the other architectures that U-Boot supports, it actually fits the model fairly well. There is nothing magic about getting the platform running. Also it turns out that x86 likes running before relocation with no DRAM, using global_data, relocating and then starting up the full U-Boot, all within the same image (Coreboot splits this into three programs which run one after the other). Perhaps this is because U-Boot was conceived before the more modern SoCs with SRAM, FAT file system code in the ROM, etc. This series contains a basic port of U-Boot to a bare x86 environment. It would be targeted at some generally available board, such as the Minnowmax, except that it doesn't seem to be generally available, at least for me. So while that remains a goal, for now the port targets link. It is already supported in U-Boot and the platform is well understood. The following are implemented in this series: - ivybridge support with some peripherals enabled - SDRAM init using a binary blob (Memory Reference Code) - Use of Intel Management Engine via another binary blob - microcode update from device tree - ifttool for creating ROMs of the required format (u-boot.rom) - GPIO Notably missing are: - PCI device support (USB, SATA) - Video support - MTRR setup (for performance) - Real time clock - Chrome OS EC - Documentation - Links to binary blobs These will be addressed in a follow-up series. Things like ACPI and SMI will come later. Unfortunately this series is quite long as it includes basic infrastructure needed on x86. But it is a solid step forward: with this series, link boots to a prompt. This series is available at u-boot-x86/working Changes in v2: - Add a common early_init file - Add mrc.bin dependency for u-boot.rom build rule - Add new patch to rename chromebook-x86 to coreboot - Add new patch to replace fill_processor_name() with cpu_get_name() - Add new patch to tidy up timer code for Intel core architecture - Adjust config to deal with changed x86-common.h - Adjust to use asm/cpu.h header for cpuid - Change commit message to indicate that SPDX license request is submitted - Correct 'peripheral controller hub' to 'platform controller hub' - Drop patch to move coreboot PCI into common cpu area - Drop patch which removes the early_board_init() feature - Expand the comment about preserving ebp - Fix incorrect subl mnemonic in start.S - Fix mangled cros_ec reg property - Move SIPI code to after CAR init - Move early init code into early_board_init - Move some features out of the common file - Remove definition of find_fdt() also - Remove prepare_fdt() also - Remove the cpuid functions since they were already added in another patch - Remove use of PCI_CPU_DEVICE and use PCH_DEV instead - Split out new patch to support use fo PCI before relocation - Use capitals for all #define declarations Simon Glass (33): Move early malloc() to before arch_cpu_init() fdt: Add a function to decode a variable-sized u32 array dm: serial: Move current serial port pointer to global_data dm: gpio: Add a function to read an ID from a list of GPIOs x86: Add ifdtool for working with Intel Flash Descriptor ROM images x86: config: Move common x86 configs to a common file x86: Add processor functions to halt and get stack pointer x86: Remove unnecessary find_fdt(), prepare_fdt() functions x86: Replace fill_processor_name() with cpu_get_name() x86: Tidy up timer code for Intel core architecture x86: Add chromebook_link board x86: Build a .rom file which can be flashed to an x86 machine x86: Emit post codes in startup code for Chromebooks x86: chromebook_link: Implement CAR support (cache as RAM) x86: Refactor PCI to permit alternate init x86: Support use of PCI before relocation x86: ivybridge: Enable PCI in early init x86: pci: Allow configuration before relocation x86: ivybridge: Add early LPC init so that serial works x86: Tidy up coreboot header usage x86: Add clr/setbits functions x86: Add msr read/write functions that use a structure x86: ivybridge: Perform initial CPU setup x86: ivybridge: Check BIST value on boot x86: ivybridge: Perform Intel microcode update on boot x86: dts: Add microcode updates for ivybridge CPU x86: ivybridge: Add early init for PCH devices x86: ivybridge: Add support for early GPIO init x86: chromebook_link: Enable GPIO support x86: Make show_boot_progress() common x86: ivybridge: Add LAPIC support x86: ivybridge: Implement SDRAM init x86: Rename chromebook-x86 to coreboot Makefile | 34 +- arch/x86/Kconfig | 56 +- arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/coreboot.c | 35 +- arch/x86/cpu/coreboot/ipchecksum.c | 2 +- arch/x86/cpu/coreboot/pci.c | 22 +- arch/x86/cpu/coreboot/tables.c | 6 +- arch/x86/cpu/cpu.c | 46 +- arch/x86/cpu/interrupts.c | 28 - arch/x86/cpu/ivybridge/Kconfig | 157 +++ arch/x86/cpu/ivybridge/Makefile | 16 + arch/x86/cpu/ivybridge/car.S | 178 ++++ arch/x86/cpu/ivybridge/cpu.c | 357 +++++++ arch/x86/cpu/ivybridge/early_init.c | 145 +++ arch/x86/cpu/ivybridge/early_me.c | 191 ++++ arch/x86/cpu/ivybridge/lpc.c | 48 + arch/x86/cpu/ivybridge/me_status.c | 195 ++++ arch/x86/cpu/ivybridge/microcode_intel.c | 151 +++ arch/x86/cpu/ivybridge/pci.c | 63 ++ arch/x86/cpu/ivybridge/report_platform.c | 98 ++ arch/x86/cpu/ivybridge/sdram.c | 571 +++++++++++ arch/x86/cpu/pci.c | 96 ++ arch/x86/cpu/start.S | 14 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/link.dts | 125 +++ arch/x86/dts/m12206a7_00000028.dtsi | 622 ++++++++++++ arch/x86/dts/m12306a9_00000017.dtsi | 750 ++++++++++++++ arch/x86/include/asm/arch-coreboot/gpio.h | 5 - arch/x86/include/asm/arch-ivybridge/gpio.h | 10 + arch/x86/include/asm/arch-ivybridge/me.h | 356 +++++++ arch/x86/include/asm/arch-ivybridge/microcode.h | 20 + arch/x86/include/asm/arch-ivybridge/model_206ax.h | 82 ++ arch/x86/include/asm/arch-ivybridge/pch.h | 356 +++++++ arch/x86/include/asm/arch-ivybridge/pei_data.h | 121 +++ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 109 ++ arch/x86/include/asm/config.h | 1 + arch/x86/include/asm/cpu.h | 11 +- arch/x86/include/asm/global_data.h | 23 + arch/x86/include/asm/gpio.h | 142 ++- arch/x86/include/asm/init_helpers.h | 2 - arch/x86/include/asm/io.h | 49 + arch/x86/include/asm/lapic.h | 59 ++ arch/x86/include/asm/lapic_def.h | 101 ++ arch/x86/include/asm/msr.h | 19 + arch/x86/include/asm/mtrr.h | 121 +++ arch/x86/include/asm/pci.h | 33 + arch/x86/include/asm/post.h | 50 + arch/x86/include/asm/processor.h | 21 + arch/x86/include/asm/u-boot-x86.h | 2 + arch/x86/lib/Makefile | 1 + arch/x86/lib/init_helpers.c | 27 - arch/x86/lib/ramtest.c | 79 ++ arch/x86/lib/tsc_timer.c | 16 +- .../{chromebook-x86 => coreboot}/coreboot/Kconfig | 2 +- .../coreboot/MAINTAINERS | 2 +- .../{chromebook-x86 => coreboot}/coreboot/Makefile | 0 .../coreboot/coreboot.c | 0 .../coreboot/coreboot_start.S | 0 board/google/chromebook_link/Kconfig | 31 + board/google/chromebook_link/MAINTAINERS | 6 + board/google/chromebook_link/Makefile | 15 + board/google/chromebook_link/link.c | 124 +++ board/google/common/Makefile | 7 + board/google/common/early_init.S | 29 + common/board_f.c | 7 +- configs/chromebook_link_defconfig | 10 + doc/device-tree-bindings/misc/intel-lpc.txt | 23 + drivers/gpio/gpio-uclass.c | 19 + drivers/gpio/intel_ich6_gpio.c | 79 +- drivers/serial/serial-uclass.c | 35 +- include/asm-generic/global_data.h | 1 + include/asm-generic/gpio.h | 11 +- include/configs/chromebook_link.h | 74 ++ include/configs/coreboot.h | 265 +---- include/configs/x86-common.h | 251 +++++ include/fdtdec.h | 18 + lib/fdtdec.c | 22 + tools/Makefile | 2 + tools/ifdtool.c | 1039 ++++++++++++++++++++ tools/ifdtool.h | 88 ++ 81 files changed, 7566 insertions(+), 419 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/Kconfig create mode 100644 arch/x86/cpu/ivybridge/Makefile create mode 100644 arch/x86/cpu/ivybridge/car.S create mode 100644 arch/x86/cpu/ivybridge/cpu.c create mode 100644 arch/x86/cpu/ivybridge/early_init.c create mode 100644 arch/x86/cpu/ivybridge/early_me.c create mode 100644 arch/x86/cpu/ivybridge/lpc.c create mode 100644 arch/x86/cpu/ivybridge/me_status.c create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c create mode 100644 arch/x86/cpu/ivybridge/pci.c create mode 100644 arch/x86/cpu/ivybridge/report_platform.c create mode 100644 arch/x86/cpu/ivybridge/sdram.c create mode 100644 arch/x86/cpu/pci.c create mode 120000 arch/x86/dts/chromebook_link.dts create mode 100644 arch/x86/dts/m12206a7_00000028.dtsi create mode 100644 arch/x86/dts/m12306a9_00000017.dtsi create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h create mode 100644 arch/x86/include/asm/arch-ivybridge/model_206ax.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pch.h create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h create mode 100644 arch/x86/include/asm/arch-ivybridge/sandybridge.h create mode 100644 arch/x86/include/asm/lapic.h create mode 100644 arch/x86/include/asm/lapic_def.h create mode 100644 arch/x86/include/asm/mtrr.h create mode 100644 arch/x86/include/asm/post.h create mode 100644 arch/x86/lib/ramtest.c rename board/{chromebook-x86 => coreboot}/coreboot/Kconfig (86%) rename board/{chromebook-x86 => coreboot}/coreboot/MAINTAINERS (78%) rename board/{chromebook-x86 => coreboot}/coreboot/Makefile (100%) rename board/{chromebook-x86 => coreboot}/coreboot/coreboot.c (100%) rename board/{chromebook-x86 => coreboot}/coreboot/coreboot_start.S (100%) create mode 100644 board/google/chromebook_link/Kconfig create mode 100644 board/google/chromebook_link/MAINTAINERS create mode 100644 board/google/chromebook_link/Makefile create mode 100644 board/google/chromebook_link/link.c create mode 100644 board/google/common/Makefile create mode 100644 board/google/common/early_init.S create mode 100644 configs/chromebook_link_defconfig create mode 100644 doc/device-tree-bindings/misc/intel-lpc.txt create mode 100644 include/configs/chromebook_link.h create mode 100644 include/configs/x86-common.h create mode 100644 tools/ifdtool.c create mode 100644 tools/ifdtool.h -- 2.1.0.rc2.206.gedb03e5

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Re: [U-Boot] Flat Image Tree and boot arguments
by Simon Glass 13 Nov '14

13 Nov '14

Hi, On 4 November 2014 08:21, Weiß Christoph <Christoph.Weiss(a)ait.ac.at> wrote: > Well, for me it works with type kernel and loading it to a higher RAM address than the load address and entry point. I'm not exactly sure if kernel_noload is supported with Tegra. Is type kernel completely wrong? I'm just not sure why you want U-Boot to load it to a new address, if the kernel itself self-decompresses and moves to a place it has decided on. > > I finally managed to execute a verified boot on the Tegra with the help of the tegra-uboot-flasher scripts and your Beaglebone vboot documentation, which was very very helpful. Great! > Thanks :) > > Cheers, Chris > [snip] Regards, Simon

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[U-Boot] [PATCH] buildman: Save *.img files too
by Tom Rini 13 Nov '14

13 Nov '14

When saving binary files we likely want to keep any .img files that have been generated as well. Signed-off-by: Tom Rini <trini(a)ti.com> --- tools/buildman/builderthread.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index a9cf68a..bc4541c 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -332,7 +332,7 @@ class BuilderThread(threading.Thread): # Now write the actual build output if keep_outputs: - patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', + patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', '*.img', 'include/autoconf.mk', 'spl/u-boot-spl', 'spl/u-boot-spl.bin'] for pattern in patterns: -- 1.7.9.5

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[U-Boot] [PATCH v3 0/7] Addition of new board Peach-Pi
by Akshay Saraswat 13 Nov '14

13 Nov '14

Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board. Changes since v1: - Rebased all the patches Changes since v2: - Rebased all the patches - Added new patch "Enable update mode for DREX controller" Akshay Saraswat (5): Exynos5800: Introduce new proid for Exynos5800 Exynos5800: Add DTS for new board Peach-Pi Config: Exynos5800: Enable build for Peach-Pi Config: Exynos5420: Refactor SDRAM Bank and Size Exynos5: ddr3: Choose between single or double channel config Alim Akhtar (1): DMC: Exynos5: Enable update mode for DREX controller Vadim Bendebury (1): Peach-Pi: Use the enhanced usb_copy() prototype arch/arm/cpu/armv7/exynos/Kconfig | 7 +- arch/arm/cpu/armv7/exynos/clock.c | 19 +-- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 29 +++++ arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/cpu/armv7/exynos/spl_boot.c | 10 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 10 +- arch/arm/include/asm/arch-exynos/dmc.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h | 4 +- board/samsung/smdk5420/Kconfig | 16 +++ board/samsung/smdk5420/MAINTAINERS | 2 + configs/peach-pi_defconfig | 5 + include/configs/exynos5420-common.h | 7 +- include/configs/peach-pi.h | 50 ++++++++ include/configs/peach-pit.h | 8 +- include/configs/smdk5420.h | 4 + 18 files changed, 311 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts create mode 100644 configs/peach-pi_defconfig create mode 100644 include/configs/peach-pi.h -- 1.9.1

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[U-Boot] [PATCH 0/9] net: rtl8169: Fix cache maintenance issues
by Thierry Reding 13 Nov '14

13 Nov '14

From: Thierry Reding <treding(a)nvidia.com> This series attempts to fix a long-standing problem in the rtl8169 driver (though the same problem may exist in other drivers as well). Let me first explain what exactly the issue is: The rtl8169 driver provides a set of RX and TX descriptors for the device to use. Once they're set up, the device is told about their location so that it can fetch the descriptors using DMA. The device will also write packet state back into these descriptors using DMA. For this to work properly, whenever a driver needs to access these descriptors it needs to invalidate the D-cache line(s) associated with them. Similarly when changes to the descriptor have been made by the driver, the cache lines need to be flushed to make sure the changes are visible to the device. The descriptors are 16 bytes in size. This causes problems when used on CPUs that have a cache-line size that is larger than 16 bytes. One example is the NVIDIA Tegra124 which has 64-byte cache-lines. That means that 4 descriptors fit into a single cache-line. So whenever the driver flushes a cache-line it has the potential to discard changes made to another descriptor by the DMA device. One typical symptom is that large transfers over TFTP will often not complete and hang somewhere midway because a device marked a packet received but the driver flushing the cache and causing the packet to be lost. Since the descriptors need to be consecutive in memory, I don't see a way to fix this other than to use uncached memory. Therefore the solution proposed in this patch series is to introduce a mechanism in U-Boot to allow a driver to allocate from a pool of uncached memory. Currently an implementation is provided only for ARM v7. The idea is that a region (of user-definable size) immediately below (taking into account architecture-specific alignment restrictions) the malloc() area is mapped uncacheable in the MMU. A driver can use the new noncached_alloc() function to allocate a chunk of memory from this pool dynamically for buffers that it can't or doesn't want to do any explicit cache-maintainance on, yet needs to be shared with DMA devices. Patches 1-3 are minor preparatory work. Patch 1 cleans up some coding style issues in the ARM v7 cache code and patch 2 uses more future-proof types for the mmu_set_region_dcache_behaviour() function arguments. Patch 3 is purely for debugging purposes. It will print out the region used by malloc() when DEBUG is enabled. This can be useful to see where the malloc() region is in the memory map (compared to the noncached region introduced in a later patch for example). Patch 4 implements the noncached API for ARM v7. It obtains the start of the malloc() area and places the noncached region immediately below it so that noncached_alloc() can allocate from it. During boot, the noncached area will be set up immediately after malloc(). Patch 5 enables noncached memory for all Tegra boards. It uses a 1 MiB chunk which should be plenty (it's also the minimum on ARM v7 because it matches the MMU section size and therefore the granularity at which U-Boot can set the cacheable attributes). Patch 6 is not really related but just something I stumbled across when going through the code. According to the top-level README file, network drivers are supposed to respect the CONFIG_SYS_RX_ETH_BUFFER. rtl8169 doesn't currently do that, so this patch fixes it. Patch 7 is the result of earlier rework that still aimed at solving the problem using explicit cache maintenance. rtl8169 hardware requires buffers to be aligned to 256 byte boundaries. The rtl8169 driver used to employ some trickery to make that work, but nowadays there are macros that can be used to the same effect, so this patch uses them and gets rid of the custom trickery. This patch also prints out a warning if it detects a potential caching issue (i.e. ARCH_DMA_MINALIGN > sizeof(struct RxDesc)). Patch 8 finally adds optional support for non-cached memory. When available the driver will now use the noncached API to obtain uncached buffers for the RX and TX descriptor rings. At the same time the cache-maintenance functions for the RX and TX descriptors become no-ops so that the code can work with or without the noncached API available. With all of the above in place, patch 9 adds support for RTL-8168/8111g as found on the NVIDIA Jetson TK1 board (which has a Tegra124 SoC). Note that this series also fixes the sporadic hangs of large TFTP transfers for earlier SoC generations of Tegra (Tegra20 and Tegra30), though they were less frequent there, probably caused by the cache-lines being 32 bytes rather than 64. Thierry Thierry Reding (9): ARM: cache_v7: Various minor cleanups ARM: cache-cp15: Use unsigned long for address and size malloc: Output region when debugging ARM: Implement non-cached memory support ARM: tegra: Enable non-cached memory net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER net: rtl8169: Properly align buffers net: rtl8169: Use non-cached memory if available net: rtl8169: Add support for RTL-8168/8111g README | 16 ++++++ arch/arm/cpu/armv7/cache_v7.c | 14 +++--- arch/arm/include/asm/system.h | 7 ++- arch/arm/lib/cache-cp15.c | 6 +-- arch/arm/lib/cache.c | 41 +++++++++++++++ common/board_r.c | 11 +++++ common/dlmalloc.c | 3 ++ drivers/net/rtl8169.c | 110 ++++++++++++++++++++++++++++++----------- include/configs/tegra-common.h | 1 + 9 files changed, 168 insertions(+), 41 deletions(-) -- 2.0.4

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[U-Boot] [PATCH 1/2] mtd: nand: omap_gpmc: Add CONFIG_SYS_NAND_USE_READY to enable ready/busy
by Stefan Roese 12 Nov '14

12 Nov '14

By defining CONFIG_SYS_NAND_USE_READY the GPMC NAND driver makes use of the ready pin / signal for busy / ready detection. This function is already available but currently only used in SPL. I don't see a reason to not use it in the main U-Boot as well. As it increases the NAND performance. I'm making it configurable, so that boards that might now have this pin connected are still supported. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Scott Wood <scottwood(a)freescale.com> Cc: Roger Meier <r.meier(a)siemens.com> Cc: Samuel Egli <samuel.egli(a)siemens.com> --- README | 5 +++++ drivers/mtd/nand/omap_gpmc.c | 20 +++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/README b/README index c3a9dfc..420c14b 100644 --- a/README +++ b/README @@ -4731,6 +4731,11 @@ Low Level (hardware related) configuration options: - drivers/mtd/nand/ndfc.c - drivers/mtd/nand/mxc_nand.c +- CONFIG_SYS_NAND_USE_READY + Defined if a ready/busy pin is available on this board + which can be used to determine the state of the NAND + chip. Currently used on the OMAP/AM33xx NAND driver. + - CONFIG_SYS_NDFC_EBC0_CFG Sets the EBC0_CFG register for the NDFC. If not defined a default value will be used. diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 40d6705..8ca95d3 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -23,6 +23,16 @@ /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ #define BCH4_BIT_PAD 4 +/* + * All OMAP / AM33xx SPL builds already use the ready / busy pin. + * So lets enable this new define to use this signal for SPL. This + * makes the check in the code easier since its reduced to a single + * macro. + */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NAND_USE_READY +#endif + #ifdef CONFIG_BCH static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; @@ -73,9 +83,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SYS_NAND_USE_READY /* Check wait pin as dev ready indicator */ -static int omap_spl_dev_ready(struct mtd_info *mtd) +static int omap_dev_ready(struct mtd_info *mtd) { return gpmc_cfg->status & (1 << 8); } @@ -887,7 +897,11 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf16; else nand->read_buf = nand_read_buf; - nand->dev_ready = omap_spl_dev_ready; #endif + +#ifdef CONFIG_SYS_NAND_USE_READY + nand->dev_ready = omap_dev_ready; +#endif + return 0; } -- 2.1.3

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[U-Boot] [PATCH v6 0/5] iMX6 SabreSD SPL Support
by John Tobias 12 Nov '14

12 Nov '14

This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board. After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC. sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69 Changes (v2): Merged the SPL support into the main board file Remove the compilation warmings Changes (v3): Removed sp and gd Use imx_ddr_size to set the ram_size Changes (v4): Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig). Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures. Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port. Changes (v5): Use the default CONFIG_SPL_STACK Add a macro #ifndef for CONFIG_SYS_TEXT_BASE to avoid compilation warning. Changes (v6): Use board_mmc_init for spl mmc initialization instead of adding spl_board_mmc_init function John Tobias (5): imx6: add spl config for mx6sabresd imx6: add data configuration file for SPL kconfig: imx6: add SUPPORT_SPL imx6: add spl in the header file imx6: SPL support for iMX6 SabreSD arch/arm/Kconfig | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 186 +++++++++++++++++++++++++- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 ++++++++ configs/mx6sabresd_spl_defconfig | 5 + include/configs/mx6sabre_common.h | 2 + include/configs/mx6sabresd.h | 6 + 6 files changed, 256 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg create mode 100644 configs/mx6sabresd_spl_defconfig -- 1.9.1

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