November 2014 - U-Boot

[U-Boot] [RFC PATCH 0/12] RFC: dm: Add I2C support
by Simon Glass 11 Nov '14

11 Nov '14

(Note this is RFC since the uclass interface needs discussion and also because only sandbox is implemented so far. But I thought it best to get this out there as soon as I wrote it as it may influence the PMIC library, etc.) This series is an initial attempt to add I2C support to driver model. It has become apparent that this is a high priority as it is widely used. It follows along to some extent from the SPI conversion. Several changes are made from the original I2C implementations. Firstly It is not necessary to specify the chip address with every call, since each chip knows its own address - it is stored in struct dm_i2c_chip which is attached to each chip on the I2C bus. However, this information *is* passed to the driver since I presume most drivers need it and it would be cumbersome to look up in every call. Secondly there is no concept of a 'current' I2C bus so all associated logic is removed. With driver model i2c_set_bus_num() and i2c_get_bus_num() are not available. Since the chip device specifies both the bus and the chip address, there is no need for this concept. It also causes problems when one driver changes the current bus and forgets to change it back. Thirdly initialisation is handled by driver model's normal probe() method on each device so there should be no need for i2c_init_all(), i2c_init(), i2c_init_board(), i2c_board_late_init() and board_i2c_init(). I2C muxes are not yet supported. To support these we will need to maintain state of the current mux settings to avoid resetting every mux every time. Probably we need to add a sandbox I2C mux driver to permit testing of this. This can probably be done later. Platform data is not yet supported either, only device tree. The U_BOOT_I2C_MKENT_COMPLETE() and U_BOOT_I2C_ADAP_COMPLETE() macros are not used. Also struct i2c_adapter is not defined anymore. This will need to be addressed, perhaps as part of converting over a board that does not use device tree. This series is available at u-boot-dm/i2c-working. Simon Glass (12): dm: core: Allow access to the device's driver_id data dm: core: Add functions to find parent and OF data dm: i2c: Add a uclass for I2C dm: i2c: Implement driver model support in the i2c command dm: i2c: Add I2C emulation driver for sandbox dm: i2c: Add a sandbox I2C driver dm: i2c: Add an I2C EEPROM simulator dm: i2c: config: Enable I2C for sandbox using driver model dm: i2c: dts: Add an I2C bus for sandbox dm: WIP: EEPROM driver dm: i2c: Add tests for I2C dm: i2c: tegra: Convert to driver model for I2C for seaboard arch/arm/cpu/tegra20-common/pmu.c | 21 +- arch/arm/include/asm/arch-tegra/tegra_i2c.h | 2 +- arch/sandbox/dts/sandbox.dts | 17 ++ board/nvidia/common/board.c | 4 - common/cmd_i2c.c | 312 +++++++++++++++++++++++---- drivers/core/device.c | 10 + drivers/core/lists.c | 17 +- drivers/i2c/Makefile | 2 + drivers/i2c/i2c-emul-uclass.c | 14 ++ drivers/i2c/i2c-uclass.c | 177 ++++++++++++++++ drivers/i2c/sandbox_i2c.c | 148 +++++++++++++ drivers/i2c/tegra_i2c.c | 313 ++++++++++------------------ drivers/misc/Makefile | 4 + drivers/misc/i2c_eeprom.c | 51 +++++ drivers/misc/i2c_eeprom_emul.c | 108 ++++++++++ drivers/power/tps6586x.c | 27 +-- include/config_fallbacks.h | 6 + include/configs/cardhu.h | 2 - include/configs/colibri_t30.h | 2 - include/configs/sandbox.h | 6 + include/configs/seaboard.h | 3 - include/configs/tegra-common.h | 1 + include/configs/tegra20-common.h | 3 - include/dm/device.h | 19 ++ include/dm/uclass-id.h | 3 + include/i2c.h | 252 ++++++++++++++++++++++ include/i2c_eeprom.h | 19 ++ include/tps6586x.h | 2 +- test/dm/Makefile | 1 + test/dm/i2c.c | 100 +++++++++ test/dm/test.dts | 17 ++ 31 files changed, 1373 insertions(+), 290 deletions(-) create mode 100644 drivers/i2c/i2c-emul-uclass.c create mode 100644 drivers/i2c/i2c-uclass.c create mode 100644 drivers/i2c/sandbox_i2c.c create mode 100644 drivers/misc/i2c_eeprom.c create mode 100644 drivers/misc/i2c_eeprom_emul.c create mode 100644 include/i2c_eeprom.h create mode 100644 test/dm/i2c.c -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH 0/2] ARM: UniPhier: some cleanups and bug fix
by Masahiro Yamada 11 Nov '14

11 Nov '14

Masahiro Yamada (2): ARM: UniPhier: consolidate board_postclk_init() function ARM: UniPhier: call pin_init() also in the normal boot arch/arm/cpu/armv7/uniphier/Kconfig | 4 +++ arch/arm/cpu/armv7/uniphier/Makefile | 1 + .../uniphier/{ph1-ld4 => }/board_postclk_init.c | 9 +++-- arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 5 +-- arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 4 +-- .../armv7/uniphier/ph1-pro4/board_postclk_init.c | 41 ---------------------- arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 5 +-- .../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 - include/configs/uniphier-common.h | 4 +-- 9 files changed, 21 insertions(+), 53 deletions(-) rename arch/arm/cpu/armv7/uniphier/{ph1-ld4 => }/board_postclk_init.c (86%) delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c delete mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c -- 1.9.1

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[U-Boot] [PATCH] ARM: UniPhier: decrease pre-reloc malloc area size
by Masahiro Yamada 11 Nov '14

11 Nov '14

In the current implementation of the boot sequence of UniPhier platform, 32KB temporary RAM is available before relocation. The malloc area and the stack shares the 32KB area. With CONFIG_SYS_MALLOC_F_LEN set to 0x7000 (28KB), only 0x1000 (4KB) is left for the stack. In some use cases, the system hangs up with stack over-flow. Even with driver-model UART enabled, the malloc area of 0x2000 (8KB) should be enough. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- include/configs/uniphier-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h index b18ae6d..ef81914 100644 --- a/include/configs/uniphier-common.h +++ b/include/configs/uniphier-common.h @@ -43,7 +43,7 @@ are defined. Select only one of them." #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE #define CONFIG_SMC911X_32_BIT -#define CONFIG_SYS_MALLOC_F_LEN 0x7000 +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 /*----------------------------------------------------------------------- * MMU and Cache Setting -- 1.9.1

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[U-Boot] [PATCH 0/2] Utilize low-level debug for UniPhier platform
by Masahiro Yamada 11 Nov '14

11 Nov '14

Masahiro Yamada (2): ARM: UniPhier: add set_pinsel macro for use in assembly code ARM: UniPhier: add UART initialization routine for low-level debug arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 4 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 1 + .../cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S | 29 ++++++++++++++++ arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 1 + .../cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S | 39 ++++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 1 + .../cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S | 29 ++++++++++++++++ arch/arm/include/asm/arch-uniphier/debug-uart.S | 24 +++++++++++++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 13 +++++++- 9 files changed, 140 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S create mode 100644 arch/arm/include/asm/arch-uniphier/debug-uart.S -- 1.9.1

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[U-Boot] [PATCH 0/4] EHCI support for Panasonic UniPhier SoCs
by Masahiro Yamada 11 Nov '14

11 Nov '14

This series includes both USB parts and Panasonic SoC-specific parts to resolve the patch dependency. Marek, please review at least 3/4 and issue your Ack if it is OK. After it is Ack'ed, I will apply this series to my repo. Masahiro Yamada (4): usb: add basic USB configs in Kconfig ARM: UniPhier: add MIO register file usb: UniPhier: add UniPhier on-chip EHCI host driver support ARM: UniPhier: enable USB features arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c | 13 +++++ arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c | 10 ++++ arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c | 13 +++++ arch/arm/include/asm/arch-uniphier/ehci-uniphier.h | 33 +++++++++++++ arch/arm/include/asm/arch-uniphier/mio-regs.h | 20 ++++++++ arch/arm/include/asm/arch-uniphier/platdevice.h | 2 + configs/ph1_ld4_defconfig | 3 ++ configs/ph1_pro4_defconfig | 3 ++ configs/ph1_sld8_defconfig | 3 ++ drivers/usb/Kconfig | 46 ++++++++++++++++++ drivers/usb/host/Kconfig | 56 ++++++++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-uniphier.c | 39 +++++++++++++++ include/configs/uniphier-common.h | 7 +++ 14 files changed, 249 insertions(+) create mode 100644 arch/arm/include/asm/arch-uniphier/ehci-uniphier.h create mode 100644 arch/arm/include/asm/arch-uniphier/mio-regs.h create mode 100644 drivers/usb/host/Kconfig create mode 100644 drivers/usb/host/ehci-uniphier.c -- 1.9.1

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[U-Boot] [PATCH] ARM: UniPhier: add EHCI host pin settings for PH1-Pro4
by Masahiro Yamada 11 Nov '14

11 Nov '14

These IO pins are necessary for port power control and over current detect. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c index 503c247..4e3d476 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -41,5 +41,12 @@ void pin_init(void) sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + writel(1, SG_LOADPINCTRL); } -- 1.9.1

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[U-Boot] [PATCH] ARM: UniPhier: move DDR related configuration to Kconfig
by Masahiro Yamada 11 Nov '14

11 Nov '14

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/arm/cpu/armv7/uniphier/Kconfig | 23 +++++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/dram_init.c | 2 +- arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 3 +-- arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 4 ---- arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 3 +-- arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 4 ---- arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 3 +-- arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c | 4 ---- include/configs/ph1_ld4.h | 2 -- include/configs/ph1_pro4.h | 2 -- include/configs/ph1_sld8.h | 2 -- 11 files changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index f013dc3..011c6d9 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -32,4 +32,27 @@ config CMD_PINMON The boot mode pins are latched when the system reset is deasserted and determine which device the system should load a boot image from. +config DRAM_INIT + bool + default SPL_BUILD + +choice + prompt "DDR3 Frequency select" + depends on DRAM_INIT + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + endmenu diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c index 5465a0e..7de657b 100644 --- a/arch/arm/cpu/armv7/uniphier/dram_init.c +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -16,7 +16,7 @@ int dram_init(void) DECLARE_GLOBAL_DATA_PTR; gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_DRAM_INIT led_write(B, 4, , ); { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 781b511..5722ee2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -7,5 +7,4 @@ obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index 1344ac1..ebcbaab 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -149,10 +149,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR Frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index e11f4f6..25a1202 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -7,5 +7,4 @@ obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index dd46287..328b2f4 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -122,10 +122,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR frequency. -#endif - #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index 781b511..5722ee2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -7,5 +7,4 @@ obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c index ff2dcb1..a44f999 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -129,10 +129,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 -#error Unsupported DDR frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h index 005a853..73a95e6 100644 --- a/include/configs/ph1_ld4.h +++ b/include/configs/ph1_ld4.h @@ -37,8 +37,6 @@ #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_FREQ 1600 - /* * Memory Size & Mapping */ diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h index 7dd6fd2..fc5132d 100644 --- a/include/configs/ph1_pro4.h +++ b/include/configs/ph1_pro4.h @@ -37,8 +37,6 @@ #define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH1 2 -#define CONFIG_DDR_FREQ 1600 - #define CONFIG_UNIPHIER_SMP /* diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h index 1062aac..e2f1102 100644 --- a/include/configs/ph1_sld8.h +++ b/include/configs/ph1_sld8.h @@ -37,8 +37,6 @@ #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_FREQ 1333 - /* #define CONFIG_DDR_STANDARD */ /* -- 1.9.1

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[U-Boot] [PATCH] ARM: UniPhier: reset on-board devices on start-up
by Masahiro Yamada 11 Nov '14

11 Nov '14

If a support card is attached to the main board, the on-board SMSC9118 LAN controller is available. It must be kept in reset state for a while on start-up. When the board is kicked via a debbuger rather than pushing the hardware reset button, on-board chips are not reset; in this case the reset signals should be asserted by software. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c | 2 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c | 2 ++ arch/arm/cpu/armv7/uniphier/reset.c | 3 --- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c index 4302277..5bb8179 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c @@ -24,6 +24,8 @@ int board_postclk_init(void) sg_init(); + uniphier_board_reset(); + pll_init(); uniphier_board_init(); diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c index 7198829..9a53743 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c @@ -21,6 +21,8 @@ int board_postclk_init(void) sg_init(); + uniphier_board_reset(); + pll_init(); uniphier_board_init(); diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c index b0dc967..50d1fed 100644 --- a/arch/arm/cpu/armv7/uniphier/reset.c +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -8,14 +8,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/sc-regs.h> -#include <asm/arch/board.h> void reset_cpu(unsigned long ignored) { u32 tmp; - uniphier_board_reset(); - writel(5, SC_IRQTIMSET); /* default value */ tmp = readl(SC_SLFRSTSEL); -- 1.9.1

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[U-Boot] [PATCH] serial: UniPhier: borrow macros from linux/serial_reg.h
by Masahiro Yamada 11 Nov '14

11 Nov '14

The same bit-field macros are defined in include/linux/serial_reg.h so let's include it and delete duplicated defines. Also, remove unnecessary inclusion of <common.h>. Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- drivers/serial/serial_uniphier.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 3f3d415..6046efb 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/serial_reg.h> #include <asm/io.h> #include <asm/errno.h> #include <dm/device.h> @@ -37,17 +37,6 @@ struct uniphier_serial { #define thr rbr -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ - struct uniphier_serial_private_data { struct uniphier_serial __iomem *membase; }; @@ -62,7 +51,7 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) const unsigned int mode_x_div = 16; unsigned int divisor; - writeb(UART_LCR_WLS_8, &port->lcr); + writeb(UART_LCR_WLEN8, &port->lcr); divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate); -- 1.9.1

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[U-Boot] [PATCH v2] mtd: nand: allow to skip BBT scanning during NAND inititialization
by Masahiro Yamada 11 Nov '14

11 Nov '14

Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14), chip->scan_bbt() is called at the end of nand_scan_tail(). It means the first read access happens immediately after the generic NAND initialization process. It causes a problem to some SoCs of UniPhier platform because some of their register values need to be fixed up after the general initialization procedure has been finished. Otherwise, read asccess fails. Such a fix-up is SoC-specific enough to be written in a board file rather than in driver code. One of possible and clean enough ways to work around this issue is postpone the BBT scanning until necessary fix-up is done in board_late_init() or somewhere else. CONFIG_MTD_NAND_SKIP_BBTSCAN, if enabled, allows to skip the BBT scanning at the end of nand_scan_tail(). Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> Cc: Scott Wood <scottwood(a)freescale.com> --- If this patch is accepted, I will turn on this config option for my boards. Changes in v2: - Bug fix ( "config" was missing from v1) drivers/mtd/nand/Kconfig | 13 +++++++++++++ drivers/mtd/nand/nand.c | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 75c2c06..e1d6fbc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -2,6 +2,19 @@ menu "NAND Device Support" if !SPL_BUILD +config MTD_NAND_SKIP_BBTSCAN + bool "Skip BBT scanning" + help + The current implementation of nand_scan_tail() calls scan_bbt handler + at the end of itself to build a bad block table. It means the first + read access happens in the initizalization procedure. It causes a + problem on some SoCs that need some extra SoC-specific settings + before starting read/write access. + + If this option is enabled, bad block scanning is skipped during the + nand device initialization. You are resposible to build a bad block + table lator. + config NAND_DENALI bool "Support Denali NAND controller" help diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 4cf4c1c..a249647 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -88,6 +88,10 @@ static void nand_init_chip(int i) mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; +#ifdef CONFIG_MTD_NAND_SKIP_BBTSCAN + nand->options |= NAND_SKIP_BBTSCAN; +#endif + if (board_nand_init(nand)) return; -- 1.9.1

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