November 2014 - U-Boot

[U-Boot] [PATCH v2] ARM: tegra: Add support for norrin board
by Simon Glass 12 Nov '14

12 Nov '14

From: Allen Martin <amartin(a)nvidia.com> Norrin (PM370) is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This board is also refered to as "nyan" in the ChromeOS trees. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). Signed-off-by: Allen Martin <amartin(a)nvidia.com> Signed-off-by: Simon Glass <sjg(a)chromium.org> (rebase, fix pinmux that resets norrin) --- Changes in v2: - Rebase and adjust for Kconfig - Fix up pinmux that reset norrin - Add note as to the Chromebook's retail name, since it is now released arch/arm/cpu/armv7/tegra124/Kconfig | 11 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra124-norrin.dts | 92 +++++++++ board/nvidia/norrin/Kconfig | 24 +++ board/nvidia/norrin/MAINTAINERS | 6 + board/nvidia/norrin/Makefile | 9 + board/nvidia/norrin/norrin.c | 29 +++ board/nvidia/norrin/pinmux-config-norrin.h | 290 +++++++++++++++++++++++++++++ board/nvidia/venice2/as3722_init.h | 2 +- configs/norrin_defconfig | 5 + include/configs/norrin.h | 76 ++++++++ 11 files changed, 544 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/tegra124-norrin.dts create mode 100644 board/nvidia/norrin/Kconfig create mode 100644 board/nvidia/norrin/MAINTAINERS create mode 100644 board/nvidia/norrin/Makefile create mode 100644 board/nvidia/norrin/norrin.c create mode 100644 board/nvidia/norrin/pinmux-config-norrin.h create mode 100644 configs/norrin_defconfig create mode 100644 include/configs/norrin.h diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig index 6a1c83a..db17819 100644 --- a/arch/arm/cpu/armv7/tegra124/Kconfig +++ b/arch/arm/cpu/armv7/tegra124/Kconfig @@ -6,6 +6,16 @@ choice config TARGET_JETSON_TK1 bool "NVIDIA Tegra124 Jetson TK1 board" +config TARGET_NORRIN + bool "NVIDIA Tegra124 Norrin" + help + Norrin (PM370) is a Tegra124 clamshell board that is very similar + to venice2, but it has a different panel, the sdcard CD and WP + sense are flipped, and it has a different revision of the AS3722 + PMIC. This board is also refered to as "nyan" in the Chrome OS + trees. The retail name is the Acer Chromebook 13 CB5-311-T7NN + (13.3-inch HD, NVIDIA Tegra K1, 2GB). + config TARGET_VENICE2 bool "NVIDIA Tegra124 Venice2" @@ -15,6 +25,7 @@ config SYS_SOC default "tegra124" source "board/nvidia/jetson-tk1/Kconfig" +source "board/nvidia/norrin/Kconfig" source "board/nvidia/venice2/Kconfig" endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 52f8926..aa1e81a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra30-tec-ng.dtb \ tegra114-dalmore.dtb \ tegra124-jetson-tk1.dtb \ + tegra124-norrin.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ diff --git a/arch/arm/dts/tegra124-norrin.dts b/arch/arm/dts/tegra124-norrin.dts new file mode 100644 index 0000000..b07630c --- /dev/null +++ b/arch/arm/dts/tegra124-norrin.dts @@ -0,0 +1,92 @@ +/dts-v1/; + +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Norrin"; + compatible = "nvidia,norrin", "nvidia,tegra124"; + + aliases { + console = &uarta; + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + i2c5 = "/i2c@7000d100"; + sdhci0 = "/sdhci@700b0600"; + sdhci1 = "/sdhci@700b0400"; + spi0 = "/spi@7000d400"; + spi1 = "/spi@7000da00"; + usb0 = "/usb@7d000000"; + usb1 = "/usb@7d008000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d100 { + status = "okay"; + clock-frequency = <400000>; + }; + + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@700b0400 { + status = "okay"; + cd-gpios = <&gpio 170 1>; /* gpio PV2 */ + power-gpios = <&gpio 136 0>; /* gpio PR0 */ + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */ + }; + + usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */ + }; +}; diff --git a/board/nvidia/norrin/Kconfig b/board/nvidia/norrin/Kconfig new file mode 100644 index 0000000..cea6528 --- /dev/null +++ b/board/nvidia/norrin/Kconfig @@ -0,0 +1,24 @@ +if TARGET_NORRIN + +config SYS_CPU + string + default "arm720t" if SPL_BUILD + default "armv7" if !SPL_BUILD + +config SYS_BOARD + string + default "norrin" + +config SYS_VENDOR + string + default "nvidia" + +config SYS_SOC + string + default "tegra124" + +config SYS_CONFIG_NAME + string + default "norrin" + +endif diff --git a/board/nvidia/norrin/MAINTAINERS b/board/nvidia/norrin/MAINTAINERS new file mode 100644 index 0000000..e1463ae --- /dev/null +++ b/board/nvidia/norrin/MAINTAINERS @@ -0,0 +1,6 @@ +NORRIN BOARD +M: Allen Martin <amartin(a)nvidia.com> +S: Maintained +F: board/nvidia/norrin/ +F: include/configs/norrin.h +F: configs/norrin_defconfig diff --git a/board/nvidia/norrin/Makefile b/board/nvidia/norrin/Makefile new file mode 100644 index 0000000..5e490bb --- /dev/null +++ b/board/nvidia/norrin/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../venice2/as3722_init.o +obj-y += norrin.o diff --git a/board/nvidia/norrin/norrin.c b/board/nvidia/norrin/norrin.c new file mode 100644 index 0000000..6f0050c --- /dev/null +++ b/board/nvidia/norrin/norrin.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "pinmux-config-norrin.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_set_tristate_input_clamping(); + + gpio_config_table(norrin_gpio_inits, + ARRAY_SIZE(norrin_gpio_inits)); + + pinmux_config_pingrp_table(norrin_pingrps, + ARRAY_SIZE(norrin_pingrps)); + + pinmux_config_drvgrp_table(norrin_drvgrps, + ARRAY_SIZE(norrin_drvgrps)); +} diff --git a/board/nvidia/norrin/pinmux-config-norrin.h b/board/nvidia/norrin/pinmux-config-norrin.h new file mode 100644 index 0000000..d4f1f66 --- /dev/null +++ b/board/nvidia/norrin/pinmux-config-norrin.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_NORRIN_H_ +#define _PINMUX_CONFIG_NORRIN_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config norrin_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(C7, IN), + GPIO_INIT(G0, IN), + GPIO_INIT(G1, IN), + GPIO_INIT(G2, IN), + GPIO_INIT(G3, IN), + GPIO_INIT(H2, IN), + GPIO_INIT(H4, IN), + GPIO_INIT(H6, IN), + GPIO_INIT(H7, OUT1), + GPIO_INIT(I0, IN), + GPIO_INIT(I1, IN), + GPIO_INIT(I5, OUT1), + GPIO_INIT(I6, IN), + GPIO_INIT(I7, IN), + GPIO_INIT(J0, IN), + GPIO_INIT(J7, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, IN), + GPIO_INIT(K4, OUT0), + GPIO_INIT(K6, OUT0), + GPIO_INIT(K7, IN), + GPIO_INIT(N7, IN), + GPIO_INIT(P2, OUT0), + GPIO_INIT(Q0, IN), + GPIO_INIT(Q2, IN), + GPIO_INIT(Q3, IN), + GPIO_INIT(Q6, IN), + GPIO_INIT(Q7, IN), + GPIO_INIT(R0, OUT0), + GPIO_INIT(R1, IN), + GPIO_INIT(R4, IN), + GPIO_INIT(R7, IN), + GPIO_INIT(S3, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S7, IN), + GPIO_INIT(T1, IN), + GPIO_INIT(U4, IN), + GPIO_INIT(U5, IN), + GPIO_INIT(U6, IN), + GPIO_INIT(V0, IN), + GPIO_INIT(W3, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ + } + +static const struct pmux_pingrp_config norrin_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */ + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), +/* + * This casues nyan to reset after 4 seconds + * PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + */ + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL), + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config norrin_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_NORRIN_H */ diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h index 06c366e..d1e0ec3 100644 --- a/board/nvidia/venice2/as3722_init.h +++ b/board/nvidia/venice2/as3722_init.h @@ -18,7 +18,7 @@ #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ #define AS3722_LDCONTROL_REG 0x4E -#ifdef CONFIG_TARGET_JETSON_TK1 +#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NORRIN) #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) #else #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) diff --git a/configs/norrin_defconfig b/configs/norrin_defconfig new file mode 100644 index 0000000..a18c09b --- /dev/null +++ b/configs/norrin_defconfig @@ -0,0 +1,5 @@ ++S:CONFIG_ARM=y ++S:CONFIG_TEGRA=y ++S:CONFIG_TEGRA124=y ++S:CONFIG_TARGET_NORRIN=y +CONFIG_DEFAULT_DEVICE_TREE="tegra124-norrin" diff --git a/include/configs/norrin.h b/include/configs/norrin.h new file mode 100644 index 0000000..ef0b63d --- /dev/null +++ b/include/configs/norrin.h @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/sizes.h> + +#include "tegra124-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Norrin) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Norrin" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- 2.1.0.rc2.206.gedb03e5

2 4

[U-Boot] [PATCH v3 0/8] *** iMX6 SabreSD SPL Support ***
by John Tobias 12 Nov '14

12 Nov '14

This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board. After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC. sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69 Changes (v2): Merged the SPL support into the main board file Remove the compilation warmings Changes (v3): Removed sp and gd Use imx_ddr_size to set the ram_size John Tobias (8): mmc: add spl_board_mmc_init mmc: imx6: call spl_board_mmc_init imx6: add spl on include header file imx6: add some flexibility for defining macros imx6: add spl on board configuration imx6: add data configuration file for SPL imx6: SPL support for iMX6 SabreSD kconfig: imx6: add SUPPORT_SPL arch/arm/Kconfig | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 211 +++++++++++++++++++++++++- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++++++ configs/mx6qsabresd_defconfig | 7 +- drivers/mmc/mmc.c | 9 +- include/configs/imx6_spl.h | 4 + include/configs/mx6sabresd.h | 7 + include/mmc.h | 3 + 8 files changed, 288 insertions(+), 8 deletions(-) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg -- 1.9.1

2 19

[U-Boot] [PATCH v4 0/7] iMX6 SabreSD SPL Support
by John Tobias 12 Nov '14

12 Nov '14

This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board. After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC. sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69 Changes (v2): Merged the SPL support into the main board file Remove the compilation warmings Changes (v3): Removed sp and gd Use imx_ddr_size to set the ram_size Changes (v4): Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig). Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures. Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port. John Tobias (7): imx6: add spl config for mx6sabresd kconfig: imx6: add SUPPORT_SPL mmc: imx6: call spl_board_mmc_init imx6: add spl in the header file imx6: add some flexibility for defining macros imx6: SPL support for iMX6 SabreSD imx6: add data configuration file for SPL arch/arm/Kconfig | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 187 +++++++++++++++++++++++++- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 ++++++++ configs/mx6sabresd_spl_defconfig | 5 + drivers/mmc/mmc.c | 9 +- include/configs/imx6_spl.h | 4 + include/configs/mx6sabresd.h | 7 + include/mmc.h | 3 + 8 files changed, 269 insertions(+), 5 deletions(-) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg create mode 100644 configs/mx6sabresd_spl_defconfig -- 1.9.1

6 16

[U-Boot] [PATCH v6 0/3] Adds support for Exynos5422 odroid xu3 board
by Hyungwon Hwang 12 Nov '14

12 Nov '14

This is v6 of the patchset adding support Odroud XU3 board. link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ v5: https://patchwork.ozlabs.org/patch/407941/ This patchset fixes GPIO information of Exynos5420 which is needed to support Exynos5422 Odroid XU3 board. On the base of the fixes, this patchset adds support for Exynos5422 Odroid XU3 board. I have done this work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1: 26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat. link: https://patchwork.ozlabs.org/patch/405246/ (updated) How to test this patch: 1. git clone http://git.denx.de/u-boot-samsung.git 2. git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370 3. Get and apply the patchset of Akshay Saraswat https://patchwork.ozlabs.org/patch/405246/ https://patchwork.ozlabs.org/patch/405247/ https://patchwork.ozlabs.org/patch/405248/ https://patchwork.ozlabs.org/patch/405249/ https://patchwork.ozlabs.org/patch/405250/ https://patchwork.ozlabs.org/patch/405251/ https://patchwork.ozlabs.org/patch/405252/ 4. Apply this patchset 5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config 6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8 7. Now you can use u-boot-dtb.bin for your downloading Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id. diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SECURE_BL1_ONLY diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ + "if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ + "elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ + "elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ + "mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ Changes for v2: - Add a patch to add new common setup header file for Odroid X2/U3 and Odroid XU3 Changes for v3: - Remove the patch which adds new common setup header file from v2 - Remove the wrong patch to fix GPIO information of Exynos 5800 - Remove unnecessary node from DT file - Remove unnecessary features from config file - Fix some trivial typos in comments Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file Changes for v5: - Add the specific build instruction - Update the information of patchset by Akshay Saraswat - Convert /include/ to #include in DT file Chagnes for v6: - Separate out the documentation to new commit - Remove unnecessary header file inclusuib from the board-specific setup file - Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined Hyungwon Hwang (3): exynos5: fix GPIO information of exynos5420 Odroid-XU3: Add support for Odroid-XU3 Odroid-XU3: Add documentation for Odroid-XU3 arch/arm/cpu/armv7/exynos/Kconfig | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 60 +++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- board/samsung/odroid-xu3/Kconfig | 12 ++ board/samsung/odroid-xu3/MAINTAINERS | 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 +++++++++++++ configs/odroid-xu3_defconfig | 4 + doc/README.odroid-xu3 | 134 ++++++++++++++++++ include/configs/odroid_xu3.h | 144 ++++++++++++++++++++ 13 files changed, 708 insertions(+), 127 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 doc/README.odroid-xu3 create mode 100644 include/configs/odroid_xu3.h -- 1.8.3.2

3 8

[U-Boot] [PATCH v2 2/4] x86: Do TSC MSR calibration only for known/supported CPUs
by Bin Meng 12 Nov '14

12 Nov '14

Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on processors which do not have this MSR. Instead only doing the MSR calibration for known/supported CPUs. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> Tested-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/lib/tsc_timer.c | 116 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 109 insertions(+), 7 deletions(-) diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index 8b38702..fafbbfc 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -1,6 +1,9 @@ /* * Copyright (c) 2012 The Chromium OS Authors. * + * TSC calibration codes are adapted from Linux kernel + * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,8 +15,108 @@ #include <asm/msr.h> #include <asm/u-boot-x86.h> +/* CPU reference clock frequency: in KHz */ +#define FREQ_83 83200 +#define FREQ_100 99840 +#define FREQ_133 133200 +#define FREQ_166 166400 + +#define MAX_NUM_FREQS 8 + DECLARE_GLOBAL_DATA_PTR; +/* + * According to Intel 64 and IA-32 System Programming Guide, + * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be + * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. + * Unfortunately some Intel Atom SoCs aren't quite compliant to this, + * so we need manually differentiate SoC families. This is what the + * field msr_plat does. + */ +struct freq_desc { + u8 x86_family; /* CPU family */ + u8 x86_model; /* model */ + u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */ + u32 freqs[MAX_NUM_FREQS]; +}; + +static struct freq_desc freq_desc_tables[] = { + /* PNW */ + { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, + /* CLV+ */ + { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } }, + /* TNG */ + { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } }, + /* VLV2 */ + { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } }, + /* ANN */ + { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, +}; + +static int match_cpu(u8 family, u8 model) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) { + if ((family == freq_desc_tables[i].x86_family) && + (model == freq_desc_tables[i].x86_model)) + return i; + } + + return -1; +} + +/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */ +#define id_to_freq(cpu_index, freq_id) \ + (freq_desc_tables[cpu_index].freqs[freq_id]) + +/* + * Do MSR calibration only for known/supported CPUs. + * + * Returns the calibration value or 0 if MSR calibration failed. + */ +static unsigned long try_msr_calibrate_tsc(void) +{ + u32 lo, hi, ratio, freq_id, freq; + unsigned long res; + int cpu_index; + + cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model); + if (cpu_index < 0) + return 0; + + if (freq_desc_tables[cpu_index].msr_plat) { + rdmsr(MSR_PLATFORM_INFO, lo, hi); + ratio = (lo >> 8) & 0x1f; + } else { + rdmsr(MSR_IA32_PERF_STATUS, lo, hi); + ratio = (hi >> 8) & 0x1f; + } + debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio); + + if (!ratio) + goto fail; + + /* Get FSB FREQ ID */ + rdmsr(MSR_FSB_FREQ, lo, hi); + freq_id = lo & 0x7; + freq = id_to_freq(cpu_index, freq_id); + debug("Resolved frequency ID: %u, frequency: %u KHz\n", + freq_id, freq); + if (!freq) + goto fail; + + /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ + res = freq * ratio / 1000; + debug("TSC runs at %lu MHz\n", res); + + return res; + +fail: + debug("Fast TSC calibration using MSR failed\n"); + return 0; +} + void timer_set_base(u64 base) { gd->arch.tsc_base = base; @@ -34,17 +137,16 @@ u64 __attribute__((no_instrument_function)) get_ticks(void) return now_tick - gd->arch.tsc_base; } -#define PLATFORM_INFO_MSR 0xce - /* Get the speed of the TSC timer in MHz */ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void) { - u32 ratio; - u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + unsigned long fast_calibrate; + + fast_calibrate = try_msr_calibrate_tsc(); + if (!fast_calibrate) + panic("TSC frequency is ZERO"); - /* 100MHz times Max Non Turbo ratio */ - ratio = (platform_info >> 8) & 0xff; - return 100 * ratio; + return fast_calibrate; } unsigned long get_tbclk(void) -- 1.8.2.1

2 5

[U-Boot] [PATCH 0/2] mtd: denali: Use SELF_INIT to fix up registers after nand_scan_ident()
by Masahiro Yamada 12 Nov '14

12 Nov '14

This patch series is here because Scott Wood recommended me to use CONFIG_SYS_NAND_SELF_INIT to solve my problem: http://patchwork.ozlabs.org/patch/402462/ Masahiro Yamada (2): mtd: denali: use CONFIG_SYS_NAND_SELF_INIT mtd: denali: set some registers after nand_scan_ident() drivers/mtd/nand/Kconfig | 7 +++ drivers/mtd/nand/denali.c | 131 +++++++++++++++++++++++++++++++++------------- drivers/mtd/nand/denali.h | 5 +- 3 files changed, 103 insertions(+), 40 deletions(-) -- 1.9.1

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[U-Boot] [PATCH for-next] arndale: Enable config_distro_defaults.h
by Ian Campbell 12 Nov '14

12 Nov '14

From: Ian Campbell <ian.campbell(a)citrix.com> ...and remove explicit setting of things which this implies. I'm mainly interested in CONFIG_CMD_BOOTZ and CONFIG_SUPPORT_RAW_INITRD Signed-off-by: Ian Campbell <ian.campbell(a)citrix.com> --- include/configs/arndale.h | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 75f9933..197d0fc 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -45,7 +45,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD @@ -98,15 +97,9 @@ /* Command definition*/ #include <config_cmd_default.h> -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF #define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET #define CONFIG_CMD_HASH -#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* USB */ @@ -133,8 +126,6 @@ #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "ARNDALE # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ @@ -201,8 +192,6 @@ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION #define CONFIG_CMD_PART #define CONFIG_PARTITION_UUIDS @@ -221,6 +210,8 @@ #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 #define CONFIG_I2C_EDID +#include <config_distro_defaults.h> + /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C @@ -238,15 +229,6 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - /* Enable Time Command */ #define CONFIG_CMD_TIME -- 2.1.0

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[U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420
by Shaveta Leekha 12 Nov '14

12 Nov '14

Addded Alternate options with LC VCO for following protocols: 0x02 --> 0x01 0x08 --> 0x07 0x18 --> 0x17 0x1E --> 0x1D 0x49 --> 0x48 0x6F --> 0x6E 0x9A --> 0x99 0x9E --> 0x9D Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com>i Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2 Reviewed-on: http://git.am.freescale.net:8181/23352 Tested-by: Review Code-CDREVIEW <CDREVIEW(a)freescale.com> Reviewed-by: Yusong Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index cf18be5..63172de 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -18,6 +18,8 @@ struct serdes_config { #ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ + {0x01, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x02, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x04, {AURORA, AURORA, CPRI6, CPRI5, @@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, CPRI2, CPRI1} }, {0x06, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x07, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x08, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x09, {AURORA, AURORA, CPRI6, CPRI5, @@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, NONE, NONE} }, {0x0F, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, + {0x17, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x18, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, {0x1B, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x1D, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, {0x1E, {NONE, NONE, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x21, {NONE, NONE, AURORA, AURORA, @@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = { {} }; static struct serdes_config serdes2_cfg_tbl[] = { + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, + {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x99, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x9A, {PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE} }, {} -- 1.7.6.GIT

1 0

[U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420
by Shaveta Leekha 12 Nov '14

12 Nov '14

Addded Alternate options with LC VCO for following protocols: 0x02 --> 0x01 0x08 --> 0x07 0x18 --> 0x17 0x1E --> 0x1D 0x49 --> 0x48 0x6F --> 0x6E 0x9A --> 0x99 0x9E --> 0x9D Signed-off-by: Shaveta Leekha <shaveta(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com>i Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2 Reviewed-on: http://git.am.freescale.net:8181/23352 Tested-by: Review Code-CDREVIEW <CDREVIEW(a)freescale.com> Reviewed-by: Yusong Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index cf18be5..63172de 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -18,6 +18,8 @@ struct serdes_config { #ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ + {0x01, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x02, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x04, {AURORA, AURORA, CPRI6, CPRI5, @@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, CPRI2, CPRI1} }, {0x06, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x07, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x08, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x09, {AURORA, AURORA, CPRI6, CPRI5, @@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, NONE, NONE} }, {0x0F, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, + {0x17, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x18, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, {0x1B, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x1D, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, {0x1E, {NONE, NONE, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x21, {NONE, NONE, AURORA, AURORA, @@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = { {} }; static struct serdes_config serdes2_cfg_tbl[] = { + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, + {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x99, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x9A, {PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE} }, {} -- 1.7.6.GIT

1 2

[U-Boot] [PATCH] mx28evk: README: Revision C is also supported
by Fabio Estevam 12 Nov '14

12 Nov '14

Adjust the text to mention that rev C of the board is also supported. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx28evk/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README index 958ebc6..f9d6324 100644 --- a/board/freescale/mx28evk/README +++ b/board/freescale/mx28evk/README @@ -1,7 +1,7 @@ FREESCALE MX28EVK ================== -Supported hardware: only MX28EVK rev D is supported in U-boot. +Supported hardware: MX28EVK rev C and D are supported in U-boot. Files of the MX28EVK port -------------------------- -- 1.9.1

2 1