November 2014 - U-Boot

[U-Boot] [PATCH] dfu: thor: fix: Modify dfu_get_alt() function to support absolute paths
by Lukasz Majewski 14 Nov '14

14 Nov '14

Recently the ext4 file system imposed passing absolute path with its file name parameter. As a result dfu_alt_info env variable has been modified to provide absolute path when ext4 file system is accessed (e.g. /uImage ext4 0 2;). Unfortunately, lthor flashing program provides plain file name (like uImage) and hence those two file names do not match anymore. Presented commit also allows lthor to write files to sub directories (like /boot/bin/uImage). Signed-off-by: Lukasz Majewski <l.majewski(a)samsung.com> --- drivers/dfu/dfu.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 55e6a83..1e9ccdc 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -544,10 +544,35 @@ struct dfu_entity *dfu_get_entity(int alt) int dfu_get_alt(char *name) { struct dfu_entity *dfu; + char *str; list_for_each_entry(dfu, &dfu_list, list) { - if (!strncmp(dfu->name, name, strlen(dfu->name))) - return dfu->alt; + if (dfu->name[0] != '/') { + if (!strncmp(dfu->name, name, strlen(dfu->name))) + return dfu->alt; + } else { + /* + * One must also consider absolute path + * (/boot/bin/uImage) available at dfu->name when + * compared "plain" file name (uImage) + * + * It is the case for e.g. thor gadget where lthor SW + * sends only the file name, so only the very last part + * of patch must be checked for equality + */ + + str = strstr(dfu->name, name); + if (!str) + continue; + + /* + * Check if matching substring is the last element of + * dfu->name (uImage) + */ + if (strlen(dfu->name) == + ((str - dfu->name) + strlen(name))) + return dfu->alt; + } } return -ENODEV; -- 2.0.0.rc2

2 4

[U-Boot] [ANN] U-Boot v2015.01-rc1 released
by Tom Rini 14 Nov '14

14 Nov '14

Hey all, I've pushed v2015.01-rc1 out to the repository and tarballs should exist soon. The merge window is now closed. Per both the min-summit and the follow up emails, I'm going to try and get into the every 2 week RC tagging groove. And, I'm going to be relying on everyones best judgement about what level of changes they're going to put into a pull request to me. When I do a buildman of most things I see: blackfin: + ip04 arm: + Ippo_q8h_v5 novena openrd_base maxbcm openrd_ultimate openrd_client tricorder db-mv784mp-gp Linksprite_pcDuino3_fdt tricorder_flash cm_t3517 powerpc: + kmcoge4 taishan kmlion1 dlvision And I'd really like to see those sorted out, one way or another for -rc2. As always, if anything is broken please speak up. Thanks all! -- Tom

8 12

[U-Boot] [PATCH] test: ums: Add sleep before unmount directory
by Lukasz Majewski 14 Nov '14

14 Nov '14

This change helps to run script on machines with quite long uptime. Without this the following error emerges: File: ./dat_14M.img umount: /mnt/tmp-ums-test: device is busy. (In some cases useful info about processes that use the device is found by lsof(8) or fuser(1)) TX: md5sum:083d3d22b542d3ecba61b12d17e03f9f mount: /dev/sdd6 already mounted or /mnt/tmp-ums-test busy mount: according to mtab, /dev/sdd6 is already mounted on /mnt/tmp-ums-test Signed-off-by: Lukasz Majewski <l.majewski(a)samsung.com> --- test/ums/ums_gadget_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/test/ums/ums_gadget_test.sh b/test/ums/ums_gadget_test.sh index 56d4616..f862332 100755 --- a/test/ums/ums_gadget_test.sh +++ b/test/ums/ums_gadget_test.sh @@ -59,6 +59,7 @@ ums_test_file () { fi cp ./$1 $MNT_DIR + sleep 2 umount $MNT_DIR -- 2.0.0.rc2

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[U-Boot] [PATCH v3] arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target
by Stefan Roese 14 Nov '14

14 Nov '14

This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Pavel Machek <pavel(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> --- v3: - Add missing gpio.h (even if empty). This header is needed for lib/fdtdec.c to compile. v2: - As mentioned in the commit text, this new version does not move the default target to DT (yet). It adds support for the SoCrates board now based on this DT support as the first example. Nothing changes for the current socfpga_cyclone5 target. arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga.dtsi | 755 +++++++++++++++++++++++++++++ arch/arm/dts/socfpga_cyclone5.dtsi | 51 ++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 50 ++ arch/arm/include/asm/arch-socfpga/gpio.h | 10 + configs/socfpga_socrates_defconfig | 5 + include/dt-bindings/reset/altr,rst-mgr.h | 90 ++++ 7 files changed, 963 insertions(+) create mode 100644 arch/arm/dts/socfpga.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts create mode 100644 arch/arm/include/asm/arch-socfpga/gpio.h create mode 100644 configs/socfpga_socrates_defconfig create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 52f8926..b946abe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -40,6 +40,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb +dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi new file mode 100644 index 0000000..4472fd9 --- /dev/null +++ b/arch/arm/dts/socfpga.dtsi @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2012 Altera <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + clk-phase = <0 135>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + }; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + L2: l2-cache@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + }; + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + uart1: serial1@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi new file mode 100644 index 0000000..28c05e7 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 0000000..a1814b4 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar(a)pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc { + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/include/asm/arch-socfpga/gpio.h new file mode 100644 index 0000000..6c61f18 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_GPIO_H +#define _SOCFPGA_GPIO_H + +#endif /* _SOCFPGA_GPIO_H */ diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig new file mode 100644 index 0000000..0f3896d --- /dev/null +++ b/configs/socfpga_socrates_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000..3f04908 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar(a)pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif -- 2.1.3

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[U-Boot] [PATCH v2 0/4] ls102xa: HYP/non-sec: for ls102xa.
by Xiubo Li 14 Nov '14

14 Nov '14

Change for V2: - All the registers are defined as a struct, here use it. - Use CONFIG_PEN_ADDR_BIG_ENDIAN instead of CONFIG_SOC_BIG_ENDIAN. Xiubo Li (4): ARM: HYP/non-sec: add the pen address byte reverting support. ARM: HYP/non-sec: Fix the ARCH Timer frequency setting. ls102xa: HYP/non-sec: support for ls102xa boards ARM: ls102xa: allow all the peripheral access permissions as R/W. arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++ arch/arm/cpu/armv7/nonsec_virt.S | 7 +- arch/arm/include/asm/arch-ls102xa/config.h | 3 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 + arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++++++++++++++++++++++ board/freescale/common/Makefile | 2 + board/freescale/common/ns_access.c | 32 ++++++ board/freescale/ls1021aqds/ls1021aqds.c | 92 +++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 91 +++++++++++++++++ include/configs/ls1021aqds.h | 8 ++ include/configs/ls1021atwr.h | 8 ++ include/configs/sun7i.h | 1 + 12 files changed, 379 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h create mode 100644 board/freescale/common/ns_access.c -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support
by Alison Wang 14 Nov '14

14 Nov '14

This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> --- include/configs/ls1021aqds.h | 3 +++ include/configs/ls1021atwr.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d49696d..1201221 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -409,6 +409,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /*SPI device */ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SPANSION diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index ba2d8a7..bbbe4b2 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -261,6 +261,9 @@ #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /*SPI device */ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/33] x86: Add additional system setup for ivybridge
by Simon Glass 14 Nov '14

14 Nov '14

This series adds full support for the LPC (Low Pin Count) bridge, the PCH (Platform Controller Hub), PCI devices like USB and SATA and more CPU init support (turbo mode, etc.) With this series, chromebook_link can use SATA and USB at the command line. Simon Glass (33): Add build date values to Makefile Align embedded device tree correctly Add ALIGN_DOWN() to find next smallest alignment pci: Update pci_ids.h to include some missing IDs x86: Remove board_early_init_r() x86: Panic if there is not relocation data x86: Ensure that all relocation data is included in the image WIP: x86: Drop u-boot.srec from the Makefile x86: Factor out common values in the link script rtc: mc146818: Set up RTC at start of day x86: Add ioapic.h header x86: pci: Add handlers before and after a PCI hose scan x86: config: Enable plug-and-play for link PCI pci: Add functions to read and write a BAR address x86: ivybridge: Add support for BD82x6x PCH x86: Add basic i8259 implementation x86: Add ISA DMA implementation x86: Add a simple header file for ACPI x86: ivybridge: Add PCH init x86: ivybridge: Add additional LPC init x86: dts: Move PCI peripherals into a pci node x86: dts: Add LPC settings for link x86: ivybridge: Add SATA init x86: dts: Add SATA settings for link x86: ivybridge: Set up EHCI USB x86: config: Enable USB on link x86: ivybridge: Set up XHCI USB x86: Add Intel speedstep and turbo mode code x86: Add LAPIC setup code x86: Add init for model 206AX CPU x86: Drop some msr functions that we don't support x86: ivybridge: Add northbridge init functions x86: config: Enable SPI for chromebook_link Makefile | 12 +- arch/x86/cpu/Makefile | 2 + arch/x86/cpu/config.mk | 5 +- arch/x86/cpu/coreboot/coreboot.c | 11 - arch/x86/cpu/ivybridge/Makefile | 7 + arch/x86/cpu/ivybridge/bd82x6x.c | 135 ++++++ arch/x86/cpu/ivybridge/lpc.c | 529 +++++++++++++++++++++- arch/x86/cpu/ivybridge/model_206ax.c | 514 +++++++++++++++++++++ arch/x86/cpu/ivybridge/northbridge.c | 188 ++++++++ arch/x86/cpu/ivybridge/pch.c | 123 +++++ arch/x86/cpu/ivybridge/pci.c | 40 ++ arch/x86/cpu/ivybridge/sata.c | 243 ++++++++++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 ++ arch/x86/cpu/ivybridge/usb_xhci.c | 32 ++ arch/x86/cpu/lapic.c | 68 +++ arch/x86/cpu/pci.c | 14 +- arch/x86/cpu/turbo.c | 98 ++++ arch/x86/cpu/u-boot.lds | 17 +- arch/x86/dts/link.dts | 41 +- arch/x86/include/asm/acpi.h | 24 + arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 21 + arch/x86/include/asm/arch-ivybridge/model_206ax.h | 4 + arch/x86/include/asm/arch-ivybridge/pch.h | 120 +++++ arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 +- arch/x86/include/asm/i8259.h | 3 + arch/x86/include/asm/ioapic.h | 38 ++ arch/x86/include/asm/isa_dma.h | 14 + arch/x86/include/asm/lapic.h | 123 +++++ arch/x86/include/asm/msr-index.h | 2 + arch/x86/include/asm/msr.h | 11 - arch/x86/include/asm/pci.h | 3 + arch/x86/include/asm/post.h | 1 + arch/x86/include/asm/speedstep.h | 89 ++++ arch/x86/include/asm/turbo.h | 31 ++ arch/x86/lib/Makefile | 2 + arch/x86/lib/i8259.c | 134 ++++++ arch/x86/lib/isa_dma.c | 56 +++ arch/x86/lib/relocate.c | 3 + board/google/chromebook_link/link.c | 5 - common/board_r.c | 3 - doc/device-tree-bindings/ata/intel-sata.txt | 26 ++ doc/device-tree-bindings/misc/intel-lpc.txt | 47 +- drivers/pci/pci.c | 24 +- drivers/rtc/mc146818.c | 49 +- include/common.h | 15 + include/configs/chromebook_link.h | 11 +- include/fdtdec.h | 2 + include/pci.h | 23 + include/pci_ids.h | 187 +++++++- include/rtc.h | 7 + lib/fdtdec.c | 2 + scripts/Makefile.lib | 2 + 52 files changed, 3125 insertions(+), 78 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/bd82x6x.c create mode 100644 arch/x86/cpu/ivybridge/model_206ax.c create mode 100644 arch/x86/cpu/ivybridge/northbridge.c create mode 100644 arch/x86/cpu/ivybridge/pch.c create mode 100644 arch/x86/cpu/ivybridge/sata.c create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c create mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c create mode 100644 arch/x86/cpu/lapic.c create mode 100644 arch/x86/cpu/turbo.c create mode 100644 arch/x86/include/asm/acpi.h create mode 100644 arch/x86/include/asm/arch-ivybridge/bd82x6x.h create mode 100644 arch/x86/include/asm/ioapic.h create mode 100644 arch/x86/include/asm/isa_dma.h create mode 100644 arch/x86/include/asm/speedstep.h create mode 100644 arch/x86/include/asm/turbo.h create mode 100644 arch/x86/lib/i8259.c create mode 100644 arch/x86/lib/isa_dma.c create mode 100644 doc/device-tree-bindings/ata/intel-sata.txt -- 2.1.0.rc2.206.gedb03e5

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Re: [U-Boot] putc
by Simon Glass 14 Nov '14

14 Nov '14

Hi Martin, On 30 October 2014 00:45, Martin Dorwig <dorwig(a)tetronik.com> wrote: > Am Mittwoch, 29. Oktober 2014, 13:03:41 schrieben Sie: >> Hi Martin, >> >> On 28 October 2014 07:23, Martin Dorwig <dorwig(a)tetronik.com> wrote: >> > Hello, >> > after updating u-boot from git v2014.10 >> > i just noticed that my standalone application outputs garbage using putc. >> > after some investigation i found that the gd->jt[XF_putc] is assigned a >> > dev->putc pointer in "common/console.c function console_setfile" >> > >> > the dev->putc is declared in include/stdio_dev.h as >> > void (*putc)(struct stdio_dev *dev, const char c); >> > >> > int include/exports.h this function is declared as >> > void putc(const char); >> > >> > this was introduced with commit id >> > 709ea543b92489e7729d2d7ddd6c9f451e52158c >> >> That's unfortunate. Is the stdio device pointer available in the >> standalone application? >> >> Perhaps gd->jt should point to a structure of strongly-typed >> functions? Then we would get a build error in this case. >> >> Regards, >> Simon > > What is the motivation to override the jumptable slots ? > Why can't they be untouched like this > gd->jt[XF_getc] = getc; > gd->jt[XF_tstc] = tstc; > gd->jt[XF_putc] = putc; > gd->jt[XF_puts] = puts; > redirection of the console to another device is honored in the implementation > of the functions themselves. > for example the putc function: > it calls pre_console_putc before a console is present > if GD_FLG_DEVINIT is set, it calls fputc(stdout,c) which calls > console_putc(stdout,c) which in turn calls stdio_devices[stdout]- >>putc(stdio_devices[file], c); > else it calls serial_putc(c) I have taken a bit of a look at this. I have not actually touched the jumptable slots. The one you mention was assigned to dev->putc() before and after. The problem is that now dev->putc() has two parameters, the first being 'dev'. dev->putc() is the device's putc function - typically the serial port or a display. The putc() function you mention is the console out, that outputs to all stdout devices. So yes we could change the bahaviour so that it calls putc(). I think this will work, and it probably isn't going to result in a change in behaviour for many boards since they only have a single stdout. Alternatively we could require the stdio device parameter to be passed in. I'm not sure that will work though - how will the external program get at it? In any case, teh void *gd->jt[] is not serving our purpose here - it should be changed to proper function pointer types so that the compiler can check that this sort of thing doesn't happen. Please let me know what you think should be done here. Regards, Simon

3 4

[U-Boot] [PATCH v2] tools/kwbimage: Fix compilation warning
by Stefan Roese 13 Nov '14

13 Nov '14

This patch fixes a compilation warning of kwbimage.c: tools/kwbimage.c: In function ‘kwbimage_set_header’: tools/kwbimage.c:784:8: warning: ‘headersz’ may be used uninitialized in this function [-Wmaybe-uninitialized] memcpy(ptr, image, headersz); ^ Instead of using multiple if statements, use a switch statement with a default entry. And return with error if an unsupported version is configured in the cfg file. Signed-off-by: Stefan Roese <sr(a)denx.de> --- v2: - Change error message so that it really makes sense (unsupported version instead of no version) - Change this also in the commit text - Small change (s/is/if) tools/kwbimage.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 1120e9b..0179c74 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -752,14 +752,25 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd, } version = image_get_version(); - /* Fallback to version 0 is no version is provided in the cfg file */ - if (version == -1) - version = 0; - - if (version == 0) + switch (version) { + /* + * Fallback to version 0 if no version is provided in the + * cfg file + */ + case -1: + case 0: image = image_create_v0(&headersz, params, sbuf->st_size); - else if (version == 1) + break; + + case 1: image = image_create_v1(&headersz, params, sbuf->st_size); + break; + + default: + fprintf(stderr, "Unsupported version %d\n", version); + free(image_cfg); + exit(EXIT_FAILURE); + } if (!image) { fprintf(stderr, "Could not create image\n"); -- 2.1.2

4 3

Re: [U-Boot] [PATCH v3 0/7] Addition of new board Peach-Pi
by Akshay Saraswat 13 Nov '14

13 Nov '14

Hi Simon, >Hi Akshay, > >On 31 October 2014 02:55, Akshay Saraswat <akshay.s(a)samsung.com> wrote: >> Now we are adding a new Peach-Pi board which is a variant of Peach-Pit >> and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, >> hence, most of the hardware config and settings are reused for this board. >> >> Changes since v1: >> - Rebased all the patches >> >> Changes since v2: >> - Rebased all the patches >> - Added new patch "Enable update mode for DREX controller" >> > >This last patch fixed USB for me, pleased you found the problem! > >The display doesn't work yet - will that be the next series? Thanks for testing. Ajay will send the patch for display. > >Also I had to drop the clock to 900MHz as with Pit. It must be >something odd I am doing, but I'm not sure what. > For my board it works fine. I am trying to reproduce it. I'll post the fix as soon as I see the problem. >Regards, >Simon Regards, Akshay Saraswat

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