November 2014 - U-Boot

[U-Boot] [PATCH] sun7i: Drop CONFIG_ARMV7_PSCI_NR_CPUS
by Hans de Goede 16 Nov '14

16 Nov '14

It is not used anywhere. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- include/configs/sun7i.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 966cbd8..7f7369c 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -33,7 +33,6 @@ #define CONFIG_ARMV7_VIRT 1 #define CONFIG_ARMV7_NONSEC 1 #define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 2 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_SYS_CLK_FREQ 24000000 -- 2.1.0

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[U-Boot] [PATCH 0/6] arm: socfpga: Add Designware SPI support
by Stefan Roese 16 Nov '14

16 Nov '14

Hi! This patchset adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible. As mentioned above, this patchset depends on the SoCFPGA DT support. And its also done on-top of the Cadence QSPI support I posted a short while ago. But it doesn't depend on it. Its just that the patch series will most likely generate merge conflicts if not applied in this sequence. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Thanks, Stefan Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com>

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[U-Boot] [PATCH 0/7] MIPS: bootm fixes and initial device tree support
by Daniel Schwierzeck 16 Nov '14

16 Nov '14

This patch series fixes and prepares bootm to initially support the hand over of flattened device trees to the kernel. The first patch fixes the missing initramfs relocation if bootm is used without subcommands. Patches 3 and 4 make the legacy boot interface configurable. Patch 5 adds mem, rd_start and rd_size to kernel command line for targets those do not use the legacy Linux env. Patch 6 adds the required code to prepare a flattened device tree for the kernel. The final hand over to the kernel is not yet implemented. After the community agreed on the official MIPS boot interface for device trees, the corresponding code will be added. Daniel Schwierzeck (7): MIPS: bootm: add missing initramfs relocation MIPS: bootm: remove unused or redundant header files MIPS: bootm: refactor preparation of Linux kernel command line MIPS: bootm: refactor preparation of Linux kernel environment MIPS: bootm: add mem, rd_start and rd_size to kernel command line MIPS: bootm: prepare a flattened device tree for the kernel MIPS: bootm: add bootstage reporting arch/mips/Kconfig | 33 ++++++++++++++ arch/mips/lib/bootm.c | 121 ++++++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 146 insertions(+), 8 deletions(-) -- 2.1.3

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[U-Boot] [patch] net: micrel: configure skew values for
by Pavel Machek 16 Nov '14

16 Nov '14

This adds skew timing configuration for micrel ksz9021 configuration. With this patch, I can add #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" #define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 #define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" #define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 to my board's configuration file, and get working networking in u-boot. Signed-off-by: Pavel Machek <pavel(a)denx.de> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 507b9a3..7e4dbd6 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -117,12 +119,31 @@ static int ksz9021_config(struct phy_device *phydev) { unsigned ctrl1000 = 0; const unsigned master = CTRL1000_PREFER_MASTER | - CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; + CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG; unsigned features = phydev->drv->features; + /* min rx data delay */ + if (ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16, + CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0) + return -1; + /* min tx data delay */ + if (ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + getenv_ulong(CONFIG_KSZ9021_DATA_SKEW_ENV, 16, + CONFIG_KSZ9021_DATA_SKEW_VAL)) < 0) + return -1; + /* max rx/tx clock delay, min rx/tx control */ + if (ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + getenv_ulong(CONFIG_KSZ9021_CLK_SKEW_ENV, 16, + CONFIG_KSZ9021_CLK_SKEW_VAL)) < 0) + return -1; + if (getenv("disable_giga")) features &= ~(SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full); + SUPPORTED_1000baseT_Full); /* force master mode for 1000BaseT due to chip errata */ if (features & SUPPORTED_1000baseT_Half) ctrl1000 |= ADVERTISE_1000HALF | master; -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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[U-Boot] [PATCH v2] arm: socfpga: set skew settings for ethernet phy
by dinguyen＠opensource.altera.com 16 Nov '14

16 Nov '14

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5 hardware. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Vince Bridgers <vbridger(a)opensource.altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Wolfgang Denk <wd(a)denx.de> --- v2: Added comments on why it is necessary for setting the skew values. --- board/altera/socfpga/socfpga_cyclone5.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d89..543a143 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -8,7 +8,9 @@ #include <asm/arch/reset_manager.h> #include <asm/io.h> +#include <micrel.h> #include <netdev.h> +#include <phy.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,3 +41,17 @@ int board_init(void) return 0; } + +int board_phy_config(struct phy_device *phydev) +{ + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); +} -- 2.0.3

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[U-Boot] iMX6 DDR Calibration Value
by John Tobias 15 Nov '14

15 Nov '14

Hi Fabio / Stefano, May be you could help me to get some answer regarding with calibrations value for DDR. I have a 4 custom boards based on iMX6SL (2) Micron DDR and (2) Samsung DDR. The boards has exact DDR footprints (like density, bus width and so on). In fact the uboot that I am using works on both DDR chips. I re-ran the DDR tools twice for each boards, entered the same information. The tools returned different calibration values for each boards but, the two results for each boards were the same. e.g: board1 Read DQS Gating calibration MPDGCTRL0 PHY0 (0x021b083c) = 0x412C0130 MPDGCTRL1 PHY0 (0x021b0840) = 0x01140118 Read calibration MPRDDLCTL PHY0 (0x021b0848) = 0x3E404244 Write calibration MPWRDLCTL PHY0 (0x021b0850) = 0x383C3E36 board2: Read DQS Gating calibration MPDGCTRL0 PHY0 (0x021b083c) = 0x412C0130 MPDGCTRL1 PHY0 (0x021b0840) = 0x01140118 Read calibration MPRDDLCTL PHY0 (0x021b0848) = 0x3E3E4244 Write calibration MPWRDLCTL PHY0 (0x021b0850) = 0x383C3E36 Is there any procedures or rules of thumb you follow dealing with the calibration settings?. Regards, John

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[U-Boot] Memory test post relocation
by DaveKucharczyk 15 Nov '14

15 Nov '14

We have 2GB’s of RAM starting at 0x70000000 on our Freescale MX53 based board. With old U-Boot we defined TEXT_BASE at the bottom of RAM at 0x70600000 and CONFIG_SKIP_RELOCATE_UBOOT, presumably so that we can run memory tests all the way to the top of RAM (this was brought over from the mx53loco board and precedes me). Why else would CONFIG_SKIP_RELOCATE_UBOOT be set? In new U-Boot we are not skipping relocation. I define CONFIG_SYS_TEXT_BASE = 0xeff89000 so that relocation offset is 0x00000000. I run with DEBUG on to doublecheck where things get setup… I run a memory test from 0x70000000 to 0xefe88cb0, but I get a mismatch fail at 0xefe88aa4. Shouldn’t I be able to run mem test all the way to the stack? I don’t see anything else being setup under the stack. -- View this message in context: http://u-boot.10912.n7.nabble.com/Memory-test-post-relocation-tp196088.html Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [Patch v2] driver/ddr/fsl: Add workaround for faulty SPD
by York Sun 15 Nov '14

15 Nov '14

Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun(a)freescale.com> --- Change log v2: Fix typo in commit subject drivers/ddr/fsl/ddr4_dimm_params.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index 4745b7f..eb82e50 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -126,6 +126,12 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, { unsigned int retval; int i; + const u8 udimm_rc_e_dq[18] = { + 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15, + 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36 + }; + int spd_error = 0; + u8 *ptr; if (spd->mem_type) { if (spd->mem_type != SPD_MEMTYPE_DDR4) { @@ -179,6 +185,22 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, /* Unbuffered DIMMs */ if (spd->mod_section.unbuffered.addr_mapping & 0x1) pdimm->mirrored_dimm = 1; + if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 && + (spd->mod_section.unbuffered.ref_raw_card == 0x04)) { + /* Fix SPD error found on DIMMs with raw card E0 */ + for (i = 0; i < 18; i++) { + if (spd->mapping[i] == udimm_rc_e_dq[i]) + continue; + spd_error = 1; + debug("SPD byte %d: 0x%x, should be 0x%x\n", + 60 + i, spd->mapping[i], + udimm_rc_e_dq[i]); + ptr = (u8 *)&spd->mapping[i]; + *ptr = udimm_rc_e_dq[i]; + } + if (spd_error) + puts("SPD DQ mapping error fixed\n"); + } break; default: -- 1.7.9.5

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[U-Boot] [PATCH] driver/ddr/fsl: Add workaround for fauty SPD
by York Sun 15 Nov '14

15 Nov '14

Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun(a)freescale.com> --- drivers/ddr/fsl/ddr4_dimm_params.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index 4745b7f..eb82e50 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -126,6 +126,12 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, { unsigned int retval; int i; + const u8 udimm_rc_e_dq[18] = { + 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15, + 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36 + }; + int spd_error = 0; + u8 *ptr; if (spd->mem_type) { if (spd->mem_type != SPD_MEMTYPE_DDR4) { @@ -179,6 +185,22 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, /* Unbuffered DIMMs */ if (spd->mod_section.unbuffered.addr_mapping & 0x1) pdimm->mirrored_dimm = 1; + if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 && + (spd->mod_section.unbuffered.ref_raw_card == 0x04)) { + /* Fix SPD error found on DIMMs with raw card E0 */ + for (i = 0; i < 18; i++) { + if (spd->mapping[i] == udimm_rc_e_dq[i]) + continue; + spd_error = 1; + debug("SPD byte %d: 0x%x, should be 0x%x\n", + 60 + i, spd->mapping[i], + udimm_rc_e_dq[i]); + ptr = (u8 *)&spd->mapping[i]; + *ptr = udimm_rc_e_dq[i]; + } + if (spd_error) + puts("SPD DQ mapping error fixed\n"); + } break; default: -- 1.7.9.5

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[U-Boot] [PATCH v4] powerpc/85xx: enable some P1/P2 boards mtdparts for nor flash
by Yangbo Lu 14 Nov '14

14 Nov '14

Enable these boards mtdparts for nor flash: p1020rdb-pd, p1021rdb-pc, p1022ds, p1025twr, and p2020rdb-pc. Signed-off-by: Xie Xiaobo <X.Xie(a)freescale.com> Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> Cc: Scott Wood <scottwood(a)freescale.com> --- Changes for v2: - changed commit message - fixed max line length problem in code Changes for v3: - added a Cc to York Sun Changes for v4 - added 36-bit physical address support --- include/configs/P1022DS.h | 19 ++++++++++++++++++ include/configs/p1_p2_rdb_pc.h | 44 ++++++++++++++++++++++++++++++++++++++++++ include/configs/p1_twr.h | 12 ++++++++++++ 3 files changed, 75 insertions(+) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 139d4fe..5828ecf 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -620,6 +620,25 @@ #endif /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fe8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=e8000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ + "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ + "512k(dtb),768k(u-boot)" +#endif + +/* * Environment */ #ifdef CONFIG_SPIFLASH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 07b6179..a973246 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -77,6 +77,16 @@ #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ + "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif #if defined(CONFIG_P1021RDB) @@ -95,6 +105,24 @@ #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#endif #endif #if defined(CONFIG_P1024RDB) @@ -142,6 +170,22 @@ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#endif #endif #ifdef CONFIG_SDCARD diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index c296a07..d3093f5 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -389,6 +389,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TWR-P1025 */ /* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),5632k(kernel),57856k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" + +/* * Environment */ #ifdef CONFIG_SYS_RAMBOOT -- 2.1.0.27.g96db324

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