September 2013 - U-Boot

[U-Boot] [PATCH] powerpc/B4860: enable PBL tool for B4860
by shh.xie＠gmail.com 27 Sep '13

27 Sep '13

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/b4860qds/b4_pbi.cfg | 27 +++++++++++++++++++++++++++ board/freescale/b4860qds/b4_rcw.cfg | 7 +++++++ include/configs/B4860QDS.h | 2 ++ 3 files changed, 36 insertions(+), 0 deletions(-) create mode 100644 board/freescale/b4860qds/b4_pbi.cfg create mode 100644 board/freescale/b4860qds/b4_rcw.cfg diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg new file mode 100644 index 0000000..57b726e --- /dev/null +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -0,0 +1,27 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg new file mode 100644 index 0000000..7bf0066 --- /dev/null +++ b/board/freescale/b4860qds/b4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x2A_0x98 +140e0018 0f001218 00000000 00000000 +54980000 9000a000 f8025000 a9000000 +01000000 00000000 00000000 0001b1f8 +00000000 14000020 00000000 00000011 diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 3082d00..05c1632 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -32,6 +32,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/t4240: updated rcw_cfg to align with default hardware configuration
by shh.xie＠gmail.com 27 Sep '13

27 Sep '13

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/t4qds/t4_rcw.cfg | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 6ac95ff..74df01a 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 #serdes protocol 1_28_6_12 -14180019 0c101916 00000000 00000000 -04383060 30548c00 6c020000 19000000 -00000000 ee0000ee 00000000 000187fc -00000000 00000000 00000000 00000018 +120c0019 0c101915 00000000 00000000 +04383063 30548c00 6c020000 1d000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000020 -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/usb: Mention usb1 before usb2 inside default hwconfig string
by Ramneek Mehresh 27 Sep '13

27 Sep '13

For USB device-tree fix-up to work properly, its necessary to mention USB1 options before that of USB2 inside default hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> --- include/configs/corenet_ds.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c3fb80c..1ccefb0 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -700,8 +700,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1;" \ - "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ -- 1.7.11.7

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[U-Boot] [PATCH][v2] board/bsc9131rdb: Update IFC timings for NAND flash
by Prabhakar Kushwaha 27 Sep '13

27 Sep '13

Current IFC timings for NAND flash are not able to support existing K9F1G08U0B and new K9F1G08U0D flash. so Update the timings to support both. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: updated subject include/configs/BSC9131RDB.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 948394e..1d06c50 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -181,18 +181,18 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ - | FTIM0_NAND_TWP(0x06) \ - | FTIM0_NAND_TWCHT(0x03) \ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ + | FTIM0_NAND_TWP(0x05) \ + | FTIM0_NAND_TWCHT(0x02) \ | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ - | FTIM1_NAND_TWBE(0x23) \ - | FTIM1_NAND_TRR(0x08) \ +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ + | FTIM1_NAND_TWBE(0x1E) \ + | FTIM1_NAND_TRR(0x07) \ | FTIM1_NAND_TRP(0x05)) #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x3f)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + | FTIM2_NAND_TWHRE(0x11)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -- 1.7.9.5

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[U-Boot] [PATCH 1/3] powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPL
by ying.zhang＠freescale.com 27 Sep '13

27 Sep '13

From: Ying Zhang <b40530(a)freescale.com> Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530(a)freescale.com> --- board/freescale/p1_p2_rdb_pc/Makefile | 3 + board/freescale/p1_p2_rdb_pc/spl.c | 98 +++++++++++++++++++++++++++++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 21 +++---- include/configs/p1_p2_rdb_pc.h | 59 +++++++++++++++----- 4 files changed, 155 insertions(+), 26 deletions(-) create mode 100644 board/freescale/p1_p2_rdb_pc/spl.c diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index f8d0b35..202b4a5 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -21,6 +21,9 @@ ifdef MINIMAL COBJS-y += spl_minimal.o tlb.o law.o else +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +endif COBJS-y += $(BOARD).o COBJS-y += ddr.o diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c new file mode 100644 index 0000000..5b8e0ff --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -0,0 +1,98 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ns16550.h> +#include <malloc.h> +#include <mmc.h> +#include <nand.h> +#include <i2c.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = bus_clk; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + env_init(); +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ + env_relocate(); + +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + gd->ram_size = initdram(0); + puts("Second program loader running in sram...\n"); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#endif +} diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index d4561c7..d6afa7b 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -78,17 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1), -#else +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -101,8 +92,14 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), #endif /* P1020MBG */ -#endif /* not L2 SRAM */ #endif /* RAMBOOT/SPL */ + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 5f0c4fb..19a1699 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -144,19 +144,33 @@ #define CONFIG_SYS_L2_SIZE (512 << 10) #endif -#if CONFIG_SYS_L2_SIZE >= (512 << 10) -/* must be 32-bit */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#endif - #ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE (96 * 1024) +#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #ifdef CONFIG_SPIFLASH @@ -526,6 +540,23 @@ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif +/* + * Config the L2 Cache as L2 SRAM +*/ +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#endif +#endif + /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 @@ -536,7 +567,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) #define CONFIG_NS16550_MIN_FUNCTIONS #endif @@ -742,7 +773,7 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_RAMBOOT_SDCARD) +#elif defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 -- 1.7.0.4

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[U-Boot] [PATCH 1/2] Corenet/p5040/SGMII:fix the problem for SGMII5/6
by Zhao Qiang 27 Sep '13

27 Sep '13

SGMII5/6 and SGMII7/8 are not on the same slot on P5040 according to the serdes protocol. So it is not proper to organize SGMII5/6 and SGMII7/8 on one bus and SGMII5/6 can't work. So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for SGMII5/6 Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- board/freescale/corenet_ds/eth_superhydra.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index ae07073..00925a6 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -465,6 +465,8 @@ int board_eth_init(bd_t *bis) "SUPER_HYDRA_FM1_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM2_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM3_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM1_TGEC_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, @@ -654,10 +656,22 @@ int board_eth_init(bd_t *bis) break; }; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); + if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { + super_hydra_mdio_set_mux( + "SUPER_HYDRA_FM3_SGMII_MDIO", + mdio_mux[i].mask, + mdio_mux[i].val); + fm_info_set_mdio(i, miiphy_get_dev_by_name( + "SUPER_HYDRA_FM3_SGMII_MDIO")); + } else { + super_hydra_mdio_set_mux( + "SUPER_HYDRA_FM2_SGMII_MDIO", + mdio_mux[i].mask, + mdio_mux[i].val); + fm_info_set_mdio(i, miiphy_get_dev_by_name( + "SUPER_HYDRA_FM2_SGMII_MDIO")); + } + break; case PHY_INTERFACE_MODE_RGMII: /* -- 1.8.0

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[U-Boot] [PATCH][v2] powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator
by Prabhakar Kushwaha 27 Sep '13

27 Sep '13

CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: Rebased with respect to below patch "[PATCH][v2] powerpc/mpc85xx:Update processor defines for T1040" arch/powerpc/cpu/mpc85xx/speed.c | 114 +++++++++++++++++------------ arch/powerpc/include/asm/config_mpc85xx.h | 14 ++++ arch/powerpc/include/asm/immap_85xx.h | 21 ++---- 3 files changed, 89 insertions(+), 60 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 07690f9..c7054c8 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -18,6 +18,10 @@ DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif /* --------------------------------------------------------------- */ void get_sys_info(sys_info_t *sys_info) @@ -30,6 +34,9 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; +#endif const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -60,8 +67,11 @@ void get_sys_info(sys_info_t *sys_info) [13] = 2, /* CC4 PPL / 2 */ [14] = 4, /* CC4 PPL / 4 */ }; - uint i, freq_cc_pll[6], rcw_tmp; - uint ratio[6]; + uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) + uint rcw_tmp; +#endif + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; @@ -81,37 +91,36 @@ void get_sys_info(sys_info_t *sys_info) else sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; - ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; - ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; - ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; - ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; - ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f; - ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f; - for (i = 0; i < 6; i++) { + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; if (ratio[i] > 4) - freq_cc_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = sysclk * ratio[i]; else - freq_cc_pll[i] = sys_info->freq_systembus * ratio[i]; + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* + * As per CHASSIS2 architeture total 12 clusters are posible and * Each cluster has up to 4 cores, sharing the same PLL selection. - * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are - * cluster group A, feeding cores on cluster 1 and cluster 2. - * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3 - * and cluster 4 if existing. + * The cluster clock assignment is SoC defined. + * + * Total 4 clock groups are possible with 3 PLLs each. + * as per array indices, clock group A has 0, 1, 2 numbered PLLs & + * clock group B has 3, 4, 6 and so on. + * + * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster + * depends upon the SoC architeture. Same applies to other + * clock groups and clusters. + * */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { int cluster = fsl_qoriq_core_to_cluster(cpu); u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; - if (cplx_pll > 3) - printf("Unsupported architecture configuration" - " in function %s\n", __func__); - cplx_pll += (cluster / 2) * 3; + cplx_pll += cc_group[cluster] - 1; sys_info->freq_processor[cpu] = - freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } #ifdef CONFIG_PPC_B4860 #define FM1_CLK_SEL 0xe0000000 @@ -122,27 +131,30 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) rcw_tmp = in_be32(&gur->rcwsr[7]); +#endif #ifdef CONFIG_SYS_DPAA_PME +#ifndef CONFIG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sys_info->freq_pme = freq_cc_pll[0]; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; break; case 2: - sys_info->freq_pme = freq_cc_pll[0] / 2; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; break; case 3: - sys_info->freq_pme = freq_cc_pll[0] / 3; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; break; case 4: - sys_info->freq_pme = freq_cc_pll[0] / 4; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; break; case 6: - sys_info->freq_pme = freq_cc_pll[1] / 2; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; break; case 7: - sys_info->freq_pme = freq_cc_pll[1] / 3; + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); @@ -151,6 +163,10 @@ void get_sys_info(sys_info_t *sys_info) break; } +#else + sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + +#endif #endif #ifdef CONFIG_SYS_DPAA_QBMAN @@ -158,27 +174,28 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sys_info->freq_fman[0] = freq_cc_pll[3]; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; break; case 2: - sys_info->freq_fman[0] = freq_cc_pll[3] / 2; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; break; case 3: - sys_info->freq_fman[0] = freq_cc_pll[3] / 3; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; break; case 4: - sys_info->freq_fman[0] = freq_cc_pll[3] / 4; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; break; case 5: sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[0] = freq_cc_pll[4] / 2; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; break; case 7: - sys_info->freq_fman[0] = freq_cc_pll[4] / 3; + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); @@ -187,27 +204,28 @@ void get_sys_info(sys_info_t *sys_info) break; } #if (CONFIG_SYS_NUM_FMAN) == 2 +#ifdef CONFIG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sys_info->freq_fman[1] = freq_cc_pll[4]; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; break; case 2: - sys_info->freq_fman[1] = freq_cc_pll[4] / 2; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; break; case 3: - sys_info->freq_fman[1] = freq_cc_pll[4] / 3; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; break; case 4: - sys_info->freq_fman[1] = freq_cc_pll[4] / 4; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; break; case 6: - sys_info->freq_fman[1] = freq_cc_pll[3] / 2; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; break; case 7: - sys_info->freq_fman[1] = freq_cc_pll[3] / 3; + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); @@ -215,8 +233,12 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_fman[1] = sys_info->freq_systembus / 2; break; } +#endif #endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_SYS_DPAA_FMAN */ +#else + sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; +#endif +#endif #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ @@ -226,7 +248,7 @@ void get_sys_info(sys_info_t *sys_info) u32 cplx_pll = core_cplx_PLL[c_pll_sel]; sys_info->freq_processor[cpu] = - freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 @@ -246,9 +268,9 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4; + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; else - sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2; + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; } else { sys_info->freq_pme = sys_info->freq_systembus / 2; } @@ -257,18 +279,18 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4; + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; else - sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2; + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; } else { sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) - sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4; + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; else - sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2; + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; } else { sys_info->freq_fman[1] = sys_info->freq_systembus / 2; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b744049..5adee17 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -538,6 +538,7 @@ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 @@ -545,6 +546,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 3 #else #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 7 @@ -559,9 +561,12 @@ #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM1_CLK 3 +#define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" @@ -589,6 +594,7 @@ #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 @@ -605,6 +611,7 @@ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 2 @@ -616,6 +623,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -633,15 +641,21 @@ #define CONFIG_MAX_CPUS 2 #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_SDHC_CLOCK 0 #define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_PME_PLAT_CLK_DIV 2 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 +#define CONFIG_FM_PLAT_CLK_DIV 1 +#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3a10d77..00f17b6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2016,20 +2016,13 @@ typedef struct ccsr_clk { u8 res_004[0x0c]; u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ u8 res_014[0x0c]; - } clkcsr[8]; - u8 res_100[0x700]; /* 0x100 */ - u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */ - u8 res10[0x1c]; - u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */ - u8 res11[0x1c]; - u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */ - u8 res12[0x1c]; - u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */ - u8 res13[0x1c]; - u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */ - u8 res14[0x1c]; - u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */ - u8 res15[0x35c]; + } clkcsr[12]; + u8 res_100[0x680]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res10[0x1c]; + } pllcgsr[12]; + u8 res21[0x280]; u32 pllpgsr; /* 0xc00 Platform PLL General Status */ u8 res16[0x1c]; u32 plldgsr; /* 0xc20 DDR PLL General Status */ -- 1.7.9.5

2 1

[U-Boot] [PATCH][v2] powerpc/mpc85xx:Update processor defines for T1040
by Prabhakar Kushwaha 27 Sep '13

27 Sep '13

T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities So, update the defines accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2: - Remove LIODIN changes. It will be send later arch/powerpc/include/asm/config_mpc85xx.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 15e44de..b744049 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -20,6 +20,7 @@ #define CONFIG_PPC_SPINTABLE_COMPATIBLE #define FSL_DDR_VER_4_7 47 +#define FSL_DDR_VER_5_0 50 /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) @@ -626,22 +627,24 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#define CONFIG_MAX_CPUS 2 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 16 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -- 1.7.9.5

2 1

[U-Boot] [PATCH][v3] powerpc: Fix CamelCase warnings in DDR related code
by Priyanka Jain 27 Sep '13

27 Sep '13

Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Changes for v3: Updated patch description. Fix warning related to force_2T in board specific files. Changes for v2: Corrected CamelCase error related to twoT_en and threeT_en which got missed in v0 patch. Thanks to Prabhakar Kushwaha for helping in finding this issue. .../powerpc/cpu/mpc8xxx/ddr/common_timing_params.h | 46 ++-- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 76 +++--- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 2 +- arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c | 52 ++-- arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 52 ++-- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 54 ++-- arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 312 ++++++++++---------- .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 214 +++++++------- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 6 +- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 34 +- arch/powerpc/include/asm/fsl_ddr_dimm_params.h | 48 ++-- arch/powerpc/include/asm/fsl_ddr_sdram.h | 28 +- arch/powerpc/include/asm/immap_512x.h | 4 +- board/exmeritus/hww1u1a/ddr.c | 2 +- board/freescale/b4860qds/ddr.c | 32 +- board/freescale/bsc9131rdb/ddr.c | 26 +- board/freescale/bsc9132qds/ddr.c | 26 +- board/freescale/c29xpcie/ddr.c | 26 +- board/freescale/corenet_ds/ddr.c | 6 +- board/freescale/mpc8349emds/ddr.c | 8 +- board/freescale/mpc8540ads/ddr.c | 2 +- board/freescale/mpc8544ds/ddr.c | 2 +- board/freescale/mpc8560ads/ddr.c | 2 +- board/freescale/mpc8572ds/ddr.c | 6 +- board/freescale/mpc8610hpcd/ddr.c | 2 +- board/freescale/mpc8641hpcn/ddr.c | 2 +- board/freescale/p1010rdb/ddr.c | 26 +- board/freescale/p1022ds/ddr.c | 6 +- board/freescale/p1023rdb/ddr.c | 26 +- board/freescale/p1_p2_rdb_pc/ddr.c | 130 ++++---- board/freescale/p2020ds/ddr.c | 6 +- board/freescale/p2041rdb/ddr.c | 6 +- board/freescale/t4qds/ddr.c | 4 +- board/freescale/t4qds/ddr.h | 2 +- board/stx/stxgp3/ddr.c | 2 +- board/stx/stxssa/ddr.c | 2 +- board/xes/xpedite550x/ddr.c | 2 +- include/ddr_spd.h | 56 ++-- 38 files changed, 670 insertions(+), 668 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h index 06706ed..17d8d9f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h @@ -12,39 +12,39 @@ typedef struct { /* parameters to constrict */ - unsigned int tCKmin_X_ps; - unsigned int tCKmax_ps; - unsigned int tCKmax_max_ps; - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; - - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* maximum = 255 ns + 256 ns + .75 ns + unsigned int tckmin_x_ps; + unsigned int tckmax_ps; + unsigned int tckmax_max_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; + + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns = 511750 ps */ - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ unsigned int ndimms_present; unsigned int lowest_common_SPD_caslat; unsigned int highest_common_derated_caslat; unsigned int additive_latency; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; - unsigned int all_DIMMs_ECC_capable; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + unsigned int all_dimms_ecc_capable; unsigned long long total_mem; unsigned long long base_address; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 242eb47..d7333ba 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -353,14 +353,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, /* Control Adjust */ unsigned int cntl_adj = 0; - ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4; - ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4; - ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4; + ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; + ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; + ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; ext_caslat = (2 * cas_latency - 1) >> 4; - ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; + ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ - ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) + - (popts->OTF_burst_chop_en ? 2 : 0)) >> 4; + ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + + (popts->otf_burst_chop_en ? 2 : 0)) >> 4; ddr->timing_cfg_3 = (0 | ((ext_pretoact & 0x1) << 28) @@ -400,9 +400,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, static const u8 wrrec_table[] = { 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; - pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps); - acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps); + pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); + acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); + acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); /* * Translate CAS Latency to a DDR controller field value: @@ -433,17 +433,17 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, caslat_ctrl = 2 * cas_latency - 1; #endif - refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); + refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; + wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); if (wrrec_mclk > 16) printf("Error: WRREC doesn't support more than 16 clocks\n"); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; - if (popts->OTF_burst_chop_en) + if (popts->otf_burst_chop_en) wrrec_mclk += 2; - acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps); + acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); /* * JEDEC has min requirement for tRRD */ @@ -451,7 +451,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, if (acttoact_mclk < 4) acttoact_mclk = 4; #endif - wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); + wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); /* * JEDEC has some min requirements for tWTR */ @@ -462,7 +462,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, if (wrtord_mclk < 4) wrtord_mclk = 4; #endif - if (popts->OTF_burst_chop_en) + if (popts->otf_burst_chop_en) wrtord_mclk += 2; ddr->timing_cfg_1 = (0 @@ -518,7 +518,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, wr_lat = compute_cas_write_latency(); #endif - rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps); + rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); /* * JEDEC has some min requirements for tRTP */ @@ -531,12 +531,12 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, #endif if (additive_latency) rd_to_pre += additive_latency; - if (popts->OTF_burst_chop_en) + if (popts->otf_burst_chop_en) rd_to_pre += 2; /* according to UM */ wr_data_delay = popts->write_data_delay; - cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps); - four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); + cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps); + four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); ddr->timing_cfg_2 = (0 | ((add_lat_mclk & 0xf) << 28) @@ -555,8 +555,8 @@ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm) { - if (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered) { + if (common_dimm->all_dimms_registered && + !common_dimm->all_dimms_unbuffered) { if (popts->rcw_override) { ddr->ddr_sdram_rcw_1 = popts->rcw_1; ddr->ddr_sdram_rcw_2 = popts->rcw_2; @@ -599,8 +599,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int dbw; /* DRAM dta bus width */ unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ unsigned int ncap = 0; /* Non-concurrent auto-precharge */ - unsigned int threeT_en; /* Enable 3T timing */ - unsigned int twoT_en; /* Enable 2T timing */ + unsigned int threet_en; /* Enable 3T timing */ + unsigned int twot_en; /* Enable 2T timing */ unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ unsigned int x32_en = 0; /* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ @@ -610,20 +610,20 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, mem_en = 1; sren = popts->self_refresh_in_sleep; - if (common_dimm->all_DIMMs_ECC_capable) { + if (common_dimm->all_dimms_ecc_capable) { /* Allow setting of ECC only if all DIMMs are ECC. */ - ecc_en = popts->ECC_mode; + ecc_en = popts->ecc_mode; } else { ecc_en = 0; } - if (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered) { + if (common_dimm->all_dimms_registered && + !common_dimm->all_dimms_unbuffered) { rd_en = 1; - twoT_en = 0; + twot_en = 0; } else { rd_en = 0; - twoT_en = popts->twoT_en; + twot_en = popts->twot_en; } sdram_type = CONFIG_FSL_SDRAM_TYPE; @@ -643,7 +643,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, eight_be = 1; } - threeT_en = popts->threeT_en; + threet_en = popts->threet_en; ba_intlv_ctl = popts->ba_intlv_ctl; hse = popts->half_strength_driver_enable; @@ -657,8 +657,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((dbw & 0x3) << 19) | ((eight_be & 0x1) << 18) | ((ncap & 0x1) << 17) - | ((threeT_en & 0x1) << 16) - | ((twoT_en & 0x1) << 15) + | ((threet_en & 0x1) << 16) + | ((twot_en & 0x1) << 15) | ((ba_intlv_ctl & 0x7F) << 8) | ((x32_en & 0x1) << 5) | ((pchb8 & 0x1) << 4) @@ -691,7 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, int i; dll_rst_dis = 1; /* Make this configurable */ - dqs_cfg = popts->DQS_config; + dqs_cfg = popts->dqs_config; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (popts->cs_local_opts[i].odt_rd_cfg || popts->cs_local_opts[i].odt_wr_cfg) { @@ -710,7 +710,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, * << DDR_SDRAM_INTERVAL[REFINT] */ #if defined(CONFIG_FSL_DDR3) - obc_cfg = popts->OTF_burst_chop_en; + obc_cfg = popts->otf_burst_chop_en; #else obc_cfg = 0; #endif @@ -730,7 +730,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ - d_init = popts->ECC_init_using_memctl; + d_init = popts->ecc_init_using_memctl; ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); #else @@ -939,7 +939,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, */ dll_on = 1; - wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; + wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps; if (wr_mclk <= 16) { wr = wr_table[wr_mclk - 5]; } else { @@ -1101,7 +1101,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR2) const unsigned int mclk_ps = get_memory_clk_period_ps(); #endif - dqs_en = !popts->DQS_config; + dqs_en = !popts->dqs_config; rtt = fsl_ddr_get_rtt(); al = additive_latency; @@ -1130,7 +1130,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR1) wr = 0; /* Historical */ #elif defined(CONFIG_FSL_DDR2) - wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1; + wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1; #endif dll_res = 0; mode = 0; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index c173a5a..e3b414e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -72,7 +72,7 @@ unsigned int compute_lowest_common_dimm_parameters( const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); -unsigned int populate_memctl_options(int all_DIMMs_registered, +unsigned int populate_memctl_options(int all_dimms_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c index 376be2f..f137fce 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c @@ -287,57 +287,57 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, * The SPD clk_cycle field (tCKmin) is measured in tenths of * nanoseconds and represented as BCD. */ - pdimm->tCKmin_X_ps + pdimm->tckmin_x_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tCKmin_X_minus_1_ps + pdimm->tckmin_x_minus_1_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tCKmin_X_minus_2_ps + pdimm->tckmin_x_minus_2_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - pdimm->tCKmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); + pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); /* * Compute CAS latencies defined by SPD - * The SPD caslat_X should have at least 1 and at most 3 bits set. + * The SPD caslat_x should have at least 1 and at most 3 bits set. * * If cas_lat after masking is 0, the __ilog2 function returns * 255 into the variable. This behavior is abused once. */ - pdimm->caslat_X = __ilog2(spd->cas_lat); - pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X)); - pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X) - & ~(1 << pdimm->caslat_X_minus_1)); + pdimm->caslat_x = __ilog2(spd->cas_lat); + pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x)); + pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x) + & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); /* Compute timing parameters */ - pdimm->tRCD_ps = spd->trcd * 250; - pdimm->tRP_ps = spd->trp * 250; - pdimm->tRAS_ps = spd->tras * 1000; + pdimm->trcd_ps = spd->trcd * 250; + pdimm->trp_ps = spd->trp * 250; + pdimm->tras_ps = spd->tras * 1000; - pdimm->tWR_ps = mclk_to_picos(3); - pdimm->tWTR_ps = mclk_to_picos(1); - pdimm->tRFC_ps = compute_trfc_ps_from_spd(0, spd->trfc); + pdimm->twr_ps = mclk_to_picos(3); + pdimm->twtr_ps = mclk_to_picos(1); + pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); - pdimm->tRRD_ps = spd->trrd * 250; - pdimm->tRC_ps = compute_trc_ps_from_spd(0, spd->trc); + pdimm->trrd_ps = spd->trrd * 250; + pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tDS_ps + pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); + pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); + pdimm->tds_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tDH_ps + pdimm->tdh_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - pdimm->tRTP_ps = mclk_to_picos(2); /* By the book. */ - pdimm->tDQSQ_max_ps = spd->tdqsq * 10; - pdimm->tQHS_ps = spd->tqhs * 10; + pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ + pdimm->tdqsq_max_ps = spd->tdqsq * 10; + pdimm->tqhs_ps = spd->tqhs * 10; return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index f637f3d..e4d02e8 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -286,57 +286,57 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, * The SPD clk_cycle field (tCKmin) is measured in tenths of * nanoseconds and represented as BCD. */ - pdimm->tCKmin_X_ps + pdimm->tckmin_x_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tCKmin_X_minus_1_ps + pdimm->tckmin_x_minus_1_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tCKmin_X_minus_2_ps + pdimm->tckmin_x_minus_2_ps = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); + pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); /* * Compute CAS latencies defined by SPD - * The SPD caslat_X should have at least 1 and at most 3 bits set. + * The SPD caslat_x should have at least 1 and at most 3 bits set. * * If cas_lat after masking is 0, the __ilog2 function returns * 255 into the variable. This behavior is abused once. */ - pdimm->caslat_X = __ilog2(spd->cas_lat); - pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X)); - pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_X) - & ~(1 << pdimm->caslat_X_minus_1)); + pdimm->caslat_x = __ilog2(spd->cas_lat); + pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x)); + pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x) + & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); /* Compute timing parameters */ - pdimm->tRCD_ps = spd->trcd * 250; - pdimm->tRP_ps = spd->trp * 250; - pdimm->tRAS_ps = spd->tras * 1000; + pdimm->trcd_ps = spd->trcd * 250; + pdimm->trp_ps = spd->trp * 250; + pdimm->tras_ps = spd->tras * 1000; - pdimm->tWR_ps = spd->twr * 250; - pdimm->tWTR_ps = spd->twtr * 250; - pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); + pdimm->twr_ps = spd->twr * 250; + pdimm->twtr_ps = spd->twtr * 250; + pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); - pdimm->tRRD_ps = spd->trrd * 250; - pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); + pdimm->trrd_ps = spd->trrd * 250; + pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tDS_ps + pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); + pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); + pdimm->tds_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tDH_ps + pdimm->tdh_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - pdimm->tRTP_ps = spd->trtp * 250; - pdimm->tDQSQ_max_ps = spd->tdqsq * 10; - pdimm->tQHS_ps = spd->tqhs * 10; + pdimm->trtp_ps = spd->trtp * 250; + pdimm->tdqsq_max_ps = spd->tdqsq * 10; + pdimm->tqhs_ps = spd->tqhs * 10; return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index b67158c..d82eb67 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -210,12 +210,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * sdram minimum cycle time * we assume the MTB is 0.125ns * eg: - * tCK_min=15 MTB (1.875ns) ->DDR3-1066 + * tck_min=15 MTB (1.875ns) ->DDR3-1066 * =12 MTB (1.5ns) ->DDR3-1333 * =10 MTB (1.25ns) ->DDR3-1600 */ - pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps + - (spd->fine_tCK_min * ftb_10th_ps) / 10; + pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + + (spd->fine_tck_min * ftb_10th_ps) / 10; /* * CAS latency supported @@ -223,55 +223,55 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * bit5 - CL5 * bit18 - CL18 */ - pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; + pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; /* * min CAS latency time - * eg: tAA_min = + * eg: taa_min = * DDR3-800D 100 MTB (12.5ns) * DDR3-1066F 105 MTB (13.125ns) * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25ns) */ - pdimm->tAA_ps = spd->tAA_min * mtb_ps + - (spd->fine_tAA_min * ftb_10th_ps) / 10; + pdimm->taa_ps = spd->taa_min * mtb_ps + + (spd->fine_taa_min * ftb_10th_ps) / 10; /* * min write recovery time * eg: - * tWR_min = 120 MTB (15ns) -> all speed grades. + * twr_min = 120 MTB (15ns) -> all speed grades. */ - pdimm->tWR_ps = spd->tWR_min * mtb_ps; + pdimm->twr_ps = spd->twr_min * mtb_ps; /* * min RAS to CAS delay time - * eg: tRCD_min = + * eg: trcd_min = * DDR3-800 100 MTB (12.5ns) * DDR3-1066F 105 MTB (13.125ns) * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25) */ - pdimm->tRCD_ps = spd->tRCD_min * mtb_ps + - (spd->fine_tRCD_min * ftb_10th_ps) / 10; + pdimm->trcd_ps = spd->trcd_min * mtb_ps + + (spd->fine_trcd_min * ftb_10th_ps) / 10; /* * min row active to row active delay time - * eg: tRRD_min = + * eg: trrd_min = * DDR3-800(1KB page) 80 MTB (10ns) * DDR3-1333(1KB page) 48 MTB (6ns) */ - pdimm->tRRD_ps = spd->tRRD_min * mtb_ps; + pdimm->trrd_ps = spd->trrd_min * mtb_ps; /* * min row precharge delay time - * eg: tRP_min = + * eg: trp_min = * DDR3-800D 100 MTB (12.5ns) * DDR3-1066F 105 MTB (13.125ns) * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25ns) */ - pdimm->tRP_ps = spd->tRP_min * mtb_ps + - (spd->fine_tRP_min * ftb_10th_ps) / 10; + pdimm->trp_ps = spd->trp_min * mtb_ps + + (spd->fine_trp_min * ftb_10th_ps) / 10; /* min active to precharge delay time * eg: tRAS_min = @@ -280,7 +280,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 288 MTB (36ns) * DDR3-1600H 280 MTB (35ns) */ - pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb) + pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) * mtb_ps; /* * min active to actice/refresh delay time @@ -290,8 +290,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 396 MTB (49.5ns) * DDR3-1600H 370 MTB (46.25ns) */ - pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb) - * mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10; + pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) + * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; /* * min refresh recovery delay time * eg: tRFC_min = @@ -299,21 +299,21 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * 1Gb 880 MTB (110ns) * 2Gb 1280 MTB (160ns) */ - pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb) + pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) * mtb_ps; /* * min internal write to read command delay time - * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins. + * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. * tWRT is at least 4 mclk independent of operating freq. */ - pdimm->tWTR_ps = spd->tWTR_min * mtb_ps; + pdimm->twtr_ps = spd->twtr_min * mtb_ps; /* * min internal read to precharge command delay time - * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins. + * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. * tRTP is at least 4 mclk independent of operating freq. */ - pdimm->tRTP_ps = spd->tRTP_min * mtb_ps; + pdimm->trtp_ps = spd->trtp_min * mtb_ps; /* * Average periodic refresh interval @@ -324,13 +324,13 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, /* * min four active window delay time - * eg: tFAW_min = + * eg: tfaw_min = * DDR3-800(1KB page) 320 MTB (40ns) * DDR3-1066(1KB page) 300 MTB (37.5ns) * DDR3-1333(1KB page) 240 MTB (30ns) * DDR3-1600(1KB page) 240 MTB (30ns) */ - pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) + pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) * mtb_ps; return 0; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index 260fce5..3b66112 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -150,33 +150,33 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; static const struct options_string options[] = { - COMMON_TIMING(tCKmin_X_ps), - COMMON_TIMING(tCKmax_ps), - COMMON_TIMING(tCKmax_max_ps), - COMMON_TIMING(tRCD_ps), - COMMON_TIMING(tRP_ps), - COMMON_TIMING(tRAS_ps), - COMMON_TIMING(tWR_ps), - COMMON_TIMING(tWTR_ps), - COMMON_TIMING(tRFC_ps), - COMMON_TIMING(tRRD_ps), - COMMON_TIMING(tRC_ps), + COMMON_TIMING(tckmin_x_ps), + COMMON_TIMING(tckmax_ps), + COMMON_TIMING(tckmax_max_ps), + COMMON_TIMING(trcd_ps), + COMMON_TIMING(trp_ps), + COMMON_TIMING(tras_ps), + COMMON_TIMING(twr_ps), + COMMON_TIMING(twtr_ps), + COMMON_TIMING(trfc_ps), + COMMON_TIMING(trrd_ps), + COMMON_TIMING(trc_ps), COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tIS_ps), - COMMON_TIMING(tIH_ps), - COMMON_TIMING(tDS_ps), - COMMON_TIMING(tDH_ps), - COMMON_TIMING(tRTP_ps), - COMMON_TIMING(tDQSQ_max_ps), - COMMON_TIMING(tQHS_ps), + COMMON_TIMING(tis_ps), + COMMON_TIMING(tih_ps), + COMMON_TIMING(tds_ps), + COMMON_TIMING(tdh_ps), + COMMON_TIMING(trtp_ps), + COMMON_TIMING(tdqsq_max_ps), + COMMON_TIMING(tqhs_ps), COMMON_TIMING(ndimms_present), COMMON_TIMING(lowest_common_SPD_caslat), COMMON_TIMING(highest_common_derated_caslat), COMMON_TIMING(additive_latency), - COMMON_TIMING(all_DIMMs_burst_lengths_bitmask), - COMMON_TIMING(all_DIMMs_registered), - COMMON_TIMING(all_DIMMs_unbuffered), - COMMON_TIMING(all_DIMMs_ECC_capable), + COMMON_TIMING(all_dimms_burst_lengths_bitmask), + COMMON_TIMING(all_dimms_registered), + COMMON_TIMING(all_dimms_unbuffered), + COMMON_TIMING(all_dimms_ecc_capable), COMMON_TIMING(total_mem), COMMON_TIMING(base_address), }; @@ -214,34 +214,34 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(burst_lengths_bitmask), DIMM_PARM(row_density), - DIMM_PARM(tCKmin_X_ps), - DIMM_PARM(tCKmin_X_minus_1_ps), - DIMM_PARM(tCKmin_X_minus_2_ps), - DIMM_PARM(tCKmax_ps), + DIMM_PARM(tckmin_x_ps), + DIMM_PARM(tckmin_x_minus_1_ps), + DIMM_PARM(tckmin_x_minus_2_ps), + DIMM_PARM(tckmax_ps), - DIMM_PARM(caslat_X), - DIMM_PARM(caslat_X_minus_1), - DIMM_PARM(caslat_X_minus_2), + DIMM_PARM(caslat_x), + DIMM_PARM(caslat_x_minus_1), + DIMM_PARM(caslat_x_minus_2), DIMM_PARM(caslat_lowest_derated), - DIMM_PARM(tRCD_ps), - DIMM_PARM(tRP_ps), - DIMM_PARM(tRAS_ps), - DIMM_PARM(tWR_ps), - DIMM_PARM(tWTR_ps), - DIMM_PARM(tRFC_ps), - DIMM_PARM(tRRD_ps), - DIMM_PARM(tRC_ps), + DIMM_PARM(trcd_ps), + DIMM_PARM(trp_ps), + DIMM_PARM(tras_ps), + DIMM_PARM(twr_ps), + DIMM_PARM(twtr_ps), + DIMM_PARM(trfc_ps), + DIMM_PARM(trrd_ps), + DIMM_PARM(trc_ps), DIMM_PARM(refresh_rate_ps), - DIMM_PARM(tIS_ps), - DIMM_PARM(tIH_ps), - DIMM_PARM(tDS_ps), - DIMM_PARM(tDH_ps), - DIMM_PARM(tRTP_ps), - DIMM_PARM(tDQSQ_max_ps), - DIMM_PARM(tQHS_ps), + DIMM_PARM(tis_ps), + DIMM_PARM(tih_ps), + DIMM_PARM(tds_ps), + DIMM_PARM(tdh_ps), + DIMM_PARM(trtp_ps), + DIMM_PARM(tdqsq_max_ps), + DIMM_PARM(tqhs_ps), DIMM_PARM(rank_density), DIMM_PARM(capacity), @@ -271,34 +271,34 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(edc_config), DIMM_PARM(n_banks_per_sdram_device), - DIMM_PARM(tCKmin_X_ps), - DIMM_PARM(tCKmin_X_minus_1_ps), - DIMM_PARM(tCKmin_X_minus_2_ps), - DIMM_PARM(tCKmax_ps), + DIMM_PARM(tckmin_x_ps), + DIMM_PARM(tckmin_x_minus_1_ps), + DIMM_PARM(tckmin_x_minus_2_ps), + DIMM_PARM(tckmax_ps), - DIMM_PARM(caslat_X), - DIMM_PARM(tAA_ps), - DIMM_PARM(caslat_X_minus_1), - DIMM_PARM(caslat_X_minus_2), + DIMM_PARM(caslat_x), + DIMM_PARM(taa_ps), + DIMM_PARM(caslat_x_minus_1), + DIMM_PARM(caslat_x_minus_2), DIMM_PARM(caslat_lowest_derated), - DIMM_PARM(tRCD_ps), - DIMM_PARM(tRP_ps), - DIMM_PARM(tRAS_ps), - DIMM_PARM(tWR_ps), - DIMM_PARM(tWTR_ps), - DIMM_PARM(tRFC_ps), - DIMM_PARM(tRRD_ps), - DIMM_PARM(tRC_ps), + DIMM_PARM(trcd_ps), + DIMM_PARM(trp_ps), + DIMM_PARM(tras_ps), + DIMM_PARM(twr_ps), + DIMM_PARM(twtr_ps), + DIMM_PARM(trfc_ps), + DIMM_PARM(trrd_ps), + DIMM_PARM(trc_ps), DIMM_PARM(refresh_rate_ps), - DIMM_PARM(tIS_ps), - DIMM_PARM(tIH_ps), - DIMM_PARM(tDS_ps), - DIMM_PARM(tDH_ps), - DIMM_PARM(tRTP_ps), - DIMM_PARM(tDQSQ_max_ps), - DIMM_PARM(tQHS_ps), + DIMM_PARM(tis_ps), + DIMM_PARM(tih_ps), + DIMM_PARM(tds_ps), + DIMM_PARM(tdh_ps), + DIMM_PARM(trtp_ps), + DIMM_PARM(tdqsq_max_ps), + DIMM_PARM(tqhs_ps), }; static const unsigned int n_opts = ARRAY_SIZE(options); @@ -325,41 +325,41 @@ static void print_lowest_common_dimm_parameters( const common_timing_params_t *plcd_dimm_params) { static const struct options_string options[] = { - COMMON_TIMING(tCKmax_max_ps), - COMMON_TIMING(tRCD_ps), - COMMON_TIMING(tRP_ps), - COMMON_TIMING(tRAS_ps), - COMMON_TIMING(tWR_ps), - COMMON_TIMING(tWTR_ps), - COMMON_TIMING(tRFC_ps), - COMMON_TIMING(tRRD_ps), - COMMON_TIMING(tRC_ps), + COMMON_TIMING(tckmax_max_ps), + COMMON_TIMING(trcd_ps), + COMMON_TIMING(trp_ps), + COMMON_TIMING(tras_ps), + COMMON_TIMING(twr_ps), + COMMON_TIMING(twtr_ps), + COMMON_TIMING(trfc_ps), + COMMON_TIMING(trrd_ps), + COMMON_TIMING(trc_ps), COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tIS_ps), - COMMON_TIMING(tDS_ps), - COMMON_TIMING(tDH_ps), - COMMON_TIMING(tRTP_ps), - COMMON_TIMING(tDQSQ_max_ps), - COMMON_TIMING(tQHS_ps), + COMMON_TIMING(tis_ps), + COMMON_TIMING(tds_ps), + COMMON_TIMING(tdh_ps), + COMMON_TIMING(trtp_ps), + COMMON_TIMING(tdqsq_max_ps), + COMMON_TIMING(tqhs_ps), COMMON_TIMING(lowest_common_SPD_caslat), COMMON_TIMING(highest_common_derated_caslat), COMMON_TIMING(additive_latency), COMMON_TIMING(ndimms_present), - COMMON_TIMING(all_DIMMs_registered), - COMMON_TIMING(all_DIMMs_unbuffered), - COMMON_TIMING(all_DIMMs_ECC_capable), + COMMON_TIMING(all_dimms_registered), + COMMON_TIMING(all_dimms_unbuffered), + COMMON_TIMING(all_dimms_ecc_capable), }; static const unsigned int n_opts = ARRAY_SIZE(options); /* Clock frequencies */ - printf("tCKmin_X_ps = %u (%u MHz)\n", - plcd_dimm_params->tCKmin_X_ps, - picos_to_mhz(plcd_dimm_params->tCKmin_X_ps)); - printf("tCKmax_ps = %u (%u MHz)\n", - plcd_dimm_params->tCKmax_ps, - picos_to_mhz(plcd_dimm_params->tCKmax_ps)); - printf("all_DIMMs_burst_lengths_bitmask = %02X\n", - plcd_dimm_params->all_DIMMs_burst_lengths_bitmask); + printf("tckmin_x_ps = %u (%u MHz)\n", + plcd_dimm_params->tckmin_x_ps, + picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); + printf("tckmax_ps = %u (%u MHz)\n", + plcd_dimm_params->tckmax_ps, + picos_to_mhz(plcd_dimm_params->tckmax_ps)); + printf("all_dimms_burst_lengths_bitmask = %02X\n", + plcd_dimm_params->all_dimms_burst_lengths_bitmask); print_option_table(options, n_opts, plcd_dimm_params); @@ -421,9 +421,9 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(memctl_interleaving), CTRL_OPTIONS(memctl_interleaving_mode), CTRL_OPTIONS(ba_intlv_ctl), - CTRL_OPTIONS(ECC_mode), - CTRL_OPTIONS(ECC_init_using_memctl), - CTRL_OPTIONS(DQS_config), + CTRL_OPTIONS(ecc_mode), + CTRL_OPTIONS(ecc_init_using_memctl), + CTRL_OPTIONS(dqs_config), CTRL_OPTIONS(self_refresh_in_sleep), CTRL_OPTIONS(dynamic_power), CTRL_OPTIONS(data_bus_width), @@ -442,8 +442,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, * These can probably be changed to 2T_EN and 3T_EN * (using a leading numerical character) without problem */ - CTRL_OPTIONS(twoT_en), - CTRL_OPTIONS(threeT_en), + CTRL_OPTIONS(twot_en), + CTRL_OPTIONS(threet_en), CTRL_OPTIONS(ap_en), CTRL_OPTIONS(x4_en), CTRL_OPTIONS(bstopre), @@ -455,8 +455,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(rcw_2), CTRL_OPTIONS(ddr_cdr1), CTRL_OPTIONS(ddr_cdr2), - CTRL_OPTIONS(tCKE_clock_pulse_width_ps), - CTRL_OPTIONS(tFAW_window_four_activates_ps), + CTRL_OPTIONS(tcke_clock_pulse_width_ps), + CTRL_OPTIONS(tfaw_window_four_activates_ps), CTRL_OPTIONS(trwt_override), CTRL_OPTIONS(trwt), }; @@ -666,9 +666,9 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(memctl_interleaving), CTRL_OPTIONS(memctl_interleaving_mode), CTRL_OPTIONS_HEX(ba_intlv_ctl), - CTRL_OPTIONS(ECC_mode), - CTRL_OPTIONS(ECC_init_using_memctl), - CTRL_OPTIONS(DQS_config), + CTRL_OPTIONS(ecc_mode), + CTRL_OPTIONS(ecc_init_using_memctl), + CTRL_OPTIONS(dqs_config), CTRL_OPTIONS(self_refresh_in_sleep), CTRL_OPTIONS(dynamic_power), CTRL_OPTIONS(data_bus_width), @@ -686,8 +686,8 @@ static void print_memctl_options(const memctl_options_t *popts) * These can probably be changed to 2T_EN and 3T_EN * (using a leading numerical character) without problem */ - CTRL_OPTIONS(twoT_en), - CTRL_OPTIONS(threeT_en), + CTRL_OPTIONS(twot_en), + CTRL_OPTIONS(threet_en), CTRL_OPTIONS(registered_dimm_en), CTRL_OPTIONS(ap_en), CTRL_OPTIONS(x4_en), @@ -700,8 +700,8 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(rcw_2), CTRL_OPTIONS_HEX(ddr_cdr1), CTRL_OPTIONS_HEX(ddr_cdr2), - CTRL_OPTIONS(tCKE_clock_pulse_width_ps), - CTRL_OPTIONS(tFAW_window_four_activates_ps), + CTRL_OPTIONS(tcke_clock_pulse_width_ps), + CTRL_OPTIONS(tfaw_window_four_activates_ps), CTRL_OPTIONS(trwt_override), CTRL_OPTIONS(trwt), }; @@ -958,10 +958,10 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); printf("%-3d : %02x %s\n", 46, spd->pll_relock, " spd->pll_relock, * 46 PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->Tcasemax, - " spd->Tcasemax, * 47 Tcasemax *"); - printf("%-3d : %02x %s\n", 48, spd->psiTAdram, - " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package " + printf("%-3d : %02x %s\n", 47, spd->t_casemax, + " spd->t_casemax, * 47 t_casemax *"); + printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, + " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " "from Top (Case) to Ambient (Psi T-A DRAM) *"); printf("%-3d : %02x %s\n", 49, spd->dt0_mode, " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " @@ -996,11 +996,11 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) " spd->dt7, * 57 DRAM Case Temperature Rise from " "Ambient due to Bank Interleave Reads with " "Auto-Precharge (DT7) *"); - printf("%-3d : %02x %s\n", 58, spd->psiTApll, - " spd->psiTApll, * 58 Thermal Resistance of PLL Package form" + printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, + " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" " Top (Case) to Ambient (Psi T-A PLL) *"); - printf("%-3d : %02x %s\n", 59, spd->psiTAreg, - " spd->psiTAreg, * 59 Thermal Reisitance of Register Package" + printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, + " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" " from Top (Case) to Ambient (Psi T-A Register) *"); printf("%-3d : %02x %s\n", 60, spd->dtpllactive, " spd->dtpllactive, * 60 PLL Case Temperature Rise from " @@ -1087,43 +1087,43 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) "mtb_dividend Medium Timebase (MTB) Dividend"); PRINT_NXS(11, spd->mtb_divisor, "mtb_divisor Medium Timebase (MTB) Divisor"); - PRINT_NXS(12, spd->tCK_min, - "tCK_min SDRAM Minimum Cycle Time"); + PRINT_NXS(12, spd->tck_min, + "tck_min SDRAM Minimum Cycle Time"); PRINT_NXS(13, spd->res_13, "res_13 Reserved"); PRINT_NXS(14, spd->caslat_lsb, "caslat_lsb CAS Latencies Supported, LSB"); PRINT_NXS(15, spd->caslat_msb, "caslat_msb CAS Latencies Supported, MSB"); - PRINT_NXS(16, spd->tAA_min, - "tAA_min Min CAS Latency Time"); - PRINT_NXS(17, spd->tWR_min, - "tWR_min Min Write REcovery Time"); - PRINT_NXS(18, spd->tRCD_min, - "tRCD_min Min RAS# to CAS# Delay Time"); - PRINT_NXS(19, spd->tRRD_min, - "tRRD_min Min Row Active to Row Active Delay Time"); - PRINT_NXS(20, spd->tRP_min, - "tRP_min Min Row Precharge Delay Time"); - PRINT_NXS(21, spd->tRAS_tRC_ext, - "tRAS_tRC_ext Upper Nibbles for tRAS and tRC"); - PRINT_NXS(22, spd->tRAS_min_lsb, - "tRAS_min_lsb Min Active to Precharge Delay Time, LSB"); - PRINT_NXS(23, spd->tRC_min_lsb, - "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB"); - PRINT_NXS(24, spd->tRFC_min_lsb, - "tRFC_min_lsb Min Refresh Recovery Delay Time LSB"); - PRINT_NXS(25, spd->tRFC_min_msb, - "tRFC_min_msb Min Refresh Recovery Delay Time MSB"); - PRINT_NXS(26, spd->tWTR_min, - "tWTR_min Min Internal Write to Read Command Delay Time"); - PRINT_NXS(27, spd->tRTP_min, - "tRTP_min " - "Min Internal Read to Precharge Command Delay Time"); - PRINT_NXS(28, spd->tFAW_msb, - "tFAW_msb Upper Nibble for tFAW"); - PRINT_NXS(29, spd->tFAW_min, - "tFAW_min Min Four Activate Window Delay Time"); + PRINT_NXS(16, spd->taa_min, + "taa_min Min CAS Latency Time"); + PRINT_NXS(17, spd->twr_min, + "twr_min Min Write REcovery Time"); + PRINT_NXS(18, spd->trcd_min, + "trcd_min Min RAS# to CAS# Delay Time"); + PRINT_NXS(19, spd->trrd_min, + "trrd_min Min Row Active to Row Active Delay Time"); + PRINT_NXS(20, spd->trp_min, + "trp_min Min Row Precharge Delay Time"); + PRINT_NXS(21, spd->tras_trc_ext, + "tras_trc_ext Upper Nibbles for tRAS and tRC"); + PRINT_NXS(22, spd->tras_min_lsb, + "tras_min_lsb Min Active to Precharge Delay Time, LSB"); + PRINT_NXS(23, spd->trc_min_lsb, + "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); + PRINT_NXS(24, spd->trfc_min_lsb, + "trfc_min_lsb Min Refresh Recovery Delay Time LSB"); + PRINT_NXS(25, spd->trfc_min_msb, + "trfc_min_msb Min Refresh Recovery Delay Time MSB"); + PRINT_NXS(26, spd->twtr_min, + "twtr_min Min Internal Write to Read Command Delay Time"); + PRINT_NXS(27, spd->trtp_min, + "trtp_min " + "Min Internal Read to Precharge Command Delay Time"); + PRINT_NXS(28, spd->tfaw_msb, + "tfaw_msb Upper Nibble for tFAW"); + PRINT_NXS(29, spd->tfaw_min, + "tfaw_min Min Four Activate Window Delay Time"); PRINT_NXS(30, spd->opt_features, "opt_features SDRAM Optional Features"); PRINT_NXS(31, spd->therm_ref_opt, @@ -1132,16 +1132,16 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) "therm_sensor SDRAM Thermal Sensor"); PRINT_NXS(33, spd->device_type, "device_type SDRAM Device Type"); - PRINT_NXS(34, spd->fine_tCK_min, - "fine_tCK_min Fine offset for tCKmin"); - PRINT_NXS(35, spd->fine_tAA_min, - "fine_tAA_min Fine offset for tAAmin"); - PRINT_NXS(36, spd->fine_tRCD_min, - "fine_tRCD_min Fine offset for tRCDmin"); - PRINT_NXS(37, spd->fine_tRP_min, - "fine_tRP_min Fine offset for tRPmin"); - PRINT_NXS(38, spd->fine_tRC_min, - "fine_tRC_min Fine offset for tRCmin"); + PRINT_NXS(34, spd->fine_tck_min, + "fine_tck_min Fine offset for tCKmin"); + PRINT_NXS(35, spd->fine_taa_min, + "fine_taa_min Fine offset for tAAmin"); + PRINT_NXS(36, spd->fine_trcd_min, + "fine_trcd_min Fine offset for tRCDmin"); + PRINT_NXS(37, spd->fine_trp_min, + "fine_trp_min Fine offset for tRPmin"); + PRINT_NXS(38, spd->fine_trc_min, + "fine_trc_min Fine offset for tRCmin"); printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 56128a7..3affcee 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -18,8 +18,8 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, unsigned int number_of_dimms) { unsigned int i; - unsigned int tAAmin_ps = 0; - unsigned int tCKmin_X_ps = 0; + unsigned int taamin_ps = 0; + unsigned int tckmin_x_ps = 0; unsigned int common_caslat; unsigned int caslat_actual; unsigned int retry = 16; @@ -27,26 +27,26 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, const unsigned int mclk_ps = get_memory_clk_period_ps(); /* compute the common CAS latency supported between slots */ - tmp = dimm_params[0].caslat_X; + tmp = dimm_params[0].caslat_x; for (i = 1; i < number_of_dimms; i++) { if (dimm_params[i].n_ranks) - tmp &= dimm_params[i].caslat_X; + tmp &= dimm_params[i].caslat_x; } common_caslat = tmp; /* compute the max tAAmin tCKmin between slots */ for (i = 0; i < number_of_dimms; i++) { - tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps); - tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps); + taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); + tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); } /* validate if the memory clk is in the range of dimms */ - if (mclk_ps < tCKmin_X_ps) { + if (mclk_ps < tckmin_x_ps) { printf("DDR clock (MCLK cycle %u ps) is faster than " "the slowest DIMM(s) (tCKmin %u ps) can support.\n", - mclk_ps, tCKmin_X_ps); + mclk_ps, tckmin_x_ps); } /* determine the acutal cas latency */ - caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps; + caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps; /* check if the dimms support the CAS latency */ while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { caslat_actual++; @@ -80,25 +80,25 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, { unsigned int i, j; - unsigned int tCKmin_X_ps = 0; - unsigned int tCKmax_ps = 0xFFFFFFFF; - unsigned int tCKmax_max_ps = 0; - unsigned int tRCD_ps = 0; - unsigned int tRP_ps = 0; - unsigned int tRAS_ps = 0; - unsigned int tWR_ps = 0; - unsigned int tWTR_ps = 0; - unsigned int tRFC_ps = 0; - unsigned int tRRD_ps = 0; - unsigned int tRC_ps = 0; + unsigned int tckmin_x_ps = 0; + unsigned int tckmax_ps = 0xFFFFFFFF; + unsigned int tckmax_max_ps = 0; + unsigned int trcd_ps = 0; + unsigned int trp_ps = 0; + unsigned int tras_ps = 0; + unsigned int twr_ps = 0; + unsigned int twtr_ps = 0; + unsigned int trfc_ps = 0; + unsigned int trrd_ps = 0; + unsigned int trc_ps = 0; unsigned int refresh_rate_ps = 0; - unsigned int tIS_ps = 0; - unsigned int tIH_ps = 0; - unsigned int tDS_ps = 0; - unsigned int tDH_ps = 0; - unsigned int tRTP_ps = 0; - unsigned int tDQSQ_max_ps = 0; - unsigned int tQHS_ps = 0; + unsigned int tis_ps = 0; + unsigned int tih_ps = 0; + unsigned int tds_ps = 0; + unsigned int tdh_ps = 0; + unsigned int trtp_ps = 0; + unsigned int tdqsq_max_ps = 0; + unsigned int tqhs_ps = 0; unsigned int temp1, temp2; unsigned int additive_latency = 0; @@ -141,39 +141,39 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, } #endif /* - * Find minimum tCKmax_ps to find fastest slow speed, + * Find minimum tckmax_ps to find fastest slow speed, * i.e., this is the slowest the whole system can go. */ - tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps); + tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps); /* Either find maximum value to determine slowest * speed, delay, time, period, etc */ - tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps); - tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps); - tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps); - tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps); - tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps); - tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps); - tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps); - tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps); - tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps); - tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps); - tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps); - tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps); - tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps); - tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps); - tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps); - tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps); + tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); + tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps); + trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps); + trp_ps = max(trp_ps, dimm_params[i].trp_ps); + tras_ps = max(tras_ps, dimm_params[i].tras_ps); + twr_ps = max(twr_ps, dimm_params[i].twr_ps); + twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps); + trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps); + trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps); + trc_ps = max(trc_ps, dimm_params[i].trc_ps); + tis_ps = max(tis_ps, dimm_params[i].tis_ps); + tih_ps = max(tih_ps, dimm_params[i].tih_ps); + tds_ps = max(tds_ps, dimm_params[i].tds_ps); + tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps); + trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); + tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps); refresh_rate_ps = max(refresh_rate_ps, dimm_params[i].refresh_rate_ps); /* - * Find maximum tDQSQ_max_ps to find slowest. + * Find maximum tdqsq_max_ps to find slowest. * * FIXME: is finding the slowest value the correct * strategy for this parameter? */ - tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps); + tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps); } outpdimm->ndimms_present = number_of_dimms - temp1; @@ -183,25 +183,25 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, return 0; } - outpdimm->tCKmin_X_ps = tCKmin_X_ps; - outpdimm->tCKmax_ps = tCKmax_ps; - outpdimm->tCKmax_max_ps = tCKmax_max_ps; - outpdimm->tRCD_ps = tRCD_ps; - outpdimm->tRP_ps = tRP_ps; - outpdimm->tRAS_ps = tRAS_ps; - outpdimm->tWR_ps = tWR_ps; - outpdimm->tWTR_ps = tWTR_ps; - outpdimm->tRFC_ps = tRFC_ps; - outpdimm->tRRD_ps = tRRD_ps; - outpdimm->tRC_ps = tRC_ps; + outpdimm->tckmin_x_ps = tckmin_x_ps; + outpdimm->tckmax_ps = tckmax_ps; + outpdimm->tckmax_max_ps = tckmax_max_ps; + outpdimm->trcd_ps = trcd_ps; + outpdimm->trp_ps = trp_ps; + outpdimm->tras_ps = tras_ps; + outpdimm->twr_ps = twr_ps; + outpdimm->twtr_ps = twtr_ps; + outpdimm->trfc_ps = trfc_ps; + outpdimm->trrd_ps = trrd_ps; + outpdimm->trc_ps = trc_ps; outpdimm->refresh_rate_ps = refresh_rate_ps; - outpdimm->tIS_ps = tIS_ps; - outpdimm->tIH_ps = tIH_ps; - outpdimm->tDS_ps = tDS_ps; - outpdimm->tDH_ps = tDH_ps; - outpdimm->tRTP_ps = tRTP_ps; - outpdimm->tDQSQ_max_ps = tDQSQ_max_ps; - outpdimm->tQHS_ps = tQHS_ps; + outpdimm->tis_ps = tis_ps; + outpdimm->tih_ps = tih_ps; + outpdimm->tds_ps = tds_ps; + outpdimm->tdh_ps = tdh_ps; + outpdimm->trtp_ps = trtp_ps; + outpdimm->tdqsq_max_ps = tdqsq_max_ps; + outpdimm->tqhs_ps = tqhs_ps; /* Determine common burst length for all DIMMs. */ temp1 = 0xff; @@ -210,7 +210,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, temp1 &= dimm_params[i].burst_lengths_bitmask; } } - outpdimm->all_DIMMs_burst_lengths_bitmask = temp1; + outpdimm->all_dimms_burst_lengths_bitmask = temp1; /* Determine if all DIMMs registered buffered. */ temp1 = temp2 = 0; @@ -232,19 +232,19 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, } } - outpdimm->all_DIMMs_registered = 0; - outpdimm->all_DIMMs_unbuffered = 0; + outpdimm->all_dimms_registered = 0; + outpdimm->all_dimms_unbuffered = 0; if (temp1 && !temp2) { - outpdimm->all_DIMMs_registered = 1; + outpdimm->all_dimms_registered = 1; } else if (!temp1 && temp2) { - outpdimm->all_DIMMs_unbuffered = 1; + outpdimm->all_dimms_unbuffered = 1; } else { printf("ERROR: Mix of registered buffered and unbuffered " "DIMMs detected!\n"); } temp1 = 0; - if (outpdimm->all_DIMMs_registered) + if (outpdimm->all_dimms_registered) for (j = 0; j < 16; j++) { outpdimm->rcw[j] = dimm_params[0].rcw[j]; for (i = 1; i < number_of_dimms; i++) { @@ -279,13 +279,13 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, for (i = 0; i < number_of_dimms; i++) { if (dimm_params[i].n_ranks) { temp2 = 0; - temp2 |= 1 << dimm_params[i].caslat_X; - temp2 |= 1 << dimm_params[i].caslat_X_minus_1; - temp2 |= 1 << dimm_params[i].caslat_X_minus_2; + temp2 |= 1 << dimm_params[i].caslat_x; + temp2 |= 1 << dimm_params[i].caslat_x_minus_1; + temp2 |= 1 << dimm_params[i].caslat_x_minus_2; /* * FIXME: If there was no entry for X-2 (X-1) in - * the SPD, then caslat_X_minus_2 - * (caslat_X_minus_1) contains either 255 or + * the SPD, then caslat_x_minus_2 + * (caslat_x_minus_1) contains either 255 or * 0xFFFFFFFF because that's what the glorious * __ilog2 function returns for an input of 0. * On 32-bit PowerPC, left shift counts with bit @@ -313,42 +313,42 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, if (!dimm_params[i].n_ranks) { continue; } - if (dimm_params[i].caslat_X == temp2) { - if (mclk_ps >= dimm_params[i].tCKmin_X_ps) { + if (dimm_params[i].caslat_x == temp2) { + if (mclk_ps >= dimm_params[i].tckmin_x_ps) { debug("CL = %u ok on DIMM %u at tCK=%u" " ps with its tCKmin_X_ps of %u\n", temp2, i, mclk_ps, - dimm_params[i].tCKmin_X_ps); + dimm_params[i].tckmin_x_ps); continue; } else { not_ok++; } } - if (dimm_params[i].caslat_X_minus_1 == temp2) { - unsigned int tCKmin_X_minus_1_ps - = dimm_params[i].tCKmin_X_minus_1_ps; - if (mclk_ps >= tCKmin_X_minus_1_ps) { + if (dimm_params[i].caslat_x_minus_1 == temp2) { + unsigned int tckmin_x_minus_1_ps + = dimm_params[i].tckmin_x_minus_1_ps; + if (mclk_ps >= tckmin_x_minus_1_ps) { debug("CL = %u ok on DIMM %u at " "tCK=%u ps with its " - "tCKmin_X_minus_1_ps of %u\n", + "tckmin_x_minus_1_ps of %u\n", temp2, i, mclk_ps, - tCKmin_X_minus_1_ps); + tckmin_x_minus_1_ps); continue; } else { not_ok++; } } - if (dimm_params[i].caslat_X_minus_2 == temp2) { - unsigned int tCKmin_X_minus_2_ps - = dimm_params[i].tCKmin_X_minus_2_ps; - if (mclk_ps >= tCKmin_X_minus_2_ps) { + if (dimm_params[i].caslat_x_minus_2 == temp2) { + unsigned int tckmin_x_minus_2_ps + = dimm_params[i].tckmin_x_minus_2_ps; + if (mclk_ps >= tckmin_x_minus_2_ps) { debug("CL = %u ok on DIMM %u at " "tCK=%u ps with its " - "tCKmin_X_minus_2_ps of %u\n", + "tckmin_x_minus_2_ps of %u\n", temp2, i, mclk_ps, - tCKmin_X_minus_2_ps); + tckmin_x_minus_2_ps); continue; } else { not_ok++; @@ -397,11 +397,11 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, } else { debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); } - outpdimm->all_DIMMs_ECC_capable = temp1; + outpdimm->all_dimms_ecc_capable = temp1; #ifndef CONFIG_FSL_DDR3 /* FIXME: move to somewhere else to validate. */ - if (mclk_ps > tCKmax_max_ps) { + if (mclk_ps > tckmax_max_ps) { printf("Warning: some of the installed DIMMs " "can not operate this slowly.\n"); return 1; @@ -464,10 +464,10 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, #if defined(CONFIG_FSL_DDR2) if (lowest_good_caslat < 4) { - additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat) - ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0; - if (mclk_to_picos(additive_latency) > tRCD_ps) { - additive_latency = picos_to_mclk(tRCD_ps); + additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat) + ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0; + if (mclk_to_picos(additive_latency) > trcd_ps) { + additive_latency = picos_to_mclk(trcd_ps); debug("setting additive_latency to %u because it was " " greater than tRCD_ps\n", additive_latency); } @@ -487,7 +487,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, * * AL <= tRCD(min) */ - if (mclk_to_picos(additive_latency) > tRCD_ps) { + if (mclk_to_picos(additive_latency) > trcd_ps) { printf("Error: invalid additive latency exceeds tRCD(min).\n"); return 1; } @@ -507,15 +507,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, */ outpdimm->additive_latency = additive_latency; - debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps); - debug("tRCD_ps = %u\n", outpdimm->tRCD_ps); - debug("tRP_ps = %u\n", outpdimm->tRP_ps); - debug("tRAS_ps = %u\n", outpdimm->tRAS_ps); - debug("tWR_ps = %u\n", outpdimm->tWR_ps); - debug("tWTR_ps = %u\n", outpdimm->tWTR_ps); - debug("tRFC_ps = %u\n", outpdimm->tRFC_ps); - debug("tRRD_ps = %u\n", outpdimm->tRRD_ps); - debug("tRC_ps = %u\n", outpdimm->tRC_ps); + debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps); + debug("trcd_ps = %u\n", outpdimm->trcd_ps); + debug("trp_ps = %u\n", outpdimm->trp_ps); + debug("tras_ps = %u\n", outpdimm->tras_ps); + debug("twr_ps = %u\n", outpdimm->twr_ps); + debug("twtr_ps = %u\n", outpdimm->twtr_ps); + debug("trfc_ps = %u\n", outpdimm->trfc_ps); + debug("trrd_ps = %u\n", outpdimm->trrd_ps); + debug("trc_ps = %u\n", outpdimm->trc_ps); return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 842bf19..b9ae950 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -457,7 +457,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, * which is currently STEP_ASSIGN_ADDRESSES. */ populate_memctl_options( - timing_params[i].all_DIMMs_registered, + timing_params[i].all_dimms_registered, &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); /* @@ -466,7 +466,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, * using fixed parameters, this function should be * be called from board init file. */ - if (timing_params[i].all_DIMMs_registered) + if (timing_params[i].all_dimms_registered) assert_reset = 1; } if (assert_reset) { @@ -589,7 +589,7 @@ phys_size_t fsl_ddr_sdram(void) */ deassert_reset = board_need_mem_reset(); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.common_timing_params[i].all_DIMMs_registered) + if (info.common_timing_params[i].all_dimms_registered) deassert_reset = 1; } for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 30cdca4..1297845 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) return 0; } -unsigned int populate_memctl_options(int all_DIMMs_registered, +unsigned int populate_memctl_options(int all_dimms_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) @@ -635,20 +635,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->ba_intlv_ctl = 0; /* Memory Organization Parameters */ - popts->registered_dimm_en = all_DIMMs_registered; + popts->registered_dimm_en = all_dimms_registered; /* Operational Mode Paramters */ /* Pick ECC modes */ - popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ + popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ #ifdef CONFIG_DDR_ECC if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) - popts->ECC_mode = 1; + popts->ecc_mode = 1; } else - popts->ECC_mode = 1; + popts->ecc_mode = 1; #endif - popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ + popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ /* * Choose DQS config @@ -656,9 +656,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * 1 for DDR2 */ #if defined(CONFIG_FSL_DDR1) - popts->DQS_config = 0; + popts->dqs_config = 0; #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - popts->DQS_config = 1; + popts->dqs_config = 1; #endif /* Choose self-refresh during sleep. */ @@ -705,15 +705,15 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) #if defined(CONFIG_E500MC) - popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { /* 32-bit or 16-bit bus */ - popts->OTF_burst_chop_en = 0; + popts->otf_burst_chop_en = 0; popts->burst_length = DDR_BL8; } else { - popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ } #endif @@ -756,8 +756,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * - number of components, number of active ranks * - how much time you want to spend playing around */ - popts->twoT_en = 0; - popts->threeT_en = 0; + popts->twot_en = 0; + popts->threet_en = 0; /* for RDIMM, address parity enable */ popts->ap_en = 1; @@ -775,7 +775,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->bstopre = 0x100; /* Minimum CKE pulse width -- tCKE(MIN) */ - popts->tCKE_clock_pulse_width_ps + popts->tcke_clock_pulse_width_ps = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); /* @@ -786,17 +786,17 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * FIXME: width, was considering looking at pdimm->primary_sdram_width */ #if defined(CONFIG_FSL_DDR1) - popts->tFAW_window_four_activates_ps = mclk_to_picos(1); + popts->tfaw_window_four_activates_ps = mclk_to_picos(1); #elif defined(CONFIG_FSL_DDR2) /* * x4/x8; some datasheets have 35000 * x16 wide columns only? Use 50000? */ - popts->tFAW_window_four_activates_ps = 37500; + popts->tfaw_window_four_activates_ps = 37500; #elif defined(CONFIG_FSL_DDR3) - popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps; + popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; #endif popts->zq_en = 0; popts->wrlvl_en = 0; diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index bd312ad..2cad6e2 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -45,48 +45,48 @@ typedef struct dimm_params_s { unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ + unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ + unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ /* * SDRAM clock periods * The range for these are 1000-10000 so a short should be sufficient */ - unsigned int tCKmin_X_ps; - unsigned int tCKmin_X_minus_1_ps; - unsigned int tCKmin_X_minus_2_ps; - unsigned int tCKmax_ps; + unsigned int tckmin_x_ps; + unsigned int tckmin_x_minus_1_ps; + unsigned int tckmin_x_minus_2_ps; + unsigned int tckmax_ps; /* SPD-defined CAS latencies */ - unsigned int caslat_X; - unsigned int caslat_X_minus_1; - unsigned int caslat_X_minus_2; + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; unsigned int caslat_lowest_derated; /* Derated CAS latency */ /* basic timing parameters */ - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns = 511750 ps */ - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; /* DDR3 doesn't need these as below */ - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ /* DDR3 RDIMM */ unsigned char rcw[16]; /* Register Control Word 0-15 */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index f4eec82..2c3c514 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -219,13 +219,13 @@ typedef struct fsl_ddr_cfg_regs_s { } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { - unsigned int all_DIMMs_ECC_capable; - unsigned int all_DIMMs_tCKmax_ps; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_DIMMs_minimum_tRCD_ps; + unsigned int all_dimms_minimum_trcd_ps; } memctl_options_partial_t; #define DDR_DATA_BUS_WIDTH_64 0 @@ -261,10 +261,10 @@ typedef struct memctl_options_s { unsigned int addr_hash; /* Operational mode parameters */ - unsigned int ECC_mode; /* Use ECC? */ + unsigned int ecc_mode; /* Use ECC? */ /* Initialize ECC using memory controller? */ - unsigned int ECC_init_using_memctl; - unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ /* SREN - self-refresh during sleep */ unsigned int self_refresh_in_sleep; unsigned int dynamic_power; /* DYN_PWR */ @@ -272,7 +272,7 @@ typedef struct memctl_options_s { unsigned int data_bus_width; unsigned int burst_length; /* BL4, OTF and BL8 */ /* On-The-Fly Burst Chop enable */ - unsigned int OTF_burst_chop_en; + unsigned int otf_burst_chop_en; /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; @@ -297,11 +297,11 @@ typedef struct memctl_options_s { unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; - unsigned int twoT_en; - unsigned int threeT_en; + unsigned int twot_en; + unsigned int threet_en; unsigned int bstopre; - unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ - unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + unsigned int tcke_clock_pulse_width_ps; /* tCKE */ + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 01c9eff..814a535 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -279,8 +279,8 @@ typedef struct ddr512x { u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ - u32 DQS_config_offset_count; /* DQS Config Offset Count */ - u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 dqs_config_offset_count; /* DQS Config Offset Count */ + u32 dqs_config_offset_time; /* DQS Config Offset Time */ u32 DQS_delay_status; /* DQS Delay Status */ u32 res0[0xF]; u32 prioman_config1; /* Priority Manager Configuration */ diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c index 36d02ad..23a71d5 100644 --- a/board/exmeritus/hww1u1a/ddr.c +++ b/board/exmeritus/hww1u1a/ddr.c @@ -30,5 +30,5 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = 4; popts->cpo_override = 4; popts->write_data_delay = 2; - popts->twoT_en = 0; + popts->twot_en = 0; } diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index b82b3d4..2d14923 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -31,20 +31,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 2, /* ECC */ .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1071, - .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ - .tAA_ps = 13910, - .tWR_ps = 15000, - .tRCD_ps = 13910, - .tRRD_ps = 6000, - .tRP_ps = 13910, - .tRAS_ps = 34000, - .tRC_ps = 48910, - .tRFC_ps = 260000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1071, + .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ + .taa_ps = 13910, + .twr_ps = 15000, + .trcd_ps = 13910, + .trrd_ps = 6000, + .trp_ps = 13910, + .tras_ps = 34000, + .trc_ps = 48910, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 35000, + .tfaw_ps = 35000, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, @@ -71,7 +71,7 @@ struct board_specific_parameters { u32 wrlvl_ctl_3; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -146,7 +146,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c index c82fe0a..a9e92f2 100644 --- a/board/freescale/bsc9131rdb/ddr.c +++ b/board/freescale/bsc9131rdb/ddr.c @@ -114,20 +114,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c index fdea193..b3130be 100644 --- a/board/freescale/bsc9132qds/ddr.c +++ b/board/freescale/bsc9132qds/ddr.c @@ -136,20 +136,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index b017cfd..478e0b5 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -26,20 +26,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 2, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1650, - .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ - .tAA_ps = 14050, - .tWR_ps = 15000, - .tRCD_ps = 13500, - .tRRD_ps = 75000, - .tRP_ps = 13500, - .tRAS_ps = 40000, - .tRC_ps = 49500, - .tRFC_ps = 160000, - .tWTR_ps = 75000, - .tRTP_ps = 75000, + .tckmin_x_ps = 1650, + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ + .taa_ps = 14050, + .twr_ps = 15000, + .trcd_ps = 13500, + .trrd_ps = 75000, + .trp_ps = 13500, + .tras_ps = 40000, + .trc_ps = 49500, + .trfc_ps = 160000, + .twtr_ps = 75000, + .trtp_ps = 75000, .refresh_rate_ps = 7800000, - .tFAW_ps = 30000, + .tfaw_ps = 30000, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 517e87f..18e2ff6 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -114,7 +114,7 @@ struct board_specific_parameters { u32 wrlvl_start; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -217,7 +217,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -234,7 +234,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c index c66750e..3d257d0 100644 --- a/board/freescale/mpc8349emds/ddr.c +++ b/board/freescale/mpc8349emds/ddr.c @@ -15,7 +15,7 @@ struct board_specific_parameters { u32 clk_adjust; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -70,7 +70,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -86,7 +86,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp_highest->clk_adjust; popts->cpo_override = pbsp_highest->cpo; popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -97,5 +97,5 @@ found: * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; - popts->DQS_config = 0; /* only true DQS signal is used on board */ + popts->dqs_config = 0; /* only true DQS signal is used on board */ } diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 5711374..9e79815 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index 94219b9..6cf9bc1 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 5711374..9e79815 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index a7ff668..52e4f42 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -17,7 +17,7 @@ struct board_specific_parameters { u32 clk_adjust; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -139,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -155,7 +155,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 94219b9..6cf9bc1 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -49,7 +49,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 5d35757..651652a 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -106,5 +106,5 @@ void fsl_ddr_board_options(memctl_options_t *popts, found: /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; } diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 681f052..ab1b41d 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -172,20 +172,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1875, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index a639861..94d2c2b 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -17,7 +17,7 @@ struct board_specific_parameters { u32 clk_adjust; /* Range: 0-8 */ u32 cpo; /* Range: 2-31 */ u32 write_data_delay; /* Range: 0-6 */ - u32 force_2T; + u32 force_2t; }; /* @@ -72,7 +72,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -88,7 +88,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c index ce406b2..ea21f08 100644 --- a/board/freescale/p1023rdb/ddr.c +++ b/board/freescale/p1023rdb/ddr.c @@ -33,20 +33,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1875, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 18000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 18000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index c0b72e0..81cc093 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -34,20 +34,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; #elif defined(CONFIG_P2020RDB) /* Micron MT41J128M16_15E */ @@ -65,20 +65,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1500, - .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ - .tAA_ps = 13500, - .tWR_ps = 15000, - .tRCD_ps = 13500, - .tRRD_ps = 6000, - .tRP_ps = 13500, - .tRAS_ps = 36000, - .tRC_ps = 49500, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1500, + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ + .taa_ps = 13500, + .twr_ps = 15000, + .trcd_ps = 13500, + .trrd_ps = 6000, + .trp_ps = 13500, + .tras_ps = 36000, + .trc_ps = 49500, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 30000, + .tfaw_ps = 30000, }; #elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ @@ -96,20 +96,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1870, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; #elif defined(CONFIG_P1020RDB_PC) /* @@ -133,20 +133,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1875, - .caslat_X = 0x1e << 4, /* 5,6,7,8 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 7500, - .tRP_ps = 13125, - .tRAS_ps = 37500, - .tRC_ps = 50625, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 37500, + .tfaw_ps = 37500, }; #elif defined(CONFIG_P1024RDB) || \ defined(CONFIG_P1025RDB) @@ -171,20 +171,20 @@ dimm_params_t ddr_raw_timing = { .edc_config = 0, .burst_lengths_bitmask = 0x0c, - .tCKmin_X_ps = 1500, - .caslat_X = 0x3e << 4, /* 5,6,7,8,9 */ - .tAA_ps = 13125, - .tWR_ps = 15000, - .tRCD_ps = 13125, - .tRRD_ps = 6000, - .tRP_ps = 13125, - .tRAS_ps = 36000, - .tRC_ps = 49125, - .tRFC_ps = 160000, - .tWTR_ps = 7500, - .tRTP_ps = 7500, + .tckmin_x_ps = 1500, + .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 36000, + .trc_ps = 49125, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, .refresh_rate_ps = 7800000, - .tFAW_ps = 30000, + .tfaw_ps = 30000, }; #else #error Missing raw timing data for this board diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 59034f9..b12141f 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -17,7 +17,7 @@ struct board_specific_parameters { u32 clk_adjust; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; @@ -90,7 +90,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -106,7 +106,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp_highest->clk_adjust; popts->cpo_override = pbsp_highest->cpo; popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index 6d9a5de..cc1bfae 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -21,7 +21,7 @@ struct board_specific_parameters { u32 wrlvl_start; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* @@ -76,7 +76,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -93,7 +93,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 26ac2a5..d70c310 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -56,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twoT_en = pbsp->force_2T; + popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -75,7 +75,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twoT_en = pbsp_highest->force_2T; + popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h index d0a0951..8183af7 100644 --- a/board/freescale/t4qds/ddr.h +++ b/board/freescale/t4qds/ddr.h @@ -16,7 +16,7 @@ struct board_specific_parameters { u32 wrlvl_ctl_3; u32 cpo; u32 write_data_delay; - u32 force_2T; + u32 force_2t; }; /* diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 5711374..9e79815 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 56c87b2..71be3bf 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -37,7 +37,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 3; /* 2T timing enable */ - popts->twoT_en = 1; + popts->twot_en = 1; /* * Factors to consider for half-strength driver enable: diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 993ae80..a089597 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -108,7 +108,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; - popts->twoT_en = 0; + popts->twot_en = 0; break; } pbsp++; diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 9e74d87..a9fbb73 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -126,9 +126,10 @@ typedef struct ddr2_spd_eeprom_s { unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ unsigned char pll_relock; /* 46 PLL Relock time */ - unsigned char Tcasemax; /* 47 Tcasemax */ - unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from - Top (Case) to Ambient (Psi T-A DRAM) */ + unsigned char t_casemax; /* 47 t_casemax */ + unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package + from Top (Case) to Ambient + (Psi T-A DRAM) */ unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) */ @@ -153,10 +154,11 @@ typedef struct ddr2_spd_eeprom_s { unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) */ - unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form - Top (Case) to Ambient (Psi T-A PLL) */ - unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package - from Top (Case) to Ambient + unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package + from Top (Case) to Ambient + (Psi T-A PLL) */ + unsigned char psi_ta_reg; /* 59 Thermal Resistance of Register + Package from Top (Case) to Ambient (Psi T-A Register) */ unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) */ @@ -191,41 +193,41 @@ typedef struct ddr3_spd_eeprom_s { Dividend / Divisor */ unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ - unsigned char tCK_min; /* 12 SDRAM Minimum Cycle Time */ + unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ unsigned char res_13; /* 13 Reserved */ unsigned char caslat_lsb; /* 14 CAS Latencies Supported, Least Significant Byte */ unsigned char caslat_msb; /* 15 CAS Latencies Supported, Most Significant Byte */ - unsigned char tAA_min; /* 16 Min CAS Latency Time */ - unsigned char tWR_min; /* 17 Min Write REcovery Time */ - unsigned char tRCD_min; /* 18 Min RAS# to CAS# Delay Time */ - unsigned char tRRD_min; /* 19 Min Row Active to + unsigned char taa_min; /* 16 Min CAS Latency Time */ + unsigned char twr_min; /* 17 Min Write REcovery Time */ + unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ + unsigned char trrd_min; /* 19 Min Row Active to Row Active Delay Time */ - unsigned char tRP_min; /* 20 Min Row Precharge Delay Time */ - unsigned char tRAS_tRC_ext; /* 21 Upper Nibbles for tRAS and tRC */ - unsigned char tRAS_min_lsb; /* 22 Min Active to Precharge + unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ + unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ + unsigned char tras_min_lsb; /* 22 Min Active to Precharge Delay Time */ - unsigned char tRC_min_lsb; /* 23 Min Active to Active/Refresh + unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh Delay Time, LSB */ - unsigned char tRFC_min_lsb; /* 24 Min Refresh Recovery Delay Time */ - unsigned char tRFC_min_msb; /* 25 Min Refresh Recovery Delay Time */ - unsigned char tWTR_min; /* 26 Min Internal Write to + unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ + unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ + unsigned char twtr_min; /* 26 Min Internal Write to Read Command Delay Time */ - unsigned char tRTP_min; /* 27 Min Internal Read to Precharge + unsigned char trtp_min; /* 27 Min Internal Read to Precharge Command Delay Time */ - unsigned char tFAW_msb; /* 28 Upper Nibble for tFAW */ - unsigned char tFAW_min; /* 29 Min Four Activate Window + unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ + unsigned char tfaw_min; /* 29 Min Four Activate Window Delay Time*/ unsigned char opt_features; /* 30 SDRAM Optional Features */ unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ unsigned char therm_sensor; /* 32 Module Thermal Sensor */ unsigned char device_type; /* 33 SDRAM device type */ - int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */ - int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */ - int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */ - int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */ - int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */ + int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ + int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ + int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ + int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ + int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ /* Module-Specific Section: Bytes 60-116 */ -- 1.7.4.1

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[U-Boot] [PATCH] powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2
by Prabhakar Kushwaha 27 Sep '13

27 Sep '13

CHASSIS2 architecture never defines type of L2 cache present in SoC. it is dependent upon the core present in the SoC. for example, - e6500 core has L2 cluster (Kibo) - e5500 core has Backside L2 Cache Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +++--- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 6036333..a8107a9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -284,7 +284,7 @@ static void __fsl_serdes__init(void) } __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) int enable_cluster_l2(void) { int i = 0; @@ -350,7 +350,7 @@ int cpu_init_r(void) #endif #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -533,7 +533,7 @@ int cpu_init_r(void) } skip_l2: -#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (l2cache->l2csr0 & L2CSR0_L2E) print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 533d47a..2ccd9c7 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -273,7 +273,7 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) /* Only initialize every eighth thread */ if (reg && !((*reg) % 8)) #else diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ad57a9c..f821268 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -691,7 +691,7 @@ delete_temp_tlbs: #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: /* * Create a TLB for the MMR location of CCSR -- 1.7.9.5

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