September 2013 - U-Boot

[U-Boot] [RFD] OMAP5: Working HYP mode
by Alexander Tarasikov 02 Oct '13

02 Oct '13

Hello, u-boot developers! I am attaching a patch to enable the HYP (hypervisor) mode on the OMAP5 CPU. It is based on a previous patch by Ian Molton. For some reason, Ian's patch was incorrect (loading PC with the wrong address, missing memory barriers, and, most importantly, using the wrong SMC call). I think it is because Ian was using some early omap5 prototype, and I was using the SVT OMAP5432UEVM board which is commercially available. Since this is a gross hack, I neither expect nor want it to be merged, but I think people experimenting with ARM virtualization will find it useful. I have KVM working on OMAP5 as of now (using KVM patches from openvirtualization and some linux kernel bugfixes of my own) and I plan to write a blog post soon about how to repeat my steps. My plan is to publish the patches to fix the bugs I've found. I would like to receive comments on what is the planned way to implement the HYP switching in u-boot and whether it is possible without using the TrustZone SMC calls. Have fun

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[U-Boot] [PATCH v2 1/2] Tegra114: Fix PLLX M, N, P init settings
by Thierry Reding 01 Oct '13

01 Oct '13

From: Jimmy Zhang <jimmzhang(a)nvidia.com> The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Reviewed-by: Tom Warren <twarren(a)nvidia.com> Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- Changes in v2: - clean up table layout and comments arch/arm/cpu/arm720t/tegra-common/cpu.c | 83 +++++++++++++++++++++++---------- 1 file changed, 59 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 9294611..aa1e04f 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -49,33 +49,68 @@ int get_num_cpus(void) * Timing tables for each SOC for all four oscillator options. */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { - /* T20: 1 GHz */ - /* n, m, p, cpcon */ - {{ 1000, 13, 0, 12}, /* OSC 13M */ - { 625, 12, 0, 8}, /* OSC 19.2M */ - { 1000, 12, 0, 12}, /* OSC 12M */ - { 1000, 26, 0, 12}, /* OSC 26M */ + /* + * T20: 1 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T25: 1.2 GHz */ - {{ 923, 10, 0, 12}, - { 750, 12, 0, 8}, - { 600, 6, 0, 12}, - { 600, 13, 0, 12}, + /* + * T25: 1.2 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ + { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ + { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ + { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ }, - - /* T30: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 700, 6, 0, 8}, - { 700, 13, 0, 8}, + /* + * T30: 1.4 GHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 22:20 3 + * PLLX_BASE n 17: 8 10 + * PLLX_BASE m 4: 0 5 + * PLLX_MISC cpcon 11: 8 4 + */ + { + { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ + { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */ + { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ + { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ }, - - /* T114: 1.4 GHz */ - {{ 862, 8, 0, 8}, - { 583, 8, 0, 4}, - { 696, 12, 0, 8}, - { 700, 13, 0, 8}, + /* + * T114: 700 MHz + * + * Register Field Bits Width + * ------------------------------ + * PLLX_BASE p 23:20 4 + * PLLX_BASE n 15: 8 8 + * PLLX_BASE m 7: 0 8 + */ + { + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ }, }; -- 1.8.4

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[U-Boot] [PATCH][v2] boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLD
by Prabhakar Kushwaha 01 Oct '13

01 Oct '13

NAND,CPLD AMASK register is programmed for 64K size. so Update TLB & LAW size accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master changes for v2: - Updated both CPLD and NAND board/freescale/c29xpcie/law.c | 4 ++-- board/freescale/c29xpcie/tlb.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c index cd8fc21..80e5fff 100644 --- a/board/freescale/c29xpcie/law.c +++ b/board/freescale/c29xpcie/law.c @@ -10,8 +10,8 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, LAW_TRGT_IF_PLATFORM_SRAM), }; diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c index ddd1ef8..84844ee 100644 --- a/board/freescale/c29xpcie/tlb.c +++ b/board/freescale/c29xpcie/tlb.c @@ -46,11 +46,11 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_4K, 1), + 0, 4, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_16K, 1), + 0, 5, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, -- 1.7.9.5

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[U-Boot] [PATCH 1/1] am33xx: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width
by Pekon Gupta 01 Oct '13

01 Oct '13

NAND driver needs to know bus-width of the connected NAND device, in order to perform proper I/O and initialize itself. Currently there is no CONFIG option to provide this information to NAND driver. - SPL NAND driver does not have framework to parse ONFI parameter page. - NAND drivers which cannot self initialize !defined(CONFIG_SYS_NAND_SELF_INIT) do not have any information about device bus-width during board_nand_init(), So, any device-width specific configurations are not possible there. - There should be some mechanism to pass device bus-width information for non-ONFI compliant devices. This patch (1) adds CONFIG_SYS_NAND_DEVICE_WIDTH which can take following value 16: NAND device with x16 bus-width 8: NAND device with x8 bus-width (2) removes GPMC_NAND_ECC_LP_x16_LAYOUT, as NAND layout is determined based on ecc-scheme and oobsize during initialization in board_nand_init(). Thus this config is redundant. Signed-off-by: Pekon Gupta <pekon(a)ti.com> --- doc/README.nand | 9 +++++++++ drivers/mtd/nand/omap_gpmc.c | 18 +++++++++++------- include/configs/am335x_evm.h | 2 +- include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 -- include/configs/devkit8000.h | 3 +-- include/configs/dig297.h | 2 -- include/configs/igep0033.h | 8 ++++---- include/configs/igep00x0.h | 2 +- include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 3 +-- include/configs/omap3_evm_common.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omap3_overo.h | 3 +-- include/configs/omap3_pandora.h | 2 -- include/configs/omap3_zoom1.h | 2 -- include/configs/omap3_zoom2.h | 1 - include/configs/siemens-am33x-common.h | 8 ++++---- include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 3 +-- 21 files changed, 38 insertions(+), 40 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index f9c921e..5726ff2 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -179,6 +179,15 @@ Configuration Options: This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction. + CONFIG_SYS_NAND_DEVICE_WIDTH + Specifies bus-width of the default NAND device connected to SoC. + This config is useful for driver which cannot self initialize or + parse ONFI parameter (like SPL drivers), or for supporting non-ONFI + compliant devices. + This config can take following values: + - 8: NAND devices has bus-width=x8 + - 16: NAND device has bus-width=x16 + Platform specific options ========================= diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 68786f9..584e33e 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -214,11 +214,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; u32 ecc_size_config_val = 0; u32 ecc_config_val = 0; - u32 cs_config1_val; - /* reconfigure GPMC device-width */ - cs_config1_val = readl(&gpmc_cfg->cs[cs].config1); - writel((cs_config1_val | dev_width << 12), &gpmc_cfg->cs[cs].config1); /* configure GPMC for specific ecc-scheme */ switch (bch->ecc_scheme) { case OMAP_ECC_HAM1_CODE_SW: @@ -772,10 +768,10 @@ int board_nand_init(struct nand_chip *nand) nand->priv = &bch_priv; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) + if (CONFIG_SYS_NAND_DEVICE_WIDTH == 16) nand->options |= NAND_BUSWIDTH_16; - + else + nand->options &= ~NAND_BUSWIDTH_16; nand->chip_delay = 100; nand->ecc.layout = &omap_ecclayout; @@ -795,5 +791,13 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = omap_spl_dev_ready; #endif + /* reconfigure GPMC.CONFIG1 register with correct device-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); + if (nand->options & NAND_BUSWIDTH_16) + gpmc_config |= (0x1 << 12); + else + gpmc_config &= ~(0x1 << 12); + writel(gpmc_config, &gpmc_cfg->cs[cs].config1); + return 0; } diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 978bca7..c92cb2f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -216,6 +216,7 @@ #ifdef CONFIG_NAND #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_BLOCK_SIZE 131072 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 @@ -366,7 +367,6 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 1fd2508..0985221 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -269,7 +269,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -332,6 +331,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 6500878..8593d44 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -263,7 +263,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -326,6 +325,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index bc5b66c..1e3dd0d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -164,8 +164,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* Environment information */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cb79b4e..d6c64a3 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND @@ -318,6 +316,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 30e3908..f69bcec 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -143,8 +143,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 3e18a65..ce6b9be 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -188,7 +188,6 @@ /* NAND support */ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION 1 @@ -248,11 +247,12 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 9982cf6..7e5bc9b 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -268,7 +268,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_BASE NAND_BASE -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ @@ -354,6 +353,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 5e27ab2..d508978 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -322,7 +322,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -385,6 +384,7 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c1245e7..9050f55 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -184,8 +184,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ @@ -424,6 +422,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index edf6543..564af9a 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -210,7 +210,6 @@ #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index ee6db51..e198c4c 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -298,7 +298,6 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 88380a4..de06e20 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -120,8 +120,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND @@ -317,6 +315,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 91a2568..6ea106d 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -131,8 +131,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c747d52..1dd7b9c 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -138,8 +138,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index cb8c7ec..9ca7fbe 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -158,7 +158,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Environment information */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5426ee8..197accc 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -182,11 +182,12 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ @@ -433,7 +434,6 @@ "\0" #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 60dd8ff..1f31a87 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -188,7 +188,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ @@ -252,6 +251,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 6daea50..95bbbaa 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -106,8 +106,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_BCH @@ -284,6 +282,7 @@ /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -- 1.8.1

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[U-Boot] [PATCH] Change maintainer for Avionic Design boards
by Thierry Reding 30 Sep '13

30 Sep '13

I no longer work for Avionic Design and don't have access to hardware, so I'll pass on maintainership to Alban. Acked-by: Alban Bedel <alban.bedel(a)avionic-design.de> Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- Hi Tom, I assume this is something you'd want to take through the Tegra tree? Thierry boards.cfg | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards.cfg b/boards.cfg index dbd8479..dfd874b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -342,9 +342,9 @@ Active arm armv7 vf610 freescale vf610twr Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr(a)monstr.eu> Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr(a)monstr.eu> Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren(a)nvidia.com> -Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding(a)avionic-design.de> -Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding(a)avionic-design.de> -Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding <thierry.reding(a)avionic-design.de> +Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel(a)avionic-design.de> +Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel(a)avionic-design.de> +Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel(a)avionic-design.de> Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren(a)nvidia.com>:Stephen Warren <swarren(a)nvidia.com> Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren(a)nvidia.com> -- 1.8.4

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[U-Boot] : buildman error
by Jagan Teki 30 Sep '13

30 Sep '13

Can any one encounter this! looks like some issue on python setup? $ ./tools/buildman/buildman -b master File "./tools/buildman/buildman", line 42 print result ^ SyntaxError: invalid syntax Let me know for any input, I am using Python 3.3.0 -- Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki(a)gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki

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[U-Boot] [PATCH v2 1/2] ti814x: enable support for parallel NAND flash devices
by Pekon Gupta 30 Sep '13

30 Sep '13

TI81xx (TI816x, TI814x, TI813x) family of devices include in-built GPMC and ELM hardware controllers which have the capability to support: - x8 and x16 parallel NAND, NOR flash devices. - generation and error detection of Hamming and BCH ECC schemes. This patch enables support for detection and boot via NAND flash devices for TI814x SoC. Signed-off-by: Pekon Gupta <pekon(a)ti.com> --- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 5 +++++ arch/arm/include/asm/arch-am33xx/mux_ti814x.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index ef14f47..341f341 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -188,6 +188,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) ; + + /* GPMC */ + writel(PRCM_MOD_EN, &cmalwon->gpmcclkctrl); + while (readl(&cmalwon->gpmcclkctrl) != PRCM_MOD_EN) + ; } /* diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h index a26e503..6105b27 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h @@ -19,8 +19,9 @@ /* PAD Control Fields */ #define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ #define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ +#define PULLDOWN_EN (0x1 << 17) /* Pull UP Selection */ +#define PULL_ENABLE (0x0 << 16) /* Pull up enabled */ +#define PULL_DISABLE (0x1 << 16) /* Pull up disabled */ #define MODE(val) val /* used for Readability */ #define MUX_CFG(value, offset) \ -- 1.8.1

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Re: [U-Boot] [PATCH v7 1/5] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform
by Gupta, Pekon 30 Sep '13

30 Sep '13

Hi Stefan, > From: Stefan Roese [mailto:sr@denx.de] > > On 30.09.2013 16:13, Pekon Gupta wrote: > > BCH8_ECC scheme implemented in omap_gpmc.c driver has following > favours > > +-----------------------------------+-----------------+-----------------+ > > |ECC Scheme | ECC Calculation | Error Detection | > > +-----------------------------------+-----------------+-----------------+ > > |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | > > |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH > library | > > +-----------------------------------+-----------------+-----------------+ > > > > Current implementation limits the BCH8_CODE_HW only for AM33xx > device family. > > (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also > have > > ELM hardware module, and can support ECC error detection using ELM. > > > > This patch > > - removes CONFIG_AM33xx > > Thus this driver can be reused by all devices having ELM h/w engine. > > Do you have an overview, which TI devices actually have this ELM h/w > engine integrated? Especially if its integrated in the OMAP3530 SoC? I'm > currently scanning the users manual and can't find any reference to this > IP block. > As per my knowledge, omap device families from omap44xx onwards have ELM hardware. Example: omap44xx, omap54xx. But earlier omap devices like omap2xxx, omap34xx and omap35xx do not have ELM engine. So, If you are using omap34xx, omap35xx devices then please select OMAP_ECC_BCH8_CODE_HW_DETECTION_SW ecc-scheme. In this ecc-scheme, ECC error correction would require lib/bch.c which needs to be enabled via CONFIG_BCH. with regards, pekon

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[U-Boot] SPL port for omap l138
by Laszlo Papp 30 Sep '13

30 Sep '13

Hi all, has anyone made such a port in the path that is now readily available for reuse? I wished to have it running as the second stage boot loader, but it is not yet available I might need to fall back to the TI UBL. I would be happier to use SPL, but I would not probably have the required time, money, and skills for doing such a port for now. Thank you in advance, Laszlo

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Re: [U-Boot] [PATCH][v2] powerpc/t1040qds: Add T1040QDS board
by York Sun 30 Sep '13

30 Sep '13

On 09/29/2013 08:47 PM, Jain Priyanka-B32167 wrote: > Thanks York, > > Please update Maintainers name from "Naveen Burmi <NaveenBurmi(a)freescale.com>" to "Poonam Aggrwal <poonam.aggrwal(a)freescale.com>" in boards.cfg file. > Please include this change in next patch you will submit for T1040QDS. York

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