September 2013 - U-Boot

[U-Boot] [PATCH] gpio: mxc_gpio: Fix gpio_get_value() when the GPIO is an output
by Fabio Estevam 30 Sep '13

30 Sep '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> When the GPIO is configured as an output, we should return the value from the DR register. This implements the same fix as in the following kernel commit from FSL BSP: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm… Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Otavio, I don't have i.mx hardware access at the moment to try it, but this should fix your LED problem. drivers/gpio/mxc_gpio.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 6a572d5..debbecb 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -93,7 +93,7 @@ int gpio_get_value(unsigned gpio) { unsigned int port = GPIO_TO_PORT(gpio); struct gpio_regs *regs; - u32 val; + u32 direction; if (port >= ARRAY_SIZE(gpio_ports)) return -1; @@ -102,9 +102,12 @@ int gpio_get_value(unsigned gpio) regs = (struct gpio_regs *)gpio_ports[port]; - val = (readl(&regs->gpio_psr) >> gpio) & 0x01; + direction = readl(&regs->gpio_dir); - return val; + if ((direction >> gpio) & 1) + return (readl(&regs->gpio_dr) >> gpio) & 1; /* output mode */ + else + return (readl(&regs->gpio_psr) >> gpio) & 1; /* input mode */ } int gpio_request(unsigned gpio, const char *label) -- 1.8.1.2

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[U-Boot] i.MX6 based board does not work if watchdog support is enabled
by Otavio Salvador 30 Sep '13

30 Sep '13

Hello, I am trying to add support for watchdog in one board and it is not working as expected. I did add the: #define CONFIG_HW_WATCHDOG #define CONFIG_IMX_WATCHDOG into the board config file. Into the board .c file, I added: int board_late_init(void) { ... #ifdef CONFIG_HW_WATCHDOG hw_watchdog_init(); #endif return 0; } and the hw_watchdog_init is indeed called. It starts booting and shows: U-Boot 2013.10-rc3-00046-gc1c2434-dirty (Sep 28 2013 - 21:12:53) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: WDOG Board: yyyy DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net:� and it in fact resets. I am booting the board from USB loader. May it be an issue? -- Otavio Salvador O.S. Systems http://www.ossystems.com.br http://code.ossystems.com.br Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750

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[U-Boot] [PATCH v2 0/6] Second step towards Kbuild: Descend down like Kbuild
by Masahiro Yamada 30 Sep '13

30 Sep '13

I have been just wondering why the U-Boot top Makefile is so dirty. It is sprinkled with SoC-specific code as follows: ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif ifeq ($(SOC),s5pc1xx) LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o endif ifeq ($(SOC),exynos) LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o endif ifneq ($(CONFIG_TEGRA),) LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o endif And it describes drivers not right under the top directory, which should be essentially cared by drivers/Makefile. LIBS-y += drivers/bios_emulator/libatibiosemu.o LIBS-y += drivers/block/libblock.o LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o LIBS-y += drivers/crypto/libcrypto.o LIBS-y += drivers/dma/libdma.o ... This series adds the directory descending feature like Kbuild. 1/6 tweaks scripts/Makefile.build to support 'obj-y += foo/' syntax. If the build system finds 'foo/' (trailed by a slash), it visits foo directory. 2/6-6/6 demonstarate how we can refactor makefiles with this syntax. 2/6: Move some drivers LIBS from top Makefile to drivers/Makefile 3/6: Move some fs LIBS from top Makefile to fs/Makefile 4/6: Move Tegra specific lines from top Makefile under arch/arm/ 5/6: Move OMAP specific lines from top Makefile under arch/arm/ 6/6: Move Samsung SoC specific lines from top Makefile under arch/arm/ Note: This series uses [PATCH v2]First step towards Kbuild: Use Kbuild-style makefiles (19 patch files). as a prerequisite. Please apply those patches first. I believe no boards are broken by this refactoring. In order to confirm my claim, I compiled all boards except nds32 and nios2 architrecutures. (I could not get an appropriate prebuilt cross compilers for those two arch.) For arm, avr32, sandbox, x86, I could perfectly compile all boards without any warnings. For the other architectures, I could compile some boards and I could not the others. But the SUMMARY result is still the same after applying this series. In addition I compared all the error messages and the warning messages for all boards and they are the same. This which means these patches do not introduce any additional errors, warnings. Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)ti.com> Changes for v2: 1/6: No change 2/6: additionally refactor drivers/pcmcia drivers/rtc too 3/6, 4/6: No change 5/6: rebase on the master 6/6: No change Masahiro Yamada (6): Makefile: support descending down to subdirectories drivers: move some drivers to drivers/Makefile fs: move some file system to fs/Makefile ARM: tegra: delete Tegra specific code from toplevel Makefile ARM: omap: delete OMAP specific code from toplevel Makefile ARM: s5pc, exynos: delete Samsung ARM SoC specific code from toplevel Makefile Makefile | 44 +++---------------------------------------- arch/arm/cpu/Makefile | 2 ++ arch/arm/cpu/arm720t/Makefile | 2 ++ arch/arm/cpu/armv7/Makefile | 9 +++++++++ board/LEOX/elpt860/u-boot.lds | 1 - board/tqc/tqm8xx/u-boot.lds | 4 ++-- drivers/Makefile | 15 +++++++++++++++ fs/Makefile | 11 +++++++++++ scripts/Makefile.build | 15 +++++++++++++++ spl/Makefile | 14 +------------- 10 files changed, 60 insertions(+), 57 deletions(-) create mode 100644 arch/arm/cpu/Makefile create mode 100644 drivers/Makefile -- 1.8.1.2

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[U-Boot] [PATCH 00/10] arm: vf610/vf610twr: vybrid tower fixes and enhancements
by Marcel Ziswiler 30 Sep '13

30 Sep '13

arm: vf610: vf610twr: vybrid tower fixes and enhancements This patch series addresses several vixes and enhancements for the vybrid tower. Tested on a TWR-VF65GS10 Rev G. Marcel Ziswiler (10): arm: vf610: fix anadig register struct arm: vf610: clean-up anadig register struct arm: vf610: add uart0 clock definition arm: vf610: add anadig pll5 definitions arm: vf610: add enet1 base address definition arm: vf610: add rmii clkout iomux definition arm: vf610: add uart0 tx/rx iomux definitions arm: vf610: add rmii1 iomux definitions arm: vf610: fix double iomux configuration for vf610twr board arm: vf610: remove obsolete uart port configuration arch/arm/include/asm/arch-vf610/crm_regs.h | 57 ++++++++++++++----------- arch/arm/include/asm/arch-vf610/imx-regs.h | 1 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 12 ++++++ board/freescale/vf610twr/vf610twr.c | 1 - include/configs/vf610twr.h | 1 - 5 files changed, 45 insertions(+), 27 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH v2 0/1] Fix ethernet regression on pcm051 and igep0033
by Lars Poeschel 30 Sep '13

30 Sep '13

From: Lars Poeschel <poeschel(a)lemonage.de> I compiled and tried v2013.10-rc2 on pcm051 and it fails booting over tftp. I could bisect 2bf36ac638ab2db9f0295aa47064976eeebf80c1 as the cause of the problem. It moves bd_ram_ofs from the cpsw driver to the board files. Adding the bd_ram_ofs to the board file of pcm051 fixes the problem. A quick grep revealed, that igep0033 is also be affected. The igep0033 maintainer confirmed it, so this patch does supply the old bd_ram_ofs value in the board file also. As the patch is simple and obivous and fixes a regression I'd like to get this in before the v2013.10 release. Thanks Changes v2: - supply the bd_ram_ofs for igep0033 board also Lars Poeschel (1): pcm051/igep0033: Supply bd_ram_ofs for cpsw driver board/isee/igep0033/board.c | 1 + board/phytec/pcm051/board.c | 1 + 2 files changed, 2 insertions(+) -- 1.8.4.rc3

1 1

[U-Boot] [PATCH] spl: Add bootcount/bootlimit support
by Stefan Roese 30 Sep '13

30 Sep '13

This patch adds bootcount/bootlimit support to SPL. Right now with SPL-NOR support only. But it should be easy to ad this feature to other SPL implementations as well. When the bootcounter exceeds the "bootlimit" environment variable SPL will boot into the full-blown U-Boot to handle the bootcmd switch via the altbootcmd variable. Signed-off-by: Stefan Roese <sr(a)denx.de> --- README | 3 +++ common/main.c | 7 +++++++ common/spl/spl.c | 23 +++++++++++++++++++++++ common/spl/spl_nor.c | 7 ++++++- include/spl.h | 6 ++++++ spl/Makefile | 1 + 6 files changed, 46 insertions(+), 1 deletion(-) diff --git a/README b/README index bcfffc3..6a4e56b 100644 --- a/README +++ b/README @@ -2998,6 +2998,9 @@ FIT uImage format: parameters from when MMC is being used in raw mode (for falcon mode) + CONFIG_SPL_BOOTCOUNT_SUPPORT + Support for drivers/bootcount/libbootcount.o in SPL binary + CONFIG_SPL_FAT_SUPPORT Support for fs/fat/libfat.o in SPL binary diff --git a/common/main.c b/common/main.c index 56da214..2407569 100644 --- a/common/main.c +++ b/common/main.c @@ -349,8 +349,15 @@ static void process_boot_delay(void) #ifdef CONFIG_BOOTCOUNT_LIMIT bootcount = bootcount_load(); +#if !defined(CONFIG_SPL_BOOTCOUNT_SUPPORT) + /* + * Don't increment bootcount when SPL has bootcount suport included. + * Otherwise SPL and U-Boot would increment the counter adding a + * total of 2 each bootup. + */ bootcount++; bootcount_store (bootcount); +#endif setenv_ulong("bootcount", bootcount); bootlimit = getenv_ulong("bootlimit", 10, 0); #endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/common/spl/spl.c b/common/spl/spl.c index 628c399..84f3fdf 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -144,6 +144,29 @@ static void spl_ram_load_image(void) } #endif +#ifdef CONFIG_BOOTCOUNT_LIMIT +int spl_bootlimit_exceeded(void) +{ + u32 bootcount, bootlimit; + + /* Increment bootcounter */ + bootcount = bootcount_load(); + bootcount++; + bootcount_store(bootcount); + + /* Check if limit is exceeeded */ + env_init(); + bootlimit = getenv_ulong("bootlimit", 10, 0); + if (bootlimit && (bootcount > bootlimit)) { + printf ("Warning: Bootlimit (%u) exceeded, booting into U-Boot!\n", + bootlimit); + return 1; + } + + return 0; +} +#endif + void board_init_r(gd_t *dummy1, ulong dummy2) { u32 boot_device; diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 976e865..d3ffe67 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -26,7 +26,12 @@ void spl_nor_load_image(void) */ spl_image.flags |= SPL_COPY_PAYLOAD_ONLY; - if (spl_start_uboot()) { + /* + * Check spl_bootlimit_exceeded() first, otherwise it may not + * be executed (when spl_start_uboot returns 1). And it needs + * the be run each boot to increment the bootcounter. + */ + if (spl_bootlimit_exceeded() || spl_start_uboot()) { /* * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM diff --git a/include/spl.h b/include/spl.h index 4bc1dd1..dd6ffe4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -79,4 +79,10 @@ void spl_net_load_image(const char *device); #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif + +#ifdef CONFIG_BOOTCOUNT_LIMIT +int spl_bootlimit_exceeded(void); +#else +#define spl_bootlimit_exceeded() 0 +#endif #endif diff --git a/spl/Makefile b/spl/Makefile index 01873de..1ae3b30 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -83,6 +83,7 @@ LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o +LIBS-$(CONFIG_SPL_BOOTCOUNT_SUPPORT) += drivers/bootcount/libbootcount.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -- 1.8.4

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[U-Boot] [PATCH 3/3][v3] board/c29xpcie: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 30 Sep '13

30 Sep '13

Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v2:Sending as it is Changes for v3:Sending as it is include/configs/C29XPCIE.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..6a1e145 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -189,13 +189,14 @@ | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ + | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0c) | \ FTIM0_NAND_TWCHT(0x08) | \ @@ -222,6 +223,7 @@ #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -- 1.7.9.5

1 0

[U-Boot] [PATCH 2/3][v3] mtd/ifc: Add support of 8K page size NAND flash
by Prabhakar Kushwaha 30 Sep '13

30 Sep '13

Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Liu Po <po.liu(a)freescale.com> --- Changes for v2: sending as it is Changes for v3: Incorporated Liu Po's commetns - Updated fsl_ifc_spl 8K if conditional check arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 24 +++++++++++ arch/powerpc/include/asm/fsl_ifc.h | 2 + drivers/mtd/nand/fsl_ifc_nand.c | 78 ++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_ifc_spl.c | 5 ++- 4 files changed, 108 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 2d0fb43..64a5225 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -34,6 +34,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR0_EXT set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); #endif +#ifdef CONFIG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); @@ -43,6 +46,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR1_EXT set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); #endif +#ifdef CONFIG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -57,6 +63,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR2_EXT set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); #endif +#ifdef CONFIG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -71,6 +80,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR3_EXT set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); #endif +#ifdef CONFIG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); @@ -85,6 +97,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR4_EXT set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif +#ifdef CONFIG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#endif #if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); @@ -99,6 +114,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR5_EXT set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif +#ifdef CONFIG_SYS_CSOR5_EXT + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); +#endif #if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); @@ -113,6 +131,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR6_EXT set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif +#ifdef CONFIG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#endif #if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); @@ -127,6 +148,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR7_EXT set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif +#ifdef CONFIG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#endif #if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index a945e4b..182b1a6 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -77,6 +77,7 @@ #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 @@ -86,6 +87,7 @@ #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0..cfed549 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -125,6 +125,69 @@ static struct nand_ecclayout oob_4096_ecc8 = { .oobfree = { {2, 6}, {136, 82} }, }; +/* 8192-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_8192_ecc4 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 208} }, +}; + +/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_8192_ecc8 = { + .eccbytes = 256, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, + 256, 257, 258, 259, 260, 261, 262, 263, + }, + .oobfree = { {2, 6}, {264, 80} }, +}; /* * Generic flash bbt descriptors @@ -902,6 +965,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) priv->bufnum_mask = 1; break; + case CSOR_NAND_PGS_8K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_8192_ecc4; + nand->ecc.strength = 4; + } else { + layout = &oob_8192_ecc8; + nand->ecc.strength = 8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 0; + break; + + default: printf("ifc nand: bad csor %#x: bad page size\n", csor); return -ENODEV; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d462265..72bd61b 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -112,7 +112,10 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; - if (csor & CSOR_NAND_PGS_4K) { + if (csor & CSOR_NAND_PGS_8K) { + page_size = 8192; + bufnum_mask = 0x0; + } else if (csor & CSOR_NAND_PGS_4K) { page_size = 4096; bufnum_mask = 0x1; } else if (csor & CSOR_NAND_PGS_2K) { -- 1.7.9.5

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[U-Boot] [PATCH 1/3][v3] mtd: move & update nand_ecclayout structure
by Prabhakar Kushwaha 30 Sep '13

30 Sep '13

nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> CC: Vipin Kumar <vipin.kumar(a)st.com> --- Changes for v2: Incorporated Scott's comments - move nand_ecclayout to mtd.h - updated OOBFREE, ECCPOS max entries Changes for v3: Sending as it is include/linux/mtd/mtd.h | 14 ++++++++++++++ include/mtd/mtd-abi.h | 12 ------------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6f44abd..3a18f8f 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -96,6 +96,20 @@ struct mtd_oob_ops { uint8_t *oobbuf; }; +#define MTD_MAX_OOBFREE_ENTRIES 32 +#define MTD_MAX_ECCPOS_ENTRIES 640 + +/* + * ECC layout control structure. Exported to userspace for + * diagnosis and to allow creation of raw images + */ +struct nand_ecclayout { + uint32_t eccbytes; + uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES]; + uint32_t oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; +}; + struct mtd_info { u_char type; u_int32_t flags; diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index d51c1ab..ac3c298 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -155,18 +155,6 @@ struct nand_oobfree { uint32_t length; }; -#define MTD_MAX_OOBFREE_ENTRIES 8 -/* - * ECC layout control structure. Exported to userspace for - * diagnosis and to allow creation of raw images - */ -struct nand_ecclayout { - uint32_t eccbytes; - uint32_t eccpos[128]; - uint32_t oobavail; - struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; -}; - /** * struct mtd_ecc_stats - error correction stats * -- 1.7.9.5

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[U-Boot] [PATCH RFC] usb: Prevent using reserved registers on DM36x usb
by Andrew Murray 29 Sep '13

29 Sep '13

The musb driver defines and uses MUSB_CSR0_H_DIS_PING, however this bit is reserved on the DM36x. Thus this patch ensures that the reserved bit is not accesssed. It has been observed that some USB devices will fail to enumerate with errors such as 'error in inquiry' without this patch. See http://www.ti.com/litv/pdf/sprufh9a for details. Cc: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Signed-off-by: Andrew Murray <amurray(a)embedded-bits.co.uk> --- drivers/usb/musb/musb_core.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index ec8a038..c9a9d66 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -216,7 +216,11 @@ struct musb_regs { #define MUSB_CSR0_P_SENTSTALL 0x0004 /* CSR0 in Host mode */ +#if defined(CONFIG_SOC_DM365) +#define MUSB_CSR0_H_DIS_PING 0x0000 +#else #define MUSB_CSR0_H_DIS_PING 0x0800 +#endif #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 -- 1.7.9.5

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