March 2013 - U-Boot

[U-Boot] [PATCH v3 0/7] This patch series adds the drivers for the cros-ec protocol that is used to
by Hung-ying Tyan 30 Mar '13

30 Mar '13

communicate with the ChromeOS Embedded Controller (EC). The series also enables its use in Google Snow based on smdk5250. The series depends on the following patches: 1) http://patchwork.ozlabs.org/patch/217347 add dts file for Snow 2) mmc series: http://patchwork.ozlabs.org/patch/225008 3) power patches needed by one of the mmc patches http://patchwork.ozlabs.org/patch/220060 EXYNOS5: Add function to setup set ps hold http://patchwork.ozlabs.org/patch/220061 SMDK5250: Add PMIC voltage settings (needed by one of the mmc patches) ----- Changes in v3: - Rearranged #include directives in alphabetical order. - Removed outdated TODO and irrelevant bug reference in comments. Changes in v2: - Moved code from smdk5250.c (non-FDT) to exynos5-dt.c (FDT). - Moved code from smdk5250.h to exynos5250-dt.h. - Added gpio node to exynos5250.dtsi. - Fixed warnings of exceeding 80 chars in a line. - Added commit message to each patch. - Dropped the period from commit subjects. Hung-ying Tyan (7): cros: add cros_ec driver cros: add I2C support for cros_ec cros: add SPI support for cros_ec cros: add LPC support for cros_ec cros: adds cros_ec keyboard driver cros: exynos: add cros-ec device nodes to exynos5250-snow.dts cros: enable cros-ec for smdk5250 README | 5 + arch/arm/dts/exynos5250.dtsi | 3 + board/samsung/dts/exynos5250-snow.dts | 82 ++ board/samsung/smdk5250/exynos5-dt.c | 45 + doc/device-tree-bindings/input/cros-ec-keyb.txt | 79 ++ doc/device-tree-bindings/misc/cros-ec.txt | 38 + doc/device-tree-bindings/spi/exynos-spi.txt | 55 + drivers/input/Makefile | 1 + drivers/input/cros_ec_keyb.c | 261 ++++ drivers/misc/Makefile | 4 + drivers/misc/cros_ec.c | 1304 ++++++++++++++++++++ drivers/misc/cros_ec_i2c.c | 199 ++++ drivers/misc/cros_ec_lpc.c | 283 +++++ drivers/misc/cros_ec_spi.c | 166 +++ drivers/spi/exynos_spi.c | 22 + include/configs/exynos5250-dt.h | 10 +- include/cros_ec.h | 449 +++++++ include/cros_ec_message.h | 44 + include/ec_commands.h | 1440 +++++++++++++++++++++++ include/fdtdec.h | 2 + include/spi.h | 16 + lib/fdtdec.c | 2 + 22 files changed, 4509 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree-bindings/input/cros-ec-keyb.txt create mode 100644 doc/device-tree-bindings/misc/cros-ec.txt create mode 100644 doc/device-tree-bindings/spi/exynos-spi.txt create mode 100644 drivers/input/cros_ec_keyb.c create mode 100644 drivers/misc/cros_ec.c create mode 100644 drivers/misc/cros_ec_i2c.c create mode 100644 drivers/misc/cros_ec_lpc.c create mode 100644 drivers/misc/cros_ec_spi.c create mode 100644 include/cros_ec.h create mode 100644 include/cros_ec_message.h create mode 100644 include/ec_commands.h -- 1.8.1.3

2 14

[U-Boot] [PATCH] ARM: tegra: support T33 SKU of Tegra30
by Stephen Warren 30 Mar '13

30 Mar '13

From: Stephen Warren <swarren(a)nvidia.com> Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/cpu/tegra-common/ap.c | 1 + arch/arm/include/asm/arch-tegra/tegra.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 236cda8..3f30805 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -65,6 +65,7 @@ int tegra_get_chip_type(void) break; case CHIPID_TEGRA30: switch (tegra_sku_id) { + case SKU_ID_T33: case SKU_ID_T30: return TEGRA_SOC_T30; } diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index bf7229d..3e642e9 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -78,6 +78,7 @@ enum { SKU_ID_T25 = 0x18, SKU_ID_AP25E = 0x1b, SKU_ID_T25E = 0x1c, + SKU_ID_T33 = 0x80, SKU_ID_T30 = 0x81, /* Cardhu value */ SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ }; -- 1.7.10.4

2 1

[U-Boot] [PATCH] Tegra: Configure L2 cache control reg properly.
by Tom Warren 30 Mar '13

30 Mar '13

Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/cpu/tegra-common/Makefile | 2 +- arch/arm/cpu/tegra-common/ap.c | 9 ++----- arch/arm/cpu/tegra-common/cache.c | 48 ++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra/ap.h | 1 + 4 files changed, 52 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/cache.c diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 8e95c7e..4e0301c 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libcputegra-common.o SOBJS += lowlevel_init.o -COBJS-y += ap.o board.o sys_info.o timer.o clock.o +COBJS-y += ap.o board.o sys_info.o timer.o clock.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 3f30805..a739fe2 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -139,11 +139,6 @@ void s_init(void) enable_scu(); - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have SoC's L2 disabled too? */ + /* init the cache */ + config_cache(); } diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c new file mode 100644 index 0000000..48e9319 --- /dev/null +++ b/arch/arm/cpu/tegra-common/cache.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Tegra cache routines */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch/gp_padctrl.h> + +void config_cache(void) +{ + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + u32 reg = 0; + + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n"); + + /* Currently, only T114 needs this L2 cache change to boot Linux */ + reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); + if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + return; + /* + * Systems with an architectural L2 cache must not use the PL310. + * Config L2CTLR here for a data RAM latency of 3 cycles. + */ + asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); +} diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 73dfd39..5999f55 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -64,3 +64,4 @@ extern void _start(void); * @return SOC type - see TEGRA_SOC... */ int tegra_get_chip_type(void); +void config_cache(void); -- 1.8.1.5

2 2

[U-Boot] [PATCH v2 3/3] Add TI816X evm board support
by TENART Antoine 29 Mar '13

29 Mar '13

Signed-off-by: Antoine Tenart <atenart(a)adeneo-embedded.com> --- MAINTAINERS | 4 + arch/arm/include/asm/arch-am33xx/spl.h | 9 + board/ti/ti816x/Makefile | 48 ++ board/ti/ti816x/evm.c | 866 ++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/ti816x_evm.h | 177 +++++++ 6 files changed, 1105 insertions(+) create mode 100644 board/ti/ti816x/Makefile create mode 100644 board/ti/ti816x/evm.c create mode 100644 include/configs/ti816x_evm.h diff --git a/MAINTAINERS b/MAINTAINERS index 6b2202c..3aaac7f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -922,6 +922,10 @@ Lucas Stach <dev(a)lynxeye.de> colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core) +Antoine Tenart <atenart(a)adeneo-embedded.com> + + TI816X ARM ARMV7 (TI816x Soc) + Nick Thompson <nick.thompson(a)gefanuc.com> da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 9b5fe9e..d0c1ec9 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -23,6 +23,14 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_MMC2_2 0xFF +#else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #ifdef CONFIG_AM33XX @@ -37,3 +45,4 @@ #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif +#endif diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile new file mode 100644 index 0000000..59128ee --- /dev/null +++ b/board/ti/ti816x/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> +# Antoine Tenart, <atenart(a)adeneo-embedded.com> +# +# Based on TI-PSP-04.00.02.14 : +# +# Copyright (C) 2009, Texas Instruments, Incorporated +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation version 2. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := evm.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c new file mode 100644 index 0000000..bb9d604 --- /dev/null +++ b/board/ti/ti816x/evm.c @@ -0,0 +1,866 @@ +/* + * evm.c + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2009, Texas Instruments, Incorporated + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <spl.h> +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_TI816X_DDR3_SW_LEVELING +static void ddr3_sw_levelling(int emif); +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + return 0; +} + +#if defined(CONFIG_SPL_BUILD) + +static struct module_pin_mux mmc_pin_mux[] = { + { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, + { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { -1 }, +}; + +const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, +}; + +/* + * Routine: delay + * Description: spinning delay to use before udelay works + */ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0"(loops)); +} + +/* assume delay is aprox at least 1us */ +void ddr_delay(int d) +{ + int i; + + /* + * read a control module register. + * this is a bit more delay and cannot be optimized by the compiler + * assuming one read takes 200 cycles and A8 is runing 1 GHz + * somewhat conservative setting + */ + for (i = 0; i < 50*d; i++) + readl(CONTROL_STATUS); +} + +#ifdef CONFIG_TI816X_EVM_DDR3 +/* + * Init DDR3 on TI816X EVM + */ +static void ddr_init_settings(int emif) +{ + /* + * DLL Lockdiff DLL_Lockdiff determines effectively is the + * threshold internal to the DLL to indicate that the DLL has + * lost lock. When this happens the PHY currently issues an + * internal reset. The reset value for this is 0x4, which is + * insufficient. Set this to 15 (maximum possible - to + * prevent this reset. If the reset happens it would cause + * the data to be corrupted. + */ + if (0 == get_cpu_rev()) { + writel(0xF, DDRPHY_CONFIG_BASE + 0x028); + writel(0xF, DDRPHY_CONFIG_BASE + 0x05C); + writel(0xF, DDRPHY_CONFIG_BASE + 0x090); + writel(0xF, DDRPHY_CONFIG_BASE + 0x138); + writel(0xF, DDRPHY_CONFIG_BASE + 0x1DC); + writel(0xF, DDRPHY_CONFIG_BASE + 0x280); + writel(0xF, DDRPHY_CONFIG_BASE + 0x324); + } + + /* + * setup use_rank_delays to 1. This is only necessary when + * multiple ranks are in use. Though the EVM does not have + * multiple ranks, this is a good value to set. + */ + writel(1, DDRPHY_CONFIG_BASE + 0x134); + writel(1, DDRPHY_CONFIG_BASE + 0x1d8); + writel(1, DDRPHY_CONFIG_BASE + 0x27c); + writel(1, DDRPHY_CONFIG_BASE + 0x320); + + /* see ddr_defs.h for invert clock setting and details */ + /* invert_clk_out cmd0 */ + writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x02C); + /* invert_clk_out cmd0 */ + writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x060); + /* invert_clk_out cmd0 */ + writel(INVERT_CLOCK, DDRPHY_CONFIG_BASE + 0x094); + + /* with inv clkout: 0x100. no inv clkout: 0x80. See ddr_defs.h */ + /* cmd0 slave ratio */ + writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x01C); + /* cmd1 slave ratio */ + writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x050); + /* cmd2 slave ratio */ + writel(CMD_SLAVE_RATIO, DDRPHY_CONFIG_BASE + 0x084); + + /* for ddr3 this needs to be set to 1 */ + writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ + writel(0x1, DDRPHY_CONFIG_BASE + 0x104); + writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); + writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); + writel(0x1, DDRPHY_CONFIG_BASE + 0x240); + writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); + writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4); + writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0); + + /**** setup the initial levelinihg ratios ****/ + /* + * These are derived from board delays and may be different for + * different boards see ddr_defs.h + * We are setting the values here for both the ranks, though only + * one is in use + */ + + /* data0 writelvl init ratio */ + writel((WR_DQS_RATIO_3 << 10) | WR_DQS_RATIO_3, + DDRPHY_CONFIG_BASE + 0x0F0); + writel(0x00000, DDRPHY_CONFIG_BASE + 0x0F4); + /* data1 writelvl init ratio */ + writel((WR_DQS_RATIO_2 << 10) | WR_DQS_RATIO_2, + DDRPHY_CONFIG_BASE + 0x194); + writel(0x00000, DDRPHY_CONFIG_BASE + 0x198); + /* data2 writelvl init ratio */ + writel((WR_DQS_RATIO_1 << 10) | WR_DQS_RATIO_1, + DDRPHY_CONFIG_BASE + 0x238); + writel(0x00000, DDRPHY_CONFIG_BASE + 0x23c); + /* data3 writelvl init ratio */ + writel((WR_DQS_RATIO_0 << 10) | WR_DQS_RATIO_0, + DDRPHY_CONFIG_BASE + 0x2dc); + writel(0x00000, DDRPHY_CONFIG_BASE + 0x2e0); + + + /* data0 gatelvl init ratio */ + writel((RD_GATE_RATIO_3 << 10) | RD_GATE_RATIO_3, + DDRPHY_CONFIG_BASE + 0x0FC); + writel(0x0, DDRPHY_CONFIG_BASE + 0x100); + /* data1 gatelvl init ratio */ + writel((RD_GATE_RATIO_2 << 10) | RD_GATE_RATIO_2, + DDRPHY_CONFIG_BASE + 0x1A0); + writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4); + /* data2 gatelvl init ratio */ + writel((RD_GATE_RATIO_1 << 10) | RD_GATE_RATIO_1, + DDRPHY_CONFIG_BASE + 0x244); + writel(0x0, DDRPHY_CONFIG_BASE + 0x248); + /* data3 gatelvl init ratio */ + writel((RD_GATE_RATIO_0 << 10) | RD_GATE_RATIO_0, + DDRPHY_CONFIG_BASE + 0x2E8); + writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC); + + /* cmd0 io config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); + /* cmd0 io clk config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x010); + /* cmd1 io config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x040); + /* cmd1 io clk config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x044); + /* cmd2 io config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x074); + /* cmd2 io clk config - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x078); + /* data0 io config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); + /* data0 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); + /* data1 io config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); + /* data1 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x150); + /* data2 io config - output impedance of pa */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); + /* data2 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); + /* data3 io config - output impedance of pa */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x294); + /* data3 io clk config - output impedance of pad */ + writel(0x4, DDRPHY_CONFIG_BASE + 0x298); + + if (get_cpu_rev() == 0) { + /* fifo_we_out0 - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x338); + /* fifo_we_out1 - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x340); + /* fifo_we_in2 - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x348); + /* fifo_we_in3 - output impedance of pad */ + writel(0x5, DDRPHY_CONFIG_BASE + 0x350); + } +} + +static void emif4p_init(u32 TIM1, u32 TIM2, u32 TIM3, u32 SDREF, u32 SDCFG, + u32 RL) +{ + if (USE_EMIF0) { + /* Program EMIF0 CFG Registers */ + writel(TIM1, EMIF4_0_SDRAM_TIM_1); + writel(TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW); + writel(TIM2, EMIF4_0_SDRAM_TIM_2); + writel(TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW); + writel(TIM3, EMIF4_0_SDRAM_TIM_3); + writel(TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW); + writel(SDCFG, EMIF4_0_SDRAM_CONFIG); + writel(RL, EMIF4_0_DDR_PHY_CTRL_1); + writel(RL, EMIF4_0_DDR_PHY_CTRL_1_SHADOW); + /* initially a large refresh period */ + writel(0x0000613B, EMIF4_0_SDRAM_REF_CTRL); + /* trigger initialization */ + writel(0x1000613B, EMIF4_0_SDRAM_REF_CTRL); + writel((0x10000000|EMIF_SDREF), EMIF4_0_SDRAM_REF_CTRL); + } + + if (USE_EMIF1) { + /* Program EMIF1 CFG Registers */ + writel(TIM1, EMIF4_1_SDRAM_TIM_1); + writel(TIM1, EMIF4_1_SDRAM_TIM_1_SHADOW); + writel(TIM2, EMIF4_1_SDRAM_TIM_2); + writel(TIM2, EMIF4_1_SDRAM_TIM_2_SHADOW); + writel(TIM3, EMIF4_1_SDRAM_TIM_3); + writel(TIM3, EMIF4_1_SDRAM_TIM_3_SHADOW); + writel(SDCFG, EMIF4_1_SDRAM_CONFIG); + writel(RL, EMIF4_1_DDR_PHY_CTRL_1); + writel(RL, EMIF4_1_DDR_PHY_CTRL_1_SHADOW); + /* initially a large refresh period */ + writel(0x0000613B, EMIF4_1_SDRAM_REF_CTRL); + /* trigger initialization */ + writel(0x1000613B, EMIF4_1_SDRAM_REF_CTRL); + writel((0x10000000|EMIF_SDREF), EMIF4_1_SDRAM_REF_CTRL); + } + + delay(1000); +#ifdef CONFIG_TI816X_DDR3_SW_LEVELING + ddr3_sw_levelling(0); + ddr3_sw_levelling(1); +#endif +} + +/* needed by config_dmm() */ +void enable_dmm_clocks(void) {}; + +static void config_ti816x_sdram_ddr(void) +{ + /* Enable the EMIF Firewall clocks */ + writel(0x2, CM_DEFAULT_FW_CLKCTRL); + /* Enable the Power Domain Transition of L3 Fast Domain Peripheral */ + writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL); + /* Enable EMIF0 Clock */ + writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL); + /* Enable EMIF1 Clock */ + writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); + /* Poll for L3_FAST_GCLK & DDR_GCLK are active */ + while ((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300) + ; + /* Poll for Module is functional */ + while ((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2) + ; + /* Poll for Module is functional */ + while ((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2) + ; + + if (USE_EMIF0) + ddr_init_settings(0); + + if (USE_EMIF1) + ddr_init_settings(1); + + /* Enable EMIF1 Clock */ + writel(0x2, CM_DEFAULT_DMM_CLKCTRL); + /* Poll for Module is functional */ + while ((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2) + ; + + /* Program the DMM to for interleaved configuration */ + config_dmm(&evm_lisa_map_regs); + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); + + emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF & 0xFFFFFFF, + EMIF_SDCFG, EMIF_PHYCFG); +} + +#ifdef CONFIG_TI816X_DDR3_SW_LEVELING +static void ddr3_sw_levelling(int emif) +{ + writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); + + writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C)); + writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0)); + writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254)); + writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8)); + + writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0)); + writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x184)); + writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x228)); + writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC)); + + writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x124)); + writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8)); + writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C)); + writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x310)); + + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC)); + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x170)); + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x214)); + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8)); +} +#endif /* CONFIG_TI816X_DDR3_SW_LEVELING */ + +#endif /* CONFIG_TI816X_EVM_DDR3 */ + +#ifdef CONFIG_TI816X_EVM_DDR2 +static void ddr_init_settings(int emif) +{ + /* DLL Lockdiff */ + if (get_cpu_rev() == 0) { + writel(0xF, (DDRPHY_CONFIG_BASE + 0x028)); + writel(0xF, (DDRPHY_CONFIG_BASE + 0x05C)); + writel(0xF, (DDRPHY_CONFIG_BASE + 0x090)); + writel(0xF, (DDRPHY_CONFIG_BASE + 0x138)); + writel(0xF, (DDRPHY_CONFIG_BASE + 0x1DC)); + writel(0xF, (DDRPHY_CONFIG_BASE + 0x280)); + writel(0xF, (DDRPHY_CONFIG_BASE + 0x324)); + } + + if (get_cpu_rev() == 1) + writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); + + /* setup rank delays */ + writel(0x1, (DDRPHY_CONFIG_BASE + 0x134)); + writel(0x1, (DDRPHY_CONFIG_BASE + 0x1D8)); + writel(0x1, (DDRPHY_CONFIG_BASE + 0x27C)); + writel(0x1, (DDRPHY_CONFIG_BASE + 0x320)); + + /* invert_clk_out cmd0 */ + writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x02C)); + writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x060)); + writel(INVERT_CLK_OUT, (DDRPHY_CONFIG_BASE + 0x094)); + + /* cmd0 slave ratio */ + writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x01C)); + writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x050)); + writel(CMD_SLAVE_RATIO, (DDRPHY_CONFIG_BASE + 0x084)); + + writel(DQS_GATE_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x108)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x10C)); + writel(DQS_GATE_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1AC)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x1B0)); + writel(DQS_GATE_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x250)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x254)); + writel(DQS_GATE_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2F4)); + writel(0x00000000, (DDRPHY_CONFIG_BASE + 0x2F8)); + + writel(WR_DQS_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x0DC)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x0E0)); + writel(WR_DQS_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x180)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x184)); + writel(WR_DQS_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x224)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x228)); + writel(WR_DQS_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x2C8)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x2CC)); + + writel(WR_DATA_RATIO_BYTE_LANE0, (DDRPHY_CONFIG_BASE + 0x120)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x124)); + writel(WR_DATA_RATIO_BYTE_LANE1, (DDRPHY_CONFIG_BASE + 0x1C4)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x1C8)); + writel(WR_DATA_RATIO_BYTE_LANE2, (DDRPHY_CONFIG_BASE + 0x268)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x26C)); + writel(WR_DATA_RATIO_BYTE_LANE3, (DDRPHY_CONFIG_BASE + 0x30C)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x310)); + + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x0C8)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x0CC)); + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x16C)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x170)); + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x210)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x214)); + writel(RD_DQS_RATIO, (DDRPHY_CONFIG_BASE + 0x2B4)); + writel(0x0, (DDRPHY_CONFIG_BASE + 0x2B8)); + + writel(0x5, (DDRPHY_CONFIG_BASE + 0x00C)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x010)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x040)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x044)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x074)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x078)); + + writel(0x4, (DDRPHY_CONFIG_BASE + 0x0A8)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x0AC)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x14C)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x150)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F0)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x1F4)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x294)); + writel(0x4, (DDRPHY_CONFIG_BASE + 0x298)); + + if (get_cpu_rev() == 0) { + writel(0x5, (DDRPHY_CONFIG_BASE + 0x338)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x340)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x348)); + writel(0x5, (DDRPHY_CONFIG_BASE + 0x350)); + } + +} + +static void emif4p_init(u32 TIM1, u32 TIM2, u32 TIM3, u32 SDREF, u32 SDCFG, + u32 RL) +{ + /* Program EMIF0 CFG Registers */ + writel(TIM1, EMIF4_0_SDRAM_TIM_1); + writel(TIM1, EMIF4_0_SDRAM_TIM_1_SHADOW); + writel(TIM2, EMIF4_0_SDRAM_TIM_2); + writel(TIM2, EMIF4_0_SDRAM_TIM_2_SHADOW); + writel(TIM3, EMIF4_0_SDRAM_TIM_3); + writel(TIM3, EMIF4_0_SDRAM_TIM_3_SHADOW); + writel(SDCFG, EMIF4_0_SDRAM_CONFIG); + writel(RL, EMIF4_0_DDR_PHY_CTRL_1); + writel(RL, EMIF4_0_DDR_PHY_CTRL_1_SHADOW); + + if (CONFIG_TI816X_TWO_EMIF) { + writel(TIM1, EMIF4_1_SDRAM_TIM_1); + writel(TIM1, EMIF4_1_SDRAM_TIM_1_SHADOW); + writel(TIM2, EMIF4_1_SDRAM_TIM_2); + writel(TIM2, EMIF4_1_SDRAM_TIM_2_SHADOW); + writel(TIM3, EMIF4_1_SDRAM_TIM_3); + writel(TIM3, EMIF4_1_SDRAM_TIM_3_SHADOW); + writel(SDCFG, EMIF4_1_SDRAM_CONFIG); + writel(RL, EMIF4_1_DDR_PHY_CTRL_1); + writel(RL, EMIF4_1_DDR_PHY_CTRL_1_SHADOW); + } + + /* setup a small control period */ + writel(0x0000613B, EMIF4_0_SDRAM_REF_CTRL); + writel(0x1000613B, EMIF4_0_SDRAM_REF_CTRL); + writel((0x10000000|SDREF), EMIF4_0_SDRAM_REF_CTRL); + + if (CONFIG_TI816X_TWO_EMIF) { + /* setup a small control period */ + writel(0x0000613B, EMIF4_1_SDRAM_REF_CTRL); + writel(0x1000613B, EMIF4_1_SDRAM_REF_CTRL); + writel((0x10000000|SDREF), EMIF4_1_SDRAM_REF_CTRL); + + } + + +} + +/* needed by config_dmm() */ +void enable_dmm_clocks(void) {}; + +static void config_ti816x_sdram_ddr(void) +{ + /* Enable the Power Domain Transition of L3 Fast Domain Peripheral */ + writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL); + /* Enable EMIF0 Clock */ + writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL); + /* Enable EMIF1 Clock */ + writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL); + /* Poll for L3_FAST_GCLK & DDR_GCLK are active */ + while ((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300) + ; + /* Poll for Module is functional */ + while ((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2) + ; + /* Poll for Module is functional */ + while ((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2) + ; + + ddr_init_settings(0); + + if (CONFIG_TI816X_TWO_EMIF) + ddr_init_settings(1); + + /* Enable EMIF1 Clock */ + writel(0x2, CM_DEFAULT_DMM_CLKCTRL); + /* Poll for Module is functional */ + while ((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2) + ; + + /* Program the DMM for interleave setting */ + config_dmm(&evm_lisa_map_regs); + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); + + emif4p_init(EMIF_TIM1, EMIF_TIM2, EMIF_TIM3, EMIF_SDREF & 0xFFFFFFF, + EMIF_SDCFG, EMIF_PHYCFG); + +} +#endif + +/* + * TI816X specific functions + */ +static void main_pll_init_ti816x(u32 sil_index, u32 clk_index) +{ + u32 main_pll_ctrl = 0; + + /* + * Sequence to be followed: + * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg + * 2. Write the values of N,P in the CTRL reg + * 3. Program the freq values, divider values for the required output + * in the Control module reg + * 4. Note: Loading the freq value requires a particular bit to be set + * in the freq reg. + * 4. Program the CM divider value in the CM module reg + * 5. Enable the PLL by setting the appropriate bit in the CTRL reg of + * the PLL + */ + + /* If the registers have been set by the ROM code dont do anything */ + + main_pll_ctrl = readl(MAINPLL_CTRL); + main_pll_ctrl &= 0xFFFFFFFB; + main_pll_ctrl |= 4; + writel(main_pll_ctrl, MAINPLL_CTRL); + + main_pll_ctrl = readl(MAINPLL_CTRL); + main_pll_ctrl &= 0xFFFFFFF7; + main_pll_ctrl |= 8; + writel(main_pll_ctrl, MAINPLL_CTRL); + + main_pll_ctrl = readl(MAINPLL_CTRL); + main_pll_ctrl &= 0xFF; + main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); + writel(main_pll_ctrl, MAINPLL_CTRL); + + writel(0x0, MAINPLL_PWD); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), + MAINPLL_FREQ1); + writel(((1<<8) | MAIN_MDIV1), MAINPLL_DIV1); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), + MAINPLL_FREQ2); + writel(((1<<8) | MAIN_MDIV2), MAINPLL_DIV2); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), + MAINPLL_FREQ3); + writel(((1<<8) | MAIN_MDIV3), MAINPLL_DIV3); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), + MAINPLL_FREQ4); + writel(((1<<8) | MAIN_MDIV4), MAINPLL_DIV4); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), + MAINPLL_FREQ5); + writel(((1<<8) | MAIN_MDIV5), MAINPLL_DIV5); + + writel((1<<8 | MAIN_MDIV6), MAINPLL_DIV6); + + writel((1<<8 | MAIN_MDIV7), MAINPLL_DIV7); + + while ((readl(MAINPLL_CTRL) & 0x80) != 0x80) + ; + + main_pll_ctrl = readl(MAINPLL_CTRL); + main_pll_ctrl &= 0xFFFFFFFB; + + writel(main_pll_ctrl, MAINPLL_CTRL); + +} + +static void ddr_pll_init_ti816x(u32 sil_index, u32 clk_index) +{ + u32 ddr_pll_ctrl = 0; + + /* + * Sequence to be followed: + * 1. Put the PLL in bypass mode by setting BIT2 in its ctrl reg + * 2. Write the values of N,P in the CTRL reg + * 3. Program the freq values, divider values for the required output + * in the Control module reg + * 4. Note: Loading the freq value requires a particular bit to be set + * in the freq reg. + * 5. Program the CM divider value in the CM module reg + * 6. Enable the PLL by setting the appropriate bit in the CTRL reg of + * the PLL + */ + + /* If the registers have been set by the ROM code dont do anything */ + + ddr_pll_ctrl = readl(DDRPLL_CTRL); + ddr_pll_ctrl &= 0xFFFFFFFB; + writel(ddr_pll_ctrl, DDRPLL_CTRL); + + ddr_pll_ctrl = readl(DDRPLL_CTRL); + ddr_pll_ctrl &= 0xFFFFFFF7; + ddr_pll_ctrl |= 8; + writel(ddr_pll_ctrl, DDRPLL_CTRL); + + ddr_pll_ctrl = readl(DDRPLL_CTRL); + ddr_pll_ctrl &= 0xFF; + ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); + writel(ddr_pll_ctrl, DDRPLL_CTRL); + + /* 10usec delay */ + ddr_delay(10); + + writel(0x0, DDRPLL_PWD); + + writel(((0<<8) | DDR_MDIV1), DDRPLL_DIV1); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV1), DDRPLL_DIV1); + + writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), + DDRPLL_FREQ2); + writel(((1<<8) | DDR_MDIV2), DDRPLL_DIV2); + + writel(((0<<8) | DDR_MDIV3), DDRPLL_DIV3); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV3), DDRPLL_DIV3); + ddr_delay(1); + writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + DDRPLL_FREQ3); + ddr_delay(1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + DDRPLL_FREQ3); + + ddr_delay(5); + + /* Wait for PLL to lock */ + while ((readl(DDRPLL_CTRL) & 0x80) != 0x80) + ; + + ddr_pll_ctrl = readl(DDRPLL_CTRL); + ddr_pll_ctrl &= 0xFFFFFFFB; + ddr_pll_ctrl |= 4; + writel(ddr_pll_ctrl, DDRPLL_CTRL); + + writel(0x1, DDR_RCD); + +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (TIMER1, UART0,...) + * + ******************************************************************/ +static void peripheral_enable(void) +{ + /* DMTimers */ + writel(0x2, CM_ALWON_L3_SLOW_CLKSTCTRL); + + /* + * Note on Timers: + * There are 8 timers(0-7) out of which timer 0 is a secure timer. + * Timer 0 mux should not be changed + * For other timers, there are 3 inputs TCLKIN, 32KHz (external clk + * or SYSCLK18?) and CLKIN(27MHz) + * We select CLKIN and use that + */ + + /* + * First we need to enable the modules and setup the clk path + * Then the timers need to be configured by writing to their registers + * To access the timer registers we need the module to be + * enabled which is what we do in the first step + */ + + /* TIMER 1 */ + writel(0x2, CM_ALWON_TIMER_1_CLKCTRL); + + /* Selects CLKIN (27MHz) */ + writel(0x2, CM_TIMER1_CLKSEL); + + while (((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) + & (0x80000<<1)) >> (19+1)) != 1) + ; + + while (((readl(CM_ALWON_TIMER_1_CLKCTRL) & 0x30000)>>16) != 0) + ; + + + writel(0x2, (DM_TIMER1_BASE + 0x54)); + while (readl(DM_TIMER1_BASE + 0x10) & 1) + ; + + writel(0x1, (DM_TIMER1_BASE + 0x38)); + + /* UARTs */ + /* Note: The clock has been set to correct rate before this step */ + writel(0x2, CM_ALWON_UART_0_CLKCTRL); + while (readl(CM_ALWON_UART_0_CLKCTRL) != 0x2) + ; + + writel(0x2, CM_ALWON_UART_1_CLKCTRL); + while (readl(CM_ALWON_UART_1_CLKCTRL) != 0x2) + ; + + writel(0x2, CM_ALWON_UART_2_CLKCTRL); + while (readl(CM_ALWON_UART_2_CLKCTRL) != 0x2) + ; + + while ((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x2100) != 0x2100) + ; + + /* eFuse */ + writel(0x2, CM_ALWON_CUST_EFUSE_CLKCTRL); + while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != 0x2) + ; + + /* GPIO0 */ + writel(0x2, CM_ALWON_GPIO_0_CLKCTRL); + while (readl(CM_ALWON_GPIO_0_CLKCTRL) != 0x2) + ; + + writel((BIT(8)), CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK); + + /* SPI */ + writel(0x2, CM_ALWON_SPI_CLKCTRL); + while (readl(CM_ALWON_SPI_CLKCTRL) != 0x2) + ; + + /* I2C0 */ + writel(0x2, CM_ALWON_I2C_0_CLKCTRL); + while (readl(CM_ALWON_I2C_0_CLKCTRL) != 0x2) + ; + + /* Ethernet */ + writel(0x2, CM_ETHERNET_CLKSTCTRL); + writel(0x2, CM_ALWON_ETHERNET_0_CLKCTRL); + writel(0x2, CM_ALWON_ETHERNET_1_CLKCTRL); + + /* HSMMC */ + writel(0x2, CM_ALWON_HSMMC_CLKCTRL); + while (readl(CM_ALWON_HSMMC_CLKCTRL) != 0x2) + ; + + /* WDT */ + /* + * For WDT to be functional, it needs to be first stopped by writing + * the pattern 0xAAAA followed by 0x5555 in the WDT start/stop register. + * After that a write-once register in Control module needs to + * be configured + * to unfreeze the timer. + * Note: It is important to stop the watchdog before unfreezing it + */ + writel(0xAAAA, WDT_WSPR); + while (readl(WDT_WWPS) != 0x0) + ; + writel(0x5555, WDT_WSPR); + while (readl(WDT_WWPS) != 0x0) + ; + + /* Unfreeze WDT */ + writel(0x2, WDT_UNFREEZE); +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + *****************************************************************************/ +void prcm_init(void) +{ + /* For future */ + u32 clk_index = 0, sil_index = 0; + + writel(0x2, 0x48200010); + /* Enable the control module */ + writel(0x2, CM_ALWON_CONTROL_CLKCTRL); + + /* Fix ROM code bug */ + writel(0x0, 0x48180324); + + main_pll_init_ti816x(clk_index, sil_index); + ddr_pll_init_ti816x(clk_index, sil_index); + + /* + * With clk freqs setup to desired values, + * enable the required peripherals + */ + peripheral_enable(); +} +#endif /* CONFIG_SPL_BUILD */ + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ +void s_init(void) +{ +#ifdef CONFIG_SPL_BUILD + /* Setup the PLLs and the clocks for the peripherals */ + prcm_init(); + configure_module_pin_mux(mmc_pin_mux); + + gd = &gdata; + + preloader_console_init(); + + config_ti816x_sdram_ddr(); /* Do DDR settings */ +#endif +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0); + return 0; +} +#endif diff --git a/boards.cfg b/boards.cfg index c98495a..aab56b9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -239,6 +239,7 @@ am335x_evm_uart3 arm armv7 am335x ti am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 ti814x_evm arm armv7 ti814x ti am33xx +ti816x_evm arm armv7 ti816x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank - highbank mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h new file mode 100644 index 0000000..b5b5172 --- /dev/null +++ b/include/configs/ti816x_evm.h @@ -0,0 +1,177 @@ +/* + * ti816x_evm.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef __CONFIG_TI816X_EVM_H +#define __CONFIG_TI816X_EVM_H + +#define CONFIG_TI81XX +#define CONFIG_TI816X +#define CONFIG_SYS_NO_FLASH + +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) +#define CONFIG_SYS_LONGHELP /* undef save memory */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "u-boot/ti816x# " +#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* required for ramdisk support */ + +#include <config_cmd_default.h> /* u-boot default commands */ + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */ +#define CONFIG_EXTRA_EMV_SETTINGS \ + "verify=yes\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan 0;" \ + "fatload mmc 0 0x81000000 uImage;" \ + "bootm 0x81000000" + +#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ + +/* + * Memtest works on 8 MB in DRAM after skipping 32MB + * from start addr of ram disk + */ +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64*1024*1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + (8*1024*1024)) + +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_CMD_ASKEN +#define CONFIG_CMD_ECHO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_FS_FAT + +/* Only one of the following two options (DDR3/DDR2) should be enabled */ +/* +#define CONFIG_TI816X_EVM_DDR2 +#define CONFIG_TI816X_TWO_EMIF 1 +*/ +#define CONFIG_TI816X_EVM_DDR3 + + +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ +#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ + +#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_CLK_FREQ 27000000 +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ + +#undef CONFIG_NAND_OMAP_GPMC + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ + +#define CONFIG_BAUDRATE 115200 + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SERIAL1 +#define CONFIG_SERIAL2 +#define CONFIG_SERIAL3 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif -- 1.7.10.4

1 0

[U-Boot] [PATCH v2 2/3] Add TI816X support
by TENART Antoine 29 Mar '13

29 Mar '13

Signed-off-by: Antoine Tenart <atenart(a)adeneo-embedded.com> --- arch/arm/include/asm/arch-am33xx/clock.h | 4 + arch/arm/include/asm/arch-am33xx/clocks_ti816x.h | 136 ++++++++ arch/arm/include/asm/arch-am33xx/cpu.h | 4 + arch/arm/include/asm/arch-am33xx/cpu_ti816x.h | 194 +++++++++++ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 + arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h | 248 +++++++++++++ arch/arm/include/asm/arch-am33xx/hardware.h | 7 +- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 5 + arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 5 + arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 56 +++ arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 2 + arch/arm/include/asm/arch-am33xx/mux.h | 2 + arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 363 ++++++++++++++++++++ 13 files changed, 1025 insertions(+), 5 deletions(-) create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index ecb5901..123cc61 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -19,6 +19,10 @@ #ifndef _CLOCKS_H_ #define _CLOCKS_H_ +#if defined(CONFIG_TI816X) +#include <asm/arch/clocks_ti816x.h> +#else #include <asm/arch/clocks_am33xx.h> +#endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h new file mode 100644 index 0000000..403db33 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clocks_ti816x.h @@ -0,0 +1,136 @@ +/* + * clocks_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * Based on TI-PSP-04.00.02.14 : + * + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_TI816X_H_ +#define _CLOCKS_TI816X_H_ + +/* + * Values supported 400,531,675,796 + * + * On TI8168 rev C, use 400 or 531 MHz ! + */ +#define DDR_PLL_400 + +/* Main PLL */ +#define MAIN_N 64 +#define MAIN_P 0x1 +#define MAIN_INTFREQ1 0x8 +#define MAIN_FRACFREQ1 0x800000 +#define MAIN_MDIV1 0x2 +#define MAIN_INTFREQ2 0xE +#define MAIN_FRACFREQ2 0x0 +#define MAIN_MDIV2 0x1 +#define MAIN_INTFREQ3 0x8 +#define MAIN_FRACFREQ3 0xAAAAB0 +#define MAIN_MDIV3 0x3 +#define MAIN_INTFREQ4 0x9 +#define MAIN_FRACFREQ4 0x55554F +#define MAIN_MDIV4 0x3 +#define MAIN_INTFREQ5 0x9 +#define MAIN_FRACFREQ5 0x374BC6 +#define MAIN_MDIV5 0xC +#define MAIN_MDIV6 0x48 +#define MAIN_MDIV7 0x4 + +/* DDR PLL */ +/* For 400 MHz */ +#if defined(DDR_PLL_400) +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x4 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +/* For 531 MHz */ +#if defined(DDR_PLL_531) +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x3 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +/* For 675 MHz */ +#if defined(DDR_PLL_675) +#define DDR_N 50 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x9 +#define DDR_FRACFREQ2 0x0 +#define DDR_MDIV2 0x19 +#define DDR_INTFREQ3 0x13 +#define DDR_FRACFREQ3 0x800000 +#define DDR_MDIV3 0x2 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +/* For 796 MHz */ +#if defined(DDR_PLL_796) +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +#endif /* endif _CLOCKS_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 13c0667..34b3aa9 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -25,6 +25,10 @@ #include <asm/arch/hardware.h> +#if defined(CONFIG_TI816X) +#include <asm/arch/cpu_ti816x.h> +#endif + #define BIT(x) (1 << x) #define CL_BIT(x) (0 << x) diff --git a/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h new file mode 100644 index 0000000..515dba4 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/cpu_ti816x.h @@ -0,0 +1,194 @@ +/* + * cpu_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * Based on TI-PSP-04.00.02.14 : + * + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _TI816X_CPU_H +#define _TI816X_CPU_H + +#include <asm/arch/hardware.h> + +/* Control */ +#define CONTROL_STATUS (CTRL_BASE + 0x40) + +/* PLL related registers */ +#define MAINPLL_CTRL (CTRL_BASE + 0x0400) +#define MAINPLL_PWD (CTRL_BASE + 0x0404) +#define MAINPLL_FREQ1 (CTRL_BASE + 0x0408) +#define MAINPLL_DIV1 (CTRL_BASE + 0x040C) +#define MAINPLL_FREQ2 (CTRL_BASE + 0x0410) +#define MAINPLL_DIV2 (CTRL_BASE + 0x0414) +#define MAINPLL_FREQ3 (CTRL_BASE + 0x0418) +#define MAINPLL_DIV3 (CTRL_BASE + 0x041C) +#define MAINPLL_FREQ4 (CTRL_BASE + 0x0420) +#define MAINPLL_DIV4 (CTRL_BASE + 0x0424) +#define MAINPLL_FREQ5 (CTRL_BASE + 0x0428) +#define MAINPLL_DIV5 (CTRL_BASE + 0x042C) +#define MAINPLL_DIV6 (CTRL_BASE + 0x0434) +#define MAINPLL_DIV7 (CTRL_BASE + 0x043C) + +#define DDRPLL_CTRL (CTRL_BASE + 0x0440) +#define DDRPLL_PWD (CTRL_BASE + 0x0444) +#define DDRPLL_DIV1 (CTRL_BASE + 0x044C) +#define DDRPLL_FREQ2 (CTRL_BASE + 0x0450) +#define DDRPLL_DIV2 (CTRL_BASE + 0x0454) +#define DDRPLL_FREQ3 (CTRL_BASE + 0x0458) +#define DDRPLL_DIV3 (CTRL_BASE + 0x045C) +#define DDRPLL_FREQ4 (CTRL_BASE + 0x0460) +#define DDRPLL_DIV4 (CTRL_BASE + 0x0464) +#define DDRPLL_FREQ5 (CTRL_BASE + 0x0468) +#define DDRPLL_DIV5 (CTRL_BASE + 0x046C) + +#define DDR_RCD (CTRL_BASE + 0x070C) + +/* PRCM */ +#define CM_DPLL_OFFSET (PRCM_BASE + 0x0300) + +#ifdef CONFIG_TI816X +#define CM_TIMER1_CLKSEL (CM_DPLL_OFFSET + 0x90) + +/* Timers */ +#define CM_ALWON_TIMER_0_CLKCTRL (PRCM_BASE + 0x156C) +#define CM_ALWON_TIMER_1_CLKCTRL (PRCM_BASE + 0x1570) +#define CM_ALWON_TIMER_2_CLKCTRL (PRCM_BASE + 0x1574) +#define CM_ALWON_TIMER_3_CLKCTRL (PRCM_BASE + 0x1578) +#define CM_ALWON_TIMER_4_CLKCTRL (PRCM_BASE + 0x157C) +#define CM_ALWON_TIMER_5_CLKCTRL (PRCM_BASE + 0x1580) +#define CM_ALWON_TIMER_6_CLKCTRL (PRCM_BASE + 0x1584) +#define CM_ALWON_TIMER_7_CLKCTRL (PRCM_BASE + 0x1588) +#endif + +#define CM_ALWON_WDTIMER_CLKCTRL (PRCM_BASE + 0x158C) +#define CM_ALWON_SPI_CLKCTRL (PRCM_BASE + 0x1590) +#define CM_ALWON_CONTROL_CLKCTRL (PRCM_BASE + 0x15C4) + +#define CM_ALWON_L3_SLOW_CLKSTCTRL (PRCM_BASE + 0x1400) + +#ifdef CONFIG_TI816X +#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) +#endif + +#define CM_ALWON_GPIO_0_CLKCTRL (PRCM_BASE + 0x155c) +#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (PRCM_BASE + 0x155c) + +#define CM_ALWON_GPIO_1_CLKCTRL (PRCM_BASE + 0x1560) +/* Ethernet */ +#define CM_ETHERNET_CLKSTCTRL (PRCM_BASE + 0x1404) +#define CM_ALWON_ETHERNET_0_CLKCTRL (PRCM_BASE + 0x15D4) +#define CM_ALWON_ETHERNET_1_CLKCTRL (PRCM_BASE + 0x15D8) + +/* UARTs */ +#define CM_ALWON_UART_0_CLKCTRL (PRCM_BASE + 0x1550) +#define CM_ALWON_UART_1_CLKCTRL (PRCM_BASE + 0x1554) +#define CM_ALWON_UART_2_CLKCTRL (PRCM_BASE + 0x1558) + +/* I2C */ +/* Note: In ti814x I2C0 and I2C2 have common clk control */ +#define CM_ALWON_I2C_0_CLKCTRL (PRCM_BASE + 0x1564) + +/* HSMMC */ +#ifdef CONFIG_TI816X +#define CM_ALWON_HSMMC_CLKCTRL (PRCM_BASE + 0x15B0) +#endif + +/*DMM & EMIF4 MMR Declaration*/ + +/* 0x420 = 0x460 - the lisa registers offset from the DMM region */ +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) + +#define EMIF4_0_SDRAM_ZQCR (EMIF4_0_CFG_BASE + 0xC8) +#define EMIF4_0_SDRAM_CONFIG (EMIF4_0_CFG_BASE + 0x08) +#define EMIF4_0_SDRAM_CONFIG2 (EMIF4_0_CFG_BASE + 0x0C) +#define EMIF4_0_SDRAM_REF_CTRL (EMIF4_0_CFG_BASE + 0x10) +#define EMIF4_0_SDRAM_REF_CTRL_SHADOW (EMIF4_0_CFG_BASE + 0x14) +#define EMIF4_0_SDRAM_TIM_1 (EMIF4_0_CFG_BASE + 0x18) +#define EMIF4_0_SDRAM_TIM_1_SHADOW (EMIF4_0_CFG_BASE + 0x1C) +#define EMIF4_0_SDRAM_TIM_2 (EMIF4_0_CFG_BASE + 0x20) +#define EMIF4_0_SDRAM_TIM_2_SHADOW (EMIF4_0_CFG_BASE + 0x24) +#define EMIF4_0_SDRAM_TIM_3 (EMIF4_0_CFG_BASE + 0x28) +#define EMIF4_0_SDRAM_TIM_3_SHADOW (EMIF4_0_CFG_BASE + 0x2C) +#define EMIF4_0_DDR_PHY_CTRL_1 (EMIF4_0_CFG_BASE + 0xE4) +#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW (EMIF4_0_CFG_BASE + 0xE8) +#define EMIF4_0_IODFT_TLGC (EMIF4_0_CFG_BASE + 0x60) + +#define EMIF4_1_SDRAM_ZQCR (EMIF4_1_CFG_BASE + 0xC8) +#define EMIF4_1_SDRAM_CONFIG (EMIF4_1_CFG_BASE + 0x08) +#define EMIF4_1_SDRAM_CONFIG2 (EMIF4_1_CFG_BASE + 0x0C) +#define EMIF4_1_SDRAM_REF_CTRL (EMIF4_1_CFG_BASE + 0x10) +#define EMIF4_1_SDRAM_REF_CTRL_SHADOW (EMIF4_1_CFG_BASE + 0x14) +#define EMIF4_1_SDRAM_TIM_1 (EMIF4_1_CFG_BASE + 0x18) +#define EMIF4_1_SDRAM_TIM_1_SHADOW (EMIF4_1_CFG_BASE + 0x1C) +#define EMIF4_1_SDRAM_TIM_2 (EMIF4_1_CFG_BASE + 0x20) +#define EMIF4_1_SDRAM_TIM_2_SHADOW (EMIF4_1_CFG_BASE + 0x24) +#define EMIF4_1_SDRAM_TIM_3 (EMIF4_1_CFG_BASE + 0x28) +#define EMIF4_1_SDRAM_TIM_3_SHADOW (EMIF4_1_CFG_BASE + 0x2C) +#define EMIF4_1_DDR_PHY_CTRL_1 (EMIF4_1_CFG_BASE + 0xE4) +#define EMIF4_1_DDR_PHY_CTRL_1_SHADOW (EMIF4_1_CFG_BASE + 0xE8) +#define EMIF4_1_IODFT_TLGC (EMIF4_1_CFG_BASE + 0x60) + +/*EMIF4 PRCM Defintion*/ +#define CM_DEFAULT_L3_FAST_CLKSTCTRL (PRCM_BASE + 0x0508) +#define CM_DEFAULT_EMIF_0_CLKCTRL (PRCM_BASE + 0x0520) +#define CM_DEFAULT_EMIF_1_CLKCTRL (PRCM_BASE + 0x0524) +#define CM_DEFAULT_DMM_CLKCTRL (PRCM_BASE + 0x0528) +#define CM_DEFAULT_FW_CLKCTRL (PRCM_BASE + 0x052C) + +/* GPMC related */ +#define GPMC_CONFIG_CS0 (0x60) +#define GPMC_CONFIG_CS0_BAS (GPMC_BASE + GPMC_CONFIG_CS0) +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) + +/* WDT related */ +#define WDT_WDSC (WDT_BASE + 0x010) +#define WDT_WDST (WDT_BASE + 0x014) +#define WDT_WISR (WDT_BASE + 0x018) +#define WDT_WIER (WDT_BASE + 0x01C) +#define WDT_WWER (WDT_BASE + 0x020) +#define WDT_WCLR (WDT_BASE + 0x024) +#define WDT_WCRR (WDT_BASE + 0x028) +#define WDT_WLDR (WDT_BASE + 0x02C) +#define WDT_WTGR (WDT_BASE + 0x030) +#define WDT_WWPS (WDT_BASE + 0x034) +#define WDT_WDLY (WDT_BASE + 0x044) +#define WDT_WSPR (WDT_BASE + 0x048) +#define WDT_WIRQEOI (WDT_BASE + 0x050) +#define WDT_WIRQSTATRAW (WDT_BASE + 0x054) +#define WDT_WIRQSTAT (WDT_BASE + 0x058) +#define WDT_WIRQENSET (WDT_BASE + 0x05C) +#define WDT_WIRQENCLR (WDT_BASE + 0x060) + +#define WDT_UNFREEZE (CTRL_BASE + 0x100) + +#endif /* _TI816X_CPU_H */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 15ca4c1..b959ba8 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -22,6 +22,10 @@ #include <asm/arch/hardware.h> #include <asm/emif.h> +#if defined(CONFIG_TI816X) +#include <asm/arch/ddr_defs_ti816x.h> +#endif + /* AM335X EMIF Register values */ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h new file mode 100644 index 0000000..b3449e0 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h @@ -0,0 +1,248 @@ +/* + * ddr_defs_ti816x.h + * + * ddr specific header for TI816X + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef _DDR_DEFS_TI816X_H +#define _DDR_DEFS_TI816X_H + +#include <asm/arch/hardware.h> + +#ifdef CONFIG_TI816X_EVM_DDR3 + +#define CONFIG_TI816X_DDR3_796 /* Values supported 400,531,675,796 */ +#define CONFIG_TI816X_DDR3_SW_LEVELING /* Enable software leveling (DDR3) */ + +/* + * DDR3 force values. These are board dependent + */ + +/* + * Invert clock adds an additional half cycle delay on the command + * interface. The additional half cycle, is usually meant to enable + * leveling in the situation that DQS is later than CK on the board. It + * also helps provide some additional margin for leveling. + * + * For the EVM this is helping us with additional room for the write + * leveling. Since the dqs delays are very small. + */ +#define INVERT_CLOCK 1 + +/* + * CMD_SLAVE_RATIO determines where is the command placed with respect + * to the clock edge. This is a ratio, implying 0x100 is one cycle. + * Ideally the command is centered so - this should be half cycle + * delay (0x80). But if invert clock is in use, an additional half + * cycle must be added + */ +#define CMD_SLAVE_FROM_INV_CLOCK(i) (((i) == 0) ? 0x80 : 0x100) +#define CMD_SLAVE_RATIO CMD_SLAVE_FROM_INV_CLOCK(INVERT_CLOCK) + +/* + * This represents the initial value for the leveling process. The + * value is a ratio - so 0x100 represents one cycle. The real delay + * is determined through the leveling process. + * + * During the leveling process, 0x20 is subtracted from the value, so + * we have added that to the value we want to set. We also set the + * values such that byte3 completes leveling after byte2 and byte1 + * after byte0. + */ +#define WR_DQS_RATIO_0 0x20 +#define WR_DQS_RATIO_1 0x20 +#define WR_DQS_RATIO_2 0x20 +#define WR_DQS_RATIO_3 0x20 + +/* + * This represents the initial value for the leveling process. The + * value is a ratio - so 0x100 represents one cycle. The real delay + * is determined through the leveling process. + * + * During the leveling process, 0x20 is subtracted from the value, so + * we have added that to the value we want to set. We also set the + * values such that byte3 completes leveling after byte2 and byte1 + * after byte0. + */ +#define RD_GATE_RATIO_0 0x20 +#define RD_GATE_RATIO_1 0x20 +#define RD_GATE_RATIO_2 0x20 +#define RD_GATE_RATIO_3 0x20 + +/* + * data rate in MHz. The DDR clock will be 1/2 of this value + */ +#define DDR_DATA_RATE 800 + +#define USE_EMIF0 1 +#define USE_EMIF1 1 + +/* + * EMIF Paramters. Refer the EMIF register documentation and the + * memory datasheet for details + */ +/* For 400 MHz */ +#if defined(CONFIG_TI816X_DDR3_400) +#define EMIF_TIM1 0x0CCCE524 +#define EMIF_TIM2 0x30308023 +#define EMIF_TIM3 0x009F82CF +#define EMIF_SDREF 0x10000C30 +#define EMIF_SDCFG 0x62A41032 +#define EMIF_PHYCFG 0x0000010B + +#if defined(CONFIG_TI816X_DDR3_SW_LEVELING) +/* These values are obtained from the CCS app */ +#define RD_DQS_GATE 0x12A +#define RD_DQS 0x3B +#define WR_DQS 0xA6 +#endif + +#endif /* CONFIG_TI816X_DDR3_400 */ + +/* For 531 MHz */ +#if defined(CONFIG_TI816X_DDR3_531) +#define EMIF_TIM1 0x0EF136AC +#define EMIF_TIM2 0x30408063 +#define EMIF_TIM3 0x009F83AF +#define EMIF_SDREF 0x1000102E +#define EMIF_SDCFG 0x62A51832 +#define EMIF_PHYCFG 0x0000010C + +#if defined(CONFIG_TI816X_DDR3_SW_LEVELING) +/* These values are obtained from the CCS app */ +#define RD_DQS_GATE 0x13D +#define RD_DQS 0x39 +#define WR_DQS 0xB4 +#endif + +#endif /* CONFIG_TI816X_DDR_531 */ + +/* For 675 MHz */ +#if defined(CONFIG_TI816X_DDR3_675) +#define EMIF_TIM1 0x13358875 +#define EMIF_TIM2 0x5051806C +#define EMIF_TIM3 0x009F84AF +#define EMIF_SDREF 0x10001491 +#define EMIF_SDCFG 0x62A63032 +#define EMIF_PHYCFG 0x0000010F + +#if defined(CONFIG_TI816X_DDR3_SW_LEVELING) +/* These values are obtained from the CCS app */ +#define RD_DQS_GATE 0x196 +#define RD_DQS 0x39 +#define WR_DQS 0x91 + +#endif + +#endif /* CONFIG_TI816X_DDR3_675 */ + +/* For 796 MHz */ +#if defined(CONFIG_TI816X_DDR3_796) +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_SDREF 0x10001841 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_PHYCFG 0x00000110 + +#if defined(CONFIG_TI816X_DDR3_SW_LEVELING) +/* These values are obtained from the CCS app */ +#define RD_DQS_GATE 0x1B3 +#define RD_DQS 0x35 +#define WR_DQS 0x93 + +#endif + +#endif /* CONFIG_TI816X_DDR_796 */ + + +#if defined(CONFIG_TI816X_DDR3_SW_LEVELING) +#define WR_DQS_RATIO_BYTE_LANE3 ((WR_DQS << 10) | WR_DQS) +#define WR_DQS_RATIO_BYTE_LANE2 ((WR_DQS << 10) | WR_DQS) +#define WR_DQS_RATIO_BYTE_LANE1 ((WR_DQS << 10) | WR_DQS) +#define WR_DQS_RATIO_BYTE_LANE0 ((WR_DQS << 10) | WR_DQS) + +#define WR_DATA_RATIO_BYTE_LANE3 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40)) +#define WR_DATA_RATIO_BYTE_LANE2 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40)) +#define WR_DATA_RATIO_BYTE_LANE1 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40)) +#define WR_DATA_RATIO_BYTE_LANE0 (((WR_DQS + 0x40) << 10) | (WR_DQS + 0x40)) + +#define RD_DQS_RATIO ((RD_DQS << 10) | RD_DQS) + +#define DQS_GATE_BYTE_LANE0 ((RD_DQS_GATE << 10) | RD_DQS_GATE) +#define DQS_GATE_BYTE_LANE1 ((RD_DQS_GATE << 10) | RD_DQS_GATE) +#define DQS_GATE_BYTE_LANE2 ((RD_DQS_GATE << 10) | RD_DQS_GATE) +#define DQS_GATE_BYTE_LANE3 ((RD_DQS_GATE << 10) | RD_DQS_GATE) + +#endif /* CONFIG_TI816X_DDR3_SW_LEVELING */ + +#endif /* CONFIG_TI816X_EVM_DDR3 */ + +#ifdef CONFIG_TI816X_EVM_DDR2 + +#define INVERT_CLK_OUT 0x0 +#define CMD_SLAVE_RATIO 0x80 +/* + * DDR2 ratio values. These are board dependent + * obtained from sweep experiments + */ + +/* EVM 400 MHz clock Settings */ + +#define WR_DQS_RATIO_BYTE_LANE3 ((0x4a << 10) | 0x4a) +#define WR_DQS_RATIO_BYTE_LANE2 ((0x4a << 10) | 0x4a) +#define WR_DQS_RATIO_BYTE_LANE1 ((0x4a << 10) | 0x4a) +#define WR_DQS_RATIO_BYTE_LANE0 ((0x4a << 10) | 0x4a) + +#define WR_DATA_RATIO_BYTE_LANE3 (((0x4a + 0x40) << 10) | (0x4a + 0x40)) +#define WR_DATA_RATIO_BYTE_LANE2 (((0x4a + 0x40) << 10) | (0x4a + 0x40)) +#define WR_DATA_RATIO_BYTE_LANE1 (((0x4a + 0x40) << 10) | (0x4a + 0x40)) +#define WR_DATA_RATIO_BYTE_LANE0 (((0x4a + 0x40) << 10) | (0x4a + 0x40)) + +#define RD_DQS_RATIO ((0x40 << 10) | 0x40) + +#define DQS_GATE_BYTE_LANE0 ((0x13a << 10) | 0x13a) +#define DQS_GATE_BYTE_LANE1 ((0x13a << 10) | 0x13a) +#define DQS_GATE_BYTE_LANE2 ((0x13a << 10) | 0x13a) +#define DQS_GATE_BYTE_LANE3 ((0x13a << 10) | 0x13a) + +/* + * EMIF Paramters + */ +#define EMIF_TIM1 0xAAB15E2 +#define EMIF_TIM2 0x423631D2 +#define EMIF_TIM3 0x80032F +#define EMIF_SDREF 0x10000C30 +/* 32 bit ddr2, CL=6, CWL=5, 13 rows, 8 banks, 10 bit column, 2 CS */ +#define EMIF_SDCFG 0x43801A3A + +/* + * TI816x PG1.0 EMIF_PHYCFG 0x0000030B local odt = 3, read latency = 11 + * TI816x PG1.1 EMIF_PHYCFG 0x0000010B local odt = 1, read latency = 11 + */ +#define EMIF_PHYCFG (pg_val_ti816x(0x0000030B, 0x0000010B)) + +#endif /* CONFIG_TI816X_EVM_DDR2 */ +#endif /* _DDR_DEFS_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 5a27f9c..7f3b555 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -23,6 +23,8 @@ #include <asm/arch/omap.h> #ifdef CONFIG_AM33XX #include <asm/arch/hardware_am33xx.h> +#elif defined(CONFIG_TI816X) +#include <asm/arch/hardware_ti816x.h> #elif defined(CONFIG_TI814X) #include <asm/arch/hardware_ti814x.h> #endif @@ -67,15 +69,10 @@ /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - /* GPMC Base address */ #define GPMC_BASE 0x50000000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index fa02f19..553c3bd 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -43,8 +43,13 @@ /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A101000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index a950ac3..c075274 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -42,8 +42,13 @@ /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x47C0C400 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 4 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A100800 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 0000000..60daf55 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,56 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819a000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index e0a3b8b..09d7a77 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -155,6 +155,8 @@ typedef struct hsmmc { /* Clock Configurations and Macros */ #ifdef CONFIG_AM33XX #define MMC_CLOCK_REFERENCE 96 /* MHz */ +#elif defined(CONFIG_TI816X) +#define MMC_CLOCK_REFERENCE 48 /* MHz */ #elif defined(CONFIG_TI814X) #define MMC_CLOCK_REFERENCE 192 /* MHz */ #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 1c6b65f..4caa4d8 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,8 @@ #include <asm/arch/mux_am33xx.h> #elif defined(CONFIG_TI814X) #include <asm/arch/mux_ti814x.h> +#elif defined(CONFIG_TI816X) +#include <asm/arch/mux_ti816x.h> #endif struct module_pin_mux { diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 0000000..0fcd49e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,363 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart(a)adeneo-embedded.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include <common.h> +#include <asm/io.h> + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ -- 1.7.10.4

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[U-Boot] [PATCH v2 1/3] Prepare for TI816X : reuse existing code from TI814X
by TENART Antoine 29 Mar '13

29 Mar '13

Rename some CONFIG_TI814X to a more generic CONFIG_81XX Signed-off-by: Antoine Tenart <atenart(a)adeneo-embedded.com> --- Makefile | 2 +- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/include/asm/arch-am33xx/cpu.h | 2 +- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- drivers/serial/ns16550.c | 4 ++-- spl/Makefile | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 7273fa4..811e7b6 100644 --- a/Makefile +++ b/Makefile @@ -330,7 +330,7 @@ LIBS-y += api/libapi.o LIBS-y += post/libpost.o LIBS-y += test/libtest.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index c961247..9bb2837 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,7 +32,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_TI81XX),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 55e82ba..8da8f91 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -36,7 +36,7 @@ COBJS += emif-common.o COBJS += vc.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),) COBJS += boot-common.o SOBJS += lowlevel_init.o endif diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 3d3a7c8..13c0667 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -54,7 +54,7 @@ /* Reset control */ #ifdef CONFIG_AM33XX #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #endif #define PRM_RSTST (PRM_RSTCTRL + 8) diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index d28f9a8..1a1cc18 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -31,7 +31,7 @@ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 02bc85b..c949423 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) + defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr); @@ -58,7 +58,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out(UART_LCRVAL, &com_port->lcr); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ - defined(CONFIG_TI814X) + defined(CONFIG_TI81XX) #if defined(CONFIG_APTIX) /* /13 mode so Aptix 6MHz can hit 115200 */ diff --git a/spl/Makefile b/spl/Makefile index c398a5f..8692f30 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -82,7 +82,7 @@ LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI81XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -- 1.7.10.4

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[U-Boot] [PATCH v2 0/3] Add TI816X EVM support
by TENART Antoine 29 Mar '13

29 Mar '13

This serie introduce the support of the TI816X EVM board. It applies on top of Matt Porter patches introducing the support of the TI814X EVM board ("Add TI814x EVM Support"). The serie fits into the existing AM33XX SoC support and reuse some definitions from the TI814X. Based on the implementation in the TI-PSP-04.00.02.14 vendor tree: http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=summary It has been tested booting up a Linux kernel on TI8168 refs F and C cards, with an MMC. SPL is working fine too. Changes for v2: - patches 2-7 squashed into a single patch "Add TI816X support" - removed all unused definitions - removed my definition of DMM_BASE and reworked the DMM initialization using the "common" config_dmm() from emif4.c - fixed coding style problems - now use the fallback CONFIG_SYS_BAUDRATE_TABLE - kept LONGHELP support - removed redefinition of the "device type" section in cpu_ti816x.h Antoine Tenart (3): Prepare for TI816X : reuse existing code from TI814X Add TI816X support Add TI816X evm board support MAINTAINERS | 4 + Makefile | 2 +- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/include/asm/arch-am33xx/clock.h | 4 + arch/arm/include/asm/arch-am33xx/clocks_ti816x.h | 136 +++ arch/arm/include/asm/arch-am33xx/cpu.h | 6 +- arch/arm/include/asm/arch-am33xx/cpu_ti816x.h | 194 +++++ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 + arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h | 248 ++++++ arch/arm/include/asm/arch-am33xx/hardware.h | 7 +- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 5 + arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 5 + arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 56 ++ arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 2 + arch/arm/include/asm/arch-am33xx/mux.h | 2 + arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 363 ++++++++ arch/arm/include/asm/arch-am33xx/omap.h | 2 +- arch/arm/include/asm/arch-am33xx/spl.h | 9 + board/ti/ti816x/Makefile | 48 ++ board/ti/ti816x/evm.c | 866 ++++++++++++++++++++ boards.cfg | 1 + drivers/serial/ns16550.c | 4 +- include/configs/ti816x_evm.h | 177 ++++ spl/Makefile | 2 +- 25 files changed, 2138 insertions(+), 13 deletions(-) create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/cpu_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/ddr_defs_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h create mode 100644 board/ti/ti816x/Makefile create mode 100644 board/ti/ti816x/evm.c create mode 100644 include/configs/ti816x_evm.h -- 1.7.10.4

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[U-Boot] [PATCH] disk: fix unaligned access in efi partitions
by Marc Dietrich 29 Mar '13

29 Mar '13

start_sect is not aligned to a 4 byte boundary thus causing exceptions on ARM platforms. Access this field via the get_unaligned macro. Signed-off-by: Marc Dietrich <marvin24(a)gmx.de> --- disk/part_efi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index b3fd0e9..6678a4c 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -30,6 +30,7 @@ * * This limits the maximum size of addressable storage to < 2 Terra Bytes */ +#include <asm/unaligned.h> #include <common.h> #include <command.h> #include <ide.h> @@ -505,7 +506,7 @@ err: static int pmbr_part_valid(struct partition *part) { if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && - le32_to_cpu(part->start_sect) == 1UL) { + le32_to_cpu(get_unaligned(&part->start_sect)) == 1UL) { return 1; } -- 1.7.9.5

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[U-Boot] [PATCH 1/2] OMAP4/5: I2C: New I2C driver, Makefile fix
by Lubomir Popov 29 Mar '13

29 Mar '13

See PATCH 2/2 on new I2C driver. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- drivers/i2c/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 5dbdbe3..8afc621 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -36,6 +36,8 @@ COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_DRIVER_OMAP44XX_I2C) += omap4x5x_i2c.o +COBJS-$(CONFIG_DRIVER_OMAP54XX_I2C) += omap4x5x_i2c.o COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o -- 1.7.9.5

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[U-Boot] [PATCH] OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
by Lubomir Popov 29 Mar '13

29 Mar '13

Needed in order to be able to select I2C4 and I2C5 via "i2c dev". Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- arch/arm/include/asm/arch-omap5/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h index 68be03b..ec39a53 100644 --- a/arch/arm/include/asm/arch-omap5/i2c.h +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -23,7 +23,7 @@ #ifndef _OMAP5_I2C_H_ #define _OMAP5_I2C_H_ -#define I2C_BUS_MAX 3 +#define I2C_BUS_MAX 5 #define I2C_DEFAULT_BASE I2C_BASE1 struct i2c { -- 1.7.9.5

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