March 2013 - U-Boot

Re: [U-Boot] [PATCH v7] mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support
by Jagannadha Sutradharudu Teki 03 Apr '13

03 Apr '13

Hi, Any update on this. Thanks, Jagan. > -----Original Message----- > From: Jagannadha Sutradharudu Teki [mailto:jagannadha.sutradharudu- > teki(a)xilinx.com] > Sent: 03 March 2013 16:45 > To: u-boot(a)lists.denx.de > Cc: Stefan Roese; Aaron Williams; Luka Perkov; monstr(a)monstr.eu; > Jagannadha Sutradharudu Teki > Subject: [PATCH v7] mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support > > From: aaron.williams(a)caviumnetworks.com > > This commit is based on that patch from > aaron.williams(a)caviumnetworks.com with same commit title. pulled the > same code changes into current u-boot tree. > > http://patchwork.ozlabs.org/patch/140863/ > http://lists.denx.de/pipermail/u-boot/2011-April/089606.html > > This patch corrects the addresses used when working with Spansion/AMD > FLASH chips. > Addressing for 8 and 16 bits is almost identical except in the 16-bit case the > LSB of the address is always 0. The confusion arose because the addresses in > the datasheet for 16-bit mode are word addresses but this code assumed it > was byte addresses. > > I have only been able to test this on our Octeon boards which use either an > 8-bit or 16-bit bus. I have not tested the case where there's an 8-bit part on > a 16-bit bus. > > This patch also adds some delays as suggested by Spansion. > > If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an 8- > bit bus is detected. > > Apart from the pulled changes, fixed few minor code cleanups and tested on > 256M29EW, 512M29EW flashes. > > Before this fix: > --------------- > Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors > AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF > Erase timeout: 4096 ms, write timeout: 2 ms > Buffer write timeout: 5 ms, buffer size: 1024 bytes > > After this fix: > -------------- > Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors > AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301 > Erase timeout: 4096 ms, write timeout: 2 ms > Buffer write timeout: 5 ms, buffer size: 1024 bytes > > Signed-off-by: Aaron Williams <aaron.williams(a)caviumnetworks.com> > Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> > Tested-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> > --- > Changes for v3: > - Fixed few minor code cleanups > Changes for v4: > - Updated the S-o-b for original authors Changes for v5: > - Collect all S-o-b together > Changes for v6: > - Preserving author details > Changes for v7: > - Remove Luka Perkov from T-b > > drivers/mtd/cfi_flash.c | 78 +++++++++++++++++++++++++++++++++----------- > --- > include/mtd/cfi_flash.h | 41 ++++++++++++------------ > 2 files changed, 76 insertions(+), 43 deletions(-) > > diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index > 60dbb78..6b9fc1a 100644 > --- a/drivers/mtd/cfi_flash.c > +++ b/drivers/mtd/cfi_flash.c > @@ -210,9 +210,11 @@ unsigned long flash_sector_size(flash_info_t *info, > flash_sect_t sect) static inline void * flash_map (flash_info_t * info, > flash_sect_t sect, uint offset) { > - unsigned int byte_offset = offset * info->portwidth; > + unsigned int byte_offset = offset * info->portwidth / info->chipwidth; > + unsigned int addr = (info->start[sect] + byte_offset); > + unsigned int mask = 0xffffffff << (info->portwidth - 1); > > - return (void *)(info->start[sect] + byte_offset); > + return (void *)(addr & mask); > } > > static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, @@ - > 398,6 +400,8 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t > sect, #endif > flash_write64(cword.ll, addr); > break; > + default: > + printf("fwc: Unknown port width %d\n", info->portwidth); > } > > /* Ensure all the instructions are fully finished */ @@ -585,7 +589,6 > @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, > prompt, info->start[sector], > flash_read_long (info, sector, 0)); > flash_write_cmd (info, sector, 0, info->cmd_reset); > - udelay(1); > return ERR_TIMOUT; > } > udelay (1); /* also triggers watchdog */ > @@ -753,12 +756,8 @@ static void flash_add_byte (flash_info_t * info, > cfiword_t * cword, uchar c) static flash_sect_t find_sector (flash_info_t * > info, ulong addr) { > static flash_sect_t saved_sector; /* previously found sector */ > - static flash_info_t *saved_info; /* previously used flash bank */ > flash_sect_t sector = saved_sector; > > - if ((info != saved_info) || (sector >= info->sector_count)) > - sector = 0; > - > while ((info->start[sector] < addr) > && (sector < info->sector_count - 1)) > sector++; > @@ -770,7 +769,6 @@ static flash_sect_t find_sector (flash_info_t * info, > ulong addr) > sector--; > > saved_sector = sector; > - saved_info = info; > return sector; > } > > @@ -787,12 +785,15 @@ static int flash_write_cfiword (flash_info_t * info, > ulong dest, > /* Check if Flash is (sufficiently) erased */ > switch (info->portwidth) { > case FLASH_CFI_8BIT: > + debug("%s: 8-bit 0x%02x\n", __func__, cword.c); > flag = ((flash_read8(dstaddr) & cword.c) == cword.c); > break; > case FLASH_CFI_16BIT: > + debug("%s: 16-bit 0x%04x\n", __func__, cword.w); > flag = ((flash_read16(dstaddr) & cword.w) == cword.w); > break; > case FLASH_CFI_32BIT: > + debug("%s: 32-bit 0x%08lx\n", __func__, cword.l); > flag = ((flash_read32(dstaddr) & cword.l) == cword.l); > break; > case FLASH_CFI_64BIT: > @@ -1053,6 +1054,8 @@ int flash_erase (flash_info_t * info, int s_first, int > s_last) > flash_sect_t sect; > int st; > > + debug("%s: erasing sectors %d to %d\n", __func__, s_first, s_last); > + > if (info->flash_id != FLASH_MAN_CFI) { > puts ("Can't erase unknown flash type - aborted\n"); > return 1; > @@ -1162,6 +1165,9 @@ int flash_erase (flash_info_t * info, int s_first, int > s_last) > rcode = 1; > else if (flash_verbose) > putc ('.'); > + } else { > + debug("\nSector %d is protected.\n", > + info->protect[sect]); > } > } > > @@ -1857,7 +1863,7 @@ static void flash_read_cfi (flash_info_t *info, void > *buf, > unsigned int i; > > for (i = 0; i < len; i++) > - p[i] = flash_read_uchar(info, start + i); > + p[i] = flash_read_uchar(info, start + (i * 2)); > } > > static void __flash_cmd_reset(flash_info_t *info) @@ -1878,21 +1884,40 > @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { > int cfi_offset; > > - /* Issue FLASH reset command */ > - flash_cmd_reset(info); > - > for (cfi_offset=0; > cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); > cfi_offset++) { > + /* Issue FLASH reset command */ > + flash_cmd_reset(info); > flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], > FLASH_CMD_CFI); > - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') > - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') > - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) > { > + if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && > + flash_isequal(info, 0, > + FLASH_OFFSET_CFI_RESP + 2, 'R') && > + flash_isequal(info, 0, > + FLASH_OFFSET_CFI_RESP + 4, 'Y')) { > flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, > sizeof(struct cfi_qry)); > +#ifdef CONFIG_SYS_FLASH_INTERFACE_WIDTH > + info->interface = > CONFIG_SYS_FLASH_INTERFACE_WIDTH; #else > info->interface = le16_to_cpu(qry->interface_desc); > - > + /* Some flash chips can support multiple bus widths. > + * In this case, override the interface width and > + * limit it to the port width. > + */ > + if ((info->interface == FLASH_CFI_X8X16) && > + (info->portwidth == FLASH_CFI_8BIT)) { > + debug("Overriding 16-bit interface" > + " width to 8-bit port > width.\n"); > + info->interface = FLASH_CFI_X8; > + } else if ((info->interface == FLASH_CFI_X16X32) && > + (info->portwidth == FLASH_CFI_16BIT)) { > + debug("Overriding 16-bit interface" > + " width to 16-bit port > width.\n"); > + info->interface = FLASH_CFI_X16; > + } > +#endif > info->cfi_offset = flash_offset_cfi[cfi_offset]; > debug ("device interface is %d\n", > info->interface); > @@ -1903,8 +1928,8 @@ static int __flash_detect_cfi (flash_info_t * info, > struct cfi_qry *qry) > info->chipwidth << CFI_FLASH_SHIFT_WIDTH); > > /* calculate command offsets as in the Linux driver > */ > - info->addr_unlock1 = 0x555; > - info->addr_unlock2 = 0x2aa; > + info->addr_unlock1 = 0xaaa; > + info->addr_unlock2 = 0x555; > > /* > * modify the unlock address if we are @@ -1938,8 > +1963,12 @@ static int flash_detect_cfi (flash_info_t * info, struct cfi_qry > *qry) > for (info->chipwidth = FLASH_CFI_BY8; > info->chipwidth <= info->portwidth; > info->chipwidth <<= 1) > - if (__flash_detect_cfi(info, qry)) > + if (__flash_detect_cfi(info, qry)) { > + debug("Found CFI flash, portwidth %d," > + " chipwidth %d\n", > + info->portwidth, info->chipwidth); > return 1; > + } > } > debug ("not found\n"); > return 0; > @@ -1958,7 +1987,7 @@ static void flash_fixup_amd(flash_info_t *info, > struct cfi_qry *qry) > /* CFI < 1.1, try to guess from device id */ > if ((info->device_id & 0x80) != 0) > cfi_reverse_geometry(qry); > - } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { > + } else if (flash_read_uchar(info, info->ext_addr + 0x1e) == 3) { > /* CFI >= 1.1, deduct from top/bottom flag */ > /* note: ext_addr is valid since cfi_version > 0 */ > cfi_reverse_geometry(qry); > @@ -2054,14 +2083,15 @@ ulong flash_get_size (phys_addr_t base, int > banknum) > > if (flash_detect_cfi (info, &qry)) { > info->vendor = le16_to_cpu(qry.p_id); > - info->ext_addr = le16_to_cpu(qry.p_adr); > + info->ext_addr = le16_to_cpu(qry.p_adr) * 2; > + debug("extended address is 0x%x\n", info->ext_addr); > num_erase_regions = qry.num_erase_regions; > > if (info->ext_addr) { > info->cfi_version = (ushort) flash_read_uchar (info, > - info->ext_addr + 3) << 8; > + info->ext_addr + 6) << 8; > info->cfi_version |= (ushort) flash_read_uchar (info, > - info->ext_addr + 4); > + info->ext_addr + 8); > } > > #ifdef DEBUG > @@ -2112,6 +2142,8 @@ ulong flash_get_size (phys_addr_t base, int > banknum) > debug ("device id is 0x%x\n", info->device_id); > debug ("device id2 is 0x%x\n", info->device_id2); > debug ("cfi version is 0x%04x\n", info->cfi_version); > + debug("port width: %d, chipwidth: %d, interface: %d\n", > + info->portwidth, info->chipwidth, info->interface); > > size_ratio = info->portwidth / info->chipwidth; > /* if the chip is x8/x16 reduce the ratio by half */ diff --git > a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 966b5e0..9bd76eb > 100644 > --- a/include/mtd/cfi_flash.h > +++ b/include/mtd/cfi_flash.h > @@ -78,29 +78,30 @@ > #define FLASH_CONTINUATION_CODE 0x7F > > #define FLASH_OFFSET_MANUFACTURER_ID 0x00 > -#define FLASH_OFFSET_DEVICE_ID 0x01 > -#define FLASH_OFFSET_DEVICE_ID2 0x0E > -#define FLASH_OFFSET_DEVICE_ID3 0x0F > -#define FLASH_OFFSET_CFI 0x55 > +#define FLASH_OFFSET_DEVICE_ID 0x02 > +#define FLASH_OFFSET_DEVICE_ID2 0x1C > +#define FLASH_OFFSET_DEVICE_ID3 0x1E > +#define FLASH_OFFSET_CFI 0xAA > + > #define FLASH_OFFSET_CFI_ALT 0x555 > -#define FLASH_OFFSET_CFI_RESP 0x10 > -#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 > +#define FLASH_OFFSET_CFI_RESP 0x20 > +#define FLASH_OFFSET_PRIMARY_VENDOR 0x26 > /* extended query table primary address */ > -#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 > +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x2A > #define FLASH_OFFSET_WTOUT 0x1F > -#define FLASH_OFFSET_WBTOUT 0x20 > -#define FLASH_OFFSET_ETOUT 0x21 > -#define FLASH_OFFSET_CETOUT 0x22 > -#define FLASH_OFFSET_WMAX_TOUT 0x23 > -#define FLASH_OFFSET_WBMAX_TOUT 0x24 > -#define FLASH_OFFSET_EMAX_TOUT 0x25 > -#define FLASH_OFFSET_CEMAX_TOUT 0x26 > -#define FLASH_OFFSET_SIZE 0x27 > -#define FLASH_OFFSET_INTERFACE 0x28 > -#define FLASH_OFFSET_BUFFER_SIZE 0x2A > -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C > -#define FLASH_OFFSET_ERASE_REGIONS 0x2D > -#define FLASH_OFFSET_PROTECT 0x02 > +#define FLASH_OFFSET_WBTOUT 0x40 > +#define FLASH_OFFSET_ETOUT 0x4A > +#define FLASH_OFFSET_CETOUT 0x44 > +#define FLASH_OFFSET_WMAX_TOUT 0x46 > +#define FLASH_OFFSET_WBMAX_TOUT 0x48 > +#define FLASH_OFFSET_EMAX_TOUT 0x4A > +#define FLASH_OFFSET_CEMAX_TOUT 0x4C > +#define FLASH_OFFSET_SIZE 0x4E > +#define FLASH_OFFSET_INTERFACE 0x50 > +#define FLASH_OFFSET_BUFFER_SIZE 0x54 > +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x58 > +#define FLASH_OFFSET_ERASE_REGIONS 0x5A > +#define FLASH_OFFSET_PROTECT 0x04 > #define FLASH_OFFSET_USER_PROTECTION 0x85 > #define FLASH_OFFSET_INTEL_PROTECTION 0x81 > > -- > 1.7.4 > This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. 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[U-Boot] [PATCH 2/2] OMAP4/5: I2C: New I2C driver files added
by Lubomir Popov 02 Apr '13

02 Apr '13

New I2C driver that fixes read-related issues with some types of I2C chips. The i2c_read function now performs bulk read of the requested number of bytes in a single transaction and completes much faster. Whether to use Stop-Start or Repeated Start between the address and data phases is configurable (e.g. in the board config header). Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- The main feature of this new driver is that now i2c_read operates correctly with chips that have addressable registers wider than 8 bits (such as TI temperature sensors), or that have multiple non-addressable registers that have to be retrieved in a bulk transaction (such as TI clock distributors). The old driver (omap24xx_i2c.c) performs separate read transactions for every byte requested and returns invalid data in these cases (except possibly the first byte; this invalid data is in fact presented by the chips, so the driver does not know that it is invalid). The new driver performs a standard bulk read transaction (with S-P by default, or with Sr if configured so) and works correctly with all types of I2C devices. The i2c_write and i2c_probe functions have also been modified. I have tested the driver on OMAP4430, 4460, 4470 and 5430 and found no issues so far. Nevertheless, folks, any additional testing is strongly encouraged; the driver should also work on OMAP3 and derivatives, but I didn't have this opportunity, so any feedback is welcome. drivers/i2c/omap4x5x_i2c.c | 562 ++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/omap4x5x_i2c.h | 176 ++++++++++++++ 2 files changed, 738 insertions(+) create mode 100644 drivers/i2c/omap4x5x_i2c.c create mode 100644 drivers/i2c/omap4x5x_i2c.h diff --git a/drivers/i2c/omap4x5x_i2c.c b/drivers/i2c/omap4x5x_i2c.c new file mode 100644 index 0000000..44d7813 --- /dev/null +++ b/drivers/i2c/omap4x5x_i2c.c @@ -0,0 +1,562 @@ +/* + * Basic I2C functions + * + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Author: Jian Zhang jzhang(a)ti.com, Texas Instruments + * + * Copyright (c) 2003 Wolfgang Denk, wd(a)denx.de + * Rewritten to fit into the current U-Boot framework + * + * Adapted for OMAP2420 I2C, r-woodruff2(a)ti.com + * + * Copyright (c) 2013 Lubomir Popov <lpopov(a)mm-sol.com>, MM Solutions + * Based on omap24xx_i2c.c and modified for OMAP4/5: + * - i2c_read now operates correctly, with bulk transfer; + * - i2c_probe performs write access vs read; + * - Driver tries to identify I2C pads not properly padconf'd; + * - Should work with OMAP3/AM33xx as well, but is not tested. + */ + +#include <common.h> + +#include <asm/arch/i2c.h> +#include <asm/io.h> + +#include "omap4x5x_i2c.h" + +#undef I2C_DBG + +#ifdef I2C_DBG +#define I2C_PRINTF(fmt, args...) printf(fmt , ##args) +#else +#define I2C_PRINTF(fmt, args...) +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define I2C_TIMEOUT 1000 + +static int wait_for_bus_free(void); +static u16 wait_for_event(void); +static void flush_fifo(void); + +/* + * For SPL boot some boards need i2c before SDRAM is initialised so force + * variables to live in SRAM + */ +static struct i2c __attribute__((section (".data"))) *i2c_base = + (struct i2c *)I2C_DEFAULT_BASE; +static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = + { [0 ... (I2C_BUS_MAX-1)] = 0 }; +static unsigned int __attribute__((section (".data"))) current_bus = 0; + +void i2c_init(int speed, int slaveadd) +{ + int psc, fsscll, fssclh; + int hsscll = 0, hssclh = 0; + u32 scll, sclh; + int timeout = I2C_TIMEOUT; + + /* Only handle standard, fast and high speeds */ + if ((speed != OMAP_I2C_STANDARD) && + (speed != OMAP_I2C_FAST_MODE) && + (speed != OMAP_I2C_HIGH_SPEED)) { + printf("Error : I2C unsupported speed %d\n", speed); + return; + } + + psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; + psc -= 1; + if (psc < I2C_PSC_MIN) { + printf("Error : I2C unsupported prescalar %d\n", psc); + return; + } + + if (speed == OMAP_I2C_HIGH_SPEED) { + /* High speed */ + + /* For first phase of HS mode */ + fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / + (2 * OMAP_I2C_FAST_MODE); + + fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; + fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; + if (((fsscll < 0) || (fssclh < 0)) || + ((fsscll > 255) || (fssclh > 255))) { + printf("Error : I2C initializing first phase clock\n"); + return; + } + + /* For second phase of HS mode */ + hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + + hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; + hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; + if (((fsscll < 0) || (fssclh < 0)) || + ((fsscll > 255) || (fssclh > 255))) { + printf("Error : I2C initializing second phase clock\n"); + return; + } + + scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; + sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; + + } else { + /* Standard and fast speed */ + fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + + fsscll -= I2C_FASTSPEED_SCLL_TRIM; + fssclh -= I2C_FASTSPEED_SCLH_TRIM; + if (((fsscll < 0) || (fssclh < 0)) || + ((fsscll > 255) || (fssclh > 255))) { + printf("Error : I2C initializing clock\n"); + return; + } + + scll = (unsigned int)fsscll; + sclh = (unsigned int)fssclh; + } + + I2C_PRINTF("i2c_init: bus %x, base %p\n", current_bus, i2c_base); + + if (readw(&i2c_base->con) & I2C_CON_EN) { + writew(0, &i2c_base->con); + udelay(50000); + } + + writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ + udelay(1000); + + writew(I2C_CON_EN, &i2c_base->con); + while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { + if (timeout <= 0) { + printf("ERROR: Timeout in soft-reset\n"); + return; + } + udelay(1000); + } + + writew(0, &i2c_base->con); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); + + /* own address */ + writew(slaveadd, &i2c_base->oa); + writew(I2C_CON_EN, &i2c_base->con); + + /* have to enable intrrupts or OMAP i2c module doesn't work */ + writew(I2C_IE_BF_IE | I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); + udelay(1000); + + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + + if (gd->flags & GD_FLG_RELOC) { + bus_initialized[current_bus] = 1; + } +} + +static void flush_fifo(void) +{ u16 stat; + + /* note: if you try and read data when its not there or ready + * you get a bus error + */ + while (1) { + stat = readw(&i2c_base->stat); + if (stat == I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) + readb(&i2c_base->data); +#else + readw(&i2c_base->data); +#endif + writew(I2C_STAT_RRDY, &i2c_base->stat); + udelay(1000); + } else + break; + } +} + +/* i2c_probe: Use write access + */ +int i2c_probe(uchar chip) +{ + u16 status; + int res = 1; /* default = fail */ + + if (chip == readw(&i2c_base->oa)) + return res; + + /* wait until bus is free */ + if (wait_for_bus_free()) + return res; + + /* No data transfer, slave addr only */ + writew(0, &i2c_base->cnt); + /* set slave address */ + writew(chip, &i2c_base->sa); + /* stop bit needed here */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); + + status = wait_for_event(); + I2C_PRINTF("%02x: RAW=%04x ST=%04x\n", chip, status, readw(&i2c_base->stat)); + + if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) + goto pr_exit; /* If pads are not configured for I2C */ + + /* check for ACK (!NAK) */ + if (!(status & I2C_STAT_NACK)) { + res = 0; /* Device found */ + /* abort transfer (force idle state) */ + writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset cntrlr */ + udelay(1000); + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); /* STP */ + } +pr_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return res; +} + +/* i2c_read: Function now uses a single I2C read transaction with bulk transfer of + * up to 64 bytes ('i2c md' command limits this to 16 bytes anyway). If + * CONFIG_I2C_REPEATED_START is defined in the board config header, this + * transaction shall be with Repeated Start (Sr) between the address and + * data phases; otherwise Stop-Start (P-S) shall be used (some I2C chips do + * require a Stop-Start). + * The address (reg offset) may be 0, 1 or 2 bytes long. + * Function now reads correctly from chips that return more than one byte + * of data per addressed register (such as TI temperature sensors), or that + * do not need a register address (such as some clock distributors). + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i2c_error = 0; + u16 status, acnt; + + if (alen < 0) { + printf("I2C read: addr len < 0\n"); + return 1; + } + if (len < 0) { + printf("I2C read: data len < 0\n"); + return 1; + } + if (buffer == NULL) { + printf("I2C read: NULL pointer passed\n"); + return 1; + } + + if (alen > 2) { + printf("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (len > 64) { + printf("I2C read: max data len 64 (0x40) allowed\n"); + return 1; + } + + acnt = alen; + + /* Wait until bus is free */ + if (wait_for_bus_free()) + return 1; + + /* Zero, one or two bytes reg address (offset) */ + writew(acnt, &i2c_base->cnt); + /* Set slave address */ + writew(chip, &i2c_base->sa); + + if (acnt) { + /* Must write reg offset first */ +#ifdef CONFIG_I2C_REPEATED_START + /* No stop bit, use Repeated Start */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_TRX, &i2c_base->con); +#else + /* Stop - Start */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | + I2C_CON_TRX, &i2c_base->con); +#endif + /* Send register offset */ + while (1) { + status = wait_for_event(); + I2C_PRINTF("RD: WR offs: ST=%04X\n", status); + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_read: pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto rd_exit; + } + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", + status); + goto rd_exit; + } + if (acnt) { + if (status & I2C_STAT_XRDY) { + acnt--; + /* Do we have to use byte access? */ + writeb((addr >> (8 * acnt)) & 0xff, &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + } + } + /* Set slave address */ + writew(chip, &i2c_base->sa); + /* Read len bytes from slave */ + writew(len, &i2c_base->cnt); + /* Need stop bit here */ + writew(I2C_CON_EN | I2C_CON_MST | + I2C_CON_STT | I2C_CON_STP, + &i2c_base->con); + + /* Receive data */ + while (1) { + status = wait_for_event(); + I2C_PRINTF("RD: RD data: ST=%04X\n", status); + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + goto rd_exit; + } + if (status & I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) + *buffer++ = readb(&i2c_base->data); +#else + *buffer++ = readw(&i2c_base->data) & 0xff; +#endif + writew(I2C_STAT_RRDY, &i2c_base->stat); + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + } + +rd_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return i2c_error; +} + +/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. + * Up to 64 total bytes (addr + data) may be transferred. + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + u16 status, acnt; + int i2c_error = 0; + + if (alen < 0) { + printf("I2C write: addr len < 0\n"); + return 1; + } + if (len < 0) { + printf("I2C write: data len < 0\n"); + return 1; + } + if (buffer == NULL) { + printf("I2C write: NULL pointer passed\n"); + return 1; + } + if (alen > 2) { + printf("I2C write: addr len %d not supported\n", alen); + return 1; + } + if (alen + len > 64) { + printf("I2C write: max (alen + len) of 64 (0x40) allowed\n"); + return 1; + } + + acnt = alen; + + /* Wait until bus is free */ + if (wait_for_bus_free()) + return 1; + + /* Start address phase - will write regoffset + len bytes data */ + writew(alen + len, &i2c_base->cnt); + /* Set slave address */ + writew(chip, &i2c_base->sa); + /* Stop bit needed */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c_base->con); + + while (acnt) { + /* Must write reg offset (one or two bytes) */ + status = wait_for_event(); + I2C_PRINTF("WR: WR offs: ST=%04X\n", status); + /* Try to identify bus that is not padconf'd for I2C */ + if (status == I2C_STAT_XRDY) { + i2c_error = 2; + printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", + current_bus, status); + goto wr_exit; + } + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", + status); + goto wr_exit; + } + if (status & I2C_STAT_XRDY) { + acnt--; + writeb((addr >> (8 * acnt)) & 0xff, &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + else { + i2c_error = 1; + printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", + status); + goto wr_exit; + } + } + /* Address phase is over, now write data */ + for (i = 0; i < len; i++) { + status = wait_for_event(); + I2C_PRINTF("WR: WR data: ST=%04X\n", status); + if (status == 0 || status & I2C_STAT_NACK) { + i2c_error = 1; + printf("i2c_write: error waiting for data ACK (status=0x%x)\n", + status); + goto wr_exit; + } + if (status & I2C_STAT_XRDY) { + writeb(buffer[i], &i2c_base->data); + writew(I2C_STAT_XRDY, &i2c_base->stat); + } + else { + i2c_error = 1; + printf("i2c_write: bus not ready for data Tx (i=%d)\n", i); + goto wr_exit; + } + } + +wr_exit: + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return i2c_error; +} + +/* Wait for the bus to be free by checking the Bus Busy (BB) + * bit to become clear + */ +static int wait_for_bus_free(void) +{ + int timeout = I2C_TIMEOUT, res = 0; + u16 stat; + + writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ + /* Read RAW status */ + while ((stat = readw(&i2c_base->irqstatus_raw) & I2C_STAT_BB) && timeout--) { + writew(stat, &i2c_base->stat); + udelay(200); + } + + if (timeout <= 0) { + printf("Timed out in wait_for_bus_free: I2C_STAT_RAW=%x\n", + readw(&i2c_base->irqstatus_raw)); + res = 1; + } + writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff */ + return res; +} + +/* Wait for the I2C controller to complete current action + * and update status + */ +static u16 wait_for_event(void) +{ + u16 status; + int timeout = I2C_TIMEOUT; + + do { + udelay(200); + status = readw(&i2c_base->irqstatus_raw); + } while (!(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf("Timed out in wait_for_event: I2C_STAT_RAW=%x\n", + readw(&i2c_base->irqstatus_raw)); + writew(0xFFFF, &i2c_base->stat); + status = 0; + } + return status; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= I2C_BUS_MAX) { + printf("Bad bus: %x\n", bus); + return -1; + } + + switch (bus) { + default: + bus = 0; /* Fall through */ + case 0: + i2c_base = (struct i2c *)I2C_BASE1; + break; + case 1: + i2c_base = (struct i2c *)I2C_BASE2; + break; +#if (I2C_BUS_MAX > 2) + case 2: + i2c_base = (struct i2c *)I2C_BASE3; + break; +#if (I2C_BUS_MAX > 3) + case 3: + i2c_base = (struct i2c *)I2C_BASE4; + break; +#if (I2C_BUS_MAX > 4) + case 4: + i2c_base = (struct i2c *)I2C_BASE5; + break; +#endif +#endif +#endif + } + current_bus = bus; + + if (!bus_initialized[current_bus]) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return 0; +} + +int i2c_get_bus_num(void) +{ + return (int) current_bus; +} + diff --git a/drivers/i2c/omap4x5x_i2c.h b/drivers/i2c/omap4x5x_i2c.h new file mode 100644 index 0000000..1277abe --- /dev/null +++ b/drivers/i2c/omap4x5x_i2c.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, <www.ti.com> + * + * Copyright (c) 2013 Lubomir Popov <lpopov(a)mm-sol.com>, MM Solutions + * Based on omap24xx_i2c.h and modified for OMAP4/5 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP4x5x_I2C_H_ +#define _OMAP4x5x_I2C_H_ + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IRQENABLE_SET): */ + +#define I2C_IE_XDR_IE (1 << 14) +#define I2C_IE_RDR_IE (1 << 13) +#define I2C_IE_ROVR_IE (1 << 11) +#define I2C_IE_XUDF_IE (1 << 10) +#define I2C_IE_ASS_IE (1 << 9) +#define I2C_IE_BF_IE (1 << 8) /* Bus Free interrupt enable */ +#define I2C_IE_AERR_IE (1 << 7) +#define I2C_IE_STC_IE (1 << 6) +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Registers (I2C_IRQSTATUS and I2C_IRQSTATUS_RAW): */ + +#define I2C_STAT_XDR (1 << 14) /* Transmit Draining */ +#define I2C_STAT_RDR (1 << 13) /* Receive Draining */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Addressed as slave */ +#define I2C_STAT_BF (1 << 8) /* Bus Free */ +#define I2C_STAT_AERR (1 << 7) /* Access Error */ +#define I2C_STAT_STC (1 << 6) /* Start Condition */ +#define I2C_STAT_GC (1 << 5) /* General Call */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ + /* (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +/* I2C System Status Register (I2C_SYSS): */ + +#define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ + +#define I2C_SCLL_SCLL 0 +#define I2C_SCLL_SCLL_M 0xFF +#define I2C_SCLL_HSSCLL 8 +#define I2C_SCLH_HSSCLL_M 0xFF +#define I2C_SCLH_SCLH 0 +#define I2C_SCLH_SCLH_M 0xFF +#define I2C_SCLH_HSSCLH 8 +#define I2C_SCLH_HSSCLH_M 0xFF + +#define OMAP_I2C_STANDARD 100000 +#define OMAP_I2C_FAST_MODE 400000 +#define OMAP_I2C_HIGH_SPEED 3400000 + +#define SYSTEM_CLOCK_12 12000000 +#define SYSTEM_CLOCK_13 13000000 +#define SYSTEM_CLOCK_192 19200000 +#define SYSTEM_CLOCK_96 96000000 + +/* Use the reference value of 96MHz if not explicitly set by the board */ +#ifndef I2C_IP_CLK +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#endif + +/* + * The reference minimum clock for high speed is 19.2MHz. + * The linux 2.6.30 kernel uses this value. + * The reference minimum clock for fast mode is 9.6MHz + * The reference minimum clock for standard mode is 4MHz + * In TRM, the value of 12MHz is used. + */ +#ifndef I2C_INTERNAL_SAMPLING_CLK +#define I2C_INTERNAL_SAMPLING_CLK 19200000 +#endif + +/* + * The equation for the low and high time is + * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed + * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed + * + * If the duty cycle is 50% + * + * tlow = scll + scll_trim = sampling clock / (2 * speed) + * thigh = sclh + sclh_trim = sampling clock / (2 * speed) + * + * In TRM + * scll_trim = 7 + * sclh_trim = 5 + * + * The linux 2.6.30 kernel uses + * scll_trim = 6 + * sclh_trim = 6 + * + * These are the trim values for standard and fast speed + */ +#ifndef I2C_FASTSPEED_SCLL_TRIM +#define I2C_FASTSPEED_SCLL_TRIM 6 +#endif +#ifndef I2C_FASTSPEED_SCLH_TRIM +#define I2C_FASTSPEED_SCLH_TRIM 6 +#endif + +/* These are the trim values for high speed */ +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM +#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM +#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM +#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM +#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM +#endif + +#define I2C_PSC_MAX 0x0f +#define I2C_PSC_MIN 0x00 + +#endif /* _OMAP4x5x_I2C_H_ */ -- 1.7.9.5

2 1

[U-Boot] [PATCH v7] mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support
by Jagannadha Sutradharudu Teki 02 Apr '13

02 Apr '13

From: aaron.williams(a)caviumnetworks.com This commit is based on that patch from aaron.williams(a)caviumnetworks.com with same commit title. pulled the same code changes into current u-boot tree. http://patchwork.ozlabs.org/patch/140863/ http://lists.denx.de/pipermail/u-boot/2011-April/089606.html This patch corrects the addresses used when working with Spansion/AMD FLASH chips. Addressing for 8 and 16 bits is almost identical except in the 16-bit case the LSB of the address is always 0. The confusion arose because the addresses in the datasheet for 16-bit mode are word addresses but this code assumed it was byte addresses. I have only been able to test this on our Octeon boards which use either an 8-bit or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit bus. This patch also adds some delays as suggested by Spansion. If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an 8-bit bus is detected. Apart from the pulled changes, fixed few minor code cleanups and tested on 256M29EW, 512M29EW flashes. Before this fix: --------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes After this fix: -------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301 Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Signed-off-by: Aaron Williams <aaron.williams(a)caviumnetworks.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v3: - Fixed few minor code cleanups Changes for v4: - Updated the S-o-b for original authors Changes for v5: - Collect all S-o-b together Changes for v6: - Preserving author details Changes for v7: - Remove Luka Perkov from T-b drivers/mtd/cfi_flash.c | 78 +++++++++++++++++++++++++++++++++-------------- include/mtd/cfi_flash.h | 41 ++++++++++++------------ 2 files changed, 76 insertions(+), 43 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 60dbb78..6b9fc1a 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -210,9 +210,11 @@ unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) static inline void * flash_map (flash_info_t * info, flash_sect_t sect, uint offset) { - unsigned int byte_offset = offset * info->portwidth; + unsigned int byte_offset = offset * info->portwidth / info->chipwidth; + unsigned int addr = (info->start[sect] + byte_offset); + unsigned int mask = 0xffffffff << (info->portwidth - 1); - return (void *)(info->start[sect] + byte_offset); + return (void *)(addr & mask); } static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, @@ -398,6 +400,8 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t sect, #endif flash_write64(cword.ll, addr); break; + default: + printf("fwc: Unknown port width %d\n", info->portwidth); } /* Ensure all the instructions are fully finished */ @@ -585,7 +589,6 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, prompt, info->start[sector], flash_read_long (info, sector, 0)); flash_write_cmd (info, sector, 0, info->cmd_reset); - udelay(1); return ERR_TIMOUT; } udelay (1); /* also triggers watchdog */ @@ -753,12 +756,8 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) static flash_sect_t find_sector (flash_info_t * info, ulong addr) { static flash_sect_t saved_sector; /* previously found sector */ - static flash_info_t *saved_info; /* previously used flash bank */ flash_sect_t sector = saved_sector; - if ((info != saved_info) || (sector >= info->sector_count)) - sector = 0; - while ((info->start[sector] < addr) && (sector < info->sector_count - 1)) sector++; @@ -770,7 +769,6 @@ static flash_sect_t find_sector (flash_info_t * info, ulong addr) sector--; saved_sector = sector; - saved_info = info; return sector; } @@ -787,12 +785,15 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, /* Check if Flash is (sufficiently) erased */ switch (info->portwidth) { case FLASH_CFI_8BIT: + debug("%s: 8-bit 0x%02x\n", __func__, cword.c); flag = ((flash_read8(dstaddr) & cword.c) == cword.c); break; case FLASH_CFI_16BIT: + debug("%s: 16-bit 0x%04x\n", __func__, cword.w); flag = ((flash_read16(dstaddr) & cword.w) == cword.w); break; case FLASH_CFI_32BIT: + debug("%s: 32-bit 0x%08lx\n", __func__, cword.l); flag = ((flash_read32(dstaddr) & cword.l) == cword.l); break; case FLASH_CFI_64BIT: @@ -1053,6 +1054,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_sect_t sect; int st; + debug("%s: erasing sectors %d to %d\n", __func__, s_first, s_last); + if (info->flash_id != FLASH_MAN_CFI) { puts ("Can't erase unknown flash type - aborted\n"); return 1; @@ -1162,6 +1165,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) rcode = 1; else if (flash_verbose) putc ('.'); + } else { + debug("\nSector %d is protected.\n", + info->protect[sect]); } } @@ -1857,7 +1863,7 @@ static void flash_read_cfi (flash_info_t *info, void *buf, unsigned int i; for (i = 0; i < len; i++) - p[i] = flash_read_uchar(info, start + i); + p[i] = flash_read_uchar(info, start + (i * 2)); } static void __flash_cmd_reset(flash_info_t *info) @@ -1878,21 +1884,40 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { int cfi_offset; - /* Issue FLASH reset command */ - flash_cmd_reset(info); - for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); cfi_offset++) { + /* Issue FLASH reset command */ + flash_cmd_reset(info); flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && + flash_isequal(info, 0, + FLASH_OFFSET_CFI_RESP + 2, 'R') && + flash_isequal(info, 0, + FLASH_OFFSET_CFI_RESP + 4, 'Y')) { flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); +#ifdef CONFIG_SYS_FLASH_INTERFACE_WIDTH + info->interface = CONFIG_SYS_FLASH_INTERFACE_WIDTH; +#else info->interface = le16_to_cpu(qry->interface_desc); - + /* Some flash chips can support multiple bus widths. + * In this case, override the interface width and + * limit it to the port width. + */ + if ((info->interface == FLASH_CFI_X8X16) && + (info->portwidth == FLASH_CFI_8BIT)) { + debug("Overriding 16-bit interface" + " width to 8-bit port width.\n"); + info->interface = FLASH_CFI_X8; + } else if ((info->interface == FLASH_CFI_X16X32) && + (info->portwidth == FLASH_CFI_16BIT)) { + debug("Overriding 16-bit interface" + " width to 16-bit port width.\n"); + info->interface = FLASH_CFI_X16; + } +#endif info->cfi_offset = flash_offset_cfi[cfi_offset]; debug ("device interface is %d\n", info->interface); @@ -1903,8 +1928,8 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) info->chipwidth << CFI_FLASH_SHIFT_WIDTH); /* calculate command offsets as in the Linux driver */ - info->addr_unlock1 = 0x555; - info->addr_unlock2 = 0x2aa; + info->addr_unlock1 = 0xaaa; + info->addr_unlock2 = 0x555; /* * modify the unlock address if we are @@ -1938,8 +1963,12 @@ static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; info->chipwidth <<= 1) - if (__flash_detect_cfi(info, qry)) + if (__flash_detect_cfi(info, qry)) { + debug("Found CFI flash, portwidth %d," + " chipwidth %d\n", + info->portwidth, info->chipwidth); return 1; + } } debug ("not found\n"); return 0; @@ -1958,7 +1987,7 @@ static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) /* CFI < 1.1, try to guess from device id */ if ((info->device_id & 0x80) != 0) cfi_reverse_geometry(qry); - } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + } else if (flash_read_uchar(info, info->ext_addr + 0x1e) == 3) { /* CFI >= 1.1, deduct from top/bottom flag */ /* note: ext_addr is valid since cfi_version > 0 */ cfi_reverse_geometry(qry); @@ -2054,14 +2083,15 @@ ulong flash_get_size (phys_addr_t base, int banknum) if (flash_detect_cfi (info, &qry)) { info->vendor = le16_to_cpu(qry.p_id); - info->ext_addr = le16_to_cpu(qry.p_adr); + info->ext_addr = le16_to_cpu(qry.p_adr) * 2; + debug("extended address is 0x%x\n", info->ext_addr); num_erase_regions = qry.num_erase_regions; if (info->ext_addr) { info->cfi_version = (ushort) flash_read_uchar (info, - info->ext_addr + 3) << 8; + info->ext_addr + 6) << 8; info->cfi_version |= (ushort) flash_read_uchar (info, - info->ext_addr + 4); + info->ext_addr + 8); } #ifdef DEBUG @@ -2112,6 +2142,8 @@ ulong flash_get_size (phys_addr_t base, int banknum) debug ("device id is 0x%x\n", info->device_id); debug ("device id2 is 0x%x\n", info->device_id2); debug ("cfi version is 0x%04x\n", info->cfi_version); + debug("port width: %d, chipwidth: %d, interface: %d\n", + info->portwidth, info->chipwidth, info->interface); size_ratio = info->portwidth / info->chipwidth; /* if the chip is x8/x16 reduce the ratio by half */ diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 966b5e0..9bd76eb 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -78,29 +78,30 @@ #define FLASH_CONTINUATION_CODE 0x7F #define FLASH_OFFSET_MANUFACTURER_ID 0x00 -#define FLASH_OFFSET_DEVICE_ID 0x01 -#define FLASH_OFFSET_DEVICE_ID2 0x0E -#define FLASH_OFFSET_DEVICE_ID3 0x0F -#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_DEVICE_ID 0x02 +#define FLASH_OFFSET_DEVICE_ID2 0x1C +#define FLASH_OFFSET_DEVICE_ID3 0x1E +#define FLASH_OFFSET_CFI 0xAA + #define FLASH_OFFSET_CFI_ALT 0x555 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_CFI_RESP 0x20 +#define FLASH_OFFSET_PRIMARY_VENDOR 0x26 /* extended query table primary address */ -#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x2A #define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_WBTOUT 0x40 +#define FLASH_OFFSET_ETOUT 0x4A +#define FLASH_OFFSET_CETOUT 0x44 +#define FLASH_OFFSET_WMAX_TOUT 0x46 +#define FLASH_OFFSET_WBMAX_TOUT 0x48 +#define FLASH_OFFSET_EMAX_TOUT 0x4A +#define FLASH_OFFSET_CEMAX_TOUT 0x4C +#define FLASH_OFFSET_SIZE 0x4E +#define FLASH_OFFSET_INTERFACE 0x50 +#define FLASH_OFFSET_BUFFER_SIZE 0x54 +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x58 +#define FLASH_OFFSET_ERASE_REGIONS 0x5A +#define FLASH_OFFSET_PROTECT 0x04 #define FLASH_OFFSET_USER_PROTECTION 0x85 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 -- 1.7.4

2 1

[U-Boot] [PATCH] mtd: cfi_flash: Write buffer size adjustment for M29EW Numonyx devices
by Jagannadha Sutradharudu Teki 02 Apr '13

02 Apr '13

This patch addjusted the write buffer size for M29EW devices those are operated in 8-bit mode. The M29EW devices seem to report the CFI information wrong when it's in 8 bit mode. There's an app note from Numonyx on this issue and there's a patch in the open source as well for Linux, but it doesn't seem to be in mainline. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- drivers/mtd/cfi_flash.c | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 6b9fc1a..328c76d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2053,6 +2053,26 @@ static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) } } +static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) +{ + /* + * The M29EW devices seem to report the CFI information wrong + * when it's in 8 bit mode. + * There's an app note from Numonyx on this issue. + * So adjust the buffer size for M29EW while operating in 8-bit mode + */ + if (((qry->max_buf_write_size) > 0x8) && + (info->device_id == 0x7E) && + (info->device_id2 == 0x2201 || + info->device_id2 == 0x2301 || + info->device_id2 == 0x2801 || + info->device_id2 == 0x4801)) { + debug("Adjusted buffer size on Numonyx flash" + " M29EW family in 8 bit mode\n"); + qry->max_buf_write_size = 0x8; + } +} + /* * The following code cannot be run from FLASH! * @@ -2135,6 +2155,9 @@ ulong flash_get_size (phys_addr_t base, int banknum) case 0x00bf: /* SST */ flash_fixup_sst(info, &qry); break; + case 0x0089: /* Numonyx */ + flash_fixup_num(info, &qry); + break; } debug ("manufacturer is %d\n", info->vendor); -- 1.7.4

2 1

[U-Boot] [PATCH 1/3] arm:goni: Adjustment of configuration for goni target
by a.wlodarczyk＠samsung.com 02 Apr '13

02 Apr '13

From: Arkadiusz Wlodarczyk <a.wlodarczyk(a)samsung.com> Signed-off-by: Arkadiusz Wlodarczyk <a.wlodarczyk(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> Tested-by: Arkadiusz Wlodarczyk <a.wlodarczyk(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- Changes This change encompasses set of adjustments in the configuration of the u-boot in the include/configs/s5p_goni.h, particularly change of rootfs type, change in kernel booting method and added DFU support. All those changes are connected with adjusting of existing goni configuration to latest changes in kernel. --- board/samsung/goni/goni.c | 7 +++++++ include/configs/s5p_goni.h | 37 ++++++++++++++++++++++++++++++++----- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index ff76963..3c53106 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -155,4 +155,11 @@ struct s3c_plat_otg_data s5pc110_otg_data = { .regs_otg = S5PC110_OTG_BASE, .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL, }; + +void board_usb_init(void) +{ + debug("USB_udc_probe\n"); + s3c_udc_probe(&s5pc110_otg_data); +} + #endif diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 56e8347..8a824c7 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -86,6 +86,17 @@ #define CONFIG_CMD_ONENAND #define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" #define CONFIG_BOOTDELAY 1 #define CONFIG_ZERO_BOOTDELAY_CHECK @@ -105,9 +116,13 @@ ",60m(qboot)"\ ",-(UBI)\0" +#define CONFIG_DFU_ALT \ + "u-boot mmc 80 400;" \ + "uImage fat 0 2\0" \ + #define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT -#define CONFIG_BOOTCOMMAND "run ubifsboot" +#define CONFIG_BOOTCOMMAND "run mmcboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" @@ -137,7 +152,7 @@ "onenand erase 0x01560000 0x1eaa0000;" \ "onenand write 0x32000000 0x1260000 0x8C0000\0" \ "bootk=" \ - "onenand read 0x30007FC0 0xc00000 0x600000;" \ + "run loaduimage;" \ "bootm 0x30007FC0\0" \ "flashboot=" \ "set bootargs root=/dev/mtdblock${bootblock} " \ @@ -156,21 +171,28 @@ "set bootargs " CONFIG_RAMDISK_BOOT \ " initrd=0x33000000,8M ramdisk=8192\0" \ "mmcboot=" \ - "set bootargs root=${mmcblk} rootfstype=${rootfstype}" \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "rootfstype=${rootfstype}" \ CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ CONFIG_COMMON_BOOT "; run bootk\0" \ "boottrace=setenv opts initcall_debug; run bootcmd\0" \ "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ "verify=n\0" \ - "rootfstype=cramfs\0" \ + "rootfstype=ext4\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ "mtdparts=" MTDPARTS_DEFAULT \ "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=5\0" \ "mmcblk=/dev/mmcblk1p1\0" \ "bootblock=9\0" \ "ubiblock=8\0" \ "ubi=enabled\0" \ - "opts=always_resume=1" + "opts=always_resume=1\0" \ + "dfu_alt_info=" CONFIG_DFU_ALT + /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -211,6 +233,10 @@ #define CONFIG_DOS_PARTITION 1 +/* FAT */ +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -233,5 +259,6 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 #endif /* __CONFIG_H */ -- 1.7.1

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[U-Boot] [RFC] Bootcount improvements
by Alexandre Dilly 02 Apr '13

02 Apr '13

Hi, I'm working on an open source automatic updater for embedded systems. The goal of this project is to split a flash memory or disk in multiple partition (2 or more) and install a new root filesystem on an empty or outdated partition. After reboot, we count the boot attempts on this new version of the system and if it fails to boot, we switch back to the last working partition. This guarantees that we will eventually boot on a correct partition and that there is no chance to have an unsupervised equipment hang at the u-boot prompt. The u-boot environment would contain the name of the partition to test and the partition to fallback to. I would rewrite the u-boot environment after installing the new partition and use CONFIG_ENV_OFFSET_REDUND to make it powerfail-safe. To handle the boot attempts count, I've seen the 'bootcount' driver. However, it doesn't support all cpu and memories. I intend to improve the 'bootcount' driver by adding two features: - add eeprom and flash memories as places to load/save the bootcount value. - add an environment variable 'enable_bootcount' to enable/disable bootcount from the environment (and not at compile time) to avoid writing to flash/eeprom once the partition is known to be good and thus avoid useless memory wear. I intend to upstream these features but I would like early input/criticism/ideas. Moreover I would like to make sure this goes well into the general philosophy of U-Boot and, if it doesn't, how I can change it to have it fit. Any suggestion is welcome Best regards, Alexandre Dilly

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[U-Boot] [PATCH 0/2] Introduce Samsung's new board Trats2
by Piotr Wilczek 02 Apr '13

02 Apr '13

This patchset add support for a new Samsung board Trats2 Piotr Wilczek (2): pmic:max77686: add function to set voltage and mode samsung: trats2: add support for new board Trats2 board/samsung/trats2/Makefile | 50 ++++ board/samsung/trats2/trats2.c | 465 ++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + drivers/power/pmic/pmic_max77686.c | 186 +++++++++++++++ include/configs/trats2.h | 291 ++++++++++++++++++++++ include/power/max77686_pmic.h | 11 + 6 files changed, 1004 insertions(+) create mode 100644 board/samsung/trats2/Makefile create mode 100644 board/samsung/trats2/trats2.c create mode 100644 include/configs/trats2.h -- 1.7.9.5

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[U-Boot] Support required for loading U-boot on SDRAM
by Sadashiva Reddy 02 Apr '13

02 Apr '13

Hi Sir, I am using AMCC PPC440Gx processor for our project presently the board is working fine with vxWorks(BSP + OS + Application). But our customer new requirement is same board should be ported with linux. 1. We are using BDI2000 JTAG tool for porting u-boot and kernel. 2. We are not able to load the u-boot or u-boot.bin file directly to SDRAM location. 3. When we try to load its load to the flash loaction i.e what ever we mention in the macro CONFIG_SYS_TEXT_BASE from board.h file its loads to that location and when we give go command it throws an error called JTAG instruction overrun. 4. When we build the u-boot code the file size of u-boot.bin is always created with the macro initialized by CONFIG_SYS_TEXT_BASE from the board.h file. 5. We are able to load u-boot.bin to a flash location directly but u-boot is not coming up. So to debug the u-boot we are trying to load directly to SDRAM location. VxWorks is coming up when we load directly to SDRAM location. 6. I think the u-boot is creating a u-boot.bin file to load for flash loaction. How to create an image or bin file to load on SDRAM location directly. Best Regards, Sadashiv

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[U-Boot] [PATCH 0/4 V3] SMDK5250: FDT: Add device tree support for console
by Rajeshwari Shinde 02 Apr '13

02 Apr '13

Enabled fdt support for default console on SMDK5250. Changes in V2: - Changed the compatible string to "samsung,exynos4210-uart" Changes in V3: - Rebased the patchset on latest u-boot-samsung branch. - Added a alias console as we will support one at any point of time. - Moved driver config structure to data section. - Changed silent_console to silent-console. - Did put a check for base address before doing fdt decoding. Rajeshwari Shinde (4): EXYNOS5: FDT: Add compatible strings for Serial EXYNOS5: FDT: Add serial device node values S5P: Serial: Add fdt support to driver CONFIG: EXYNOS5: Enable silent console arch/arm/dts/exynos5250.dtsi | 27 ++++++++++ board/samsung/dts/exynos5250-smdk5250.dts | 2 + drivers/serial/serial_s5p.c | 79 +++++++++++++++++++++++++++++ include/configs/exynos5250-dt.h | 2 + include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 6 files changed, 112 insertions(+), 0 deletions(-) -- 1.7.4.4

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[U-Boot] [PATCH 0/3 V4] EXYNOS5: Add GPIO numbering feature
by Rajeshwari Shinde 02 Apr '13

02 Apr '13

Changes in V2: - Enabled CMD_GPIO as suggested by Simon Glass and supported same for EXYNOS5 Changes in V3: - New patch added to rename S5P GPIO definitions to S5P_GPIO - GPIO Table added to calculate the base address of input gpio bank. Changes in V4: - To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. - Function and table to support gpio command moved to s5p-gpio driver - Rebased on latest u-boot-samsung tree Rajeshwari Shinde (3): EXYNOS5: Add gpio pin numbering feature S5P: Rename GPIO definitions EXYNOS5: GPIO: Enable GPIO Command for EXYNOS5 arch/arm/cpu/armv7/exynos/pinmux.c | 206 +++++++--------- arch/arm/include/asm/arch-exynos/cpu.h | 10 +- arch/arm/include/asm/arch-exynos/gpio.h | 410 ++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 26 +- board/samsung/goni/goni.c | 4 +- board/samsung/origen/origen.c | 8 +- board/samsung/smdk5250/smdk5250.c | 24 +-- board/samsung/smdkc100/smdkc100.c | 2 +- board/samsung/smdkv310/smdkv310.c | 10 +- board/samsung/trats/trats.c | 16 +- board/samsung/universal_c210/universal.c | 36 ++-- drivers/gpio/s5p_gpio.c | 134 +++++++++- include/configs/exynos5250-dt.h | 1 + 13 files changed, 669 insertions(+), 218 deletions(-) -- 1.7.4.4

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