March 2013 - U-Boot

[U-Boot] [PATCH] video: bcm2835: fix build issues
by Anatolij Gustschin 02 Apr '13

02 Apr '13

After merging LCD patches for v2013.04 the bcm2835 video driver building is broken due to removal of many global variables. Fix the driver. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Stephen Warren <swarren(a)wwwdotorg.org> --- common/lcd.c | 12 ++++++++++++ drivers/video/bcm2835.c | 11 ----------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index b98eea6..b81be31 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -493,6 +493,18 @@ static int lcd_init(void *lcdbase) debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); lcd_ctrl_init(lcdbase); + + /* + * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores + * the 'lcdbase' argument and uses custom lcd base address + * by setting up gd->fb_base. Check for this condition and fixup + * 'lcd_base' address. + */ + if ((unsigned long)lcdbase != gd->fb_base) + lcd_base = (void *)gd->fb_base; + + debug("[LCD] Using LCD frambuffer at %p\n", lcd_base); + lcd_get_size(&lcd_line_length); lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; lcd_is_enabled = 1; diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 1e9a84a..0c77d17 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -23,17 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Global variables that lcd.c expects to exist */ -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; -void *lcd_base; -void *lcd_console_address; -short console_col; -short console_row; vidinfo_t panel_info; -char lcd_cursor_enabled; -ushort lcd_cursor_width; -ushort lcd_cursor_height; struct msg_query { struct bcm2835_mbox_hdr hdr; @@ -119,7 +109,6 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; gd->fb_base = msg_setup->allocate_buffer.body.resp.fb_address; - lcd_base = (void *)gd->fb_base; } void lcd_enable(void) -- 1.7.5.4

2 3

[U-Boot] [PATCH] Add initial support for mx6slevk board
by Fabio Estevam 02 Apr '13

02 Apr '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> mx6slevk board is a development board from Freescale based on the mx6 solo lite processor. For details about mx6slevk, please refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&pa… Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- MAINTAINERS | 1 + arch/arm/cpu/armv7/mx6/clock.c | 38 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h | 63 +- arch/arm/include/asm/arch-mx6/mx6-pins.h | 4 + arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 1374 ++++++++++++++++++++++++++++ board/freescale/mx6slevk/Makefile | 28 + board/freescale/mx6slevk/imximage.cfg | 118 +++ board/freescale/mx6slevk/mx6slevk.c | 102 +++ boards.cfg | 1 + include/configs/mx6slevk.h | 189 ++++ 11 files changed, 1916 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/mx6sl_pins.h create mode 100644 board/freescale/mx6slevk/Makefile create mode 100644 board/freescale/mx6slevk/imximage.cfg create mode 100644 board/freescale/mx6slevk/mx6slevk.c create mode 100644 include/configs/mx6slevk.h diff --git a/MAINTAINERS b/MAINTAINERS index 0f19078..723a316 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -665,6 +665,7 @@ Fabio Estevam <fabio.estevam(a)freescale.com> mx6qsabresd i.MX6Q mx6qsabreauto i.MX6Q wandboard i.MX6DL/S + mx6slevk i.MX6SL Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index a50db70..8cba4fd 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -186,12 +186,16 @@ static u32 get_ipg_per_clk(void) static u32 get_uart_clk(void) { u32 reg, uart_podf; - + u32 freq = PLL3_80M; reg = __raw_readl(&imx_ccm->cscdr1); +#ifdef CONFIG_MX6SL + if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) + freq = MXC_HCLK; +#endif reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; - return PLL3_80M / (uart_podf + 1); + return freq / (uart_podf + 1); } static u32 get_cspi_clk(void) @@ -252,6 +256,35 @@ static u32 get_emi_slow_clk(void) return root_freq / (emi_slow_pof + 1); } +#ifdef CONFIG_MX6SL +static u32 get_mmdc_ch0_clk(void) +{ + u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); + u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); + u32 freq, podf; + + podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \ + >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; + + switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) { + case 0: + freq = decode_pll(PLL_BUS, MXC_HCLK); + break; + case 1: + freq = PLL2_PFD2_FREQ; + break; + case 2: + freq = PLL2_PFD0_FREQ; + break; + case 3: + freq = PLL2_PFD2_DIV_FREQ; + } + + return freq / (podf + 1); + +} +#else static u32 get_mmdc_ch0_clk(void) { u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); @@ -260,6 +293,7 @@ static u32 get_mmdc_ch0_clk(void) return get_periph_clk() / (mmdc_ch0_podf + 1); } +#endif static u32 get_usdhc_clk(u32 port) { diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 7676457..ede384d 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -246,6 +246,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Define the bits in register CS1CDR */ #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index eaa7439..2d8fe69 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -25,6 +25,13 @@ #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF + +#ifdef CONFIG_MX6SL +#define GPU_2D_ARB_BASE_ADDR 0x02200000 +#define GPU_2D_ARB_END_ADDR 0x02203FFF +#define OPENVG_ARB_BASE_ADDR 0x02204000 +#define OPENVG_ARB_END_ADDR 0x02207FFF +#else #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00103FFF #define APBH_DMA_ARB_BASE_ADDR 0x00110000 @@ -37,9 +44,14 @@ #define GPU_2D_ARB_END_ADDR 0x00137FFF #define DTCP_ARB_BASE_ADDR 0x00138000 #define DTCP_ARB_END_ADDR 0x0013BFFF - +#endif /* CONFIG_MX6SL */ /* GPV - PL301 configuration ports */ +#ifdef CONFIG_MX6SL +#define GPV2_BASE_ADDR 0x00D00000 +#else #define GPV2_BASE_ADDR 0x00200000 +#endif + #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 #define IRAM_BASE_ADDR 0x00900000 @@ -70,10 +82,17 @@ #define WEIM_ARB_BASE_ADDR 0x08000000 #define WEIM_ARB_END_ADDR 0x0FFFFFFF +#ifdef CONFIG_MX6SL +#define MMDC0_ARB_BASE_ADDR 0x80000000 +#define MMDC0_ARB_END_ADDR 0xFFFFFFFF +#define MMDC1_ARB_BASE_ADDR 0xC0000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#else #define MMDC0_ARB_BASE_ADDR 0x10000000 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF #define MMDC1_ARB_BASE_ADDR 0x80000000 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#endif #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 @@ -89,6 +108,16 @@ #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) +#ifdef CONFIG_MX6SL +#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) +#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) +#else #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) @@ -96,6 +125,8 @@ #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#endif + #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) @@ -128,18 +159,35 @@ #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) +#ifdef CONFIG_MX6SL +#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#endif #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#ifdef CONFIG_MX6SL +#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) +#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) +#else #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) +#endif + #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) +#ifdef CONFIG_MX6SL +#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#else #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#endif + #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) @@ -149,7 +197,12 @@ #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) +#ifdef CONFIG_MX6SL +#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#else #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#endif + #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) @@ -364,12 +417,20 @@ struct cspi_regs { #define MXC_CSPICON_POL 4 #define MXC_CSPICON_PHA 0 #define MXC_CSPICON_SSPOL 12 +#ifdef CONFIG_MX6SL +#define MXC_SPI_BASE_ADDRESSES \ + ECSPI1_BASE_ADDR, \ + ECSPI2_BASE_ADDR, \ + ECSPI3_BASE_ADDR, \ + ECSPI4_BASE_ADDR +#else #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ ECSPI3_BASE_ADDR, \ ECSPI4_BASE_ADDR, \ ECSPI5_BASE_ADDR +#endif struct iim_regs { u32 ctrl; diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index 63f4856..ce865a6 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -24,7 +24,11 @@ #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #include "mx6dl_pins.h" #else +#if defined(CONFIG_MX6SL) +#include "mx6sl_pins.h" +#else #error "Please select cpu" +#endif /* CONFIG_MX6SL */ #endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h new file mode 100644 index 0000000..cd974d8 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -0,0 +1,1374 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__ +#define __ASM_ARCH_MX6_MX6SL_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +/* Use to set PAD control */ +#define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_PUS_100K_DOWN (0 << 14) +#define PAD_CTL_PUS_47K_UP (1 << 14) +#define PAD_CTL_PUS_100K_UP (2 << 14) +#define PAD_CTL_PUS_22K_UP (3 << 14) + +#define PAD_CTL_PUE (1 << 13) +#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_ODE (1 << 11) +#define PAD_CTL_SPEED_LOW (1 << 6) +#define PAD_CTL_SPEED_MED (2 << 6) +#define PAD_CTL_SPEED_HIGH (3 << 6) +#define PAD_CTL_DSE_DISABLE (0 << 3) +#define PAD_CTL_DSE_240ohm (1 << 3) +#define PAD_CTL_DSE_120ohm (2 << 3) +#define PAD_CTL_DSE_80ohm (3 << 3) +#define PAD_CTL_DSE_60ohm (4 << 3) +#define PAD_CTL_DSE_48ohm (5 << 3) +#define PAD_CTL_DSE_40ohm (6 << 3) +#define PAD_CTL_DSE_34ohm (7 << 3) +#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) + +#define IOMUX_CONFIG_SION 0x10 +#define NO_MUX_I 0 +#define NO_PAD_I 0 +enum { + MX6_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT = IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__PWM4_PWMO = IOMUX_PAD(0x02A4, 0x004C, 1, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__ECSPI3_RDY = IOMUX_PAD(0x02A4, 0x004C, 2, 0x06B4, 0, 0), + MX6_PAD_AUD_MCLK__FEC_MDC = IOMUX_PAD(0x02A4, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x02A4, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__GPIO_1_6 = IOMUX_PAD(0x02A4, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_AUD_MCLK__SPDIF_SPDIF_EXT_CLK = IOMUX_PAD(0x02A4, 0x004C, 6, 0x07F4, 0, 0), + MX6_PAD_AUD_MCLK__TPSMP_HDATA_27 = IOMUX_PAD(0x02A4, 0x004C, 7, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__AUDMUX_AUD3_RXC = IOMUX_PAD(0x02A8, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__I2C1_SDA = IOMUX_PAD(0x02A8, 0x0050, 17, 0x0720, 0, 0), + MX6_PAD_AUD_RXC__UART3_TXD = IOMUX_PAD(0x02A8, 0x0050, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__UART3_RXD = IOMUX_PAD(0x02A8, 0x0050, 2, 0x080C, 0, 0), + MX6_PAD_AUD_RXC__FEC_TX_CLK = IOMUX_PAD(0x02A8, 0x0050, 3, 0x070C, 0, 0), + MX6_PAD_AUD_RXC__I2C3_SDA = IOMUX_PAD(0x02A8, 0x0050, 20, 0x0730, 0, 0), + MX6_PAD_AUD_RXC__GPIO_1_1 = IOMUX_PAD(0x02A8, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXC__ECSPI3_SS1 = IOMUX_PAD(0x02A8, 0x0050, 6, 0x06C4, 0, 0), + MX6_PAD_AUD_RXC__PL301_SIM_MX6_PER1_HREADYOUT = IOMUX_PAD(0x02A8, 0x0050, 7, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__AUDMUX_AUD3_RXD = IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__ECSPI3_MOSI = IOMUX_PAD(0x02AC, 0x0054, 1, 0x06BC, 0, 0), + MX6_PAD_AUD_RXD__UART4_TXD = IOMUX_PAD(0x02AC, 0x0054, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__UART4_RXD = IOMUX_PAD(0x02AC, 0x0054, 2, 0x0814, 0, 0), + MX6_PAD_AUD_RXD__FEC_RX_ER = IOMUX_PAD(0x02AC, 0x0054, 3, 0x0708, 0, 0), + MX6_PAD_AUD_RXD__USDHC1_LCTL = IOMUX_PAD(0x02AC, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__GPIO_1_2 = IOMUX_PAD(0x02AC, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__SRC_INT_BOOT = IOMUX_PAD(0x02AC, 0x0054, 6, 0x0000, 0, 0), + MX6_PAD_AUD_RXD__PL301_SIM_MX6_PER1_HRESP = IOMUX_PAD(0x02AC, 0x0054, 7, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x02B0, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__I2C1_SCL = IOMUX_PAD(0x02B0, 0x0058, 17, 0x071C, 0, 0), + MX6_PAD_AUD_RXFS__UART3_TXD = IOMUX_PAD(0x02B0, 0x0058, 2, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__UART3_RXD = IOMUX_PAD(0x02B0, 0x0058, 2, 0x080C, 1, 0), + MX6_PAD_AUD_RXFS__FEC_MDIO = IOMUX_PAD(0x02B0, 0x0058, 3, 0x06F4, 0, 0), + MX6_PAD_AUD_RXFS__I2C3_SCL = IOMUX_PAD(0x02B0, 0x0058, 20, 0x072C, 0, 0), + MX6_PAD_AUD_RXFS__GPIO_1_0 = IOMUX_PAD(0x02B0, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_AUD_RXFS__ECSPI3_SS0 = IOMUX_PAD(0x02B0, 0x0058, 6, 0x06C0, 0, 0), + MX6_PAD_AUD_RXFS__PL301_SIM_MX6_PER1_HPROT_1 = IOMUX_PAD(0x02B0, 0x0058, 7, 0x07EC, 0, 0), + MX6_PAD_AUD_TXC__AUDMUX_AUD3_TXC = IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__ECSPI3_MISO = IOMUX_PAD(0x02B4, 0x005C, 1, 0x06B8, 0, 0), + MX6_PAD_AUD_TXC__UART4_TXD = IOMUX_PAD(0x02B4, 0x005C, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__UART4_RXD = IOMUX_PAD(0x02B4, 0x005C, 2, 0x0814, 1, 0), + MX6_PAD_AUD_TXC__FEC_RX_DV = IOMUX_PAD(0x02B4, 0x005C, 3, 0x0704, 0, 0), + MX6_PAD_AUD_TXC__USDHC2_LCTL = IOMUX_PAD(0x02B4, 0x005C, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__GPIO_1_3 = IOMUX_PAD(0x02B4, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__SRC_SYSTEM_RST = IOMUX_PAD(0x02B4, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_AUD_TXC__TPSMP_HDATA_24 = IOMUX_PAD(0x02B4, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__AUDMUX_AUD3_TXD = IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__ECSPI3_SCLK = IOMUX_PAD(0x02B8, 0x0060, 1, 0x06B0, 0, 0), + MX6_PAD_AUD_TXD__UART4_CTS = IOMUX_PAD(0x02B8, 0x0060, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__UART4_RTS = IOMUX_PAD(0x02B8, 0x0060, 2, 0x0810, 0, 0), + MX6_PAD_AUD_TXD__FEC_TDATA_0 = IOMUX_PAD(0x02B8, 0x0060, 3, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__USDHC4_LCTL = IOMUX_PAD(0x02B8, 0x0060, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__GPIO_1_5 = IOMUX_PAD(0x02B8, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__ANATOP_ANATOP_TESTI_1 = IOMUX_PAD(0x02B8, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_AUD_TXD__TPSMP_HDATA_26 = IOMUX_PAD(0x02B8, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__PWM3_PWMO = IOMUX_PAD(0x02BC, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__UART4_CTS = IOMUX_PAD(0x02BC, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__UART4_RTS = IOMUX_PAD(0x02BC, 0x0064, 2, 0x0810, 1, 0), + MX6_PAD_AUD_TXFS__FEC_RDATA_1 = IOMUX_PAD(0x02BC, 0x0064, 3, 0x06FC, 0, 0), + MX6_PAD_AUD_TXFS__USDHC3_LCTL = IOMUX_PAD(0x02BC, 0x0064, 4, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__GPIO_1_4 = IOMUX_PAD(0x02BC, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__ANATOP_ANATOP_TESTI_0 = IOMUX_PAD(0x02BC, 0x0064, 6, 0x0000, 0, 0), + MX6_PAD_AUD_TXFS__TPSMP_HDATA_25 = IOMUX_PAD(0x02BC, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x02C0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x02C4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x02C8, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x02CC, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x02D0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x02D4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x02D8, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x02DC, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x02E0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x02E4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x02E8, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x02EC, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x02F0, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x02F4, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x02F8, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x02FC, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x0300, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0304, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0308, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x030C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x0310, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0314, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0318, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x031C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x0320, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0324, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0328, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x032C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0330, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0334, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0338, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x033C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x0340, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x0344, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x0348, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x034C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x0350, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x0354, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0), + MX6_PAD_ECSPI1_MISO__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0358, 0x0068, 1, 0x05F8, 0, 0), + MX6_PAD_ECSPI1_MISO__UART5_CTS = IOMUX_PAD(0x0358, 0x0068, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__UART5_RTS = IOMUX_PAD(0x0358, 0x0068, 2, 0x0818, 0, 0), + MX6_PAD_ECSPI1_MISO__EPDC_BDR_0 = IOMUX_PAD(0x0358, 0x0068, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__USDHC2_WP = IOMUX_PAD(0x0358, 0x0068, 4, 0x0834, 0, 0), + MX6_PAD_ECSPI1_MISO__GPIO_4_10 = IOMUX_PAD(0x0358, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__CCM_PLL3_BYP = IOMUX_PAD(0x0358, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MISO__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x0358, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0), + MX6_PAD_ECSPI1_MOSI__AUDMUX_AUD4_TXC = IOMUX_PAD(0x035C, 0x006C, 1, 0x05F4, 0, 0), + MX6_PAD_ECSPI1_MOSI__UART5_TXD = IOMUX_PAD(0x035C, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__UART5_RXD = IOMUX_PAD(0x035C, 0x006C, 2, 0x081C, 0, 0), + MX6_PAD_ECSPI1_MOSI__EPDC_VCOM_1 = IOMUX_PAD(0x035C, 0x006C, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__GPIO_4_9 = IOMUX_PAD(0x035C, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__CCM_PLL2_BYP = IOMUX_PAD(0x035C, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_ECSPI1_MOSI__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x035C, 0x006C, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0), + MX6_PAD_ECSPI1_SCLK__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0360, 0x0070, 1, 0x05E8, 0, 0), + MX6_PAD_ECSPI1_SCLK__UART5_TXD = IOMUX_PAD(0x0360, 0x0070, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__UART5_RXD = IOMUX_PAD(0x0360, 0x0070, 2, 0x081C, 1, 0), + MX6_PAD_ECSPI1_SCLK__EPDC_VCOM_0 = IOMUX_PAD(0x0360, 0x0070, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__USDHC2_RST = IOMUX_PAD(0x0360, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__GPIO_4_8 = IOMUX_PAD(0x0360, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SCLK__USB_USBOTG2_OC = IOMUX_PAD(0x0360, 0x0070, 6, 0x0820, 0, 0), + MX6_PAD_ECSPI1_SCLK__TPSMP_HDATA_18 = IOMUX_PAD(0x0360, 0x0070, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0364, 0x0074, 0, 0x068C, 0, 0), + MX6_PAD_ECSPI1_SS0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0364, 0x0074, 1, 0x05E4, 0, 0), + MX6_PAD_ECSPI1_SS0__UART5_CTS = IOMUX_PAD(0x0364, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__UART5_RTS = IOMUX_PAD(0x0364, 0x0074, 2, 0x0818, 1, 0), + MX6_PAD_ECSPI1_SS0__EPDC_BDR_1 = IOMUX_PAD(0x0364, 0x0074, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__USDHC2_CD = IOMUX_PAD(0x0364, 0x0074, 4, 0x0830, 0, 0), + MX6_PAD_ECSPI1_SS0__GPIO_4_11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__USB_USBOTG2_PWR = IOMUX_PAD(0x0364, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_ECSPI1_SS0__PL301_SIM_MX6_PER1_HADDR_23 = IOMUX_PAD(0x0364, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__GPIO_4_14 = IOMUX_PAD(0x0368, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__USB_USBOTG1_OC = IOMUX_PAD(0x0368, 0x0078, 6, 0x0824, 0, 0), + MX6_PAD_ECSPI2_MISO__TPSMP_HDATA_23 = IOMUX_PAD(0x0368, 0x0078, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0368, 0x0078, 0, 0x06A0, 0, 0), + MX6_PAD_ECSPI2_MISO__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x0368, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__UART3_CTS = IOMUX_PAD(0x0368, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__UART3_RTS = IOMUX_PAD(0x0368, 0x0078, 2, 0x0808, 0, 0), + MX6_PAD_ECSPI2_MISO__CSI_MCLK = IOMUX_PAD(0x0368, 0x0078, 3, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MISO__USDHC1_WP = IOMUX_PAD(0x0368, 0x0078, 4, 0x082C, 0, 0), + MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x036C, 0x007C, 0, 0x06A4, 0, 0), + MX6_PAD_ECSPI2_MOSI__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x036C, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__UART3_TXD = IOMUX_PAD(0x036C, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__UART3_RXD = IOMUX_PAD(0x036C, 0x007C, 2, 0x080C, 2, 0), + MX6_PAD_ECSPI2_MOSI__CSI_HSYNC = IOMUX_PAD(0x036C, 0x007C, 3, 0x0670, 0, 0), + MX6_PAD_ECSPI2_MOSI__USDHC1_VSELECT = IOMUX_PAD(0x036C, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__GPIO_4_13 = IOMUX_PAD(0x036C, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__ANATOP_ANATOP_TESTO_1 = IOMUX_PAD(0x036C, 0x007C, 6, 0x0000, 0, 0), + MX6_PAD_ECSPI2_MOSI__TPSMP_HDATA_22 = IOMUX_PAD(0x036C, 0x007C, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0370, 0x0080, 0, 0x069C, 0, 0), + MX6_PAD_ECSPI2_SCLK__SPDIF_SPDIF_EXT_CLK = IOMUX_PAD(0x0370, 0x0080, 1, 0x07F4, 1, 0), + MX6_PAD_ECSPI2_SCLK__UART3_TXD = IOMUX_PAD(0x0370, 0x0080, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__UART3_RXD = IOMUX_PAD(0x0370, 0x0080, 2, 0x080C, 3, 0), + MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK = IOMUX_PAD(0x0370, 0x0080, 3, 0x0674, 0, 0), + MX6_PAD_ECSPI2_SCLK__USDHC1_RST = IOMUX_PAD(0x0370, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__GPIO_4_12 = IOMUX_PAD(0x0370, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SCLK__USB_USBOTG2_OC = IOMUX_PAD(0x0370, 0x0080, 6, 0x0820, 1, 0), + MX6_PAD_ECSPI2_SCLK__TPSMP_HDATA_21 = IOMUX_PAD(0x0370, 0x0080, 7, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0374, 0x0084, 0, 0x06A8, 0, 0), + MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 = IOMUX_PAD(0x0374, 0x0084, 1, 0x0698, 0, 0), + MX6_PAD_ECSPI2_SS0__UART3_CTS = IOMUX_PAD(0x0374, 0x0084, 2, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__UART3_RTS = IOMUX_PAD(0x0374, 0x0084, 2, 0x0808, 1, 0), + MX6_PAD_ECSPI2_SS0__CSI_VSYNC = IOMUX_PAD(0x0374, 0x0084, 3, 0x0678, 0, 0), + MX6_PAD_ECSPI2_SS0__USDHC1_CD = IOMUX_PAD(0x0374, 0x0084, 4, 0x0828, 0, 0), + MX6_PAD_ECSPI2_SS0__GPIO_4_15 = IOMUX_PAD(0x0374, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__USB_USBOTG1_PWR = IOMUX_PAD(0x0374, 0x0084, 6, 0x0000, 0, 0), + MX6_PAD_ECSPI2_SS0__PL301_SIM_MX6_PER1_HADDR_24 = IOMUX_PAD(0x0374, 0x0084, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__EPDC_BDR_0 = IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__USDHC4_CLK = IOMUX_PAD(0x0378, 0x0088, 1, 0x0850, 0, 0), + MX6_PAD_EPDC_BDR0__UART3_CTS = IOMUX_PAD(0x0378, 0x0088, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__UART3_RTS = IOMUX_PAD(0x0378, 0x0088, 2, 0x0808, 2, 0), + MX6_PAD_EPDC_BDR0__WEIM_WEIM_A_26 = IOMUX_PAD(0x0378, 0x0088, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__TCON_RL = IOMUX_PAD(0x0378, 0x0088, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__GPIO_2_5 = IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__EPDC_SDCE_7 = IOMUX_PAD(0x0378, 0x0088, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0378, 0x0088, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__EPDC_BDR_1 = IOMUX_PAD(0x037C, 0x008C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__USDHC4_CMD = IOMUX_PAD(0x037C, 0x008C, 1, 0x0858, 0, 0), + MX6_PAD_EPDC_BDR1__UART3_CTS = IOMUX_PAD(0x037C, 0x008C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__UART3_RTS = IOMUX_PAD(0x037C, 0x008C, 2, 0x0808, 3, 0), + MX6_PAD_EPDC_BDR1__WEIM_WEIM_CRE = IOMUX_PAD(0x037C, 0x008C, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__TCON_UD = IOMUX_PAD(0x037C, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__GPIO_2_6 = IOMUX_PAD(0x037C, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__EPDC_SDCE_8 = IOMUX_PAD(0x037C, 0x008C, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR1__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x037C, 0x008C, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__EPDC_SDDO_0 = IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__ECSPI4_MOSI = IOMUX_PAD(0x0380, 0x0090, 1, 0x06D8, 0, 0), + MX6_PAD_EPDC_D0__LCDIF_DAT_24 = IOMUX_PAD(0x0380, 0x0090, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__CSI_D_0 = IOMUX_PAD(0x0380, 0x0090, 3, 0x0630, 0, 0), + MX6_PAD_EPDC_D0__TCON_E_DATA_0 = IOMUX_PAD(0x0380, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__GPIO_1_7 = IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__ANATOP_USBPHY1_TSTI_TX_HS_MODE = IOMUX_PAD(0x0380, 0x0090, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__OBSERVE_MUX_OUT_0 = IOMUX_PAD(0x0380, 0x0090, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__EPDC_SDDO_1 = IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__ECSPI4_MISO = IOMUX_PAD(0x0384, 0x0094, 1, 0x06D4, 0, 0), + MX6_PAD_EPDC_D1__LCDIF_DAT_25 = IOMUX_PAD(0x0384, 0x0094, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__CSI_D_1 = IOMUX_PAD(0x0384, 0x0094, 3, 0x0634, 0, 0), + MX6_PAD_EPDC_D1__TCON_E_DATA_1 = IOMUX_PAD(0x0384, 0x0094, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__GPIO_1_8 = IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__ANATOP_USBPHY1_TSTI_TX_LS_MODE = IOMUX_PAD(0x0384, 0x0094, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__OBSERVE_MUX_OUT_1 = IOMUX_PAD(0x0384, 0x0094, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D10__EPDC_SDDO_10 = IOMUX_PAD(0x0388, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D10__ECSPI3_SS0 = IOMUX_PAD(0x0388, 0x0098, 1, 0x06C0, 1, 0), + MX6_PAD_EPDC_D10__EPDC_PWRCTRL_2 = IOMUX_PAD(0x0388, 0x0098, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D10__WEIM_WEIM_A_18 = IOMUX_PAD(0x0388, 0x0098, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D10__TCON_E_DATA_10 = IOMUX_PAD(0x0388, 0x0098, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D10__GPIO_1_17 = IOMUX_PAD(0x0388, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D10__USDHC4_WP = IOMUX_PAD(0x0388, 0x0098, 6, 0x087C, 0, 0), + MX6_PAD_EPDC_D10__MMDC_MMDC_DEBUG_29 = IOMUX_PAD(0x0388, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D11__EPDC_SDDO_11 = IOMUX_PAD(0x038C, 0x009C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D11__ECSPI3_SCLK = IOMUX_PAD(0x038C, 0x009C, 1, 0x06B0, 1, 0), + MX6_PAD_EPDC_D11__EPDC_PWRCTRL_3 = IOMUX_PAD(0x038C, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D11__WEIM_WEIM_A_19 = IOMUX_PAD(0x038C, 0x009C, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D11__TCON_E_DATA_11 = IOMUX_PAD(0x038C, 0x009C, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D11__GPIO_1_18 = IOMUX_PAD(0x038C, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D11__USDHC4_CD = IOMUX_PAD(0x038C, 0x009C, 6, 0x0854, 0, 0), + MX6_PAD_EPDC_D11__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x038C, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__EPDC_SDDO_12 = IOMUX_PAD(0x0390, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__UART2_TXD = IOMUX_PAD(0x0390, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__UART2_RXD = IOMUX_PAD(0x0390, 0x00A0, 1, 0x0804, 0, 0), + MX6_PAD_EPDC_D12__EPDC_PWRCOM = IOMUX_PAD(0x0390, 0x00A0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__WEIM_WEIM_A_20 = IOMUX_PAD(0x0390, 0x00A0, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__TCON_E_DATA_12 = IOMUX_PAD(0x0390, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__GPIO_1_19 = IOMUX_PAD(0x0390, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D12__ECSPI3_SS1 = IOMUX_PAD(0x0390, 0x00A0, 6, 0x06C4, 1, 0), + MX6_PAD_EPDC_D12__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0390, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D13__EPDC_SDDO_13 = IOMUX_PAD(0x0394, 0x00A4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D13__UART2_TXD = IOMUX_PAD(0x0394, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_D13__UART2_RXD = IOMUX_PAD(0x0394, 0x00A4, 1, 0x0804, 1, 0), + MX6_PAD_EPDC_D13__EPDC_PWRIRQ = IOMUX_PAD(0x0394, 0x00A4, 2, 0x06E8, 0, 0), + MX6_PAD_EPDC_D13__WEIM_WEIM_A_21 = IOMUX_PAD(0x0394, 0x00A4, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D13__TCON_E_DATA_13 = IOMUX_PAD(0x0394, 0x00A4, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D13__GPIO_1_20 = IOMUX_PAD(0x0394, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D13__ECSPI3_SS2 = IOMUX_PAD(0x0394, 0x00A4, 6, 0x06C8, 0, 0), + MX6_PAD_EPDC_D13__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x0394, 0x00A4, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D14__EPDC_SDDO_14 = IOMUX_PAD(0x0398, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D14__UART2_CTS = IOMUX_PAD(0x0398, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_D14__UART2_RTS = IOMUX_PAD(0x0398, 0x00A8, 1, 0x0800, 0, 0), + MX6_PAD_EPDC_D14__EPDC_PWRSTAT = IOMUX_PAD(0x0398, 0x00A8, 2, 0x06EC, 0, 0), + MX6_PAD_EPDC_D14__WEIM_WEIM_A_22 = IOMUX_PAD(0x0398, 0x00A8, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D14__TCON_E_DATA_14 = IOMUX_PAD(0x0398, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D14__GPIO_1_21 = IOMUX_PAD(0x0398, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D14__ECSPI3_SS3 = IOMUX_PAD(0x0398, 0x00A8, 6, 0x06CC, 0, 0), + MX6_PAD_EPDC_D14__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x0398, 0x00A8, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__EPDC_SDDO_15 = IOMUX_PAD(0x039C, 0x00AC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__UART2_CTS = IOMUX_PAD(0x039C, 0x00AC, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__UART2_RTS = IOMUX_PAD(0x039C, 0x00AC, 1, 0x0800, 1, 0), + MX6_PAD_EPDC_D15__EPDC_PWRWAKE = IOMUX_PAD(0x039C, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__WEIM_WEIM_A_23 = IOMUX_PAD(0x039C, 0x00AC, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__TCON_E_DATA_15 = IOMUX_PAD(0x039C, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__GPIO_1_22 = IOMUX_PAD(0x039C, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D15__ECSPI3_RDY = IOMUX_PAD(0x039C, 0x00AC, 6, 0x06B4, 1, 0), + MX6_PAD_EPDC_D15__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x039C, 0x00AC, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__EPDC_SDDO_2 = IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__ECSPI4_SS0 = IOMUX_PAD(0x03A0, 0x00B0, 1, 0x06DC, 0, 0), + MX6_PAD_EPDC_D2__LCDIF_DAT_26 = IOMUX_PAD(0x03A0, 0x00B0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__CSI_D_2 = IOMUX_PAD(0x03A0, 0x00B0, 3, 0x0638, 0, 0), + MX6_PAD_EPDC_D2__TCON_E_DATA_2 = IOMUX_PAD(0x03A0, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__GPIO_1_9 = IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__ANATOP_USBPHY1_TSTI_TX_DN = IOMUX_PAD(0x03A0, 0x00B0, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__TPSMP_HDATA_28 = IOMUX_PAD(0x03A0, 0x00B0, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__EPDC_SDDO_3 = IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__ECSPI4_SCLK = IOMUX_PAD(0x03A4, 0x00B4, 1, 0x06D0, 0, 0), + MX6_PAD_EPDC_D3__LCDIF_DAT_27 = IOMUX_PAD(0x03A4, 0x00B4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__CSI_D_3 = IOMUX_PAD(0x03A4, 0x00B4, 3, 0x063C, 0, 0), + MX6_PAD_EPDC_D3__TCON_E_DATA_3 = IOMUX_PAD(0x03A4, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__GPIO_1_10 = IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__ANATOP_USBPHY1_TSTI_TX_DP = IOMUX_PAD(0x03A4, 0x00B4, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__TPSMP_HDATA_29 = IOMUX_PAD(0x03A4, 0x00B4, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__EPDC_SDDO_4 = IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__ECSPI4_SS1 = IOMUX_PAD(0x03A8, 0x00B8, 1, 0x06E0, 0, 0), + MX6_PAD_EPDC_D4__LCDIF_DAT_28 = IOMUX_PAD(0x03A8, 0x00B8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__CSI_D_4 = IOMUX_PAD(0x03A8, 0x00B8, 3, 0x0640, 0, 0), + MX6_PAD_EPDC_D4__TCON_E_DATA_4 = IOMUX_PAD(0x03A8, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__GPIO_1_11 = IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__ANATOP_USBPHY1_TSTI_TX_EN = IOMUX_PAD(0x03A8, 0x00B8, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__TPSMP_HDATA_30 = IOMUX_PAD(0x03A8, 0x00B8, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__EPDC_SDDO_5 = IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__ECSPI4_SS2 = IOMUX_PAD(0x03AC, 0x00BC, 1, 0x06E4, 0, 0), + MX6_PAD_EPDC_D5__LCDIF_DAT_29 = IOMUX_PAD(0x03AC, 0x00BC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__CSI_D_5 = IOMUX_PAD(0x03AC, 0x00BC, 3, 0x0644, 0, 0), + MX6_PAD_EPDC_D5__TCON_E_DATA_5 = IOMUX_PAD(0x03AC, 0x00BC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__GPIO_1_12 = IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__ANATOP_USBPHY1_TSTI_TX_HIZ = IOMUX_PAD(0x03AC, 0x00BC, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__TPSMP_HDATA_31 = IOMUX_PAD(0x03AC, 0x00BC, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__EPDC_SDDO_6 = IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__ECSPI4_SS3 = IOMUX_PAD(0x03B0, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__LCDIF_DAT_30 = IOMUX_PAD(0x03B0, 0x00C0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__CSI_D_6 = IOMUX_PAD(0x03B0, 0x00C0, 3, 0x0648, 0, 0), + MX6_PAD_EPDC_D6__TCON_E_DATA_6 = IOMUX_PAD(0x03B0, 0x00C0, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__GPIO_1_13 = IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x03B0, 0x00C0, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__TPSMP_HDATA_20 = IOMUX_PAD(0x03B0, 0x00C0, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__EPDC_SDDO_7 = IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__ECSPI4_RDY = IOMUX_PAD(0x03B4, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__LCDIF_DAT_31 = IOMUX_PAD(0x03B4, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__CSI_D_7 = IOMUX_PAD(0x03B4, 0x00C4, 3, 0x064C, 0, 0), + MX6_PAD_EPDC_D7__TCON_E_DATA_7 = IOMUX_PAD(0x03B4, 0x00C4, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__GPIO_1_14 = IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__ANATOP_USBPHY2_TSTO_RX_FS_RXD = IOMUX_PAD(0x03B4, 0x00C4, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__MMDC_MMDC_DEBUG_32 = IOMUX_PAD(0x03B4, 0x00C4, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__EPDC_SDDO_8 = IOMUX_PAD(0x03B8, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__ECSPI3_MOSI = IOMUX_PAD(0x03B8, 0x00C8, 1, 0x06BC, 1, 0), + MX6_PAD_EPDC_D8__EPDC_PWRCTRL_0 = IOMUX_PAD(0x03B8, 0x00C8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__WEIM_WEIM_A_16 = IOMUX_PAD(0x03B8, 0x00C8, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__TCON_E_DATA_8 = IOMUX_PAD(0x03B8, 0x00C8, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__GPIO_1_15 = IOMUX_PAD(0x03B8, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__USDHC4_RST = IOMUX_PAD(0x03B8, 0x00C8, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D8__MMDC_MMDC_DEBUG_31 = IOMUX_PAD(0x03B8, 0x00C8, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__EPDC_SDDO_9 = IOMUX_PAD(0x03BC, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__ECSPI3_MISO = IOMUX_PAD(0x03BC, 0x00CC, 1, 0x06B8, 1, 0), + MX6_PAD_EPDC_D9__EPDC_PWRCTRL_1 = IOMUX_PAD(0x03BC, 0x00CC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__WEIM_WEIM_A_17 = IOMUX_PAD(0x03BC, 0x00CC, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__TCON_E_DATA_9 = IOMUX_PAD(0x03BC, 0x00CC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__GPIO_1_16 = IOMUX_PAD(0x03BC, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__USDHC4_VSELECT = IOMUX_PAD(0x03BC, 0x00CC, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_D9__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x03BC, 0x00CC, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 = IOMUX_PAD(0x03C0, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__TCON_YCKR = IOMUX_PAD(0x03C0, 0x00D0, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__CSI_PIXCLK = IOMUX_PAD(0x03C0, 0x00D0, 3, 0x0674, 1, 0), + MX6_PAD_EPDC_GDCLK__TCON_YCKL = IOMUX_PAD(0x03C0, 0x00D0, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__GPIO_1_31 = IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__USDHC2_RST = IOMUX_PAD(0x03C0, 0x00D0, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03C0, 0x00D0, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__ECSPI2_SS3 = IOMUX_PAD(0x03C4, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__TCON_YOER = IOMUX_PAD(0x03C4, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__CSI_HSYNC = IOMUX_PAD(0x03C4, 0x00D4, 3, 0x0670, 1, 0), + MX6_PAD_EPDC_GDOE__TCON_YOEL = IOMUX_PAD(0x03C4, 0x00D4, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__GPIO_2_0 = IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__USDHC2_VSELECT = IOMUX_PAD(0x03C4, 0x00D4, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x03C4, 0x00D4, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__ECSPI2_RDY = IOMUX_PAD(0x03C8, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__TCON_YDIOUR = IOMUX_PAD(0x03C8, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__CSI_MCLK = IOMUX_PAD(0x03C8, 0x00D8, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__TCON_YDIOUL = IOMUX_PAD(0x03C8, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__GPIO_2_1 = IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__USDHC2_WP = IOMUX_PAD(0x03C8, 0x00D8, 6, 0x0834, 1, 0), + MX6_PAD_EPDC_GDRL__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x03C8, 0x00D8, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__PWM4_PWMO = IOMUX_PAD(0x03CC, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__TCON_YDIODR = IOMUX_PAD(0x03CC, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__CSI_VSYNC = IOMUX_PAD(0x03CC, 0x00DC, 3, 0x0678, 1, 0), + MX6_PAD_EPDC_GDSP__TCON_YDIODL = IOMUX_PAD(0x03CC, 0x00DC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__GPIO_2_2 = IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__USDHC2_CD = IOMUX_PAD(0x03CC, 0x00DC, 6, 0x0830, 1, 0), + MX6_PAD_EPDC_GDSP__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x03CC, 0x00DC, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCOM__EPDC_PWRCOM = IOMUX_PAD(0x03D0, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCOM__USDHC4_DAT0 = IOMUX_PAD(0x03D0, 0x00E0, 1, 0x085C, 0, 0), + MX6_PAD_EPDC_PWRCOM__LCDIF_DAT_20 = IOMUX_PAD(0x03D0, 0x00E0, 2, 0x07C8, 0, 0), + MX6_PAD_EPDC_PWRCOM__WEIM_WEIM_BCLK = IOMUX_PAD(0x03D0, 0x00E0, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + MX6_PAD_EPDC_PWRCOM__GPIO_2_11 = IOMUX_PAD(0x03D0, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCOM__USDHC3_RST = IOMUX_PAD(0x03D0, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCOM__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03D0, 0x00E0, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL_0 = IOMUX_PAD(0x03D4, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03D4, 0x00E4, 1, 0x0604, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__LCDIF_DAT_16 = IOMUX_PAD(0x03D4, 0x00E4, 2, 0x07B8, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__WEIM_WEIM_RW = IOMUX_PAD(0x03D4, 0x00E4, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__TCON_YCKL = IOMUX_PAD(0x03D4, 0x00E4, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 = IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__USDHC4_RST = IOMUX_PAD(0x03D4, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03D4, 0x00E4, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL_1 = IOMUX_PAD(0x03D8, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x03D8, 0x00E8, 1, 0x0610, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__LCDIF_DAT_17 = IOMUX_PAD(0x03D8, 0x00E8, 2, 0x07BC, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__WEIM_WEIM_OE = IOMUX_PAD(0x03D8, 0x00E8, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__TCON_YOEL = IOMUX_PAD(0x03D8, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__GPIO_2_8 = IOMUX_PAD(0x03D8, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__USDHC4_VSELECT = IOMUX_PAD(0x03D8, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03D8, 0x00E8, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL_2 = IOMUX_PAD(0x03DC, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__AUDMUX_AUD5_TXD = IOMUX_PAD(0x03DC, 0x00EC, 1, 0x0600, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__LCDIF_DAT_18 = IOMUX_PAD(0x03DC, 0x00EC, 2, 0x07C0, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__WEIM_WEIM_CS_0 = IOMUX_PAD(0x03DC, 0x00EC, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__TCON_YDIOUL = IOMUX_PAD(0x03DC, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 = IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__USDHC4_WP = IOMUX_PAD(0x03DC, 0x00EC, 6, 0x087C, 1, 0), + MX6_PAD_EPDC_PWRCTRL2__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03DC, 0x00EC, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__EPDC_PWRCTRL_3 = IOMUX_PAD(0x03E0, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__AUDMUX_AUD5_TXC = IOMUX_PAD(0x03E0, 0x00F0, 1, 0x060C, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__LCDIF_DAT_19 = IOMUX_PAD(0x03E0, 0x00F0, 2, 0x07C4, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__WEIM_WEIM_CS_1 = IOMUX_PAD(0x03E0, 0x00F0, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__TCON_YDIODL = IOMUX_PAD(0x03E0, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 = IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__USDHC4_CD = IOMUX_PAD(0x03E0, 0x00F0, 6, 0x0854, 1, 0), + MX6_PAD_EPDC_PWRCTRL3__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03E0, 0x00F0, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRINT__EPDC_PWRIRQ = IOMUX_PAD(0x03E4, 0x00F4, 0, 0x06E8, 1, 0), + MX6_PAD_EPDC_PWRINT__USDHC4_DAT1 = IOMUX_PAD(0x03E4, 0x00F4, 1, 0x0860, 0, 0), + MX6_PAD_EPDC_PWRINT__LCDIF_DAT_21 = IOMUX_PAD(0x03E4, 0x00F4, 2, 0x07CC, 0, 0), + MX6_PAD_EPDC_PWRINT__WEIM_ACLK_FREERUN = IOMUX_PAD(0x03E4, 0x00F4, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRINT__ANATOP_USBOTG2_ID = IOMUX_PAD(0x03E4, 0x00F4, 4, 0x05E0, 0, 0), + MX6_PAD_EPDC_PWRINT__GPIO_2_12 = IOMUX_PAD(0x03E4, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRINT__USDHC3_VSELECT = IOMUX_PAD(0x03E4, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRINT__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03E4, 0x00F4, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT = IOMUX_PAD(0x03E8, 0x00F8, 0, 0x06EC, 1, 0), + MX6_PAD_EPDC_PWRSTAT__USDHC4_DAT2 = IOMUX_PAD(0x03E8, 0x00F8, 1, 0x0864, 0, 0), + MX6_PAD_EPDC_PWRSTAT__LCDIF_DAT_22 = IOMUX_PAD(0x03E8, 0x00F8, 2, 0x07D0, 0, 0), + MX6_PAD_EPDC_PWRSTAT__WEIM_WEIM_WAIT = IOMUX_PAD(0x03E8, 0x00F8, 3, 0x0884, 0, 0), + MX6_PAD_EPDC_PWRSTAT__KITTEN_EVENTI = IOMUX_PAD(0x03E8, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 = IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRSTAT__USDHC3_WP = IOMUX_PAD(0x03E8, 0x00F8, 6, 0x084C, 0, 0), + MX6_PAD_EPDC_PWRSTAT__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03E8, 0x00F8, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__EPDC_PWRWAKE = IOMUX_PAD(0x03EC, 0x00FC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__USDHC4_DAT3 = IOMUX_PAD(0x03EC, 0x00FC, 1, 0x0868, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__LCDIF_DAT_23 = IOMUX_PAD(0x03EC, 0x00FC, 2, 0x07D4, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x03EC, 0x00FC, 3, 0x0880, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__KITTEN_EVENTO = IOMUX_PAD(0x03EC, 0x00FC, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 = IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__USDHC3_CD = IOMUX_PAD(0x03EC, 0x00FC, 6, 0x0838, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__MMDC_MMDC_DEBUG_0 = IOMUX_PAD(0x03EC, 0x00FC, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 = IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 = IOMUX_PAD(0x03F0, 0x0100, 1, 0x06AC, 0, 0), + MX6_PAD_EPDC_SDCE0__PWM3_PWMO = IOMUX_PAD(0x03F0, 0x0100, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__WEIM_WEIM_CS_2 = IOMUX_PAD(0x03F0, 0x0100, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__TCON_YCKR = IOMUX_PAD(0x03F0, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__GPIO_1_27 = IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x03F0, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03F0, 0x0100, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 = IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__WDOG2_WDOG_B = IOMUX_PAD(0x03F4, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__PWM4_PWMO = IOMUX_PAD(0x03F4, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__WEIM_WEIM_LBA = IOMUX_PAD(0x03F4, 0x0104, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__TCON_YOER = IOMUX_PAD(0x03F4, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__GPIO_1_28 = IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__ANATOP_USBPHY1_TSTO_RX_FS_RXD = IOMUX_PAD(0x03F4, 0x0104, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03F4, 0x0104, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 = IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__I2C3_SCL = IOMUX_PAD(0x03F8, 0x0108, 17, 0x072C, 1, 0), + MX6_PAD_EPDC_SDCE2__PWM1_PWMO = IOMUX_PAD(0x03F8, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__WEIM_WEIM_EB_0 = IOMUX_PAD(0x03F8, 0x0108, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__TCON_YDIOUR = IOMUX_PAD(0x03F8, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__GPIO_1_29 = IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__ANATOP_USBPHY1_TSTO_RX_HS_RXD = IOMUX_PAD(0x03F8, 0x0108, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03F8, 0x0108, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__EPDC_SDCE_3 = IOMUX_PAD(0x03FC, 0x010C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__I2C3_SDA = IOMUX_PAD(0x03FC, 0x010C, 17, 0x0730, 1, 0), + MX6_PAD_EPDC_SDCE3__PWM2_PWMO = IOMUX_PAD(0x03FC, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__WEIM_WEIM_EB_1 = IOMUX_PAD(0x03FC, 0x010C, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__TCON_YDIODR = IOMUX_PAD(0x03FC, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__GPIO_1_30 = IOMUX_PAD(0x03FC, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__ANATOP_USBPHY1_TSTO_RX_SQUELCH = IOMUX_PAD(0x03FC, 0x010C, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE3__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03FC, 0x010C, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI = IOMUX_PAD(0x0400, 0x0110, 1, 0x06A4, 1, 0), + MX6_PAD_EPDC_SDCLK__I2C2_SCL = IOMUX_PAD(0x0400, 0x0110, 18, 0x0724, 0, 0), + MX6_PAD_EPDC_SDCLK__CSI_D_8 = IOMUX_PAD(0x0400, 0x0110, 3, 0x0650, 0, 0), + MX6_PAD_EPDC_SDCLK__TCON_CL = IOMUX_PAD(0x0400, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__GPIO_1_23 = IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__ANATOP_USBPHY2_TSTO_RX_HS_RXD = IOMUX_PAD(0x0400, 0x0110, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__MMDC_MMDC_DEBUG_23 = IOMUX_PAD(0x0400, 0x0110, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__ECSPI2_MISO = IOMUX_PAD(0x0404, 0x0114, 1, 0x06A0, 1, 0), + MX6_PAD_EPDC_SDLE__I2C2_SDA = IOMUX_PAD(0x0404, 0x0114, 18, 0x0728, 0, 0), + MX6_PAD_EPDC_SDLE__CSI_D_9 = IOMUX_PAD(0x0404, 0x0114, 3, 0x0654, 0, 0), + MX6_PAD_EPDC_SDLE__TCON_LD = IOMUX_PAD(0x0404, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__GPIO_1_24 = IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__ANATOP_USBPHY2_TSTO_RX_SQUELCH = IOMUX_PAD(0x0404, 0x0114, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x0404, 0x0114, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__ECSPI2_SS0 = IOMUX_PAD(0x0408, 0x0118, 1, 0x06A8, 1, 0), + MX6_PAD_EPDC_SDOE__TCON_XDIOR = IOMUX_PAD(0x0408, 0x0118, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__CSI_D_10 = IOMUX_PAD(0x0408, 0x0118, 3, 0x0658, 0, 0), + MX6_PAD_EPDC_SDOE__TCON_XDIOL = IOMUX_PAD(0x0408, 0x0118, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__GPIO_1_25 = IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV = IOMUX_PAD(0x0408, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x0408, 0x0118, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x011C, 1, 0x069C, 1, 0), + MX6_PAD_EPDC_SDSHR__EPDC_SDCE_4 = IOMUX_PAD(0x040C, 0x011C, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__CSI_D_11 = IOMUX_PAD(0x040C, 0x011C, 3, 0x065C, 0, 0), + MX6_PAD_EPDC_SDSHR__TCON_XDIOR = IOMUX_PAD(0x040C, 0x011C, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__GPIO_1_26 = IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x040C, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x040C, 0x011C, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__EPDC_VCOM_0 = IOMUX_PAD(0x0410, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x0120, 1, 0x0608, 0, 0), + MX6_PAD_EPDC_VCOM0__UART3_TXD = IOMUX_PAD(0x0410, 0x0120, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__UART3_RXD = IOMUX_PAD(0x0410, 0x0120, 2, 0x080C, 4, 0), + MX6_PAD_EPDC_VCOM0__WEIM_WEIM_A_24 = IOMUX_PAD(0x0410, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__TCON_VCOM_0 = IOMUX_PAD(0x0410, 0x0120, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__GPIO_2_3 = IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__EPDC_SDCE_5 = IOMUX_PAD(0x0410, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0410, 0x0120, 7, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__EPDC_VCOM_1 = IOMUX_PAD(0x0414, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0414, 0x0124, 1, 0x05FC, 0, 0), + MX6_PAD_EPDC_VCOM1__UART3_TXD = IOMUX_PAD(0x0414, 0x0124, 2, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__UART3_RXD = IOMUX_PAD(0x0414, 0x0124, 2, 0x080C, 5, 0), + MX6_PAD_EPDC_VCOM1__WEIM_WEIM_A_25 = IOMUX_PAD(0x0414, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__TCON_VCOM_1 = IOMUX_PAD(0x0414, 0x0124, 4, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__GPIO_2_4 = IOMUX_PAD(0x0414, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__EPDC_SDCE_6 = IOMUX_PAD(0x0414, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM1__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0414, 0x0124, 7, 0x0000, 0, 0), + MX6_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x0418, 0x0128, 0, 0x0704, 1, 0), + MX6_PAD_FEC_CRS_DV__USDHC4_DAT1 = IOMUX_PAD(0x0418, 0x0128, 1, 0x0860, 1, 0), + MX6_PAD_FEC_CRS_DV__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0418, 0x0128, 2, 0x0624, 0, 0), + MX6_PAD_FEC_CRS_DV__ECSPI4_MISO = IOMUX_PAD(0x0418, 0x0128, 3, 0x06D4, 1, 0), + MX6_PAD_FEC_CRS_DV__GPT_CMPOUT2 = IOMUX_PAD(0x0418, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_FEC_CRS_DV__GPIO_4_25 = IOMUX_PAD(0x0418, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_FEC_CRS_DV__KITTEN_TRACE_31 = IOMUX_PAD(0x0418, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_FEC_CRS_DV__PL301_SIM_MX6_PER1_HADDR_3 = IOMUX_PAD(0x0418, 0x0128, 7, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x041C, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__USDHC4_DAT4 = IOMUX_PAD(0x041C, 0x012C, 1, 0x086C, 0, 0), + MX6_PAD_FEC_MDC__AUDMUX_AUDIO_CLK_OUT = IOMUX_PAD(0x041C, 0x012C, 2, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__USDHC1_RST = IOMUX_PAD(0x041C, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__USDHC3_RST = IOMUX_PAD(0x041C, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__GPIO_4_23 = IOMUX_PAD(0x041C, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__KITTEN_TRACE_29 = IOMUX_PAD(0x041C, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_FEC_MDC__PL301_SIM_MX6_PER1_HADDR_8 = IOMUX_PAD(0x041C, 0x012C, 7, 0x0000, 0, 0), + MX6_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x0420, 0x0130, 0, 0x06F4, 1, 0), + MX6_PAD_FEC_MDIO__USDHC4_CLK = IOMUX_PAD(0x0420, 0x0130, 1, 0x0850, 1, 0), + MX6_PAD_FEC_MDIO__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0420, 0x0130, 2, 0x0620, 0, 0), + MX6_PAD_FEC_MDIO__ECSPI4_SS0 = IOMUX_PAD(0x0420, 0x0130, 3, 0x06DC, 1, 0), + MX6_PAD_FEC_MDIO__GPT_CAPIN1 = IOMUX_PAD(0x0420, 0x0130, 4, 0x0710, 0, 0), + MX6_PAD_FEC_MDIO__GPIO_4_20 = IOMUX_PAD(0x0420, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_FEC_MDIO__KITTEN_TRACE_26 = IOMUX_PAD(0x0420, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_FEC_MDIO__PL301_SIM_MX6_PER1_HADDR_15 = IOMUX_PAD(0x0420, 0x0130, 7, 0x0000, 0, 0), + MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x0424, 0x0134, 0x10, 0x0000, 0, 0), + MX6_PAD_FEC_REF_CLK__USDHC4_RST = IOMUX_PAD(0x0424, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_FEC_REF_CLK__WDOG1_WDOG_B = IOMUX_PAD(0x0424, 0x0134, 2, 0x0000, 0, 0), + MX6_PAD_FEC_REF_CLK__PWM4_PWMO = IOMUX_PAD(0x0424, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_FEC_REF_CLK__CCM_PMIC_RDY = IOMUX_PAD(0x0424, 0x0134, 4, 0x062C, 0, 0), + MX6_PAD_FEC_REF_CLK__GPIO_4_26 = IOMUX_PAD(0x0424, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_FEC_REF_CLK__SPDIF_SPDIF_EXT_CLK = IOMUX_PAD(0x0424, 0x0134, 6, 0x07F4, 2, 0), + MX6_PAD_FEC_REF_CLK__PL301_SIM_MX6_PER1_HADDR_0 = IOMUX_PAD(0x0424, 0x0134, 7, 0x0000, 0, 0), + MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_FEC_RX_ER__KITTEN_TRACE_25 = IOMUX_PAD(0x0428, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_FEC_RX_ER__PL301_SIM_MX6_PER1_HADDR_5 = IOMUX_PAD(0x0428, 0x0138, 7, 0x0000, 0, 0), + MX6_PAD_FEC_RX_ER__FEC_RX_ER = IOMUX_PAD(0x0428, 0x0138, 0, 0x0708, 1, 0), + MX6_PAD_FEC_RX_ER__USDHC4_DAT0 = IOMUX_PAD(0x0428, 0x0138, 1, 0x085C, 1, 0), + MX6_PAD_FEC_RX_ER__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0428, 0x0138, 2, 0x0614, 0, 0), + MX6_PAD_FEC_RX_ER__ECSPI4_MOSI = IOMUX_PAD(0x0428, 0x0138, 3, 0x06D8, 1, 0), + MX6_PAD_FEC_RX_ER__GPT_CMPOUT1 = IOMUX_PAD(0x0428, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_FEC_RXD0__FEC_RDATA_0 = IOMUX_PAD(0x042C, 0x013C, 0, 0x06F8, 0, 0), + MX6_PAD_FEC_RXD0__USDHC4_DAT5 = IOMUX_PAD(0x042C, 0x013C, 1, 0x0870, 0, 0), + MX6_PAD_FEC_RXD0__ANATOP_USBOTG1_ID = IOMUX_PAD(0x042C, 0x013C, 2, 0x05DC, 1, 0), + MX6_PAD_FEC_RXD0__USDHC1_VSELECT = IOMUX_PAD(0x042C, 0x013C, 3, 0x0000, 0, 0), + MX6_PAD_FEC_RXD0__USDHC3_VSELECT = IOMUX_PAD(0x042C, 0x013C, 4, 0x0000, 0, 0), + MX6_PAD_FEC_RXD0__GPIO_4_17 = IOMUX_PAD(0x042C, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_FEC_RXD0__KITTEN_TRACE_24 = IOMUX_PAD(0x042C, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_FEC_RXD0__PL301_SIM_MX6_PER1_HADDR_7 = IOMUX_PAD(0x042C, 0x013C, 7, 0x0000, 0, 0), + MX6_PAD_FEC_RXD1__FEC_RDATA_1 = IOMUX_PAD(0x0430, 0x0140, 0, 0x06FC, 1, 0), + MX6_PAD_FEC_RXD1__USDHC4_DAT2 = IOMUX_PAD(0x0430, 0x0140, 1, 0x0864, 1, 0), + MX6_PAD_FEC_RXD1__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0430, 0x0140, 2, 0x0628, 0, 0), + MX6_PAD_FEC_RXD1__ECSPI4_SS1 = IOMUX_PAD(0x0430, 0x0140, 3, 0x06E0, 1, 0), + MX6_PAD_FEC_RXD1__GPT_CMPOUT3 = IOMUX_PAD(0x0430, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_FEC_RXD1__GPIO_4_18 = IOMUX_PAD(0x0430, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_FEC_RXD1__FEC_COL = IOMUX_PAD(0x0430, 0x0140, 6, 0x06F0, 0, 0), + MX6_PAD_FEC_RXD1__PL301_SIM_MX6_PER1_HADDR_9 = IOMUX_PAD(0x0430, 0x0140, 7, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x0434, 0x0144, 0, 0x070C, 1, 0), + MX6_PAD_FEC_TX_CLK__USDHC4_CMD = IOMUX_PAD(0x0434, 0x0144, 1, 0x0858, 1, 0), + MX6_PAD_FEC_TX_CLK__AUDMUX_AUD6_RXC = IOMUX_PAD(0x0434, 0x0144, 2, 0x061C, 0, 0), + MX6_PAD_FEC_TX_CLK__ECSPI4_SCLK = IOMUX_PAD(0x0434, 0x0144, 3, 0x06D0, 1, 0), + MX6_PAD_FEC_TX_CLK__GPT_CAPIN2 = IOMUX_PAD(0x0434, 0x0144, 4, 0x0714, 0, 0), + MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__KITTEN_TRACE_27 = IOMUX_PAD(0x0434, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_FEC_TX_CLK__PL301_SIM_MX6_PER1_HADDR_4 = IOMUX_PAD(0x0434, 0x0144, 7, 0x0000, 0, 0), + MX6_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x0438, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_FEC_TX_EN__USDHC4_DAT6 = IOMUX_PAD(0x0438, 0x0148, 1, 0x0874, 0, 0), + MX6_PAD_FEC_TX_EN__SPDIF_IN1 = IOMUX_PAD(0x0438, 0x0148, 2, 0x07F0, 0, 0), + MX6_PAD_FEC_TX_EN__USDHC1_WP = IOMUX_PAD(0x0438, 0x0148, 3, 0x082C, 1, 0), + MX6_PAD_FEC_TX_EN__USDHC3_WP = IOMUX_PAD(0x0438, 0x0148, 4, 0x084C, 1, 0), + MX6_PAD_FEC_TX_EN__GPIO_4_22 = IOMUX_PAD(0x0438, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TX_EN__KITTEN_TRACE_28 = IOMUX_PAD(0x0438, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_FEC_TX_EN__PL301_SIM_MX6_PER1_HADDR_1 = IOMUX_PAD(0x0438, 0x0148, 7, 0x0000, 0, 0), + MX6_PAD_FEC_TXD0__FEC_TDATA_0 = IOMUX_PAD(0x043C, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_FEC_TXD0__USDHC4_DAT3 = IOMUX_PAD(0x043C, 0x014C, 1, 0x0868, 1, 0), + MX6_PAD_FEC_TXD0__AUDMUX_AUD6_TXD = IOMUX_PAD(0x043C, 0x014C, 2, 0x0618, 0, 0), + MX6_PAD_FEC_TXD0__ECSPI4_SS2 = IOMUX_PAD(0x043C, 0x014C, 3, 0x06E4, 1, 0), + MX6_PAD_FEC_TXD0__GPT_CLKIN = IOMUX_PAD(0x043C, 0x014C, 4, 0x0718, 0, 0), + MX6_PAD_FEC_TXD0__GPIO_4_24 = IOMUX_PAD(0x043C, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TXD0__KITTEN_TRACE_30 = IOMUX_PAD(0x043C, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_FEC_TXD0__PL301_SIM_MX6_PER1_HADDR_2 = IOMUX_PAD(0x043C, 0x014C, 7, 0x0000, 0, 0), + MX6_PAD_FEC_TXD1__FEC_TDATA_1 = IOMUX_PAD(0x0440, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_FEC_TXD1__USDHC4_DAT7 = IOMUX_PAD(0x0440, 0x0150, 1, 0x0878, 0, 0), + MX6_PAD_FEC_TXD1__SPDIF_OUT1 = IOMUX_PAD(0x0440, 0x0150, 2, 0x0000, 0, 0), + MX6_PAD_FEC_TXD1__USDHC1_CD = IOMUX_PAD(0x0440, 0x0150, 3, 0x0828, 1, 0), + MX6_PAD_FEC_TXD1__USDHC3_CD = IOMUX_PAD(0x0440, 0x0150, 4, 0x0838, 1, 0), + MX6_PAD_FEC_TXD1__GPIO_4_16 = IOMUX_PAD(0x0440, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_FEC_TXD1__FEC_RX_CLK = IOMUX_PAD(0x0440, 0x0150, 6, 0x0700, 0, 0), + MX6_PAD_FEC_TXD1__PL301_SIM_MX6_PER1_HADDR_6 = IOMUX_PAD(0x0440, 0x0150, 7, 0x0000, 0, 0), + MX6_PAD_HSIC_DAT__USB_H_DATA = IOMUX_PAD(0x0444, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_HSIC_DAT__I2C1_SCL = IOMUX_PAD(0x0444, 0x0154, 17, 0x071C, 1, 0), + MX6_PAD_HSIC_DAT__PWM1_PWMO = IOMUX_PAD(0x0444, 0x0154, 2, 0x0000, 0, 0), + MX6_PAD_HSIC_DAT__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x0444, 0x0154, 3, 0x0000, 0, 0), + MX6_PAD_HSIC_DAT__OSC32K_32K_OUT = IOMUX_PAD(0x0444, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_HSIC_DAT__GPIO_3_19 = IOMUX_PAD(0x0444, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_HSIC_STROBE__USB_H_STROBE = IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_HSIC_STROBE__I2C1_SDA = IOMUX_PAD(0x0448, 0x0158, 17, 0x0720, 1, 0), + MX6_PAD_HSIC_STROBE__PWM2_PWMO = IOMUX_PAD(0x0448, 0x0158, 2, 0x0000, 0, 0), + MX6_PAD_HSIC_STROBE__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0448, 0x0158, 3, 0x0000, 0, 0), + MX6_PAD_HSIC_STROBE__GPIO_3_20 = IOMUX_PAD(0x0448, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 16, 0x071C, 2, 0), + MX6_PAD_I2C1_SCL__UART1_CTS = IOMUX_PAD(0x044C, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__UART1_RTS = IOMUX_PAD(0x044C, 0x015C, 1, 0x07F8, 0, 0), + MX6_PAD_I2C1_SCL__ECSPI3_SS2 = IOMUX_PAD(0x044C, 0x015C, 2, 0x06C8, 1, 0), + MX6_PAD_I2C1_SCL__FEC_RDATA_0 = IOMUX_PAD(0x044C, 0x015C, 3, 0x06F8, 1, 0), + MX6_PAD_I2C1_SCL__USDHC3_RST = IOMUX_PAD(0x044C, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SCL__ECSPI1_SS1 = IOMUX_PAD(0x044C, 0x015C, 6, 0x0690, 0, 0), + MX6_PAD_I2C1_SCL__PL301_SIM_MX6_PER1_HSIZE_0 = IOMUX_PAD(0x044C, 0x015C, 7, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 16, 0x0720, 2, 0), + MX6_PAD_I2C1_SDA__UART1_CTS = IOMUX_PAD(0x0450, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__UART1_RTS = IOMUX_PAD(0x0450, 0x0160, 1, 0x07F8, 1, 0), + MX6_PAD_I2C1_SDA__ECSPI3_SS3 = IOMUX_PAD(0x0450, 0x0160, 2, 0x06CC, 1, 0), + MX6_PAD_I2C1_SDA__FEC_TX_EN = IOMUX_PAD(0x0450, 0x0160, 3, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__USDHC3_VSELECT = IOMUX_PAD(0x0450, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_I2C1_SDA__ECSPI1_SS2 = IOMUX_PAD(0x0450, 0x0160, 6, 0x0694, 0, 0), + MX6_PAD_I2C1_SDA__PL301_SIM_MX6_PER1_HSIZE_1 = IOMUX_PAD(0x0450, 0x0160, 7, 0x0000, 0, 0), + MX6_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0454, 0x0164, 16, 0x0724, 1, 0), + MX6_PAD_I2C2_SCL__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x0454, 0x0164, 1, 0x05F0, 0, 0), + MX6_PAD_I2C2_SCL__SPDIF_IN1 = IOMUX_PAD(0x0454, 0x0164, 2, 0x07F0, 1, 0), + MX6_PAD_I2C2_SCL__FEC_TDATA_1 = IOMUX_PAD(0x0454, 0x0164, 3, 0x0000, 0, 0), + MX6_PAD_I2C2_SCL__USDHC3_WP = IOMUX_PAD(0x0454, 0x0164, 4, 0x084C, 2, 0), + MX6_PAD_I2C2_SCL__GPIO_3_14 = IOMUX_PAD(0x0454, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_I2C2_SCL__ECSPI1_RDY = IOMUX_PAD(0x0454, 0x0164, 6, 0x0680, 0, 0), + MX6_PAD_I2C2_SCL__PL301_SIM_MX6_PER1_HSIZE_2 = IOMUX_PAD(0x0454, 0x0164, 7, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0458, 0x0168, 16, 0x0728, 1, 0), + MX6_PAD_I2C2_SDA__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0458, 0x0168, 1, 0x05EC, 0, 0), + MX6_PAD_I2C2_SDA__SPDIF_OUT1 = IOMUX_PAD(0x0458, 0x0168, 2, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__FEC_REF_OUT = IOMUX_PAD(0x0458, 0x0168, 3, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__USDHC3_CD = IOMUX_PAD(0x0458, 0x0168, 4, 0x0838, 2, 0), + MX6_PAD_I2C2_SDA__GPIO_3_15 = IOMUX_PAD(0x0458, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__ANATOP_ANATOP_TESTO_0 = IOMUX_PAD(0x0458, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_I2C2_SDA__PL301_SIM_MX6_PER1_HWRITE = IOMUX_PAD(0x0458, 0x0168, 7, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, 0), + MX6_PAD_KEY_COL0__I2C2_SCL = IOMUX_PAD(0x0474, 0x016C, 17, 0x0724, 2, 0), + MX6_PAD_KEY_COL0__LCDIF_DAT_0 = IOMUX_PAD(0x0474, 0x016C, 2, 0x0778, 0, 0), + MX6_PAD_KEY_COL0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0474, 0x016C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__USDHC1_CD = IOMUX_PAD(0x0474, 0x016C, 4, 0x0828, 2, 0), + MX6_PAD_KEY_COL0__GPIO_3_24 = IOMUX_PAD(0x0474, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL0__MSHC_SCLK = IOMUX_PAD(0x0474, 0x016C, 6, 0x07E8, 0, 0), + MX6_PAD_KEY_COL0__TPSMP_HDATA_0 = IOMUX_PAD(0x0474, 0x016C, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, 0), + MX6_PAD_KEY_COL1__ECSPI4_MOSI = IOMUX_PAD(0x0478, 0x0170, 1, 0x06D8, 2, 0), + MX6_PAD_KEY_COL1__LCDIF_DAT_2 = IOMUX_PAD(0x0478, 0x0170, 2, 0x0780, 0, 0), + MX6_PAD_KEY_COL1__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0478, 0x0170, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__USDHC3_DAT4 = IOMUX_PAD(0x0478, 0x0170, 4, 0x083C, 0, 0), + MX6_PAD_KEY_COL1__GPIO_3_26 = IOMUX_PAD(0x0478, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL1__MSHC_DATA_0 = IOMUX_PAD(0x0478, 0x0170, 6, 0x07D8, 0, 0), + MX6_PAD_KEY_COL1__TPSMP_HDATA_2 = IOMUX_PAD(0x0478, 0x0170, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, 0), + MX6_PAD_KEY_COL2__ECSPI4_SS0 = IOMUX_PAD(0x047C, 0x0174, 1, 0x06DC, 2, 0), + MX6_PAD_KEY_COL2__LCDIF_DAT_4 = IOMUX_PAD(0x047C, 0x0174, 2, 0x0788, 0, 0), + MX6_PAD_KEY_COL2__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x047C, 0x0174, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__USDHC3_DAT6 = IOMUX_PAD(0x047C, 0x0174, 4, 0x0844, 0, 0), + MX6_PAD_KEY_COL2__GPIO_3_28 = IOMUX_PAD(0x047C, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL2__MSHC_DATA_2 = IOMUX_PAD(0x047C, 0x0174, 6, 0x07E0, 0, 0), + MX6_PAD_KEY_COL2__TPSMP_HDATA_4 = IOMUX_PAD(0x047C, 0x0174, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, 0), + MX6_PAD_KEY_COL3__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0480, 0x0178, 1, 0x0620, 1, 0), + MX6_PAD_KEY_COL3__LCDIF_DAT_6 = IOMUX_PAD(0x0480, 0x0178, 2, 0x0790, 0, 0), + MX6_PAD_KEY_COL3__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0480, 0x0178, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__USDHC4_DAT6 = IOMUX_PAD(0x0480, 0x0178, 4, 0x0874, 1, 0), + MX6_PAD_KEY_COL3__GPIO_3_30 = IOMUX_PAD(0x0480, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__USDHC1_RST = IOMUX_PAD(0x0480, 0x0178, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL3__TPSMP_HDATA_6 = IOMUX_PAD(0x0480, 0x0178, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x0484, 0x017C, 0, 0x0744, 0, 0), + MX6_PAD_KEY_COL4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0484, 0x017C, 1, 0x0614, 1, 0), + MX6_PAD_KEY_COL4__LCDIF_DAT_8 = IOMUX_PAD(0x0484, 0x017C, 2, 0x0798, 0, 0), + MX6_PAD_KEY_COL4__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0484, 0x017C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USDHC4_CLK = IOMUX_PAD(0x0484, 0x017C, 4, 0x0850, 2, 0), + MX6_PAD_KEY_COL4__GPIO_4_0 = IOMUX_PAD(0x0484, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL4__TPSMP_HDATA_8 = IOMUX_PAD(0x0484, 0x017C, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__KPP_COL_5 = IOMUX_PAD(0x0488, 0x0180, 0, 0x0748, 0, 0), + MX6_PAD_KEY_COL5__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0488, 0x0180, 1, 0x0628, 1, 0), + MX6_PAD_KEY_COL5__LCDIF_DAT_10 = IOMUX_PAD(0x0488, 0x0180, 2, 0x07A0, 0, 0), + MX6_PAD_KEY_COL5__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0488, 0x0180, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USDHC4_DAT0 = IOMUX_PAD(0x0488, 0x0180, 4, 0x085C, 2, 0), + MX6_PAD_KEY_COL5__GPIO_4_2 = IOMUX_PAD(0x0488, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__TPSMP_HDATA_10 = IOMUX_PAD(0x0488, 0x0180, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__KPP_COL_6 = IOMUX_PAD(0x048C, 0x0184, 0, 0x074C, 0, 0), + MX6_PAD_KEY_COL6__UART4_TXD = IOMUX_PAD(0x048C, 0x0184, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__UART4_RXD = IOMUX_PAD(0x048C, 0x0184, 1, 0x0814, 2, 0), + MX6_PAD_KEY_COL6__LCDIF_DAT_12 = IOMUX_PAD(0x048C, 0x0184, 2, 0x07A8, 0, 0), + MX6_PAD_KEY_COL6__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x048C, 0x0184, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__USDHC4_DAT2 = IOMUX_PAD(0x048C, 0x0184, 4, 0x0864, 2, 0), + MX6_PAD_KEY_COL6__GPIO_4_4 = IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__USDHC3_RST = IOMUX_PAD(0x048C, 0x0184, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__TPSMP_HDATA_12 = IOMUX_PAD(0x048C, 0x0184, 7, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__KPP_COL_7 = IOMUX_PAD(0x0490, 0x0188, 0, 0x0750, 0, 0), + MX6_PAD_KEY_COL7__UART4_CTS = IOMUX_PAD(0x0490, 0x0188, 1, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__UART4_RTS = IOMUX_PAD(0x0490, 0x0188, 1, 0x0810, 2, 0), + MX6_PAD_KEY_COL7__LCDIF_DAT_14 = IOMUX_PAD(0x0490, 0x0188, 2, 0x07B0, 0, 0), + MX6_PAD_KEY_COL7__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0490, 0x0188, 3, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__USDHC4_DAT4 = IOMUX_PAD(0x0490, 0x0188, 4, 0x086C, 1, 0), + MX6_PAD_KEY_COL7__GPIO_4_6 = IOMUX_PAD(0x0490, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_KEY_COL7__USDHC1_WP = IOMUX_PAD(0x0490, 0x0188, 6, 0x082C, 2, 0), + MX6_PAD_KEY_COL7__TPSMP_HDATA_14 = IOMUX_PAD(0x0490, 0x0188, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, 0), + MX6_PAD_KEY_ROW0__I2C2_SDA = IOMUX_PAD(0x0494, 0x018C, 17, 0x0728, 2, 0), + MX6_PAD_KEY_ROW0__LCDIF_DAT_1 = IOMUX_PAD(0x0494, 0x018C, 2, 0x077C, 0, 0), + MX6_PAD_KEY_ROW0__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x0494, 0x018C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__USDHC1_WP = IOMUX_PAD(0x0494, 0x018C, 4, 0x082C, 3, 0), + MX6_PAD_KEY_ROW0__GPIO_3_25 = IOMUX_PAD(0x0494, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__MSHC_BS = IOMUX_PAD(0x0494, 0x018C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW0__TPSMP_HDATA_1 = IOMUX_PAD(0x0494, 0x018C, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, 0), + MX6_PAD_KEY_ROW1__ECSPI4_MISO = IOMUX_PAD(0x0498, 0x0190, 1, 0x06D4, 2, 0), + MX6_PAD_KEY_ROW1__LCDIF_DAT_3 = IOMUX_PAD(0x0498, 0x0190, 2, 0x0784, 0, 0), + MX6_PAD_KEY_ROW1__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0498, 0x0190, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__USDHC3_DAT5 = IOMUX_PAD(0x0498, 0x0190, 4, 0x0840, 0, 0), + MX6_PAD_KEY_ROW1__GPIO_3_27 = IOMUX_PAD(0x0498, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW1__MSHC_DATA_1 = IOMUX_PAD(0x0498, 0x0190, 6, 0x07DC, 0, 0), + MX6_PAD_KEY_ROW1__TPSMP_HDATA_3 = IOMUX_PAD(0x0498, 0x0190, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, 0), + MX6_PAD_KEY_ROW2__ECSPI4_SCLK = IOMUX_PAD(0x049C, 0x0194, 1, 0x06D0, 2, 0), + MX6_PAD_KEY_ROW2__LCDIF_DAT_5 = IOMUX_PAD(0x049C, 0x0194, 2, 0x078C, 0, 0), + MX6_PAD_KEY_ROW2__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x049C, 0x0194, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__USDHC3_DAT7 = IOMUX_PAD(0x049C, 0x0194, 4, 0x0848, 0, 0), + MX6_PAD_KEY_ROW2__GPIO_3_29 = IOMUX_PAD(0x049C, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW2__MSHC_DATA_3 = IOMUX_PAD(0x049C, 0x0194, 6, 0x07E4, 0, 0), + MX6_PAD_KEY_ROW2__TPSMP_HDATA_5 = IOMUX_PAD(0x049C, 0x0194, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, 0), + MX6_PAD_KEY_ROW3__AUDMUX_AUD6_RXC = IOMUX_PAD(0x04A0, 0x0198, 1, 0x061C, 1, 0), + MX6_PAD_KEY_ROW3__LCDIF_DAT_7 = IOMUX_PAD(0x04A0, 0x0198, 2, 0x0794, 0, 0), + MX6_PAD_KEY_ROW3__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x04A0, 0x0198, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__USDHC4_DAT7 = IOMUX_PAD(0x04A0, 0x0198, 4, 0x0878, 1, 0), + MX6_PAD_KEY_ROW3__GPIO_3_31 = IOMUX_PAD(0x04A0, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x04A0, 0x0198, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW3__TPSMP_HDATA_7 = IOMUX_PAD(0x04A0, 0x0198, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x04A4, 0x019C, 0, 0x0764, 0, 0), + MX6_PAD_KEY_ROW4__AUDMUX_AUD6_TXC = IOMUX_PAD(0x04A4, 0x019C, 1, 0x0624, 1, 0), + MX6_PAD_KEY_ROW4__LCDIF_DAT_9 = IOMUX_PAD(0x04A4, 0x019C, 2, 0x079C, 0, 0), + MX6_PAD_KEY_ROW4__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x04A4, 0x019C, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USDHC4_CMD = IOMUX_PAD(0x04A4, 0x019C, 4, 0x0858, 2, 0), + MX6_PAD_KEY_ROW4__GPIO_4_1 = IOMUX_PAD(0x04A4, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW4__USB_USBOTG1_OC = IOMUX_PAD(0x04A4, 0x019C, 6, 0x0824, 1, 0), + MX6_PAD_KEY_ROW4__TPSMP_HDATA_9 = IOMUX_PAD(0x04A4, 0x019C, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__KPP_ROW_5 = IOMUX_PAD(0x04A8, 0x01A0, 0, 0x0768, 0, 0), + MX6_PAD_KEY_ROW5__AUDMUX_AUD6_TXD = IOMUX_PAD(0x04A8, 0x01A0, 1, 0x0618, 1, 0), + MX6_PAD_KEY_ROW5__LCDIF_DAT_11 = IOMUX_PAD(0x04A8, 0x01A0, 2, 0x07A4, 0, 0), + MX6_PAD_KEY_ROW5__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x04A8, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__USDHC4_DAT1 = IOMUX_PAD(0x04A8, 0x01A0, 4, 0x0860, 2, 0), + MX6_PAD_KEY_ROW5__GPIO_4_3 = IOMUX_PAD(0x04A8, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW5__USB_USBOTG2_OC = IOMUX_PAD(0x04A8, 0x01A0, 6, 0x0820, 2, 0), + MX6_PAD_KEY_ROW5__TPSMP_HDATA_11 = IOMUX_PAD(0x04A8, 0x01A0, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__KPP_ROW_6 = IOMUX_PAD(0x04AC, 0x01A4, 0, 0x076C, 0, 0), + MX6_PAD_KEY_ROW6__UART4_TXD = IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__UART4_RXD = IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0814, 3, 0), + MX6_PAD_KEY_ROW6__LCDIF_DAT_13 = IOMUX_PAD(0x04AC, 0x01A4, 2, 0x07AC, 0, 0), + MX6_PAD_KEY_ROW6__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x04AC, 0x01A4, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__USDHC4_DAT3 = IOMUX_PAD(0x04AC, 0x01A4, 4, 0x0868, 2, 0), + MX6_PAD_KEY_ROW6__GPIO_4_5 = IOMUX_PAD(0x04AC, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__USDHC3_VSELECT = IOMUX_PAD(0x04AC, 0x01A4, 6, 0x0000, 0, 0), + MX6_PAD_KEY_ROW6__TPSMP_HDATA_13 = IOMUX_PAD(0x04AC, 0x01A4, 7, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__KPP_ROW_7 = IOMUX_PAD(0x04B0, 0x01A8, 0, 0x0770, 0, 0), + MX6_PAD_KEY_ROW7__UART4_CTS = IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__UART4_RTS = IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0810, 3, 0), + MX6_PAD_KEY_ROW7__LCDIF_DAT_15 = IOMUX_PAD(0x04B0, 0x01A8, 2, 0x07B4, 0, 0), + MX6_PAD_KEY_ROW7__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x04B0, 0x01A8, 3, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__USDHC4_DAT5 = IOMUX_PAD(0x04B0, 0x01A8, 4, 0x0870, 1, 0), + MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_KEY_ROW7__USDHC1_CD = IOMUX_PAD(0x04B0, 0x01A8, 6, 0x0828, 3, 0), + MX6_PAD_KEY_ROW7__TPSMP_HDATA_15 = IOMUX_PAD(0x04B0, 0x01A8, 7, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x04B4, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__USDHC4_DAT4 = IOMUX_PAD(0x04B4, 0x01AC, 1, 0x086C, 2, 0), + MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x04B4, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__WEIM_WEIM_RW = IOMUX_PAD(0x04B4, 0x01AC, 3, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__PWM4_PWMO = IOMUX_PAD(0x04B4, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO_2_15 = IOMUX_PAD(0x04B4, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__SRC_EARLY_RST = IOMUX_PAD(0x04B4, 0x01AC, 6, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__TPSMP_HTRANS_0 = IOMUX_PAD(0x04B4, 0x01AC, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT0__LCDIF_DAT_0 = IOMUX_PAD(0x04B8, 0x01B0, 0, 0x0778, 1, 0), + MX6_PAD_LCD_DAT0__ECSPI1_MOSI = IOMUX_PAD(0x04B8, 0x01B0, 1, 0x0688, 1, 0), + MX6_PAD_LCD_DAT0__ANATOP_USBOTG2_ID = IOMUX_PAD(0x04B8, 0x01B0, 2, 0x05E0, 1, 0), + MX6_PAD_LCD_DAT0__PWM1_PWMO = IOMUX_PAD(0x04B8, 0x01B0, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT0__UART5_DTR = IOMUX_PAD(0x04B8, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT0__GPIO_2_20 = IOMUX_PAD(0x04B8, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT0__KITTEN_TRACE_0 = IOMUX_PAD(0x04B8, 0x01B0, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT0__SRC_BT_CFG_0 = IOMUX_PAD(0x04B8, 0x01B0, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT1__LCDIF_DAT_1 = IOMUX_PAD(0x04BC, 0x01B4, 0, 0x077C, 1, 0), + MX6_PAD_LCD_DAT1__ECSPI1_MISO = IOMUX_PAD(0x04BC, 0x01B4, 1, 0x0684, 1, 0), + MX6_PAD_LCD_DAT1__ANATOP_USBOTG1_ID = IOMUX_PAD(0x04BC, 0x01B4, 2, 0x05DC, 2, 0), + MX6_PAD_LCD_DAT1__PWM2_PWMO = IOMUX_PAD(0x04BC, 0x01B4, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04BC, 0x01B4, 4, 0x05F0, 1, 0), + MX6_PAD_LCD_DAT1__GPIO_2_21 = IOMUX_PAD(0x04BC, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT1__KITTEN_TRACE_1 = IOMUX_PAD(0x04BC, 0x01B4, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT1__SRC_BT_CFG_1 = IOMUX_PAD(0x04BC, 0x01B4, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x04C0, 0x01B8, 0, 0x07A0, 1, 0), + MX6_PAD_LCD_DAT10__KPP_COL_1 = IOMUX_PAD(0x04C0, 0x01B8, 1, 0x0738, 1, 0), + MX6_PAD_LCD_DAT10__CSI_D_7 = IOMUX_PAD(0x04C0, 0x01B8, 2, 0x064C, 1, 0), + MX6_PAD_LCD_DAT10__WEIM_WEIM_D_4 = IOMUX_PAD(0x04C0, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT10__ECSPI2_MISO = IOMUX_PAD(0x04C0, 0x01B8, 4, 0x06A0, 2, 0), + MX6_PAD_LCD_DAT10__GPIO_2_30 = IOMUX_PAD(0x04C0, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT10__KITTEN_TRACE_10 = IOMUX_PAD(0x04C0, 0x01B8, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT10__SRC_BT_CFG_10 = IOMUX_PAD(0x04C0, 0x01B8, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT11__LCDIF_DAT_11 = IOMUX_PAD(0x04C4, 0x01BC, 0, 0x07A4, 1, 0), + MX6_PAD_LCD_DAT11__KPP_ROW_1 = IOMUX_PAD(0x04C4, 0x01BC, 1, 0x0758, 1, 0), + MX6_PAD_LCD_DAT11__CSI_D_6 = IOMUX_PAD(0x04C4, 0x01BC, 2, 0x0648, 1, 0), + MX6_PAD_LCD_DAT11__WEIM_WEIM_D_5 = IOMUX_PAD(0x04C4, 0x01BC, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT11__ECSPI2_SS1 = IOMUX_PAD(0x04C4, 0x01BC, 4, 0x06AC, 1, 0), + MX6_PAD_LCD_DAT11__GPIO_2_31 = IOMUX_PAD(0x04C4, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT11__KITTEN_TRACE_11 = IOMUX_PAD(0x04C4, 0x01BC, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT11__SRC_BT_CFG_11 = IOMUX_PAD(0x04C4, 0x01BC, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT12__LCDIF_DAT_12 = IOMUX_PAD(0x04C8, 0x01C0, 0, 0x07A8, 1, 0), + MX6_PAD_LCD_DAT12__KPP_COL_2 = IOMUX_PAD(0x04C8, 0x01C0, 1, 0x073C, 1, 0), + MX6_PAD_LCD_DAT12__CSI_D_5 = IOMUX_PAD(0x04C8, 0x01C0, 2, 0x0644, 1, 0), + MX6_PAD_LCD_DAT12__WEIM_WEIM_D_6 = IOMUX_PAD(0x04C8, 0x01C0, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT12__UART5_CTS = IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT12__UART5_RTS = IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0818, 2, 0), + MX6_PAD_LCD_DAT12__GPIO_3_0 = IOMUX_PAD(0x04C8, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT12__KITTEN_TRACE_12 = IOMUX_PAD(0x04C8, 0x01C0, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT12__SRC_BT_CFG_12 = IOMUX_PAD(0x04C8, 0x01C0, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT13__LCDIF_DAT_13 = IOMUX_PAD(0x04CC, 0x01C4, 0, 0x07AC, 1, 0), + MX6_PAD_LCD_DAT13__KPP_ROW_2 = IOMUX_PAD(0x04CC, 0x01C4, 1, 0x075C, 1, 0), + MX6_PAD_LCD_DAT13__CSI_D_4 = IOMUX_PAD(0x04CC, 0x01C4, 2, 0x0640, 1, 0), + MX6_PAD_LCD_DAT13__WEIM_WEIM_D_7 = IOMUX_PAD(0x04CC, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT13__UART5_CTS = IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT13__UART5_RTS = IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0818, 3, 0), + MX6_PAD_LCD_DAT13__GPIO_3_1 = IOMUX_PAD(0x04CC, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT13__KITTEN_TRACE_13 = IOMUX_PAD(0x04CC, 0x01C4, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT13__SRC_BT_CFG_13 = IOMUX_PAD(0x04CC, 0x01C4, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT14__LCDIF_DAT_14 = IOMUX_PAD(0x04D0, 0x01C8, 0, 0x07B0, 1, 0), + MX6_PAD_LCD_DAT14__KPP_COL_3 = IOMUX_PAD(0x04D0, 0x01C8, 1, 0x0740, 1, 0), + MX6_PAD_LCD_DAT14__CSI_D_3 = IOMUX_PAD(0x04D0, 0x01C8, 2, 0x063C, 1, 0), + MX6_PAD_LCD_DAT14__WEIM_WEIM_D_8 = IOMUX_PAD(0x04D0, 0x01C8, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT14__UART5_TXD = IOMUX_PAD(0x04D0, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT14__UART5_RXD = IOMUX_PAD(0x04D0, 0x01C8, 4, 0x081C, 2, 0), + MX6_PAD_LCD_DAT14__GPIO_3_2 = IOMUX_PAD(0x04D0, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT14__KITTEN_TRACE_14 = IOMUX_PAD(0x04D0, 0x01C8, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT14__SRC_BT_CFG_14 = IOMUX_PAD(0x04D0, 0x01C8, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT15__LCDIF_DAT_15 = IOMUX_PAD(0x04D4, 0x01CC, 0, 0x07B4, 1, 0), + MX6_PAD_LCD_DAT15__KPP_ROW_3 = IOMUX_PAD(0x04D4, 0x01CC, 1, 0x0760, 1, 0), + MX6_PAD_LCD_DAT15__CSI_D_2 = IOMUX_PAD(0x04D4, 0x01CC, 2, 0x0638, 1, 0), + MX6_PAD_LCD_DAT15__WEIM_WEIM_D_9 = IOMUX_PAD(0x04D4, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT15__UART5_TXD = IOMUX_PAD(0x04D4, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT15__UART5_RXD = IOMUX_PAD(0x04D4, 0x01CC, 4, 0x081C, 3, 0), + MX6_PAD_LCD_DAT15__GPIO_3_3 = IOMUX_PAD(0x04D4, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT15__KITTEN_TRACE_15 = IOMUX_PAD(0x04D4, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT15__SRC_BT_CFG_15 = IOMUX_PAD(0x04D4, 0x01CC, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT16__LCDIF_DAT_16 = IOMUX_PAD(0x04D8, 0x01D0, 0, 0x07B8, 1, 0), + MX6_PAD_LCD_DAT16__KPP_COL_4 = IOMUX_PAD(0x04D8, 0x01D0, 1, 0x0744, 1, 0), + MX6_PAD_LCD_DAT16__CSI_D_1 = IOMUX_PAD(0x04D8, 0x01D0, 2, 0x0634, 1, 0), + MX6_PAD_LCD_DAT16__WEIM_WEIM_D_10 = IOMUX_PAD(0x04D8, 0x01D0, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT16__I2C2_SCL = IOMUX_PAD(0x04D8, 0x01D0, 20, 0x0724, 3, 0), + MX6_PAD_LCD_DAT16__GPIO_3_4 = IOMUX_PAD(0x04D8, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT16__KITTEN_TRACE_16 = IOMUX_PAD(0x04D8, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT16__SRC_BT_CFG_24 = IOMUX_PAD(0x04D8, 0x01D0, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT17__LCDIF_DAT_17 = IOMUX_PAD(0x04DC, 0x01D4, 0, 0x07BC, 1, 0), + MX6_PAD_LCD_DAT17__KPP_ROW_4 = IOMUX_PAD(0x04DC, 0x01D4, 1, 0x0764, 1, 0), + MX6_PAD_LCD_DAT17__CSI_D_0 = IOMUX_PAD(0x04DC, 0x01D4, 2, 0x0630, 1, 0), + MX6_PAD_LCD_DAT17__WEIM_WEIM_D_11 = IOMUX_PAD(0x04DC, 0x01D4, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT17__I2C2_SDA = IOMUX_PAD(0x04DC, 0x01D4, 20, 0x0728, 3, 0), + MX6_PAD_LCD_DAT17__GPIO_3_5 = IOMUX_PAD(0x04DC, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT17__KITTEN_TRACE_17 = IOMUX_PAD(0x04DC, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT17__SRC_BT_CFG_25 = IOMUX_PAD(0x04DC, 0x01D4, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT18__LCDIF_DAT_18 = IOMUX_PAD(0x04E0, 0x01D8, 0, 0x07C0, 1, 0), + MX6_PAD_LCD_DAT18__KPP_COL_5 = IOMUX_PAD(0x04E0, 0x01D8, 1, 0x0748, 1, 0), + MX6_PAD_LCD_DAT18__CSI_D_15 = IOMUX_PAD(0x04E0, 0x01D8, 2, 0x066C, 0, 0), + MX6_PAD_LCD_DAT18__WEIM_WEIM_D_12 = IOMUX_PAD(0x04E0, 0x01D8, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT18__GPT_CAPIN1 = IOMUX_PAD(0x04E0, 0x01D8, 4, 0x0710, 1, 0), + MX6_PAD_LCD_DAT18__GPIO_3_6 = IOMUX_PAD(0x04E0, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT18__KITTEN_TRACE_18 = IOMUX_PAD(0x04E0, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT18__SRC_BT_CFG_26 = IOMUX_PAD(0x04E0, 0x01D8, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT19__LCDIF_DAT_19 = IOMUX_PAD(0x04E4, 0x01DC, 0, 0x07C4, 1, 0), + MX6_PAD_LCD_DAT19__KPP_ROW_5 = IOMUX_PAD(0x04E4, 0x01DC, 1, 0x0768, 1, 0), + MX6_PAD_LCD_DAT19__CSI_D_14 = IOMUX_PAD(0x04E4, 0x01DC, 2, 0x0668, 0, 0), + MX6_PAD_LCD_DAT19__WEIM_WEIM_D_13 = IOMUX_PAD(0x04E4, 0x01DC, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT19__GPT_CAPIN2 = IOMUX_PAD(0x04E4, 0x01DC, 4, 0x0714, 1, 0), + MX6_PAD_LCD_DAT19__GPIO_3_7 = IOMUX_PAD(0x04E4, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT19__KITTEN_TRACE_19 = IOMUX_PAD(0x04E4, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT19__SRC_BT_CFG_27 = IOMUX_PAD(0x04E4, 0x01DC, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT2__LCDIF_DAT_2 = IOMUX_PAD(0x04E8, 0x01E0, 0, 0x0780, 1, 0), + MX6_PAD_LCD_DAT2__ECSPI1_SS0 = IOMUX_PAD(0x04E8, 0x01E0, 1, 0x068C, 1, 0), + MX6_PAD_LCD_DAT2__EPIT2_EPITO = IOMUX_PAD(0x04E8, 0x01E0, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DAT2__PWM3_PWMO = IOMUX_PAD(0x04E8, 0x01E0, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT2__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04E8, 0x01E0, 4, 0x05EC, 1, 0), + MX6_PAD_LCD_DAT2__GPIO_2_22 = IOMUX_PAD(0x04E8, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT2__KITTEN_TRACE_2 = IOMUX_PAD(0x04E8, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT2__SRC_BT_CFG_2 = IOMUX_PAD(0x04E8, 0x01E0, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT20__LCDIF_DAT_20 = IOMUX_PAD(0x04EC, 0x01E4, 0, 0x07C8, 1, 0), + MX6_PAD_LCD_DAT20__KPP_COL_6 = IOMUX_PAD(0x04EC, 0x01E4, 1, 0x074C, 1, 0), + MX6_PAD_LCD_DAT20__CSI_D_13 = IOMUX_PAD(0x04EC, 0x01E4, 2, 0x0664, 0, 0), + MX6_PAD_LCD_DAT20__WEIM_WEIM_D_14 = IOMUX_PAD(0x04EC, 0x01E4, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT20__GPT_CMPOUT1 = IOMUX_PAD(0x04EC, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT20__GPIO_3_8 = IOMUX_PAD(0x04EC, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT20__KITTEN_TRACE_20 = IOMUX_PAD(0x04EC, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT20__SRC_BT_CFG_28 = IOMUX_PAD(0x04EC, 0x01E4, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT21__LCDIF_DAT_21 = IOMUX_PAD(0x04F0, 0x01E8, 0, 0x07CC, 1, 0), + MX6_PAD_LCD_DAT21__KPP_ROW_6 = IOMUX_PAD(0x04F0, 0x01E8, 1, 0x076C, 1, 0), + MX6_PAD_LCD_DAT21__CSI_D_12 = IOMUX_PAD(0x04F0, 0x01E8, 2, 0x0660, 0, 0), + MX6_PAD_LCD_DAT21__WEIM_WEIM_D_15 = IOMUX_PAD(0x04F0, 0x01E8, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT21__GPT_CMPOUT2 = IOMUX_PAD(0x04F0, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT21__GPIO_3_9 = IOMUX_PAD(0x04F0, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT21__KITTEN_TRACE_21 = IOMUX_PAD(0x04F0, 0x01E8, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT21__SRC_BT_CFG_29 = IOMUX_PAD(0x04F0, 0x01E8, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT22__LCDIF_DAT_22 = IOMUX_PAD(0x04F4, 0x01EC, 0, 0x07D0, 1, 0), + MX6_PAD_LCD_DAT22__KPP_COL_7 = IOMUX_PAD(0x04F4, 0x01EC, 1, 0x0750, 1, 0), + MX6_PAD_LCD_DAT22__CSI_D_11 = IOMUX_PAD(0x04F4, 0x01EC, 2, 0x065C, 1, 0), + MX6_PAD_LCD_DAT22__WEIM_WEIM_EB_3 = IOMUX_PAD(0x04F4, 0x01EC, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT22__GPT_CMPOUT3 = IOMUX_PAD(0x04F4, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT22__GPIO_3_10 = IOMUX_PAD(0x04F4, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT22__KITTEN_TRACE_22 = IOMUX_PAD(0x04F4, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT22__SRC_BT_CFG_30 = IOMUX_PAD(0x04F4, 0x01EC, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT23__LCDIF_DAT_23 = IOMUX_PAD(0x04F8, 0x01F0, 0, 0x07D4, 1, 0), + MX6_PAD_LCD_DAT23__KPP_ROW_7 = IOMUX_PAD(0x04F8, 0x01F0, 1, 0x0770, 1, 0), + MX6_PAD_LCD_DAT23__CSI_D_10 = IOMUX_PAD(0x04F8, 0x01F0, 2, 0x0658, 1, 0), + MX6_PAD_LCD_DAT23__WEIM_WEIM_EB_2 = IOMUX_PAD(0x04F8, 0x01F0, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT23__GPT_CLKIN = IOMUX_PAD(0x04F8, 0x01F0, 4, 0x0718, 1, 0), + MX6_PAD_LCD_DAT23__GPIO_3_11 = IOMUX_PAD(0x04F8, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT23__KITTEN_TRACE_23 = IOMUX_PAD(0x04F8, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT23__SRC_BT_CFG_31 = IOMUX_PAD(0x04F8, 0x01F0, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT3__LCDIF_DAT_3 = IOMUX_PAD(0x04FC, 0x01F4, 0, 0x0784, 1, 0), + MX6_PAD_LCD_DAT3__ECSPI1_SCLK = IOMUX_PAD(0x04FC, 0x01F4, 1, 0x067C, 1, 0), + MX6_PAD_LCD_DAT3__UART5_DSR = IOMUX_PAD(0x04FC, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DAT3__PWM4_PWMO = IOMUX_PAD(0x04FC, 0x01F4, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT3__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04FC, 0x01F4, 4, 0x05E4, 1, 0), + MX6_PAD_LCD_DAT3__GPIO_2_23 = IOMUX_PAD(0x04FC, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT3__KITTEN_TRACE_3 = IOMUX_PAD(0x04FC, 0x01F4, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT3__SRC_BT_CFG_3 = IOMUX_PAD(0x04FC, 0x01F4, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT4__LCDIF_DAT_4 = IOMUX_PAD(0x0500, 0x01F8, 0, 0x0788, 1, 0), + MX6_PAD_LCD_DAT4__ECSPI1_SS1 = IOMUX_PAD(0x0500, 0x01F8, 1, 0x0690, 1, 0), + MX6_PAD_LCD_DAT4__CSI_VSYNC = IOMUX_PAD(0x0500, 0x01F8, 2, 0x0678, 2, 0), + MX6_PAD_LCD_DAT4__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0500, 0x01F8, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0500, 0x01F8, 4, 0x05F4, 1, 0), + MX6_PAD_LCD_DAT4__GPIO_2_24 = IOMUX_PAD(0x0500, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT4__KITTEN_TRACE_4 = IOMUX_PAD(0x0500, 0x01F8, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT4__SRC_BT_CFG_4 = IOMUX_PAD(0x0500, 0x01F8, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT5__LCDIF_DAT_5 = IOMUX_PAD(0x0504, 0x01FC, 0, 0x078C, 1, 0), + MX6_PAD_LCD_DAT5__ECSPI1_SS2 = IOMUX_PAD(0x0504, 0x01FC, 1, 0x0694, 1, 0), + MX6_PAD_LCD_DAT5__CSI_HSYNC = IOMUX_PAD(0x0504, 0x01FC, 2, 0x0670, 2, 0), + MX6_PAD_LCD_DAT5__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0504, 0x01FC, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT5__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0504, 0x01FC, 4, 0x05F8, 1, 0), + MX6_PAD_LCD_DAT5__GPIO_2_25 = IOMUX_PAD(0x0504, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT5__KITTEN_TRACE_5 = IOMUX_PAD(0x0504, 0x01FC, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT5__SRC_BT_CFG_5 = IOMUX_PAD(0x0504, 0x01FC, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT6__LCDIF_DAT_6 = IOMUX_PAD(0x0508, 0x0200, 0, 0x0790, 1, 0), + MX6_PAD_LCD_DAT6__ECSPI1_SS3 = IOMUX_PAD(0x0508, 0x0200, 1, 0x0698, 1, 0), + MX6_PAD_LCD_DAT6__CSI_PIXCLK = IOMUX_PAD(0x0508, 0x0200, 2, 0x0674, 2, 0), + MX6_PAD_LCD_DAT6__WEIM_WEIM_D_0 = IOMUX_PAD(0x0508, 0x0200, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT6__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0508, 0x0200, 4, 0x05E8, 1, 0), + MX6_PAD_LCD_DAT6__GPIO_2_26 = IOMUX_PAD(0x0508, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT6__KITTEN_TRACE_6 = IOMUX_PAD(0x0508, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT6__SRC_BT_CFG_6 = IOMUX_PAD(0x0508, 0x0200, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT7__LCDIF_DAT_7 = IOMUX_PAD(0x050C, 0x0204, 0, 0x0794, 1, 0), + MX6_PAD_LCD_DAT7__ECSPI1_RDY = IOMUX_PAD(0x050C, 0x0204, 1, 0x0680, 1, 0), + MX6_PAD_LCD_DAT7__CSI_MCLK = IOMUX_PAD(0x050C, 0x0204, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DAT7__WEIM_WEIM_D_1 = IOMUX_PAD(0x050C, 0x0204, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT7__AUDMUX_AUDIO_CLK_OUT = IOMUX_PAD(0x050C, 0x0204, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DAT7__GPIO_2_27 = IOMUX_PAD(0x050C, 0x0204, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT7__KITTEN_TRACE_7 = IOMUX_PAD(0x050C, 0x0204, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT7__SRC_BT_CFG_7 = IOMUX_PAD(0x050C, 0x0204, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT8__LCDIF_DAT_8 = IOMUX_PAD(0x0510, 0x0208, 0, 0x0798, 1, 0), + MX6_PAD_LCD_DAT8__KPP_COL_0 = IOMUX_PAD(0x0510, 0x0208, 1, 0x0734, 1, 0), + MX6_PAD_LCD_DAT8__CSI_D_9 = IOMUX_PAD(0x0510, 0x0208, 2, 0x0654, 1, 0), + MX6_PAD_LCD_DAT8__WEIM_WEIM_D_2 = IOMUX_PAD(0x0510, 0x0208, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0510, 0x0208, 4, 0x069C, 2, 0), + MX6_PAD_LCD_DAT8__GPIO_2_28 = IOMUX_PAD(0x0510, 0x0208, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT8__KITTEN_TRACE_8 = IOMUX_PAD(0x0510, 0x0208, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT8__SRC_BT_CFG_8 = IOMUX_PAD(0x0510, 0x0208, 7, 0x0000, 0, 0), + MX6_PAD_LCD_DAT9__LCDIF_DAT_9 = IOMUX_PAD(0x0514, 0x020C, 0, 0x079C, 1, 0), + MX6_PAD_LCD_DAT9__KPP_ROW_0 = IOMUX_PAD(0x0514, 0x020C, 1, 0x0754, 1, 0), + MX6_PAD_LCD_DAT9__CSI_D_8 = IOMUX_PAD(0x0514, 0x020C, 2, 0x0650, 1, 0), + MX6_PAD_LCD_DAT9__WEIM_WEIM_D_3 = IOMUX_PAD(0x0514, 0x020C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x0514, 0x020C, 4, 0x06A4, 2, 0), + MX6_PAD_LCD_DAT9__GPIO_2_29 = IOMUX_PAD(0x0514, 0x020C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DAT9__KITTEN_TRACE_9 = IOMUX_PAD(0x0514, 0x020C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DAT9__SRC_BT_CFG_9 = IOMUX_PAD(0x0514, 0x020C, 7, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0518, 0x0210, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__USDHC4_DAT5 = IOMUX_PAD(0x0518, 0x0210, 1, 0x0870, 2, 0), + MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0518, 0x0210, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__WEIM_WEIM_OE = IOMUX_PAD(0x0518, 0x0210, 3, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART2_TXD = IOMUX_PAD(0x0518, 0x0210, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART2_RXD = IOMUX_PAD(0x0518, 0x0210, 4, 0x0804, 2, 0), + MX6_PAD_LCD_ENABLE__GPIO_2_16 = IOMUX_PAD(0x0518, 0x0210, 5, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__OCOTP_CTRL_WRAPPER_FUSE_LATCHED = IOMUX_PAD(0x0518, 0x0210, 6, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__TPSMP_HTRANS_1 = IOMUX_PAD(0x0518, 0x0210, 7, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x051C, 0x0214, 0, 0x0774, 0, 0), + MX6_PAD_LCD_HSYNC__USDHC4_DAT6 = IOMUX_PAD(0x051C, 0x0214, 1, 0x0874, 2, 0), + MX6_PAD_LCD_HSYNC__LCDIF_CS = IOMUX_PAD(0x051C, 0x0214, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__WEIM_WEIM_CS_0 = IOMUX_PAD(0x051C, 0x0214, 3, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART2_TXD = IOMUX_PAD(0x051C, 0x0214, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART2_RXD = IOMUX_PAD(0x051C, 0x0214, 4, 0x0804, 3, 0), + MX6_PAD_LCD_HSYNC__GPIO_2_17 = IOMUX_PAD(0x051C, 0x0214, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__KITTEN_TRCLK = IOMUX_PAD(0x051C, 0x0214, 6, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__TPSMP_HDATA_16 = IOMUX_PAD(0x051C, 0x0214, 7, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x0520, 0x0218, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0520, 0x0218, 1, 0x0880, 1, 0), + MX6_PAD_LCD_RESET__LCDIF_BUSY = IOMUX_PAD(0x0520, 0x0218, 2, 0x0774, 1, 0), + MX6_PAD_LCD_RESET__WEIM_WEIM_WAIT = IOMUX_PAD(0x0520, 0x0218, 3, 0x0884, 1, 0), + MX6_PAD_LCD_RESET__UART2_CTS = IOMUX_PAD(0x0520, 0x0218, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__UART2_RTS = IOMUX_PAD(0x0520, 0x0218, 4, 0x0800, 2, 0), + MX6_PAD_LCD_RESET__GPIO_2_19 = IOMUX_PAD(0x0520, 0x0218, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CCM_PMIC_RDY = IOMUX_PAD(0x0520, 0x0218, 6, 0x062C, 1, 0), + MX6_PAD_LCD_RESET__TPSMP_HDATA_DIR = IOMUX_PAD(0x0520, 0x0218, 7, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x0524, 0x021C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__USDHC4_DAT7 = IOMUX_PAD(0x0524, 0x021C, 1, 0x0878, 2, 0), + MX6_PAD_LCD_VSYNC__LCDIF_RS = IOMUX_PAD(0x0524, 0x021C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0524, 0x021C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__UART2_CTS = IOMUX_PAD(0x0524, 0x021C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__UART2_RTS = IOMUX_PAD(0x0524, 0x021C, 4, 0x0800, 3, 0), + MX6_PAD_LCD_VSYNC__GPIO_2_18 = IOMUX_PAD(0x0524, 0x021C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__KITTEN_TRCTL = IOMUX_PAD(0x0524, 0x021C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__TPSMP_HDATA_17 = IOMUX_PAD(0x0524, 0x021C, 7, 0x0000, 0, 0), + MX6_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_PWM1__PWM1_PWMO = IOMUX_PAD(0x0528, 0x0220, 0, 0x0000, 0, 0), + MX6_PAD_PWM1__CCM_CLKO = IOMUX_PAD(0x0528, 0x0220, 1, 0x0000, 0, 0), + MX6_PAD_PWM1__AUDMUX_AUDIO_CLK_OUT = IOMUX_PAD(0x0528, 0x0220, 2, 0x0000, 0, 0), + MX6_PAD_PWM1__FEC_REF_OUT = IOMUX_PAD(0x0528, 0x0220, 3, 0x0000, 0, 0), + MX6_PAD_PWM1__CSI_MCLK = IOMUX_PAD(0x0528, 0x0220, 4, 0x0000, 0, 0), + MX6_PAD_PWM1__GPIO_3_23 = IOMUX_PAD(0x0528, 0x0220, 5, 0x0000, 0, 0), + MX6_PAD_PWM1__EPIT1_EPITO = IOMUX_PAD(0x0528, 0x0220, 6, 0x0000, 0, 0), + MX6_PAD_PWM1__OBSERVE_MUX_OUT_4 = IOMUX_PAD(0x0528, 0x0220, 7, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__ANATOP_ANATOP_24M_OUT = IOMUX_PAD(0x052C, 0x0224, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__I2C3_SCL = IOMUX_PAD(0x052C, 0x0224, 17, 0x072C, 2, 0), + MX6_PAD_REF_CLK_24M__PWM3_PWMO = IOMUX_PAD(0x052C, 0x0224, 2, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__ANATOP_USBOTG2_ID = IOMUX_PAD(0x052C, 0x0224, 3, 0x05E0, 2, 0), + MX6_PAD_REF_CLK_24M__CCM_PMIC_RDY = IOMUX_PAD(0x052C, 0x0224, 4, 0x062C, 2, 0), + MX6_PAD_REF_CLK_24M__GPIO_3_21 = IOMUX_PAD(0x052C, 0x0224, 5, 0x0000, 0, 0), + MX6_PAD_REF_CLK_24M__USDHC3_WP = IOMUX_PAD(0x052C, 0x0224, 6, 0x084C, 3, 0), + MX6_PAD_REF_CLK_24M__TPSMP_HDATA_19 = IOMUX_PAD(0x052C, 0x0224, 7, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0530, 0x0228, 0, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__I2C3_SDA = IOMUX_PAD(0x0530, 0x0228, 17, 0x0730, 2, 0), + MX6_PAD_REF_CLK_32K__PWM4_PWMO = IOMUX_PAD(0x0530, 0x0228, 2, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__ANATOP_USBOTG1_ID = IOMUX_PAD(0x0530, 0x0228, 3, 0x05DC, 3, 0), + MX6_PAD_REF_CLK_32K__USDHC1_LCTL = IOMUX_PAD(0x0530, 0x0228, 4, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0), + MX6_PAD_REF_CLK_32K__USDHC3_CD = IOMUX_PAD(0x0530, 0x0228, 6, 0x0838, 3, 0), + MX6_PAD_REF_CLK_32K__OBSERVE_MUX_OUT_3 = IOMUX_PAD(0x0530, 0x0228, 7, 0x0000, 0, 0), + MX6_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__FEC_MDIO = IOMUX_PAD(0x0534, 0x022C, 1, 0x06F4, 2, 0), + MX6_PAD_SD1_CLK__KPP_COL_0 = IOMUX_PAD(0x0534, 0x022C, 2, 0x0734, 2, 0), + MX6_PAD_SD1_CLK__EPDC_SDCE_4 = IOMUX_PAD(0x0534, 0x022C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__MSHC_SCLK = IOMUX_PAD(0x0534, 0x022C, 4, 0x07E8, 1, 0), + MX6_PAD_SD1_CLK__GPIO_5_15 = IOMUX_PAD(0x0534, 0x022C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__ANATOP_ANATOP_TESTO_2 = IOMUX_PAD(0x0534, 0x022C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__PL301_SIM_MX6_PER1_HADDR_25 = IOMUX_PAD(0x0534, 0x022C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__FEC_TX_CLK = IOMUX_PAD(0x0538, 0x0230, 1, 0x070C, 2, 0), + MX6_PAD_SD1_CMD__KPP_ROW_0 = IOMUX_PAD(0x0538, 0x0230, 2, 0x0754, 2, 0), + MX6_PAD_SD1_CMD__EPDC_SDCE_5 = IOMUX_PAD(0x0538, 0x0230, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__MSHC_BS = IOMUX_PAD(0x0538, 0x0230, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO_5_14 = IOMUX_PAD(0x0538, 0x0230, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_3 = IOMUX_PAD(0x0538, 0x0230, 6, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__PL301_SIM_MX6_PER1_HADDR_26 = IOMUX_PAD(0x0538, 0x0230, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__FEC_RX_ER = IOMUX_PAD(0x053C, 0x0234, 1, 0x0708, 2, 0), + MX6_PAD_SD1_DAT0__KPP_COL_1 = IOMUX_PAD(0x053C, 0x0234, 2, 0x0738, 2, 0), + MX6_PAD_SD1_DAT0__EPDC_SDCE_6 = IOMUX_PAD(0x053C, 0x0234, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__MSHC_DATA_0 = IOMUX_PAD(0x053C, 0x0234, 4, 0x07D8, 1, 0), + MX6_PAD_SD1_DAT0__GPIO_5_11 = IOMUX_PAD(0x053C, 0x0234, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_4 = IOMUX_PAD(0x053C, 0x0234, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT0__PL301_SIM_MX6_PER1_HADDR_27 = IOMUX_PAD(0x053C, 0x0234, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__FEC_RX_DV = IOMUX_PAD(0x0540, 0x0238, 1, 0x0704, 2, 0), + MX6_PAD_SD1_DAT1__KPP_ROW_1 = IOMUX_PAD(0x0540, 0x0238, 2, 0x0758, 2, 0), + MX6_PAD_SD1_DAT1__EPDC_SDCE_7 = IOMUX_PAD(0x0540, 0x0238, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__MSHC_DATA_1 = IOMUX_PAD(0x0540, 0x0238, 4, 0x07DC, 1, 0), + MX6_PAD_SD1_DAT1__GPIO_5_8 = IOMUX_PAD(0x0540, 0x0238, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_5 = IOMUX_PAD(0x0540, 0x0238, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT1__PL301_SIM_MX6_PER1_HADDR_28 = IOMUX_PAD(0x0540, 0x0238, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__FEC_RDATA_1 = IOMUX_PAD(0x0544, 0x023C, 1, 0x06FC, 2, 0), + MX6_PAD_SD1_DAT2__KPP_COL_2 = IOMUX_PAD(0x0544, 0x023C, 2, 0x073C, 2, 0), + MX6_PAD_SD1_DAT2__EPDC_SDCE_8 = IOMUX_PAD(0x0544, 0x023C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__MSHC_DATA_2 = IOMUX_PAD(0x0544, 0x023C, 4, 0x07E0, 1, 0), + MX6_PAD_SD1_DAT2__GPIO_5_13 = IOMUX_PAD(0x0544, 0x023C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_6 = IOMUX_PAD(0x0544, 0x023C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT2__PL301_SIM_MX6_PER1_HADDR_29 = IOMUX_PAD(0x0544, 0x023C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__FEC_TDATA_0 = IOMUX_PAD(0x0548, 0x0240, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__KPP_ROW_2 = IOMUX_PAD(0x0548, 0x0240, 2, 0x075C, 2, 0), + MX6_PAD_SD1_DAT3__EPDC_SDCE_9 = IOMUX_PAD(0x0548, 0x0240, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__MSHC_DATA_3 = IOMUX_PAD(0x0548, 0x0240, 4, 0x07E4, 1, 0), + MX6_PAD_SD1_DAT3__GPIO_5_6 = IOMUX_PAD(0x0548, 0x0240, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_7 = IOMUX_PAD(0x0548, 0x0240, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT3__PL301_SIM_MX6_PER1_HADDR_30 = IOMUX_PAD(0x0548, 0x0240, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__FEC_MDC = IOMUX_PAD(0x054C, 0x0244, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__KPP_COL_3 = IOMUX_PAD(0x054C, 0x0244, 2, 0x0740, 2, 0), + MX6_PAD_SD1_DAT4__EPDC_SDCLKN = IOMUX_PAD(0x054C, 0x0244, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__UART4_TXD = IOMUX_PAD(0x054C, 0x0244, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__UART4_RXD = IOMUX_PAD(0x054C, 0x0244, 4, 0x0814, 4, 0), + MX6_PAD_SD1_DAT4__GPIO_5_12 = IOMUX_PAD(0x054C, 0x0244, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__ANATOP_ANATOP_TESTO_8 = IOMUX_PAD(0x054C, 0x0244, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT4__PL301_SIM_MX6_PER1_HADDR_31 = IOMUX_PAD(0x054C, 0x0244, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__FEC_RDATA_0 = IOMUX_PAD(0x0550, 0x0248, 1, 0x06F8, 2, 0), + MX6_PAD_SD1_DAT5__KPP_ROW_3 = IOMUX_PAD(0x0550, 0x0248, 2, 0x0760, 2, 0), + MX6_PAD_SD1_DAT5__EPDC_SDOED = IOMUX_PAD(0x0550, 0x0248, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__UART4_TXD = IOMUX_PAD(0x0550, 0x0248, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__UART4_RXD = IOMUX_PAD(0x0550, 0x0248, 4, 0x0814, 5, 0), + MX6_PAD_SD1_DAT5__GPIO_5_9 = IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__ANATOP_ANATOP_TESTO_9 = IOMUX_PAD(0x0550, 0x0248, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT5__PL301_SIM_MX6_PER1_HPROT_3 = IOMUX_PAD(0x0550, 0x0248, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__FEC_TX_EN = IOMUX_PAD(0x0554, 0x024C, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__KPP_COL_4 = IOMUX_PAD(0x0554, 0x024C, 2, 0x0744, 2, 0), + MX6_PAD_SD1_DAT6__EPDC_SDOEZ = IOMUX_PAD(0x0554, 0x024C, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__UART4_CTS = IOMUX_PAD(0x0554, 0x024C, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__UART4_RTS = IOMUX_PAD(0x0554, 0x024C, 4, 0x0810, 4, 0), + MX6_PAD_SD1_DAT6__GPIO_5_7 = IOMUX_PAD(0x0554, 0x024C, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__ANATOP_ANATOP_TESTO_10 = IOMUX_PAD(0x0554, 0x024C, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT6__PL301_SIM_MX6_PER1_HPROT_2 = IOMUX_PAD(0x0554, 0x024C, 7, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__FEC_TDATA_1 = IOMUX_PAD(0x0558, 0x0250, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__KPP_ROW_4 = IOMUX_PAD(0x0558, 0x0250, 2, 0x0764, 2, 0), + MX6_PAD_SD1_DAT7__CCM_PMIC_RDY = IOMUX_PAD(0x0558, 0x0250, 3, 0x062C, 3, 0), + MX6_PAD_SD1_DAT7__UART4_CTS = IOMUX_PAD(0x0558, 0x0250, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__UART4_RTS = IOMUX_PAD(0x0558, 0x0250, 4, 0x0810, 5, 0), + MX6_PAD_SD1_DAT7__GPIO_5_10 = IOMUX_PAD(0x0558, 0x0250, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__ANATOP_ANATOP_TESTO_11 = IOMUX_PAD(0x0558, 0x0250, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DAT7__PL301_SIM_MX6_PER1_HMASTLOCK = IOMUX_PAD(0x0558, 0x0250, 7, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x055C, 0x0254, 1, 0x05F0, 2, 0), + MX6_PAD_SD2_CLK__ECSPI3_SCLK = IOMUX_PAD(0x055C, 0x0254, 2, 0x06B0, 2, 0), + MX6_PAD_SD2_CLK__CSI_D_0 = IOMUX_PAD(0x055C, 0x0254, 3, 0x0630, 2, 0), + MX6_PAD_SD2_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x055C, 0x0254, 4, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__GPIO_5_5 = IOMUX_PAD(0x055C, 0x0254, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__ANATOP_ANATOP_TESTO_13 = IOMUX_PAD(0x055C, 0x0254, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CLK__PL301_SIM_MX6_PER1_HPROT_1 = IOMUX_PAD(0x055C, 0x0254, 7, 0x07EC, 1, 0), + MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0560, 0x0258, 1, 0x05EC, 2, 0), + MX6_PAD_SD2_CMD__ECSPI3_SS0 = IOMUX_PAD(0x0560, 0x0258, 2, 0x06C0, 2, 0), + MX6_PAD_SD2_CMD__CSI_D_1 = IOMUX_PAD(0x0560, 0x0258, 3, 0x0634, 2, 0), + MX6_PAD_SD2_CMD__EPIT1_EPITO = IOMUX_PAD(0x0560, 0x0258, 4, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__GPIO_5_4 = IOMUX_PAD(0x0560, 0x0258, 5, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__ANATOP_ANATOP_TESTO_14 = IOMUX_PAD(0x0560, 0x0258, 6, 0x0000, 0, 0), + MX6_PAD_SD2_CMD__PL301_SIM_MX6_PER1_HADDR_21 = IOMUX_PAD(0x0560, 0x0258, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0564, 0x025C, 1, 0x05E4, 2, 0), + MX6_PAD_SD2_DAT0__ECSPI3_MOSI = IOMUX_PAD(0x0564, 0x025C, 2, 0x06BC, 2, 0), + MX6_PAD_SD2_DAT0__CSI_D_2 = IOMUX_PAD(0x0564, 0x025C, 3, 0x0638, 2, 0), + MX6_PAD_SD2_DAT0__UART5_CTS = IOMUX_PAD(0x0564, 0x025C, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__UART5_RTS = IOMUX_PAD(0x0564, 0x025C, 4, 0x0818, 4, 0), + MX6_PAD_SD2_DAT0__GPIO_5_1 = IOMUX_PAD(0x0564, 0x025C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_15 = IOMUX_PAD(0x0564, 0x025C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT0__PL301_SIM_MX6_PER1_HPROT_0 = IOMUX_PAD(0x0564, 0x025C, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0568, 0x0260, 1, 0x05F4, 2, 0), + MX6_PAD_SD2_DAT1__ECSPI3_MISO = IOMUX_PAD(0x0568, 0x0260, 2, 0x06B8, 2, 0), + MX6_PAD_SD2_DAT1__CSI_D_3 = IOMUX_PAD(0x0568, 0x0260, 3, 0x063C, 2, 0), + MX6_PAD_SD2_DAT1__UART5_CTS = IOMUX_PAD(0x0568, 0x0260, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__UART5_RTS = IOMUX_PAD(0x0568, 0x0260, 4, 0x0818, 5, 0), + MX6_PAD_SD2_DAT1__GPIO_4_30 = IOMUX_PAD(0x0568, 0x0260, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0568, 0x0260, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT1__PL301_SIM_MX6_PER1_HBURST_1 = IOMUX_PAD(0x0568, 0x0260, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x056C, 0x0264, 1, 0x05F8, 2, 0), + MX6_PAD_SD2_DAT2__FEC_COL = IOMUX_PAD(0x056C, 0x0264, 2, 0x06F0, 1, 0), + MX6_PAD_SD2_DAT2__CSI_D_4 = IOMUX_PAD(0x056C, 0x0264, 3, 0x0640, 2, 0), + MX6_PAD_SD2_DAT2__UART5_TXD = IOMUX_PAD(0x056C, 0x0264, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__UART5_RXD = IOMUX_PAD(0x056C, 0x0264, 4, 0x081C, 4, 0), + MX6_PAD_SD2_DAT2__GPIO_5_3 = IOMUX_PAD(0x056C, 0x0264, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x056C, 0x0264, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT2__PL301_SIM_MX6_PER1_HADDR_22 = IOMUX_PAD(0x056C, 0x0264, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0570, 0x0268, 1, 0x05E8, 2, 0), + MX6_PAD_SD2_DAT3__FEC_RX_CLK = IOMUX_PAD(0x0570, 0x0268, 2, 0x0700, 1, 0), + MX6_PAD_SD2_DAT3__CSI_D_5 = IOMUX_PAD(0x0570, 0x0268, 3, 0x0644, 2, 0), + MX6_PAD_SD2_DAT3__UART5_TXD = IOMUX_PAD(0x0570, 0x0268, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__UART5_RXD = IOMUX_PAD(0x0570, 0x0268, 4, 0x081C, 5, 0), + MX6_PAD_SD2_DAT3__GPIO_4_28 = IOMUX_PAD(0x0570, 0x0268, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0570, 0x0268, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT3__PL301_SIM_MX6_PER1_HBURST_0 = IOMUX_PAD(0x0570, 0x0268, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__USDHC2_DAT4 = IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x0574, 0x026C, 1, 0x083C, 1, 0), + MX6_PAD_SD2_DAT4__UART2_TXD = IOMUX_PAD(0x0574, 0x026C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__UART2_RXD = IOMUX_PAD(0x0574, 0x026C, 2, 0x0804, 4, 0), + MX6_PAD_SD2_DAT4__CSI_D_6 = IOMUX_PAD(0x0574, 0x026C, 3, 0x0648, 2, 0), + MX6_PAD_SD2_DAT4__SPDIF_OUT1 = IOMUX_PAD(0x0574, 0x026C, 4, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__GPIO_5_2 = IOMUX_PAD(0x0574, 0x026C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x0574, 0x026C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT4__PL301_SIM_MX6_PER1_HADDR_10 = IOMUX_PAD(0x0574, 0x026C, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT5__USDHC2_DAT5 = IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0578, 0x0270, 1, 0x0840, 1, 0), + MX6_PAD_SD2_DAT5__UART2_TXD = IOMUX_PAD(0x0578, 0x0270, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT5__UART2_RXD = IOMUX_PAD(0x0578, 0x0270, 2, 0x0804, 5, 0), + MX6_PAD_SD2_DAT5__CSI_D_7 = IOMUX_PAD(0x0578, 0x0270, 3, 0x064C, 2, 0), + MX6_PAD_SD2_DAT5__SPDIF_IN1 = IOMUX_PAD(0x0578, 0x0270, 4, 0x07F0, 2, 0), + MX6_PAD_SD2_DAT5__GPIO_4_31 = IOMUX_PAD(0x0578, 0x0270, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT5__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0578, 0x0270, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT5__PL301_SIM_MX6_PER1_HADDR_20 = IOMUX_PAD(0x0578, 0x0270, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT6__USDHC2_DAT6 = IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x057C, 0x0274, 1, 0x0844, 1, 0), + MX6_PAD_SD2_DAT6__UART2_CTS = IOMUX_PAD(0x057C, 0x0274, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT6__UART2_RTS = IOMUX_PAD(0x057C, 0x0274, 2, 0x0800, 4, 0), + MX6_PAD_SD2_DAT6__CSI_D_8 = IOMUX_PAD(0x057C, 0x0274, 3, 0x0650, 2, 0), + MX6_PAD_SD2_DAT6__USDHC2_WP = IOMUX_PAD(0x057C, 0x0274, 4, 0x0834, 2, 0), + MX6_PAD_SD2_DAT6__GPIO_4_29 = IOMUX_PAD(0x057C, 0x0274, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT6__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x057C, 0x0274, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT6__PL301_SIM_MX6_PER1_HADDR_19 = IOMUX_PAD(0x057C, 0x0274, 7, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__USDHC2_DAT7 = IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0580, 0x0278, 1, 0x0848, 1, 0), + MX6_PAD_SD2_DAT7__UART2_CTS = IOMUX_PAD(0x0580, 0x0278, 2, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__UART2_RTS = IOMUX_PAD(0x0580, 0x0278, 2, 0x0800, 5, 0), + MX6_PAD_SD2_DAT7__CSI_D_9 = IOMUX_PAD(0x0580, 0x0278, 3, 0x0654, 2, 0), + MX6_PAD_SD2_DAT7__USDHC2_CD = IOMUX_PAD(0x0580, 0x0278, 4, 0x0830, 2, 0), + MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0580, 0x0278, 6, 0x0000, 0, 0), + MX6_PAD_SD2_DAT7__PL301_SIM_MX6_PER1_HADDR_16 = IOMUX_PAD(0x0580, 0x0278, 7, 0x0000, 0, 0), + MX6_PAD_SD2_RST__USDHC2_RST = IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0), + MX6_PAD_SD2_RST__FEC_REF_OUT = IOMUX_PAD(0x0584, 0x027C, 1, 0x0000, 0, 0), + MX6_PAD_SD2_RST__WDOG2_WDOG_B = IOMUX_PAD(0x0584, 0x027C, 2, 0x0000, 0, 0), + MX6_PAD_SD2_RST__SPDIF_OUT1 = IOMUX_PAD(0x0584, 0x027C, 3, 0x0000, 0, 0), + MX6_PAD_SD2_RST__CSI_MCLK = IOMUX_PAD(0x0584, 0x027C, 4, 0x0000, 0, 0), + MX6_PAD_SD2_RST__GPIO_4_27 = IOMUX_PAD(0x0584, 0x027C, 5, 0x0000, 0, 0), + MX6_PAD_SD2_RST__ANATOP_ANATOP_TESTO_12 = IOMUX_PAD(0x0584, 0x027C, 6, 0x0000, 0, 0), + MX6_PAD_SD2_RST__PL301_SIM_MX6_PER1_HBURST_2 = IOMUX_PAD(0x0584, 0x027C, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0588, 0x0280, 1, 0x0608, 1, 0), + MX6_PAD_SD3_CLK__KPP_COL_5 = IOMUX_PAD(0x0588, 0x0280, 2, 0x0748, 2, 0), + MX6_PAD_SD3_CLK__CSI_D_10 = IOMUX_PAD(0x0588, 0x0280, 3, 0x0658, 2, 0), + MX6_PAD_SD3_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0588, 0x0280, 4, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__GPIO_5_18 = IOMUX_PAD(0x0588, 0x0280, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__USB_USBOTG1_PWR = IOMUX_PAD(0x0588, 0x0280, 6, 0x0000, 0, 0), + MX6_PAD_SD3_CLK__PL301_SIM_MX6_PER1_HADDR_13 = IOMUX_PAD(0x0588, 0x0280, 7, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__AUDMUX_AUD5_RXC = IOMUX_PAD(0x058C, 0x0284, 1, 0x0604, 1, 0), + MX6_PAD_SD3_CMD__KPP_ROW_5 = IOMUX_PAD(0x058C, 0x0284, 2, 0x0768, 2, 0), + MX6_PAD_SD3_CMD__CSI_D_11 = IOMUX_PAD(0x058C, 0x0284, 3, 0x065C, 2, 0), + MX6_PAD_SD3_CMD__ANATOP_USBOTG2_ID = IOMUX_PAD(0x058C, 0x0284, 4, 0x05E0, 3, 0), + MX6_PAD_SD3_CMD__GPIO_5_21 = IOMUX_PAD(0x058C, 0x0284, 5, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__USB_USBOTG2_PWR = IOMUX_PAD(0x058C, 0x0284, 6, 0x0000, 0, 0), + MX6_PAD_SD3_CMD__PL301_SIM_MX6_PER1_HADDR_18 = IOMUX_PAD(0x058C, 0x0284, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0590, 0x0288, 1, 0x05FC, 1, 0), + MX6_PAD_SD3_DAT0__KPP_COL_6 = IOMUX_PAD(0x0590, 0x0288, 2, 0x074C, 2, 0), + MX6_PAD_SD3_DAT0__CSI_D_12 = IOMUX_PAD(0x0590, 0x0288, 3, 0x0660, 1, 0), + MX6_PAD_SD3_DAT0__ANATOP_USBOTG1_ID = IOMUX_PAD(0x0590, 0x0288, 4, 0x05DC, 4, 0), + MX6_PAD_SD3_DAT0__GPIO_5_19 = IOMUX_PAD(0x0590, 0x0288, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__SJC_JTAG_ACT = IOMUX_PAD(0x0590, 0x0288, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT0__PL301_SIM_MX6_PER1_HADDR_11 = IOMUX_PAD(0x0590, 0x0288, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__AUDMUX_AUD5_TXC = IOMUX_PAD(0x0594, 0x028C, 1, 0x060C, 1, 0), + MX6_PAD_SD3_DAT1__KPP_ROW_6 = IOMUX_PAD(0x0594, 0x028C, 2, 0x076C, 2, 0), + MX6_PAD_SD3_DAT1__CSI_D_13 = IOMUX_PAD(0x0594, 0x028C, 3, 0x0664, 1, 0), + MX6_PAD_SD3_DAT1__USDHC1_VSELECT = IOMUX_PAD(0x0594, 0x028C, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__GPIO_5_20 = IOMUX_PAD(0x0594, 0x028C, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__SJC_DE_B = IOMUX_PAD(0x0594, 0x028C, 6, 0x0000, 0, 0), + MX6_PAD_SD3_DAT1__PL301_SIM_MX6_PER1_HADDR_17 = IOMUX_PAD(0x0594, 0x028C, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x0598, 0x0290, 1, 0x0610, 1, 0), + MX6_PAD_SD3_DAT2__KPP_COL_7 = IOMUX_PAD(0x0598, 0x0290, 2, 0x0750, 2, 0), + MX6_PAD_SD3_DAT2__CSI_D_14 = IOMUX_PAD(0x0598, 0x0290, 3, 0x0668, 1, 0), + MX6_PAD_SD3_DAT2__EPIT1_EPITO = IOMUX_PAD(0x0598, 0x0290, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__GPIO_5_16 = IOMUX_PAD(0x0598, 0x0290, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT2__USB_USBOTG2_OC = IOMUX_PAD(0x0598, 0x0290, 6, 0x0820, 3, 0), + MX6_PAD_SD3_DAT2__PL301_SIM_MX6_PER1_HADDR_14 = IOMUX_PAD(0x0598, 0x0290, 7, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__AUDMUX_AUD5_TXD = IOMUX_PAD(0x059C, 0x0294, 1, 0x0600, 1, 0), + MX6_PAD_SD3_DAT3__KPP_ROW_7 = IOMUX_PAD(0x059C, 0x0294, 2, 0x0770, 2, 0), + MX6_PAD_SD3_DAT3__CSI_D_15 = IOMUX_PAD(0x059C, 0x0294, 3, 0x066C, 1, 0), + MX6_PAD_SD3_DAT3__EPIT2_EPITO = IOMUX_PAD(0x059C, 0x0294, 4, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__GPIO_5_17 = IOMUX_PAD(0x059C, 0x0294, 5, 0x0000, 0, 0), + MX6_PAD_SD3_DAT3__USB_USBOTG1_OC = IOMUX_PAD(0x059C, 0x0294, 6, 0x0824, 2, 0), + MX6_PAD_SD3_DAT3__PL301_SIM_MX6_PER1_HADDR_12 = IOMUX_PAD(0x059C, 0x0294, 7, 0x0000, 0, 0), + MX6_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART1_TXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0), + MX6_PAD_UART1_RXD__PWM1_PWMO = IOMUX_PAD(0x05A0, 0x0298, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART4_TXD = IOMUX_PAD(0x05A0, 0x0298, 2, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART4_RXD = IOMUX_PAD(0x05A0, 0x0298, 2, 0x0814, 6, 0), + MX6_PAD_UART1_RXD__FEC_COL = IOMUX_PAD(0x05A0, 0x0298, 3, 0x06F0, 2, 0), + MX6_PAD_UART1_RXD__UART5_TXD = IOMUX_PAD(0x05A0, 0x0298, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__UART5_RXD = IOMUX_PAD(0x05A0, 0x0298, 4, 0x081C, 6, 0), + MX6_PAD_UART1_RXD__GPIO_3_16 = IOMUX_PAD(0x05A0, 0x0298, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__ANATOP_ANATOP_TESTI_2 = IOMUX_PAD(0x05A0, 0x0298, 6, 0x0000, 0, 0), + MX6_PAD_UART1_RXD__TPSMP_CLK = IOMUX_PAD(0x05A0, 0x0298, 7, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART1_RXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x07FC, 1, 0), + MX6_PAD_UART1_TXD__PWM2_PWMO = IOMUX_PAD(0x05A4, 0x029C, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART4_TXD = IOMUX_PAD(0x05A4, 0x029C, 2, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART4_RXD = IOMUX_PAD(0x05A4, 0x029C, 2, 0x0814, 7, 0), + MX6_PAD_UART1_TXD__FEC_RX_CLK = IOMUX_PAD(0x05A4, 0x029C, 3, 0x0700, 2, 0), + MX6_PAD_UART1_TXD__UART5_TXD = IOMUX_PAD(0x05A4, 0x029C, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART5_RXD = IOMUX_PAD(0x05A4, 0x029C, 4, 0x081C, 7, 0), + MX6_PAD_UART1_TXD__GPIO_3_17 = IOMUX_PAD(0x05A4, 0x029C, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x05A4, 0x029C, 6, 0x0000, 0, 0), + MX6_PAD_UART1_TXD__UART5_DCD = IOMUX_PAD(0x05A4, 0x029C, 7, 0x0000, 0, 0), + MX6_PAD_WDOG_B__WDOG1_WDOG_B = IOMUX_PAD(0x05A8, 0x02A0, 0, 0x0000, 0, 0), + MX6_PAD_WDOG_B__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x05A8, 0x02A0, 1, 0x0000, 0, 0), + MX6_PAD_WDOG_B__UART5_RI = IOMUX_PAD(0x05A8, 0x02A0, 2, 0x0000, 0, 0), + MX6_PAD_WDOG_B__GPIO_3_18 = IOMUX_PAD(0x05A8, 0x02A0, 5, 0x0000, 0, 0), + MX6_PAD_WDOG_B__OBSERVE_MUX_OUT_2 = IOMUX_PAD(0x05A8, 0x02A0, 7, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile new file mode 100644 index 0000000..43af351 --- /dev/null +++ b/board/freescale/mx6slevk/Makefile @@ -0,0 +1,28 @@ +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx6slevk.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg new file mode 100644 index 0000000..df39a16 --- /dev/null +++ b/board/freescale/mx6slevk/imximage.cfg @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020e0344 0x00003030 +DATA 4 0x020e0348 0x00003030 +DATA 4 0x020e034c 0x00003030 +DATA 4 0x020e0350 0x00003030 +DATA 4 0x020e030c 0x00000030 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0318 0x00000030 +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e031c 0x00000030 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e0320 0x00000030 +DATA 4 0x020e032c 0x00000000 +DATA 4 0x020e033c 0x00000008 +DATA 4 0x020e0340 0x00000008 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x020e05cc 0x00000030 +DATA 4 0x020e05d4 0x00000030 +DATA 4 0x020e05d8 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05c8 0x00000030 +DATA 4 0x020e05b0 0x00020000 +DATA 4 0x020e05b4 0x00000000 +DATA 4 0x020e05c0 0x00020000 +DATA 4 0x020e05d0 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00300000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b0848 0x4241444a +DATA 4 0x021b0850 0x3030312b +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08c0 0x24911492 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A82 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001688 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x02038030 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x02038038 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x00025564 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c new file mode 100644 index 0000000..fc6353e --- /dev/null +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <asm/sizes.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6SLEVK\n"); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 199fcfa..2844712 100644 --- a/boards.cfg +++ b/boards.cfg @@ -256,6 +256,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL eco5pk arm armv7 eco5pk 8dtech omap3 nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h new file mode 100644 index 0000000..67b63f4 --- /dev/null +++ b/include/configs/mx6slevk.h @@ -0,0 +1,189 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SL EVK board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <asm/sizes.h> + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define MACH_TYPE_MX6SLEVK 4307 +#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 +#define CONFIG_SYS_TEXT_BASE 0x87800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6sl-evk.dtb\0" \ + "fdt_addr=0x81000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 256 * SZ_1M) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ -- 1.7.9.5

3 6

[U-Boot] [PATCH v2 0/7] Various patman fixes
by Simon Glass 02 Apr '13

02 Apr '13

Since checkpatch has changed in U-Boot, patman no longer detects errors properly. It seems like a good oppotunity to fix some of the bugs and annoying habits of patman that people have mentioned on the list. If I have missed any bugs / problems in this sweep, please let me know. Changes in v2: - Add comment about meaning of raise_on_error=False - Adjust to not allow any spaces in tags, change commit title - Remove 'ignore_errors' and just use 'raise_on_error' everywhere - Require sort, uniq tags to be comma-separated - Update code to remove match_count - Update commit message to add detail on what is changing - Update tests to check the 'checks' value, and add a new test - Use keyword args for raise_on_error - Use namedtuple to hold the return value from CheckPatch() function Simon Glass (7): patman: Fix up checkpatch parsing to deal with 'CHECK' lines patman: Don't allow spaces in tags patman: Fix the comment in CheckTags to mention multiple tags patman: Provide option to ignore bad aliases patman: Add -a option to refrain from test-applying the patches patman: Add Series-process-log tag to sort/uniq change logs patman: Minor help message/README fixes tools/patman/README | 11 ++++- tools/patman/checkpatch.py | 110 +++++++++++++++++++++++++++----------------- tools/patman/commit.py | 7 +-- tools/patman/gitutil.py | 65 ++++++++++++++++++-------- tools/patman/patchstream.py | 2 +- tools/patman/patman.py | 24 ++++++---- tools/patman/series.py | 19 ++++++-- tools/patman/test.py | 64 ++++++++++++++++++-------- 8 files changed, 203 insertions(+), 99 deletions(-) -- 1.8.1.3

2 11

[U-Boot] Patches for this merge window
by Simon Glass 01 Apr '13

01 Apr '13

[take 2, sorry] Hi Tom, I see quite a lot of non-x86 patches in my todo list - does that mean that I should pick them up if I am happy with them, or just assign them back to you once I've taken a look? I'm keen to get the sandbox fs and memory stuff in fairly early if possible, since I fear breakages and the longer people have to test the better. No one has screamed about map_sysmem() but I'm not sure if anyone noticed. So I could pull these in, build and send a pull if that suits? Perhaps one series at a time.... Also if Mike is having a break should I pull in the SPI ones assigned to me? There is also buildman, and I'm not sure what to do about that. It would be nice to have some feedback if people have tried it - I have had a few private emails only. I think it's a great help, but it still has some rough edges. Anyway, please let me know your expectations with the above. Re x86, I am going to start applying things this week once the board removable patch is sorted out. Generic board is also a big change, but since it is sort-of parallel to existing code and only turned on on a board-by-board basis the risk is lower - it just need some weeks of review time IMO. Regards, Simon

2 8

Re: [U-Boot] [RFC] MAKEALL: Fix case substitution for old bash
by Simon Glass 01 Apr '13

01 Apr '13

+U-Boot Hi Allen, York, On Fri, Mar 29, 2013 at 11:05 AM, Allen Martin <amartin(a)nvidia.com> wrote: > On Fri, Mar 29, 2013 at 10:56:33AM -0700, York Sun wrote: > > On 03/29/2013 10:52 AM, Allen Martin wrote: > > > On Fri, Mar 29, 2013 at 10:49:06AM -0700, York Sun wrote: > > >> On 03/29/2013 10:29 AM, Allen Martin wrote: > > >>> On Fri, Mar 29, 2013 at 09:56:41AM -0700, York Sun wrote: > > >>>> On 03/27/2013 12:55 PM, Tom Rini wrote: > > >>>>> On Thu, Mar 21, 2013 at 01:38:37PM -0700, York Sun wrote: > > >>>>>> On 03/21/2013 01:28 PM, Allen Martin wrote: > > >>>>> [snip] > > >>>>>>> PS: What happened with your bool fixup patch? I'm a big fan of > that > > >>>>>>> patch :^) > > >>>>>>> > > >>>>>> > > >>>>>> Tom asked on March 4th. I think he will accept it. > > >>>>> > > >>>>> I never got the expected acks on v7 that I thought would be > forthcoming. > > >>>>> > > >>>> > > >>>> Allen, > > >>>> > > >>>> Can you ack the v7 of the bool fixup patch? Tom seems waiting for > you. > > >>> > > >>> Oh sorry, I didn't realize there was a newer version of the patch I > > >>> hadn't ack'ed yet. I'll take a look today. Do you know if it still > > >>> applies cleanly to TOT u-boot/master, or will it need to be rebased? > > >>> > > >> > > >> It almost applies cleanly. > > >> > > >> Checking patch board/xilinx/common/xbasic_types.h... > > >> error: board/xilinx/common/xbasic_types.h: does not exist in index > > >> > > >> due to commit > > >> > > >> commit 151eeeb2754da4b2d26bb878206d45ce58276fe0 > > >> Author: Michal Simek <michal.simek(a)xilinx.com> > > >> Date: Wed Jan 23 14:11:50 2013 +0100 > > >> > > >> board: xilinx: Remove common folder > > >> > > >> All these files was used for ancient xilinx drivers > > >> which are finally gone. > > >> > > >> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> > > >> Tested-by: Rommel Custodio <sessyargc(a)gmail.com> > > >> > > >> board/xilinx/common/xbasic_types.c | 165 ---- > > >> board/xilinx/common/xbasic_types.h | 283 ------ > > >> board/xilinx/common/xbuf_descriptor.h | 252 ------ > > >> board/xilinx/common/xdma_channel.c | 738 ---------------- > > >> board/xilinx/common/xdma_channel.h | 291 ------ > > >> board/xilinx/common/xdma_channel_i.h | 110 --- > > >> board/xilinx/common/xdma_channel_sg.c | 1317 > > >> ---------------------------- > > >> board/xilinx/common/xio.h | 81 -- > > >> board/xilinx/common/xipif_v1_23_b.c | 331 ------- > > >> board/xilinx/common/xipif_v1_23_b.h | 746 ---------------- > > >> board/xilinx/common/xpacket_fifo_v1_00_b.c | 448 ---------- > > >> board/xilinx/common/xpacket_fifo_v1_00_b.h | 306 ------- > > >> board/xilinx/common/xstatus.h | 347 -------- > > >> board/xilinx/common/xversion.c | 350 -------- > > >> board/xilinx/common/xversion.h | 97 -- > > >> board/xilinx/zynq/Makefile | 3 - > > >> 16 files changed, 5865 deletions(-) > > >> > > >> > > >> Do I need to send a newer version? > > >> > > > > > > Tom will probably make you send a newer one anyway. I'll fix it up > > > locally and start testing in the mean time. > > > > > > > Allen, > > > > I didn't change anything for the version, only removed "RFC" from the > > subject. I have been there for quite a while. I thought Tom was going to > > pick it up. > > Yeah sorry, I would have re-acked it if I saw there was a new > version. Since it no longer applies cleanly I'm pretty sure he'll ask > you to send a new version that does even if there are no other > differences. > > Maybe we can talk Simon Glass into testing it out with his super fast > multi-arch u-boot builder. It's way fancier than the perl script I > use. Adding Simon. > > The patch in question is: > http://patchwork.ozlabs.org/patch/217088/ Yes, it needs a rebase, but the change is minor - I hope we can get this in. York can you do a rebase? Here are the boards that seem to fail: EVB64260 ZUMA EVB64260_750CX P3G4 Full output: 02: Consolidate bool type powerpc: + EVB64260 ZUMA EVB64260_750CX P3G4 +In file included from memory.c:9:0: +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:62:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:63:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:66:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:70:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:77:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:82:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:83:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/include/galileo/memory.h:84:1: error: unknown type name 'bool' +memory.c:175:1: error: unknown type name 'bool' +memory.c: In function 'memoryMapBank': +memory.c:199:12: error: 'true' undeclared (first use in this function) +memory.c:199:12: note: each undeclared identifier is reported only once for each function it appears in +memory.c: At top level: +memory.c:201:1: error: unknown type name 'bool' +memory.c: In function 'memoryMapDeviceSpace': +memory.c:219:12: error: 'true' undeclared (first use in this function) +memory.c:230:1: error: unknown type name 'bool' +memory.c: In function 'memoryMapInternalRegistersSpace': +memory.c:240:12: error: 'true' undeclared (first use in this function) +memory.c:267:1: error: unknown type name 'bool' +memory.c: In function 'memorySetProtectRegion': +memory.c:280:9: error: 'true' undeclared (first use in this function) +memory.c:306:1: error: unknown type name 'bool' +memory.c: In function 'memorySetRegionSnoopMode': +memory.c:317:9: error: 'false' undeclared (first use in this function) +memory.c:324:9: error: 'true' undeclared (first use in this function) +memory.c:342:1: error: unknown type name 'bool' +memory.c: In function 'memoryRemapAddress': +memory.c:347:12: error: 'true' undeclared (first use in this function) +memory.c:360:1: error: unknown type name 'bool' +memory.c: In function 'memoryGetDeviceParam': +memory.c:403:12: error: 'true' undeclared (first use in this function) +memory.c:416:1: error: unknown type name 'bool' +memory.c: In function 'memorySetDeviceParam': +memory.c:423:9: error: 'false' undeclared (first use in this function) +memory.c:456:12: error: 'true' undeclared (first use in this function) +memory.c:457:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:404:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:348:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:332:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:289:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:241:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:220:1: warning: control reaches end of non-void function [-Wreturn-type] +memory.c:200:1: warning: control reaches end of non-void function [-Wreturn-type] +make[1]: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/build/board/evb64260/memory.o] Error 1 +make: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/12/build/board/evb64260/libevb64260.o] Error 2 +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:62:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:63:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:66:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:70:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:77:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:82:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:83:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/include/galileo/memory.h:84:1: error: unknown type name 'bool' +make[1]: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/build/board/evb64260/memory.o] Error 1 +make: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/08/build/board/evb64260/libevb64260.o] Error 2 +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:62:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:63:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:66:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:70:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:77:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:82:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:83:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/include/galileo/memory.h:84:1: error: unknown type name 'bool' +make[1]: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/build/board/evb64260/memory.o] Error 1 +make: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/16/build/board/evb64260/libevb64260.o] Error 2 +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:62:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:63:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:66:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:70:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:77:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:82:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:83:1: error: unknown type name 'bool' +/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/include/galileo/memory.h:84:1: error: unknown type name 'bool' +make[1]: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/build/board/evb64260/memory.o] Error 1 +make: *** [/c/cosarm/src/third_party/u-boot/try-york/.bm-work/07/build/board/evb64260/libevb64260.o] Error 2 Regards Simon

2 1

[U-Boot] Pull request: u-boot-staging
by Anatolij Gustschin 01 Apr '13

01 Apr '13

Hello Tom, The following changes since commit 009d75ccc11d27b9a083375a88bb93cb746b4800: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2013-03-28 18:50:01 +0100) are available in the git repository at: git://git.denx.de/u-boot-staging.git agust(a)denx.de Anatolij Gustschin (1): menu: export menu_default_choice() function Pali Rohár (3): menu: Add support for user defined item choice function New command bootmenu: ANSI terminal boot menu support RX-51: Add support for bootmenu board/ait/cam_enc_4xx/cam_enc_4xx.c | 3 +- common/Makefile | 1 + common/cmd_bootmenu.c | 517 +++++++++++++++++++++++++++++++++++ common/cmd_pxe.c | 3 +- common/menu.c | 44 +++- doc/README.bootmenu | 115 ++++++++ doc/README.menu | 9 +- include/ansi.h | 42 +++ include/configs/nokia_rx51.h | 40 +++- include/menu.h | 5 +- 10 files changed, 760 insertions(+), 19 deletions(-) create mode 100644 common/cmd_bootmenu.c create mode 100644 doc/README.bootmenu create mode 100644 include/ansi.h Please pull. Thanks! Anatolij

2 1

[U-Boot] [PATCH v4 0/3] i.MX6 SabreSD and SabreAUTO bmode support
by Otavio Salvador 01 Apr '13

01 Apr '13

This adds the bmode support for i.MX6 SabreSD and SabreAUTO boards. This allows user to choose the boot mode at runtime making it easy to boot from USB or other media. Changes in v4: - Fix switch code to proper break (Stefano) Changes in v3: - Drop change in bootdelay; the change where done by me while testing it and I mistakenly included it. Changes in v2: - Rework code to use a 'ret' variable (Fabio) - Improve commit log Otavio Salvador (3): mx6qsabresd: Fix card detection for invalid card id case mx6qsabresd: Document the mapping of USDHC[2-4] mx6qsabre{sd,auto}: Add boot mode select board/freescale/mx6qsabreauto/mx6qsabreauto.c | 17 ++++++++++++ board/freescale/mx6qsabresd/mx6qsabresd.c | 38 ++++++++++++++++++++++++--- include/configs/mx6qsabre_common.h | 2 ++ 3 files changed, 53 insertions(+), 4 deletions(-) -- 1.8.1

2 6

[U-Boot] [PATCH V7 00/10] EXYNOS5: Enable DWMMC, add FDT support for DWMMC and enable EMMC boot
by Amar 01 Apr '13

01 Apr '13

This patch set enables and initialises DWMMC for Exynos5250 on SMDK5250. Adds driver changes required for DWMMC. Adds FDT support for DWMMC. Adds EMMC boot support for SMDK5250. This patch set is based on: "EXYNOS: mmc: support DesignWare Controller for Samsung-SoC", which is merged in u-boot-mmc. "Exynos: clock: support get_mmc_clk for exynos". "Add DT based ethernet driver for SMDK5250". "SMDK5250: Add FDT support" present at the following link http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/149991 Changes from V1: 1)Corrected in response to review comments. 2)Created separate board files for FDT and non-FDT versions. 3)Added binding file for DWMMC device node. 4)Removed the propname 'index' from device node. 5)Prefixed the vendor name 'samsung' before propname in device node. 6)Ensured to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 7)EMMC clock setting has been moved from spl_boot.c to clock_init.c. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Changes from V3: 1)Updated to use the macro DWMCI_CTRL_SEND_AS_CCSD instead of the hard coded value (1 << 10). 2)In the file exynos_dw_mmc.c, replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 3)In the file exynos_dw_mmc.c, computation of FSYS block clock divisor (pre-ratio) value is added. 4)Removed the new function exynos5_mmc_set_clk_div() from clock.c. Changes from V4: 1)Updated the function dwmci_send_cmd() to use get_timer() instead of using mdelay(1). 2)Replaced the function call 'exynos_dwmmc_init(0, 8);' with the function exynos_dwmmc_add_port() in smdk5250.c. 3)The function get_irom_func(int index) has been added to avoid type casting at many places. 4)Used the generic function "mmc_boot_part_access()" instead of two functions "mmc_boot_open()" and "mmc_boot_close()". By doing so user can specify which boot partition to be accessed (opened / closed). Changes from V5: 1)Added the 'removable' flag to mmc device node. 2)Changed the mmc clock value from 50MHz to 52MHz in the function exynos_dwmci_add_port() present in file drivers/mmc/exynos_dw_mmc.c. 3)Enabled CONFIG_LCD only for non-FDT operation. 4)Removed the function call i2c_init() present inside the function board_i2c_init(). Changes from V6: 1)Re-based to the patch "SMDK5250: Add PMIC voltage settings". Amar (10): FDT: Add compatible string for DWMMC EXYNOS5: FDT: Add DWMMC device node data DWMMC: Initialise dwmci and resolve EMMC read write issues EXYNOS5: DWMMC: Added FDT support for DWMMC EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results. SMDK5250: Initialise and Enable DWMMC, support FDT and non-FDT MMC: APIs to support resize of EMMC boot partition SMDK5250: Enable EMMC booting COMMON: MMC: Command to support EMMC booting and to resize EMMC boot partition EXYNOS5: I2C: Added FDT and non-FDT support for I2C arch/arm/cpu/armv7/exynos/clock.c | 4 +- arch/arm/dts/exynos5250.dtsi | 31 +++ arch/arm/include/asm/arch-exynos/clk.h | 3 + arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +- board/samsung/dts/exynos5250-smdk5250.dts | 24 +++ board/samsung/smdk5250/Makefile | 4 + board/samsung/smdk5250/clock_init.c | 15 ++ board/samsung/smdk5250/clock_init.h | 5 + board/samsung/smdk5250/exynos5-dt.c | 319 ++++++++++++++++++++++++++++++ board/samsung/smdk5250/smdk5250.c | 165 ++++++---------- board/samsung/smdk5250/spl_boot.c | 52 ++++- common/cmd_mmc.c | 98 ++++++++- doc/device-tree-bindings/exynos/dwmmc.txt | 54 +++++ drivers/i2c/s3c24x0_i2c.c | 12 +- drivers/mmc/dw_mmc.c | 25 ++- drivers/mmc/exynos_dw_mmc.c | 127 +++++++++++- drivers/mmc/mmc.c | 132 +++++++++++++ include/configs/exynos5250-dt.h | 8 + include/dwmmc.h | 3 + include/fdtdec.h | 1 + include/mmc.h | 26 +++ lib/fdtdec.c | 1 + 22 files changed, 974 insertions(+), 146 deletions(-) create mode 100644 board/samsung/smdk5250/exynos5-dt.c create mode 100644 doc/device-tree-bindings/exynos/dwmmc.txt -- 1.8.0

6 25

[U-Boot] Pull request: u-boot-video/master
by Anatolij Gustschin 31 Mar '13

31 Mar '13

Hello Tom, The following changes since commit 009d75ccc11d27b9a083375a88bb93cb746b4800: Merge branch 'u-boot/master' into 'u-boot-arm/master' (2013-03-28 18:50:01 +0100) are available in the git repository at: git://git.denx.de/u-boot-video.git master Anatolij Gustschin (2): Merge branch 'for-v2013.04' video: bcm2835: fix build issues Andre Renaud (1): Fix bitmap offsets for non 8-bit LCDs Jeroen Hofstee (10): lcd, amba: remove this driver since it is not used lcd, tegra: remove unused cursor functions lcd, mpc8xx: move the mpc8xx driver to drivers/video lcd, pxafb: move the pxafb to drivers/video common/lcd.c: cleanup use of global variables common/lcd.c: remove global lcd_base common/lcd: cosmetic: clean up a bit lcd, fb: remove duplicated prototypes and unused code api/api_display: use the getters for console size info common/lcd.c: move the macro's to the c file Matthias Weisser (1): video: Fix splash screen alignment Wolfgang Denk (1): common/lcd.c: cleanup use of global variables api/api_display.c | 4 +- arch/arm/cpu/pxa/Makefile | 1 - arch/powerpc/cpu/mpc8xx/Makefile | 1 - board/cm_t35/display.c | 8 - board/mcc200/lcd.c | 24 +--- common/lcd.c | 143 ++++++++++++-------- drivers/video/Makefile | 3 +- drivers/video/amba.c | 79 ----------- drivers/video/atmel_hlcdfb.c | 10 -- drivers/video/atmel_lcdfb.c | 10 -- drivers/video/bcm2835.c | 11 -- drivers/video/cfb_console.c | 14 +- drivers/video/exynos_fb.c | 16 +-- .../cpu/mpc8xx/lcd.c => drivers/video/mpc8xx_lcd.c | 61 +-------- .../arm/cpu/pxa/pxafb.c => drivers/video/pxa_lcd.c | 43 ------ drivers/video/tegra.c | 66 +--------- include/configs/R360MPI.h | 1 + include/configs/RBC823.h | 1 + include/configs/RPXlite_DW.h | 1 + include/configs/RRvision.h | 4 +- include/configs/TQM823L.h | 1 + include/configs/TQM823M.h | 1 + include/configs/lubbock.h | 1 + include/configs/lwmon.h | 1 + include/configs/palmld.h | 1 + include/configs/palmtc.h | 1 + include/configs/pxa255_idp.h | 1 + include/configs/svm_sc8xx.h | 1 + include/configs/v37.h | 1 + include/configs/zipitz2.h | 1 + include/lcd.h | 74 +++-------- 31 files changed, 138 insertions(+), 447 deletions(-) delete mode 100644 drivers/video/amba.c rename arch/powerpc/cpu/mpc8xx/lcd.c => drivers/video/mpc8xx_lcd.c (92%) rename arch/arm/cpu/pxa/pxafb.c => drivers/video/pxa_lcd.c (93%) Please pull. Thanks! Anatolij

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Re: [U-Boot] [PATCH v9 0/31] Create generic board init for ARM, x86, PPC
by Wolfgang Denk 30 Mar '13

30 Mar '13

Dear Simon Glass, In message <1363020460-14307-1-git-send-email-sjg(a)chromium.org> you wrote: > This series creates a generic board init implementation which contains > the essential functions of the major arch/xxx/lib/board.c files. It is > split into two parts: board_f.c for pre-relocation and board_r.c for > post-relocation. ... > ARM is a relatively large board.c file and one which I can test, therefore > I think it is a good target for this series. On the other hand, x86 is > relatively small and simple, but different enough that it introduces a > few issues to be solved. So I have chosen both ARM and x86 for this series. > After a suggestion from Wolfgang I have added PPC also. This is the > largest and most feature-full board, so hopefully we have all bases > covered in this series. Other archs are mostly a subset of these. I did some testing on Power Architecture systems - to be precise: CPU Board -------------------------- MPC860T TQM860L MPC5200 TQM5200S PPC405EX Kilauea PPC440EP Yosemite PPC440EX Sequoia PPC440SPe Katmai PPC460EX Canyonlands On all boards I verified at least environment access (printenv, saveenv) and network operation (TFTP download); where available also PCI. Everything appears to work fine, no problems noted. A well done job, thanks a lot! For the whole series: Tested-by: Wolfgang Denk <wd(a)denx.de> Acked-by: Wolfgang Denk <wd(a)denx.de> Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Certain old men prefer to rise at dawn, taking a cold bath and a long walk with an empty stomach and otherwise mortifying the flesh. They then point with pride to these practices as the cause of their sturdy health and ripe years; the truth being that they are hearty and old, not because of their habits, but in spite of them. The reason we find only robust persons doing this thing is that it has killed all the others who have tried it. - Ambrose Bierce, "The Devil's Dictionary"

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