August 2012 - U-Boot

[U-Boot] Blackfin BF547 board testing.
by Dimitar Penev 22 Aug '12

22 Aug '12

Hi Guys, We have developed Blackfin based board using BF547-Rev04. At the moment we face strange probably hardware issue. Let me share few details - GCC assumes rev 0.2 of the CPU is this OK with the rev 0.4 which we have on board? - The DDR routing due to a PCB mistake is not perfect now so we had to reduce the SCLK to 75 MHz - Now mtest in uboot is working OK for a very long time. - as the uCinux boots we get 2 different kind of OOPS. The OOPS trace are exactly the same on each try. Which one of the OOPS we will get depends even from the place in memory we put uImage before 'bootm' it. Let me copy one of the OOPS at the end of this message. The first reason for this behavior seems to be memory issue. At the moment we have soldered two Micron memory chips MT46V64M8BN-5B. (On the board we have footprints for 4 chips, two are not soldered and their traces are hanging as a bridged taps now) We are using Vtt active termination. The series resistors are 22 Ohm and the Vtt pull-ups are 47 Ohm. We have experimented a lot varying the SCLK and keeping EBIU_DDRCTL[0..2] as per the excel document available at http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram. The most stable behavior we have got around SCLK-75MHz. For higher and lower frequency we get worse results. With SCLK=75 MHz mtest is working stable. Can we assume that our memory is OK for this settings then? The OOPS we get looks stable as well. All the trace data are exactly repeatable. Can you please point us to the way/direction so we narrow down the issue. ================================================================================= Freeing unused kernel memory: 120k freed Undefined instruction <5> - May be used to emulate instructions that are not defined for <5> a particular processor implementation. Kernel OOPS in progress Deferred Exception context CURRENT PROCESS: COMM=mtdblock0 PID=141 CPU=0 invalid mm return address: [0x0006a5fc]; contents of: 0x0006a5d0: 0000 0000 3044 a0ea 4ee2 e3ff ffd5 a060 0x0006a5e0: 0c00 1809 304d 6c66 5201 0127 a0a1 0484 0x0006a5f0: e2fe 7568 6c66 0127 3045 a0a1 [0484] e2fe 0x0006a600: 7561 0000 e14a 001f e10a 60a0 9111 e2ff ADSP-BF547-0.2(Detected 0.4) 375(MHz CCLK) 75(MHz SCLK) (mpu off) Linux version 3.0.8-ADI-2011R1switchfin (root@Switchvoice) (gcc version 4.3.5 (ADI-2011R1-RC4) ) #2 Wed Aug 22 11:17:03 EEST 2012 SEQUENCER STATUS: Not tainted SEQSTAT: 00000021 IPEND: 8008 IMASK: 003f SYSCFG: 0006 Peripheral interrupts masked off Kernel interrupts masked off EXCAUSE : 0x21 physical IVG3 asserted : <0xffa0077c> { _trap + 0x0 } physical IVG15 asserted : <0xffa00fc4> { _evt_system_call + 0x0 } logical irq 6 mapped : <0x00006240> { _bfin_coretmr_interrupt + 0x0 } logical irq 48 mapped : <0x000d7230> { _bfin_serial_dma_rx_int + 0x0 } logical irq 49 mapped : <0x000d6fb4> { _bfin_serial_dma_tx_int + 0x0 } RETE: <0x00000000> /* Maybe null pointer? */ RETN: <0x0216ff18> /* kernel dynamic memory (maybe user-space) */ RETX: <0x00000480> /* Maybe fixed code section */ RETS: <0x000b419a> { _blk_update_request + 0x7a } PC : <0x0006a5fc> { _bio_free + 0x48 } DCPLB_FAULT_ADDR: <0x0204eca8> /* kernel dynamic memory (maybe user-space) */ ICPLB_FAULT_ADDR: <0x0006a5fc> { _bio_free + 0x48 } PROCESSOR STATE: R0 : 0204a6a0 R1 : 0204ec80 R2 : 00000000 R3 : 00000000 R4 : 00000000 R5 : 00000000 R6 : 00001000 R7 : 00001000 P0 : 001fc064 P1 : 0204a6a0 P2 : 0204a6e4 P3 : 0204a6a0 P4 : 0204eca0 P5 : 0204a6a0 FP : 0217592c SP : 0216fe3c LB0: 000c2cf6 LT0: 000c2cf6 LC0: 00000000 LB1: 00066470 LT1: 00066464 LC1: 00000008 B0 : 0000000c L0 : 00000000 M0 : 0201b92c I0 : 00000003 B1 : 0000001f L1 : 00000000 M1 : 00000001 I1 : 0605ac00 B2 : 0018589c L2 : 00000000 M2 : 00000019 I2 : 0204a6a0 B3 : 00000001 L3 : 00000000 M3 : 00000000 I3 : 00000000 A0.w: 00000000 A0.x: 00000000 A1.w: 00000000 A1.x: 00000000 USP : 00000000 ASTAT: 02003025 Hardware Trace: 0 Target : <0x00004028> { _trap_c + 0x0 } Source : <0xffa00710> { _exception_to_level5 + 0xa4 } JUMP.L 1 Target : <0xffa0066c> { _exception_to_level5 + 0x0 } Source : <0xffa00520> { _bfin_return_from_exception + 0x18 } RTX 2 Target : <0xffa00508> { _bfin_return_from_exception + 0x0 } Source : <0xffa005c4> { _ex_trap_c + 0x74 } JUMP.S 3 Target : <0xffa00550> { _ex_trap_c + 0x0 } Source : <0xffa007d6> { _trap + 0x5a } JUMP (P4) 4 Target : <0xffa0077c> { _trap + 0x0 } FAULT : <0x0006a5fc> { _bio_free + 0x48 } 0x0484 Source : <0x0006a5fa> { _bio_free + 0x46 } P1 = W[P4 + 2] 5 Target : <0x0006a5f4> { _bio_free + 0x40 } Source : <0x0006a5e2> { _bio_free + 0x2e } IF CC JUMP pcrel 6 Target : <0x0006a5de> { _bio_free + 0x2a } Source : <0x0006a5ce> { _bio_free + 0x1a } IF CC JUMP pcrel 7 Target : <0x0006a5b4> { _bio_free + 0x0 } Source : <0x0006a60e> { _bio_fs_destructor + 0xa } CALL pcrel 8 Target : <0x0006a604> { _bio_fs_destructor + 0x0 } Source : <0x000690ba> { _bio_put + 0x3a } JUMP (P2) 9 Target : <0x000690b0> { _bio_put + 0x30 } Source : <0x000690ac> { _bio_put + 0x2c } IF CC JUMP pcrel 10 Target : <0x000690aa> { _bio_put + 0x2a } Source : <0x0006909c> { _bio_put + 0x1c } IF CC JUMP pcrel (BP) 11 Target : <0x00069080> { _bio_put + 0x0 } Source : <0x0006d48c> { _mpage_end_io + 0xa8 } CALL pcrel 12 Target : <0x0006d484> { _mpage_end_io + 0xa0 } Source : <0x0006d42e> { _mpage_end_io + 0x4a } IF CC JUMP pcrel 13 Target : <0x0006d42a> { _mpage_end_io + 0x46 } Source : <0x00024028> { ___wake_up_bit + 0x24 } RTS 14 Target : <0x00024024> { ___wake_up_bit + 0x20 } Source : <0x0000b6ca> { ___wake_up + 0x32 } RTS 15 Target : <0x0000b6c4> { ___wake_up + 0x2c } Source : <0x0000b6b6> { ___wake_up + 0x1e } IF CC JUMP pcrel (BP) Kernel Stack Stack info: SP: [0x0216ff2c] <0x0216ff2c> /* kernel dynamic memory (maybe user-space) */ FP: (0x0216ffa0) Memory from 0x0216ff20 to 02170000 0216ff20: 00000000 02054eb0 001fc098 [00000000] 00000200 02158990 000b4422 0217592c 0216ff40: 001fba18 00000000 00000000 00000000 02009d30 00000000 021abe00 00000000 0216ff60: 000052d5 000b4e0c 02009d20 0217592c 000e786c 02009d20 001fba18 00000000 0216ff80: 000e787e 00000000 0217592c 000e7820 00000000 0216e008 0216e000 00208458 0216ffa0:(00000000)<00023d08> 0201bea8 000e7820 00000000 02009d20 00000000 00000000 0216ffc0: 00000000 00000000 00000000 00023cac 00000000 02009d20 00000000 0216ffdc 0216ffe0: 0216ffdc 00000000 00000000 00000000 00000000 ffffffff 00000006 Return addresses in stack: frame 1 : <0x00023d08> { _kthread + 0x5c } address : <0x00001576> { _kernel_thread_helper + 0x6 } Modules linked in: Kernel panic - not syncing: Kernel exception Hardware Trace: Stack info: SP: [0x0216fd48] <0x0216fd48> /* kernel dynamic memory (maybe user-space) */ FP: (0x0216fdfc) Memory from 0x0216fd40 to 02170000 0216fd40: 0216fd48 00000013 [001b0688] 001724ec 0216fe3c 001b0688 001ef6fb 001ef6fb 0216fd60: 001ef6fb 0216fd90 0217592c 00004464 0216fe3c ffe02014 0204a6a0 00008008 0216fd80: 00000004 00000021 00000013 0216fe3c 0000003f ffffffff 00000000 02009d20 0216fda0: 00030001 00000000 00000000 0216fddc 0000cd2a 0216fddc 00000000 0216fdf0 0216fdc0: 0000a6c4 02019d8c 00000000 0216fdfc 0000cd2a 0216fdfc 00000000 0216fe10 0216fde0: 0000a6c4 02019d8c 02054d60 02054d8c 0216fe10 0000a6d4 00000000 (00000000) 0216fe00:<0000c5c4> 02019d60 001fc064 001fc064 0216fe40 <0000af96> ffa00714 001ec000 0216fe20: 00008008 00000021 00000000 00000000 00000000 002f10b8 00000480 00000480 0216fe40: 00008008 00000021 00000000 0216ff18 00000480 0006a5fc 000b419a 0204a6a0 0216fe60: 02003025 00066470 000c2cf6 00066464 000c2cf6 00000008 00000000 00000000 0216fe80: 00000000 00000000 00000000 00000001 0018589c 0000001f 0000000c 00000000 0216fea0: 00000000 00000000 00000000 00000000 00000019 00000001 0201b92c 00000000 0216fec0: 0204a6a0 0605ac00 00000003 00000000 0217592c 0204a6a0 0204eca0 0204a6a0 0216fee0: 0204a6e4 0204a6a0 001fc064 00001000 00001000 00000000 00000000 00000000 0216ff00: 00000000 0204ec80 0204a6a0 0204a6a0 001fc064 00000006 0204a6a0 001fba18 0216ff20: 00000000 02054eb0 001fc098 00000000 00000200 02158990 000b4422 0217592c 0216ff40: 001fba18 00000000 00000000 00000000 02009d30 00000000 021abe00 00000000 0216ff60: 000052d5 000b4e0c 02009d20 0217592c 000e786c 02009d20 001fba18 00000000 0216ff80: 000e787e 00000000 0217592c 000e7820 00000000 0216e008 0216e000 00208458 0216ffa0: 00000000 <00023d08> 0201bea8 000e7820 00000000 02009d20 00000000 00000000 0216ffc0: 00000000 00000000 00000000 00023cac 00000000 02009d20 00000000 0216ffdc 0216ffe0: 0216ffdc 00000000 00000000 00000000 00000000 ffffffff 00000006 Return addresses in stack: frame 1 : <0x0000c5c4> { _activate_task + 0x40 } address : <0x0000af96> { _check_preempt_curr + 0x72 } address : <0x00023d08> { _kthread + 0x5c } address : <0x00001576> { _kernel_thread_helper + 0x6 } ======================================================================================= Thank you! Dimitar

2 1

[U-Boot] [PATCH] fsl_pci: use 'Header Type' field to judge PCIE mode
by Minghuan Lian 22 Aug '12

22 Aug '12

The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- drivers/pci/fsl_pci_init.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 1d75a82..0c61f5c 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -393,13 +393,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) } #ifndef CONFIG_PCI_NOSCAN - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); - - /* Programming Interface (PCI_CLASS_PROG) - * 0 == pci host or pcie root-complex, - * 1 == pci agent or pcie end-point - */ - if (!temp8) { + if (!fsl_is_pci_agent(hose)) { debug(" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); @@ -437,12 +431,22 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int fsl_is_pci_agent(struct pci_controller *hose) { - u8 prog_if; + u8 pcie_cap; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + if (pcie_cap == PCI_CAP_ID_EXP) { + u8 header_type; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, + &header_type); + return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; + } else { + u8 prog_if; - return (prog_if == FSL_PROG_IF_AGENT); + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + return (prog_if == FSL_PROG_IF_AGENT); + } } int fsl_pci_init_port(struct fsl_pci_info *pci_info, @@ -502,12 +506,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, void fsl_pci_config_unlock(struct pci_controller *hose) { pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); - u8 agent; u8 pcie_cap; u16 pbfr; - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); - if (!agent) + if (!fsl_is_pci_agent(hose)) return; pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -- 1.7.9.5

1 0

[U-Boot] Seeking ARM development platform suggestions
by Graeme Russ 22 Aug '12

22 Aug '12

Hi Guys, Now that I _finally_ have an ARM toolchain up and running (ELDK 5.2), it's time to play, and for that, I need something to play with :) I have a HP TouchPad which I've been compiling CyangenMod for (it has it's own toolchain) and a Raspberry Pi which I have built U-Boot for (using ELDK), but I don't have the necessary hardware for serial console yet. I'm looking for something: a) I can purchase locally (Australia) b) Is reasonably priced c) Has a mainline port of U-Boot already d) Is 'useful' (media player, NAS, firewall, machine that goes 'ping') e) Has lots of 'things' to play with (network, USB, video, SD/MMC, SATA, LEDs, GPIO, Alphanumeric LCD) - Not all have to be currently supported (actually, it would be great if some aren't so I can work on adding them) Any and all ideas appreciated Regards, Graeme

6 15

[U-Boot] [PATCH 1/3] mx53loco: Use IMX_GPIO_NR macro
by Fabio Estevam 22 Aug '12

22 Aug '12

Use IMX_GPIO_NR macro. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx53loco/mx53loco.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 7cfb3f4..3a39c3e 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ #include <linux/fb.h> #include <ipu_pixfmt.h> -#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */ +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) /* GPIO3_24 */ DECLARE_GLOBAL_DATA_PTR; -- 1.7.9.5

3 6

[U-Boot] [PATCH v2 0/5] at91: 9x5: Enable PMECC(Programmable Multibit ECC controller) support
by Josh Wu 22 Aug '12

22 Aug '12

This patch series will add PMECC support for atmel at91sam9x5ek in u-boot. The NAND flash driver patch is ported from kernel patch. The main different from kernel patch is the modification about registers access part. in this version it via a register structure to access. It is tested in atmel AT919G25EK board. Changes since v1: Add two patches that enable PMECC in 9x5 board. Nand flash driver: Change 'ecc' array's type from u32 to u8 in structure pmecc_regs (u32 ecc[11] -> u8 ecc[44]). That will make PMECC write correctly. enable 4k-page nand flash pmecc support. fix coding style errors and warnings. Josh Wu (5): at91: atmel_nand: extract HWECC initialization code into one function: atmel_hw_nand_init_param(). at91: atmel_nand: remove unused variables. at91: atmel_nand: Update driver to support Programmable Multibit ECC controller at91: 9x5: change SMC config timing that both works for PMECC & non-PMECC. at91: 9x5: Enable PMECC for 5series ek board. board/atmel/at91sam9x5ek/at91sam9x5ek.c | 12 +- drivers/mtd/nand/atmel_nand.c | 763 ++++++++++++++++++++++++++++--- drivers/mtd/nand/atmel_nand_ecc.h | 111 +++++ include/configs/at91sam9x5ek.h | 7 + 4 files changed, 833 insertions(+), 60 deletions(-) -- 1.7.9.5

3 16

[U-Boot] [PATCH 0/9] EXYNOS5: Add Audio support
by Rajeshwari Shinde 22 Aug '12

22 Aug '12

This patchset adds the audio support for EXYNOS5. This patchset plays a predefined beep sound. Rajeshwari Shinde (9): SOUND: Add I2S driver SOUND: Add WM8994 codec Sound: Add command for audio playback EXYNOS: Add I2S registers EXYNOS: Add parameters required by I2S EXYNOS: Add pinmux for I2S EXYNOS: Add I2S base address EXYNOS: Add clock for I2S EXYNOS5: Enable Sound Makefile | 1 + arch/arm/cpu/armv7/exynos/clock.c | 119 ++++ arch/arm/cpu/armv7/exynos/pinmux.c | 12 + arch/arm/include/asm/arch-exynos/clk.h | 3 + arch/arm/include/asm/arch-exynos/clock.h | 29 + arch/arm/include/asm/arch-exynos/cpu.h | 3 + arch/arm/include/asm/arch-exynos/i2s-regs.h | 66 +++ arch/arm/include/asm/arch-exynos/periph.h | 1 + arch/arm/include/asm/arch-exynos/sound.h | 44 ++ common/Makefile | 1 + common/cmd_sound.c | 90 +++ drivers/sound/Makefile | 48 ++ drivers/sound/i2s.c | 358 ++++++++++++ drivers/sound/sound.c | 220 ++++++++ drivers/sound/wm8994.c | 781 +++++++++++++++++++++++++++ drivers/sound/wm8994.h | 87 +++ drivers/sound/wm8994_registers.h | 299 ++++++++++ include/configs/smdk5250.h | 8 + include/i2s.h | 127 +++++ include/sound.h | 62 +++ 20 files changed, 2359 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/i2s-regs.h create mode 100644 arch/arm/include/asm/arch-exynos/sound.h create mode 100644 common/cmd_sound.c create mode 100644 drivers/sound/Makefile create mode 100644 drivers/sound/i2s.c create mode 100644 drivers/sound/sound.c create mode 100644 drivers/sound/wm8994.c create mode 100644 drivers/sound/wm8994.h create mode 100644 drivers/sound/wm8994_registers.h create mode 100644 include/i2s.h create mode 100644 include/sound.h -- 1.7.4.4

5 18

[U-Boot] [PATCH v6] arm: rmobile: Add support Renesas SH73A0
by Nobuhiro Iwamatsu 22 Aug '12

22 Aug '12

Renesas SH73A0 is CPU with Cortex-A9. This supports the basic register definition and GPIO. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- V6: Changed Makefile that using config. Removed unnecessary ifdefs. V5: Remove dead code. V4: Revert ICCICR. V3: Set COBJS one object per line, and sort the list. Remove ICCICR and ICCPMR. Remove white space. v2: Remove white space. Code which can be communalized was moved to lowlevel_init. arch/arm/cpu/armv7/rmobile/Makefile | 14 +- arch/arm/cpu/armv7/rmobile/board.c | 31 ++ arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c | 48 ++ arch/arm/cpu/armv7/rmobile/cpu_info.c | 36 +- arch/arm/cpu/armv7/rmobile/lowlevel_init.S | 95 ++++ arch/arm/include/asm/arch-rmobile/rmobile.h | 4 + arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h | 553 +++++++++++++++++++++++ arch/arm/include/asm/arch-rmobile/sh73a0.h | 281 ++++++++++++ arch/arm/include/asm/arch-rmobile/sys_proto.h | 29 ++ 9 files changed, 1067 insertions(+), 24 deletions(-) create mode 100644 arch/arm/cpu/armv7/rmobile/board.c create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c create mode 100644 arch/arm/cpu/armv7/rmobile/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0.h create mode 100644 arch/arm/include/asm/arch-rmobile/sys_proto.h diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index e7eb90f..77eca4b 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -25,11 +25,17 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += cpu_info.o -COBJS += timer.o +SOBJS = lowlevel_init.o +COBJS-y += cpu_info.o +COBJS-y += timer.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y)) +COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o +COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(LIB) diff --git a/arch/arm/cpu/armv7/rmobile/board.c b/arch/arm/cpu/armv7/rmobile/board.c new file mode 100644 index 0000000..2622590 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/board.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +int checkboard(void) +{ + printf("Board: %s\n", sysinfo.board_string); + return 0; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c new file mode 100644 index 0000000..3086dd8 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> + +u32 rmobile_get_cpu_type(void) +{ + u32 id; + u32 type; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + + id = readl(hpb->cccr); + type = (id >> 8) & 0xFF; + + return type; +} + +u32 get_cpu_rev(void) +{ + u32 id; + u32 rev; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + + id = readl(hpb->cccr); + rev = (id >> 4) & 0xF; + + return rev; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 789c2c3..2148958 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -22,7 +22,6 @@ */ #include <common.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) @@ -40,35 +39,32 @@ void enable_caches(void) #endif #ifdef CONFIG_DISPLAY_CPUINFO -static u32 get_cpu_type(void) +static u32 __rmobile_get_cpu_type(void) { - u32 id; - u32 type; - - id = readl(CCCR); - type = (id >> 8) & 0xFF; - - return type; + return 0x0; } +u32 rmobile_get_cpu_type(void) + __attribute__((weak, alias("__rmobile_get_cpu_type"))); -static u32 get_cpu_rev(void) +static u32 __rmobile_get_cpu_rev(void) { - u32 id; - u32 rev; - - id = readl(CCCR); - rev = (id >> 4) & 0xF; - - return rev; + return 0; } +u32 rmobile_get_cpu_rev(void) + __attribute__((weak, alias("__rmobile_get_cpu_rev"))); int print_cpuinfo(void) { - switch (get_cpu_type()) { + switch (rmobile_get_cpu_type()) { + case 0x37: + printf("CPU: Renesas Electronics SH73A0 rev %d\n", + rmobile_get_cpu_rev()); + break; default: - printf("CPU: Renesas Electronics CPU rev %d\n", get_cpu_rev()); + printf("CPU: Renesas Electronics CPU rev %d\n", + get_cpu_rev()); break; } return 0; } -#endif +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S new file mode 100644 index 0000000..2cd410b --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj(a)renesas.com> + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + ldr r0, =MERAM_BASE + mov r1, #0x0 + str r1, [r0] + + mrc p15, 0, r0, c0, c0, 5 + ands r0, r0, #0xF + beq lowlevel_init__ + b wait_interrupt + + .pool + .align 4 + +wait_interrupt: + ldr r1, =ICCICR + mov r2, #0x0 + str r2, [r1] + mov r2, #0xF0 + adds r1, r1, #4 /* ICCPMR */ + str r2, [r1] + ldr r1, =ICCICR + mov r2, #0x1 + str r2, [r1] + +wait_loop: + wfi + + ldr r2, [r1, #0xC] + str r2, [r1, #0x10] + + ldr r0, =MERAM_BASE + ldr r2, [r0] + cmp r2, #0 + movne pc, r2 + + b wait_loop + +wait_loop_end: + .pool + .align 4 + +lowlevel_init__: + + mov r0, #0x200000 + +loop0: + subs r0, r0, #1 + bne loop0 + + ldr sp, MERAM_STACK + + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init + + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + .pool + .align 4 + +ENDPROC(lowlevel_init) + .ltorg + +MERAM_STACK: + .word LOW_LEVEL_MERAM_STACK diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index bf5e22a..a3468e9 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -2,7 +2,11 @@ #define __ASM_ARCH_RMOBILE_H #if defined(CONFIG_RMOBILE) +#if defined(CONFIG_SH73A0) +#include <asm/arch/sh73a0.h> +#else #error "SOC Name not defined" +#endif #endif /* CONFIG_RMOBILE */ #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h new file mode 100644 index 0000000..398e2c1 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h @@ -0,0 +1,553 @@ +#ifndef __ASM_SH73A0_H__ +#define __ASM_SH73A0_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function and MSEL switch + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* Hardware manual Table 25-1 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, + GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, + + GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, + + GPIO_PORT288, GPIO_PORT289, + + GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, + GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, + + GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, + GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, + + /* Table 25-1 (Function 0-7) */ + GPIO_FN_VBUS_0, + GPIO_FN_GPI0, + GPIO_FN_GPI1, + GPIO_FN_GPI2, + GPIO_FN_GPI3, + GPIO_FN_GPI4, + GPIO_FN_GPI5, + GPIO_FN_GPI6, + GPIO_FN_GPI7, + GPIO_FN_SCIFA7_RXD, + GPIO_FN_SCIFA7_CTS_, + GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, + GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, + GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ + GPIO_FN_PORT16_VIO_CKOR, + GPIO_FN_SCIFA0_TXD, + GPIO_FN_SCIFA7_TXD, + GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_GPO0, + GPIO_FN_GPO1, + GPIO_FN_GPO2, GPIO_FN_STATUS0, + GPIO_FN_GPO3, GPIO_FN_STATUS1, + GPIO_FN_GPO4, GPIO_FN_STATUS2, + GPIO_FN_VINT, + GPIO_FN_TCKON, + GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ + GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, + GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ + GPIO_FN_PORT28_TPU1TO1, + GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, + GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, + GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, + GPIO_FN_SCIFA4_TXD, + GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_SCIFA4_RTS_, + GPIO_FN_SCIFA4_CTS_, + GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, + GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIBISLD, + GPIO_FN_VACK, + GPIO_FN_XTAL1L, + GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, + GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, + GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, + GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, + GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, + GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ + GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + + GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, + GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ + GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, + GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ + GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, + GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, + GPIO_FN_A0, GPIO_FN_BS_, + GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, + GPIO_FN_A14, GPIO_FN_KEYOUT5, + GPIO_FN_A15, GPIO_FN_KEYOUT4, + GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_KEYIN6, + GPIO_FN_KEYIN7, + GPIO_FN_D0_NAF0, + GPIO_FN_D1_NAF1, + GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, + GPIO_FN_D4_NAF4, + GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, + GPIO_FN_D7_NAF7, + GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, + GPIO_FN_D10_NAF10, + GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, + GPIO_FN_D13_NAF13, + GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + GPIO_FN_CS4_, + GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, + GPIO_FN_CS5B_, GPIO_FN_FCE1_, + GPIO_FN_CS6B_, GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_CS6A_, + GPIO_FN_WAIT_, GPIO_FN_DREQ0, + GPIO_FN_RD__FSC, + GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, + GPIO_FN_WE1_, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT_, + GPIO_FN_NBRST_, + GPIO_FN_BBIF2_TXD, + GPIO_FN_BBIF2_RXD, + GPIO_FN_BBIF2_SYNC, + GPIO_FN_BBIF2_SCK, + GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, + GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_TXD, + GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, + GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, + GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ + GPIO_FN_PORT115_I2C_SCL3, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ + GPIO_FN_PORT116_I2C_SDA3, + GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, + GPIO_FN_HSI_TX_FLAG, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ + GPIO_FN_LCD2D0, + + GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ + GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ + GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ + GPIO_FN_LCD2D6, + GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_LCD2D7, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ + GPIO_FN_LCD2D2, + GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_LCD2D4, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ + GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, + GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ + GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, + GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, + GPIO_FN_VIO_CKO, + GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_PORT149_KEYOUT9, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, + GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, + GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, + GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ + GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_LCDD8, GPIO_FN_D16, + GPIO_FN_LCDD9, GPIO_FN_D17, + GPIO_FN_LCDD10, GPIO_FN_D18, + GPIO_FN_LCDD11, GPIO_FN_D19, + GPIO_FN_LCDD12, GPIO_FN_D20, + GPIO_FN_LCDD13, GPIO_FN_D21, + GPIO_FN_LCDD14, GPIO_FN_D22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_LCDD17, GPIO_FN_D25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, + GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ + GPIO_FN_PORT218_VIO_CKOR, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ + GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ + GPIO_FN_LCD2DCK_2, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ + GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ + GPIO_FN_PORT221_LCD2HSYN, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_LCD2D20, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ + GPIO_FN_LCD2D21, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ + GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, + GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ + GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ + GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_SDHICLK0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, + GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, + GPIO_FN_SDHID0_3, + GPIO_FN_SDHICMD0, + GPIO_FN_SDHIWP0, + GPIO_FN_SDHICLK1, + GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, + GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, + GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, + GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, + GPIO_FN_SDHICMD1, + GPIO_FN_SDHICLK2, + GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, + GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, + GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, + GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, + GPIO_FN_SDHICMD2, + GPIO_FN_MMCCLK0, + GPIO_FN_MMCD0_0, + GPIO_FN_MMCD0_1, + GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, + GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, + GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, + GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, + GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, + GPIO_FN_MMCCMD0, + GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, + GPIO_FN_MCP_WAIT__MCP_FRB, + GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, + GPIO_FN_MCP_D15_MCP_NAF15, + GPIO_FN_MCP_D14_MCP_NAF14, + GPIO_FN_MCP_D13_MCP_NAF13, + GPIO_FN_MCP_D12_MCP_NAF12, + GPIO_FN_MCP_D11_MCP_NAF11, + GPIO_FN_MCP_D10_MCP_NAF10, + GPIO_FN_MCP_D9_MCP_NAF9, + GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, + GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, + + GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, + GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, + GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, + GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, + GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, + GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, + GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, + GPIO_FN_MCP_NBRSTOUT_, + GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, + + /* MSEL2 special case */ + GPIO_FN_TSIF2_TS_XX1, + GPIO_FN_TSIF2_TS_XX2, + GPIO_FN_TSIF2_TS_XX3, + GPIO_FN_TSIF2_TS_XX4, + GPIO_FN_TSIF2_TS_XX5, + GPIO_FN_TSIF1_TS_XX1, + GPIO_FN_TSIF1_TS_XX2, + GPIO_FN_TSIF1_TS_XX3, + GPIO_FN_TSIF1_TS_XX4, + GPIO_FN_TSIF1_TS_XX5, + GPIO_FN_TSIF0_TS_XX1, + GPIO_FN_TSIF0_TS_XX2, + GPIO_FN_TSIF0_TS_XX3, + GPIO_FN_TSIF0_TS_XX4, + GPIO_FN_TSIF0_TS_XX5, + GPIO_FN_MST1_TS_XX1, + GPIO_FN_MST1_TS_XX2, + GPIO_FN_MST1_TS_XX3, + GPIO_FN_MST1_TS_XX4, + GPIO_FN_MST1_TS_XX5, + GPIO_FN_MST0_TS_XX1, + GPIO_FN_MST0_TS_XX2, + GPIO_FN_MST0_TS_XX3, + GPIO_FN_MST0_TS_XX4, + GPIO_FN_MST0_TS_XX5, + + /* MSEL3 special cases */ + GPIO_FN_SDHI0_VCCQ_MC0_ON, + GPIO_FN_SDHI0_VCCQ_MC0_OFF, + GPIO_FN_DEBUG_MON_VIO, + GPIO_FN_DEBUG_MON_LCDD, + GPIO_FN_LCDC_LCDC0, + GPIO_FN_LCDC_LCDC1, + + /* MSEL4 special cases */ + GPIO_FN_IRQ9_MEM_INT, + GPIO_FN_IRQ9_MCP_INT, + GPIO_FN_A11, + GPIO_FN_KEYOUT8, + GPIO_FN_TPU4TO3, + GPIO_FN_RESETA_N_PU_ON, + GPIO_FN_RESETA_N_PU_OFF, + GPIO_FN_EDBGREQ_PD, + GPIO_FN_EDBGREQ_PU, + + /* Functions with pull-ups */ + GPIO_FN_KEYIN0_PU, + GPIO_FN_KEYIN1_PU, + GPIO_FN_KEYIN2_PU, + GPIO_FN_KEYIN3_PU, + GPIO_FN_KEYIN4_PU, + GPIO_FN_KEYIN5_PU, + GPIO_FN_KEYIN6_PU, + GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHICD0_PU, + GPIO_FN_SDHID0_0_PU, + GPIO_FN_SDHID0_1_PU, + GPIO_FN_SDHID0_2_PU, + GPIO_FN_SDHID0_3_PU, + GPIO_FN_SDHICMD0_PU, + GPIO_FN_SDHIWP0_PU, + GPIO_FN_SDHID1_0_PU, + GPIO_FN_SDHID1_1_PU, + GPIO_FN_SDHID1_2_PU, + GPIO_FN_SDHID1_3_PU, + GPIO_FN_SDHICMD1_PU, + GPIO_FN_SDHID2_0_PU, + GPIO_FN_SDHID2_1_PU, + GPIO_FN_SDHID2_2_PU, + GPIO_FN_SDHID2_3_PU, + GPIO_FN_SDHICMD2_PU, + GPIO_FN_MMCCMD0_PU, + GPIO_FN_MMCCMD1_PU, + GPIO_FN_MMCD0_0_PU, + GPIO_FN_MMCD0_1_PU, + GPIO_FN_MMCD0_2_PU, + GPIO_FN_MMCD0_3_PU, + GPIO_FN_MMCD0_4_PU, + GPIO_FN_MMCD0_5_PU, + GPIO_FN_MMCD0_6_PU, + GPIO_FN_MMCD0_7_PU, + GPIO_FN_FSIACK_PU, + GPIO_FN_FSIAILR_PU, + GPIO_FN_FSIAIBT_PU, + GPIO_FN_FSIAISLD_PU, + + /* end of GPIO */ + GPIO_NR, +}; + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_SCIF7_TX, + SHDMA_SLAVE_SCIF7_RX, + SHDMA_SLAVE_SCIF8_TX, + SHDMA_SLAVE_SCIF8_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, +}; + +/* + * SH73A0 IRQ LOCATION TABLE + * + * 416 ----------------------------------------- + * IRQ0-IRQ15 + * 431 ----------------------------------------- + * ... + * 448 ----------------------------------------- + * sh73a0-intcs + * sh73a0-intca-irq-pins + * 680 ----------------------------------------- + * ... + * 700 ----------------------------------------- + * sh73a0-pint0 + * 731 ----------------------------------------- + * 732 ----------------------------------------- + * sh73a0-pint1 + * 739 ----------------------------------------- + * ... + * 800 ----------------------------------------- + * IRQ16-IRQ31 + * 815 ----------------------------------------- + * ... + * 928 ----------------------------------------- + * sh73a0-intca-irq-pins + * 943 ----------------------------------------- + */ + +/* PINT interrupts are located at Linux IRQ 700 and up */ +#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) +#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) + +#endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h new file mode 100644 index 0000000..c33bf21 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh73a0.h @@ -0,0 +1,281 @@ +#ifndef __ASM_ARCH_RMOBILE_SH73A0_H +#define __ASM_ARCH_RMOBILE_SH73A0_H + +/* Global Timer */ +#define GLOBAL_TIMER_BASE_ADDR (0xF0000200) +#define MERAM_BASE (0xE5580000) + +/* GIC */ +#define GIC_BASE (0xF0000100) +#define ICCICR GIC_BASE + +/* Secure control register */ +#define LIFEC_SEC_SRC (0xE6110008) + +/* RWDT */ +#define RWDT_BASE (0xE6020000) + +/* HPB Semaphore Control Registers */ +#define HPB_BASE (0xE6001010) + +/* Bus Semaphore Control Registers */ +#define HPBSCR_BASE (0xE6001600) + +/* SBSC1 */ +#define SBSC1_BASE (0xFE400000) +#define SDMRA1A (SBSC1_BASE + 0x100000) +#define SDMRA2A (SBSC1_BASE + 0x1C0000) +#define SDMRA3A (SBSC1_BASE + 0x104000) + +/* SBSC2 */ +#define SBSC2_BASE (0xFB400000) +#define SDMRA1B (SBSC2_BASE + 0x100000) +#define SDMRA2B (SBSC2_BASE + 0x1C0000) +#define SDMRA3B (SBSC2_BASE + 0x104000) + +/* CPG */ +#define CPG_BASE (0xE6150000) +#define CPG_SRCR_BASE (CPG_BASE + 0x80A0) +#define WUPCR (CPG_BASE + 0x1010) +#define SRESCR (CPG_BASE + 0x1018) +#define PCLKCR (CPG_BASE + 0x1020) + +/* BSC */ +#define BSC_BASE (0xFEC10000) + +/* SCIF */ +#define SCIF0_BASE (0xE6C40000) +#define SCIF1_BASE (0xE6C50000) +#define SCIF2_BASE (0xE6C60000) +#define SCIF3_BASE (0xE6C70000) +#define SCIF4_BASE (0xE6C80000) +#define SCIF5_BASE (0xE6CB0000) +#define SCIF6_BASE (0xE6CC0000) +#define SCIF7_BASE (0xE6CD0000) + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct sh73a0_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 rwtcsra0; /* 0x04 */ + u16 rwtcsrb0; /* 0x08 */ +}; + +/* HPB Semaphore Control Registers */ +struct sh73a0_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; + u32 dummy1; /* 0x2C */ + u32 hpbctrl6; +}; + +/* Bus Semaphore Control Registers */ +struct sh73a0_hpb_bscr { + u32 mpsrc; /* 0x00 */ + u32 mpacctl; /* 0x04 */ + u32 dummy0[6]; + u32 smgpiosrc; /* 0x20 */ + u32 smgpioerr; + u32 smgpiotime; + u32 smgpiocnt; + u32 dummy1[4]; /* 0x30 .. 0x3C */ + u32 smcmt2src; + u32 smcmt2err; + u32 smcmt2time; + u32 smcmt2cnt; + u32 smcpgsrc; + u32 smcpgerr; + u32 smcpgtime; + u32 smcpgcnt; + u32 dummy2[4]; /* 0x60 - 0x6C */ + u32 smsyscsrc; + u32 smsyscerr; + u32 smsysctime; + u32 smsysccnt; +}; + +/* SBSC */ +struct sh73a0_sbsc { + u32 dummy0[2]; /* 0x00, 0x04 */ + u32 sdcr0; + u32 sdcr1; + u32 sdpcr; + u32 dummy1; /* 0x14 */ + u32 sdcr0s; + u32 sdcr1s; + u32 rtcsr; + u32 dummy2; /* 0x24 */ + u32 rtcor; + u32 rtcorh; + u32 rtcors; + u32 rtcorsh; + u32 dummy3[2]; /* 0x38, 0x3C */ + u32 sdwcrc0; + u32 sdwcrc1; + u32 sdwcr00; + u32 sdwcr01; + u32 sdwcr10; + u32 sdwcr11; + u32 sdpdcr0; + u32 dummy4; /* 0x5C */ + u32 sdwcr2; + u32 sdwcrc2; + u32 zqccr; + u32 dummy5[6]; /* 0x6C .. 0x80 */ + u32 sdmracr0; + u32 dummy6; /* 0x88 */ + u32 sdmrtmpcr; + u32 dummy7; /* 0x90 */ + u32 sdmrtmpmsk; + u32 dummy8; /* 0x98 */ + u32 sdgencnt; + u32 dphycnt0; + u32 dphycnt1; + u32 dphycnt2; + u32 dummy9[2]; /* 0xAC .. 0xB0 */ + u32 sddrvcr0; + u32 dummy10[14]; /* 0xB8 .. 0xEC */ + u32 dptdivcr0; + u32 dptdivcr1; + u32 dptdivcr2; + u32 dummy11; /* 0xFC */ + u32 sdptcr0; + u32 sdptcr1; + u32 sdptcr2; + u32 sdptcr3; /* 0x10C */ + u32 dummy12[145]; /* 0x110 .. 0x350 */ + u32 dllcnt0; /* 0x354 */ + u32 sbscmon0; +}; + +/* CPG */ +struct sh73a0_sbsc_cpg { + u32 frqcra; /* 0x00 */ + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 zbckcr; + u32 flckcr; + u32 fsiackcr; + u32 vclkcr3; + u32 rtstbcr; + u32 systbcr; + u32 pll1cr; + u32 pll2cr; + u32 mstpsr0; + u32 dummy0; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy1; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy2; /* 0x50 */ + u32 astat; + u32 dvfscr0; + u32 dvfscr1; + u32 dsitckcr; + u32 dsi0pckcr; + u32 dsi1pckcr; + u32 dsi0phycr; + u32 dsi1phycr; + u32 sd0ckcr; + u32 sd1ckcr; + u32 sd2ckcr; + u32 subckcr; + u32 spuackcr; + u32 msuckcr; + u32 hsickcr; + u32 fsibckcr; + u32 spuvckcr; + u32 mfck1cr; + u32 mfck2cr; + u32 dummy3[8]; /* 0xA0 .. 0xBC */ + u32 ckscr; + u32 dummy4; /* 0xC4 */ + u32 pll1stpcr; + u32 mpmode; + u32 pllecr; + u32 dummy5; /* 0xD4 */ + u32 pll0cr; + u32 pll3cr; + u32 dummy6; /* 0xE0 */ + u32 frqcrd; + u32 dummyi7; /* 0xE8 */ + u32 vrefcr; + u32 pll0stpcr; + u32 dummy8; /* 0xF4 */ + u32 pll2stpcr; + u32 pll3stpcr; + u32 dummy9[4]; /* 0x100 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy10[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; + u32 dummy11[10]; /* 0x148 .. 0x16c */ + u32 dvfscr2; + u32 dvfscr3; + u32 dvfscr4; + u32 dvfscr5; /* 0x17C */ +}; + +/* CPG SRCR part OK */ +struct sh73a0_sbsc_cpg_srcr { + u32 srcr0; + u32 dummy0; /* 0xA4 */ + u32 srcr1; + u32 dummy1; /* 0xAC */ + u32 srcr2; + u32 dummy2; /* 0xB4 */ + u32 srcr3; + u32 srcr4; + u32 dummy3; /* 0xC0 */ + u32 srcr5; +}; + +/* BSC */ +struct sh73a0_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0C */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 cs6bbcr; + u32 cs0wcr; + u32 cs2wcr; + u32 dummy1; /* 0x2C */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 cs6bwcr; + u32 rbwtcnt; + u32 busycr; + u32 dummy2; /* 0x5c */ + u32 cs7abcr; + u32 cs7awcr; + u32 dummy3[2]; /* 0x68, 0x6C */ + u32 bromtimcr; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sys_proto.h b/arch/arm/include/asm/arch-rmobile/sys_proto.h new file mode 100644 index 0000000..fad4e4e --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sys_proto.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct rmobile_sysinfo { + char *board_string; +}; +extern const struct rmobile_sysinfo sysinfo; + +#endif -- 1.7.10

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[U-Boot] [PATCH v3] arm: rmobile: Add support TMU base timer function
by Nobuhiro Iwamatsu 22 Aug '12

22 Aug '12

Some rmobile SoC has TMU base timer function. This supports TMU. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- V3: Merged arch/sh/lib/time.c Need patches * sh: tmu: Removed arch/sh/include/asm/clk.h * sh: tmu: Changed switch statement to shift operation * sh: tmu: Changed TMU driver using array of structures V2: Set COBJS one object per line, and sort the list. arch/arm/cpu/armv7/rmobile/Makefile | 3 ++- include/sh_tmu.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index a522872..dd0aede 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -27,11 +27,12 @@ LIB = $(obj)lib$(SOC).o SOBJS = lowlevel_init.o COBJS-y += cpu_info.o -COBJS-y += timer.o COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o +COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o +COBJS-$(CONFIG_TMU_TIMER) += $(TOPDIR)/arch/sh/lib/time.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/include/sh_tmu.h b/include/sh_tmu.h index a55d141..96c589d 100644 --- a/include/sh_tmu.h +++ b/include/sh_tmu.h @@ -47,7 +47,7 @@ struct tmu_regs { }; #endif /* CONFIG_SH3 */ -#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) +#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE) struct tmu_regs { u32 reserved; u8 tstr; -- 1.7.10

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[U-Boot] [Patch v3 1/2] net: introduce transparent driver private in ueth_data
by Lucas Stach 21 Aug '12

21 Aug '12

Avoid clutter in ueth_data. Individual drivers should not mess with structures belonging to the core like this. Signed-off-by: Lucas Stach <dev(a)lynxeye.de> --- drivers/usb/eth/smsc95xx.c | 48 ++++++++++++++++++++++++++++++++-------------- include/usb_ether.h | 8 ++------ 2 Dateien geändert, 36 Zeilen hinzugefügt(+), 20 Zeilen entfernt(-) diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index c62a8c1..4bf2a16 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -25,6 +25,7 @@ #include <usb.h> #include <linux/mii.h> #include "usb_ether.h" +#include "malloc.h" /* SMSC LAN95xx based USB 2.0 Ethernet Devices */ @@ -146,6 +147,12 @@ /* local vars */ static int curr_eth_dev; /* index for name of next device detected */ +/* driver private */ +struct smsc95xx_private { + size_t rx_urb_size; /* maximum USB URB size */ + u32 mac_cr; /* MAC control register value */ + int have_hwaddr; /* 1 if we have a hardware MAC address */ +}; /* * Smsc95xx infrastructure commands @@ -377,6 +384,7 @@ static int smsc95xx_init_mac_address(struct eth_device *eth, static int smsc95xx_write_hwaddr(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct smsc95xx_private *priv = dev->dev_priv; u32 addr_lo = __get_unaligned_le32(&eth->enetaddr[0]); u32 addr_hi = __get_unaligned_le16(&eth->enetaddr[4]); int ret; @@ -392,7 +400,7 @@ static int smsc95xx_write_hwaddr(struct eth_device *eth) return ret; debug("MAC %pM\n", eth->enetaddr); - dev->have_hwaddr = 1; + priv->have_hwaddr = 1; return 0; } @@ -425,19 +433,22 @@ static int smsc95xx_set_csums(struct ueth_data *dev, static void smsc95xx_set_multicast(struct ueth_data *dev) { + struct smsc95xx_private *priv = dev->dev_priv; + /* No multicast in u-boot */ - dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); } /* starts the TX path */ static void smsc95xx_start_tx_path(struct ueth_data *dev) { + struct smsc95xx_private *priv = dev->dev_priv; u32 reg_val; /* Enable Tx at MAC */ - dev->mac_cr |= MAC_CR_TXEN_; + priv->mac_cr |= MAC_CR_TXEN_; - smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr); + smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); /* Enable Tx at SCSRs */ reg_val = TX_CFG_ON_; @@ -447,8 +458,10 @@ static void smsc95xx_start_tx_path(struct ueth_data *dev) /* Starts the Receive path */ static void smsc95xx_start_rx_path(struct ueth_data *dev) { - dev->mac_cr |= MAC_CR_RXEN_; - smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr); + struct smsc95xx_private *priv = dev->dev_priv; + + priv->mac_cr |= MAC_CR_RXEN_; + smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr); } /* @@ -462,6 +475,7 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd) u32 burst_cap; int timeout; struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct smsc95xx_private *priv = (struct smsc95xx_private *)dev->dev_priv; #define TIMEOUT_RESOLUTION 50 /* ms */ int link_detected; @@ -504,9 +518,9 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd) debug("timeout waiting for PHY Reset\n"); return -1; } - if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) - dev->have_hwaddr = 1; - if (!dev->have_hwaddr) { + if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0) + priv->have_hwaddr = 1; + if (!priv->have_hwaddr) { puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); return -1; } @@ -532,16 +546,16 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd) #ifdef TURBO_MODE if (dev->pusb_dev->speed == USB_SPEED_HIGH) { burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; - dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; + priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; } else { burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; - dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; + priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; } #else burst_cap = 0; - dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE; + priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; #endif - debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); + debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); if (ret < 0) @@ -606,7 +620,7 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd) if (ret < 0) return ret; - ret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr); + ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr); if (ret < 0) return ret; @@ -857,6 +871,12 @@ int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, return 0; } dev->privptr = (void *)ss; + + /* alloc driver private */ + ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); + if (!ss->dev_priv) + return 0; + return 1; } diff --git a/include/usb_ether.h b/include/usb_ether.h index a7fb26b..7c7aecb 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -50,12 +50,8 @@ struct ueth_data { unsigned char protocol; /* .............. */ unsigned char irqinterval; /* Intervall for IRQ Pipe */ - /* private fields for each driver can go here if needed */ -#ifdef CONFIG_USB_ETHER_SMSC95XX - size_t rx_urb_size; /* maximum USB URB size */ - u32 mac_cr; /* MAC control register value */ - int have_hwaddr; /* 1 if we have a hardware MAC address */ -#endif + /* driver private */ + void *dev_priv; }; /* -- 1.7.11.4

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Re: [U-Boot] Support for USB Ethernet adapter
by Marek Vasut 21 Aug '12

21 Aug '12

Dear Daniel Ścisłowski, > Dear Mr Marek Vasut, CCing U-boot mailing list. Please keep it. > I would be grateful if you could tell me if U-Boot (currently I use > 2012.07) supports USB-Ethernet adapter Yes, it does support adapter based on ASIX chips and SMSC 95xx chips. > from MosChip Semiconductors MCS7830. Check the chipset or try it. > If not, is it possible to write driver for that device? Yes it is. It's not hard either. > Yours sincerely > Daniel Ścisłowski Best regards, Marek Vasut

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