August 2012 - U-Boot

[U-Boot] [PATCH] tegra20: rework UART GPIO handling
by Lucas Stach 21 Aug '12

21 Aug '12

Rename board provided gpio_config_uart() to gpio_early_init_uart() as it does the same thing as the equally called function provided by the uart-switch code. This allows to simply call this function in early board init whether or not we are building with CONFIG_UART_SWITCH defined. Also provide a weak symbol for this function, to avoid the need to provide this function for boards that don't need any fixup. This patch supersedes the earlier posted "tegra: convert gpio_config_uart to weak symbol". Build tested with MAKEALL -s tegra20 Signed-off-by: Lucas Stach <dev(a)lynxeye.de> --- arch/arm/cpu/arm720t/tegra20/board.h | 2 +- arch/arm/cpu/arm720t/tegra20/spl.c | 4 ---- board/avionic-design/common/tamonten.c | 7 ------- board/compal/paz00/paz00.c | 7 ------- board/compulab/trimslice/trimslice.c | 7 ------- board/nvidia/common/board.c | 10 ++++++---- board/nvidia/harmony/harmony.c | 7 ------- board/nvidia/seaboard/seaboard.c | 2 +- board/nvidia/whistler/whistler.c | 7 ------- 9 Dateien geändert, 8 Zeilen hinzugefügt(+), 45 Zeilen entfernt(-) diff --git a/arch/arm/cpu/arm720t/tegra20/board.h b/arch/arm/cpu/arm720t/tegra20/board.h index 61b91c0..260767d 100644 --- a/arch/arm/cpu/arm720t/tegra20/board.h +++ b/arch/arm/cpu/arm720t/tegra20/board.h @@ -22,4 +22,4 @@ */ void board_init_uart_f(void); -void gpio_config_uart(void); +void gpio_early_init_uart(void); diff --git a/arch/arm/cpu/arm720t/tegra20/spl.c b/arch/arm/cpu/arm720t/tegra20/spl.c index da723ef..183a2e1 100644 --- a/arch/arm/cpu/arm720t/tegra20/spl.c +++ b/arch/arm/cpu/arm720t/tegra20/spl.c @@ -65,11 +65,7 @@ void board_init_f(ulong dummy) board_init_uart_f(); /* Initialize periph GPIOs */ -#ifdef CONFIG_SPI_UART_SWITCH gpio_early_init_uart(); -#else - gpio_config_uart(); -#endif /* * We call relocate_code() with relocation target same as the diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index a0a4d1d..f5e6f6d 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -41,13 +41,6 @@ #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Tamonten - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index cd684f2..59cf41b 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -24,13 +24,6 @@ #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Paz00 - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} #ifdef CONFIG_TEGRA_MMC /* diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 5dae15b..f6de19e 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -34,13 +34,6 @@ #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on TrimSlice - no UART-related GPIOs. - */ -void gpio_config_uart(void) -{ -} void pin_mux_spi(void) { diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 7ab2040..78e136a 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -72,6 +72,11 @@ void __pin_mux_spi(void) void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); +void __gpio_early_init_uart(void) +{ +} + +void gpio_early_init_uart(void) __attribute__((weak, alias("__gpio_early_init_uart"))); /* * Routine: power_det_init * Description: turn off power detects @@ -156,11 +161,8 @@ int board_early_init_f(void) /* Initialize periph GPIOs */ gpio_early_init(); -#ifdef CONFIG_SPI_UART_SWITCH gpio_early_init_uart(); -#else - gpio_config_uart(); -#endif + return 0; } #endif /* EARLY_INIT */ diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 44977c7..5b75230 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -33,13 +33,6 @@ #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Harmony - no conflict w/SPI. - */ -void gpio_config_uart(void) -{ -} #ifdef CONFIG_TEGRA_MMC /* diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 3298a6b..7c4ff1b 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -46,7 +46,7 @@ static void gpio_config_uart_seaboard(void) gpio_direction_output(GPIO_PI3, 0); } -void gpio_config_uart(void) +void gpio_early_init_uart(void) { if (machine_is_ventana()) return; diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index c0a114d..cad7c48 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -34,13 +34,6 @@ #include <mmc.h> #endif -/* - * Routine: gpio_config_uart - * Description: Does nothing on Whistler - no UART-related GPIOs. - */ -void gpio_config_uart(void) -{ -} /* * Routine: pin_mux_mmc -- 1.7.11.4

3 2

[U-Boot] u-boot preventing access to NAND chip on imx28evk board
by Bill 21 Aug '12

21 Aug '12

All, I'm needing to access the NAND chip on the imx28evk board with the Linux (Freescale Kernel - FSL). I've compiled a recent version of the mainstream u-boot with the NAND switches and U-boot works fine. The U-boot also allows me access to the NAND chip and also boots the FSL kernel just fine. However, once the kernel is running, it can not "see" the /dev/mtdX devices. However, if I boot the *same* kernel directly (no U-boot - and attach boot-stream to kernel) the FSL kernel works fine and can gets the /dev/mtdX etc devices. I tracked this down to a couple of differences that are output during the kernel booting process. I also can replicate this problem with no NAND chip in the socket. I can do this by using the script that comes with the imx28evk that is used for formatting the SDCard for booting. The mk_mx28_sd script writes the uboot, kernel, and rootfs to an SDcard depending on the parameters. So if I write the uboot to the card and boot the imx28 from uboot and network boot uImage I get the error. If I write the kernel to the card and boot the imx28 with it I get no error (Using the same kernel). Here are the steps 1. Setup card for kernel boot - run mk_mx28_sd -b /dev/sdb (only writes kernel with bootstream on card) - place card in imx28 and boot it - the kernel (while booting) outputs these lines: ... ... i.MX GPMI NFC NFC: Version 1, 8-chip GPMI and BCH Boot ROM: Version 1, Single-chip boot area, block mark swapping supported Scanning for NAND Flash chips... No NAND device found. gpmi-nfc gpmi-nfc.0: Chip scan failed ... ... 2. Setup card for uboot -setup your host ubuntu so uboot can tftp your kernel -use *same* kernel from #1 (but use uImage) -run mk_mx28_sd -u -b /dev/sdb (only writes uboot with bootstream on card) -place card in imx28 and boot it -you may have to edit uboot parms to get your uImage from your host -Allow kernel to boot, it will output these lines: ... i.MX GPMI NFC NFC: Version 1, 8-chip GPMI and BCH gpmi-nfc: probe of gpmi-nfc.0 failed with error 1 ... ... So maybe U-boot does some things that prevents kernel from working or the kernel with the boot stream added on does the right things ? Thanks, Bill

2 5

[U-Boot] U-Boot API Problem
by Priebe, Sebastian 21 Aug '12

21 Aug '12

Hello, we recently switched to the OSELAS Toolchain for ARM1136 processors and faced a problem considering the u-boot API. If compiling the API demo with -Os (as default in u-boot) the demo does not run anymore. If activating -fno-relocate-functions in the used cflags the demo runs as before with our old toolchain. Can somebody tell me, why the demo doesn't run with relocate-functions activated? Does u-boot expect a special function on a fixed adress in the demo? Any information appreciated. Thanks. Sebastian --------------------------------------------------------------------------- +++ Willkommen bei CADCON auf der ILA Berlin Air Show +++ 11.-16.09.2012, ExpoCenter Airport, Halle 2, Stand 2204 --------------------------------------------------------------------------- CADCON Ingenieurgesellschaft mbH & Co. KG Geschaeftsfuehrer: Robert Bauer, Andreas Gundel Sitz der Gesellschaft: 86368 Gersthofen Registergericht: Amtsgericht Augsburg HRA 14521

1 0

[U-Boot] U-Boot API Demo Problem
by Priebe, Sebastian 21 Aug '12

21 Aug '12

Hello, we recently switched to the OSELAS Toolchain for ARM1136 processors and faced a problem considering the u-boot API. If compiling the API demo with -Os (as default in u-boot) the demo does not run anymore. If activating -fno-relocate-functions in the used cflags the demo runs as before with our old toolchain. Can somebody tell me, why the demo doesn't run with relocate-functions activated? Does u-boot expect a special function on a fixed adress in the demo? Any information appreciated. Thanks. Sebastian --------------------------------------------------------------------------- +++ Willkommen bei CADCON auf der ILA Berlin Air Show +++ 11.-16.09.2012, ExpoCenter Airport, Halle 2, Stand 2204 --------------------------------------------------------------------------- CADCON Ingenieurgesellschaft mbH & Co. KG Geschaeftsfuehrer: Robert Bauer, Andreas Gundel Sitz der Gesellschaft: 86368 Gersthofen Registergericht: Amtsgericht Augsburg HRA 14521

1 0

[U-Boot] [PATCH] MX28: SPI: Limit the DMA transfer length
by Marek Vasut 21 Aug '12

21 Aug '12

The upper limit for DMA transfer length on MX28 is 0x4000 bytes, otherwise the DMA refuses to operate. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/spi/mxs_spi.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index a037c13..fb6a167 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -287,9 +287,9 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; - int len = bitlen / 8; + struct mxs_spi_slave *sslave = to_mxs_slave(slave); + struct mxs_ssp_regs *regs = sslave->regs; + int len = bitlen / 8, tl, ret; char dummy; int write = 0; char *data = NULL; @@ -335,11 +335,24 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, dma = 0; } - if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { - writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); - return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); - } else { - writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); - return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); + while (len) { + if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { + tl = len; + writel(SSP_CTRL1_DMA_ENABLE, &regs->hw_ssp_ctrl1_clr); + ret = mxs_spi_xfer_pio(sslave, data, tl, write, flags); + } else { + /* 0x4000 bytes is the limit for DMA burst. */ + tl = min(len, 0x4000); + writel(SSP_CTRL1_DMA_ENABLE, &regs->hw_ssp_ctrl1_set); + ret = mxs_spi_xfer_dma(sslave, data, tl, write, flags); + } + + if (ret) + return ret; + + data += tl; + len -= tl; } + + return ret; } -- 1.7.10.4

2 1

[U-Boot] [PATCH] Take over the maintainer for sam9g10 and sam9m10g45
by Bo Shen 21 Aug '12

21 Aug '12

As the maintainer for at91sam9g10ek and at91sam9m10g45ek can not reach any more. So I wish to take over the maintainer for sam9g10 and sam9m10g45 Signed-off-by: Bo Shen <voice.shen(a)atmel.com> --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index c5a6f2f..07cc054 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -658,7 +658,7 @@ Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> meesc ARM926EJS (AT91SAM9263 SoC) otc570 ARM926EJS (AT91SAM9263 SoC) -Sedji Gaouaou<sedji.gaouaou(a)atmel.com> +Bo Shen<voice.shen(a)atmel.com> at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) -- 1.7.9.5

2 1

[U-Boot] [PATCH 1/3] powerpc/fsl-corenet: remove dead variant symbols
by Scott Wood 21 Aug '12

21 Aug '12

These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/Makefile | 3 -- arch/powerpc/include/asm/config_mpc85xx.h | 68 ++--------------------------- arch/powerpc/include/asm/immap_85xx.h | 2 +- drivers/net/fm/Makefile | 1 - include/configs/P2041RDB.h | 2 +- include/configs/P4080DS.h | 1 + include/configs/P5020DS.h | 2 +- 7 files changed, 7 insertions(+), 72 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 34f6c54..2b3a435 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -64,7 +64,6 @@ COBJS-$(CONFIG_P1024) += ddr-gen3.o COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o @@ -80,7 +79,6 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o @@ -114,7 +112,6 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b6c44bb..17bba26 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -333,30 +333,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#elif defined(CONFIG_PPC_P2040) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P2041) +#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -424,22 +401,7 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#elif defined(CONFIG_PPC_P4040) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P4080) +#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -475,31 +437,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -/* P5010 is single core version of P5020 */ -#elif defined(CONFIG_PPC_P5010) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P5020) +#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 53d563e..b49ee9b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1772,7 +1772,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif -#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \ +#if defined(CONFIG_PPC_P2041) \ || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 072b178..83ba580 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -36,7 +36,6 @@ COBJS-y += tgec_phy.o COBJS-$(CONFIG_P1017) += p1023.o COBJS-$(CONFIG_P1023) += p1023.o # The P204x, P304x, and P5020 are the same -COBJS-$(CONFIG_PPC_P2040) += p5020.o COBJS-$(CONFIG_PPC_P2041) += p5020.o COBJS-$(CONFIG_PPC_P3041) += p5020.o COBJS-$(CONFIG_PPC_P3060) += p3060.o diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1c0eb74..8a393c2 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -22,7 +22,7 @@ /* * P2041 RDB board configuration file - * + * Also supports P2040 RDB */ #ifndef __CONFIG_H #define __CONFIG_H diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 4a2e475..d6f2f5c 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -22,6 +22,7 @@ /* * P4080 DS board configuration file + * Also supports P4040 DS */ #define CONFIG_P4080DS #define CONFIG_PHYS_64BIT diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 4afc4f1..8625f76 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -22,7 +22,7 @@ /* * P5020 DS board configuration file - * + * Also supports P5010 DS */ #define CONFIG_P5020DS #define CONFIG_PHYS_64BIT -- 1.7.9.5

3 10

[U-Boot] WARNING: Caches not enabled on openrd based board
by Alex Zeffertt 21 Aug '12

21 Aug '12

Hi U-Booters, I get the following warning when I boot our openrd based board: > U-Boot 2012.07 (Aug 17 2012 - 10:45:29) > OpenRD-Base > > SoC: Kirkwood 88F6281_A1 > DRAM: 128 MiB > WARNING: Caches not enabled > NAND: 512 MiB I am running the latest code from git with a small number of changes to make it work with our hardware. (In particular we have had to rewrite board/Marvell/openrd/kwbimage.cfg.) My question is: does the warning about caches affect only U-Boot (in which case I don't mind) or will it also affect Linux? TIA, Alex

4 4

[U-Boot] [PATCH 1/5] sh: tmu: Changed TMU driver using array of structures
by Nobuhiro Iwamatsu 21 Aug '12

21 Aug '12

This changed into access using array of structure from access to the register using the definition of the register by macro. And removed white space. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/sh/include/asm/clk.h | 5 --- arch/sh/include/asm/cpu_sh7706.h | 5 +-- arch/sh/include/asm/cpu_sh7710.h | 5 +-- arch/sh/include/asm/cpu_sh7720.h | 10 ----- arch/sh/include/asm/cpu_sh7722.h | 11 +----- arch/sh/include/asm/cpu_sh7723.h | 11 +----- arch/sh/include/asm/cpu_sh7724.h | 11 +----- arch/sh/include/asm/cpu_sh7734.h | 4 +- arch/sh/include/asm/cpu_sh7750.h | 21 +---------- arch/sh/include/asm/cpu_sh7757.h | 14 +------ arch/sh/include/asm/cpu_sh7763.h | 5 +-- arch/sh/include/asm/cpu_sh7780.h | 24 +----------- arch/sh/include/asm/cpu_sh7785.h | 24 +----------- arch/sh/lib/time.c | 27 ++++++++------ include/sh_tmu.h | 75 ++++++++++++++++++++++++++++++++++++++ 15 files changed, 101 insertions(+), 151 deletions(-) create mode 100644 include/sh_tmu.h diff --git a/arch/sh/include/asm/clk.h b/arch/sh/include/asm/clk.h index 9cac6b0..2164bfb 100644 --- a/arch/sh/include/asm/clk.h +++ b/arch/sh/include/asm/clk.h @@ -27,9 +27,4 @@ static inline unsigned long get_peripheral_clk_rate(void) return CONFIG_SYS_CLK_FREQ; } -static inline unsigned long get_tmu0_clk_rate(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - #endif /* __ASM_SH_CLK_H__ */ diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h index d093f88..8066ff7 100644 --- a/arch/sh/include/asm/cpu_sh7706.h +++ b/arch/sh/include/asm/cpu_sh7706.h @@ -41,10 +41,7 @@ #define SCIF0_BASE SCSMR_2 /* Timer */ -#define TSTR0 0xFFFFFE92 -#define TSTR TSTR0 -#define TCNT0 0xFFFFFE98 -#define TCR0 0xFFFFFE9C +#define TMU_BASE 0xFFFFFE90 /* On chip oscillator circuits */ #define WTCNT 0xFFFFFF84 diff --git a/arch/sh/include/asm/cpu_sh7710.h b/arch/sh/include/asm/cpu_sh7710.h index e223f1c..e4ecef7 100644 --- a/arch/sh/include/asm/cpu_sh7710.h +++ b/arch/sh/include/asm/cpu_sh7710.h @@ -51,10 +51,7 @@ #define SCIF1_BASE SCSMR_1 /* Timer */ -#define TSTR0 0xA412FE92 -#define TSTR TSTR0 -#define TCNT0 0xa412FE98 -#define TCR0 0xa412FE9C +#define TMU_BASE 0xA412FE90 /* On chip oscillator circuits */ #define FRQCR 0xA415FF80 diff --git a/arch/sh/include/asm/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h index 1b393b8..a8013cc 100644 --- a/arch/sh/include/asm/cpu_sh7720.h +++ b/arch/sh/include/asm/cpu_sh7720.h @@ -105,16 +105,6 @@ /* TMU */ #define TMU_BASE 0xA412FE90 -#define TSTR (TMU_BASE + 0x02) -#define TCOR0 (TMU_BASE + 0x04) -#define TCNT0 (TMU_BASE + 0x08) -#define TCR0 (TMU_BASE + 0x0C) -#define TCOR1 (TMU_BASE + 0x10) -#define TCNT1 (TMU_BASE + 0x14) -#define TCR1 (TMU_BASE + 0x18) -#define TCOR2 (TMU_BASE + 0x1C) -#define TCNT2 (TMU_BASE + 0x20) -#define TCR2 (TMU_BASE + 0x24) /* TPU */ #define TPU_BASE 0xA4480000 diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h index 3157dcb..92dfe27 100644 --- a/arch/sh/include/asm/cpu_sh7722.h +++ b/arch/sh/include/asm/cpu_sh7722.h @@ -226,16 +226,7 @@ /* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 +#define TMU_BASE 0xFFD80000 /* TPU */ #define TPU_TSTR 0xA4C90000 diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h index 6dac6e9..2595f29 100644 --- a/arch/sh/include/asm/cpu_sh7723.h +++ b/arch/sh/include/asm/cpu_sh7723.h @@ -95,16 +95,7 @@ #define WTCNT RWTCNT /* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 +#define TMU_BASE 0xFFD80000 /* TPU */ diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h index 3bb51d3..cd40b6d 100644 --- a/arch/sh/include/asm/cpu_sh7724.h +++ b/arch/sh/include/asm/cpu_sh7724.h @@ -116,16 +116,7 @@ #define WTCNT RWTCNT /* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 +#define TMU_BASE 0xFFD80000 /* TPU */ diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h index 0f84b4f..179a357 100644 --- a/arch/sh/include/asm/cpu_sh7734.h +++ b/arch/sh/include/asm/cpu_sh7734.h @@ -36,9 +36,7 @@ #define SCIF5_BASE 0xFFE45000 /* Timer */ -#define TSTR 0xFFD80004 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 +#define TMU_BASE 0xFFD80000 /* PFC */ #define PMMR (0xFFFC0000) diff --git a/arch/sh/include/asm/cpu_sh7750.h b/arch/sh/include/asm/cpu_sh7750.h index b3e8424..88c4c8d 100644 --- a/arch/sh/include/asm/cpu_sh7750.h +++ b/arch/sh/include/asm/cpu_sh7750.h @@ -143,26 +143,7 @@ #define CLKSTPCLR 0xFE0A0008 /* TMU */ -#define TSTR2 0xFE100004 -#define TCOR3 0xFE100008 -#define TCNT3 0xFE10000C -#define TCR3 0xFE100010 -#define TCOR4 0xFE100014 -#define TCNT4 0xFE100018 -#define TCR4 0xFE10001C -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR TSTR0 +#define TMU_BASE 0xFFD80000 /* SCI */ #define SCSMR1 0xFFE00000 diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h index 17a6537..43c1f07 100644 --- a/arch/sh/include/asm/cpu_sh7757.h +++ b/arch/sh/include/asm/cpu_sh7757.h @@ -51,19 +51,7 @@ struct mmu_regs { #define SMR0 0xfe470000 /* TMU0 */ -#define TSTR 0xFE430004 -#define TOCR 0xFE430000 -#define TSTR0 0xFE430004 -#define TCOR0 0xFE430008 -#define TCNT0 0xFE43000C -#define TCR0 0xFE430010 -#define TCOR1 0xFE430014 -#define TCNT1 0xFE430018 -#define TCR1 0xFE43001C -#define TCOR2 0xFE430020 -#define TCNT2 0xFE430024 -#define TCR2 0xFE430028 -#define TCPR2 0xFE43002C +#define TMU_BASE 0xFE430000 /* ETHER, GETHER MAC address */ struct ether_mac_regs { diff --git a/arch/sh/include/asm/cpu_sh7763.h b/arch/sh/include/asm/cpu_sh7763.h index 78b456b..36d7065 100644 --- a/arch/sh/include/asm/cpu_sh7763.h +++ b/arch/sh/include/asm/cpu_sh7763.h @@ -43,9 +43,6 @@ #define WDTST 0xFFCC0000 /* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 +#define TMU_BASE 0xFFD80000 #endif /* _ASM_CPU_SH7763_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7780.h b/arch/sh/include/asm/cpu_sh7780.h index e9c59fe..162aa68 100644 --- a/arch/sh/include/asm/cpu_sh7780.h +++ b/arch/sh/include/asm/cpu_sh7780.h @@ -272,29 +272,7 @@ #define MSTPCR 0xFFC80030 /* Timer Unit */ -#define TSTR TSTR0 -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR1 0xFFDC0004 -#define TCOR3 0xFFDC0008 -#define TCNT3 0xFFDC000C -#define TCR3 0xFFDC0010 -#define TCOR4 0xFFDC0014 -#define TCNT4 0xFFDC0018 -#define TCR4 0xFFDC001C -#define TCOR5 0xFFDC0020 -#define TCNT5 0xFFDC0024 -#define TCR5 0xFFDC0028 +#define TMU_BASE 0xFFD80000 /* Timer/Counter */ #define CMTCFG 0xFFE30000 diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h index 4a4dfc9..8e3839d 100644 --- a/arch/sh/include/asm/cpu_sh7785.h +++ b/arch/sh/include/asm/cpu_sh7785.h @@ -46,29 +46,7 @@ #define WDTBCNT 0xFFCC0018 /* Timer Unit */ -#define TSTR TSTR0 -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR1 0xFFDC0004 -#define TCOR3 0xFFDC0008 -#define TCNT3 0xFFDC000C -#define TCR3 0xFFDC0010 -#define TCOR4 0xFFDC0014 -#define TCNT4 0xFFDC0018 -#define TCR4 0xFFDC001C -#define TCOR5 0xFFDC0020 -#define TCNT5 0xFFDC0024 -#define TCR5 0xFFDC0028 +#define TMU_BASE 0xFFD80000 /* Serial Communication Interface with FIFO */ #define SCIF1_BASE 0xffeb0000 diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index a01596c..4840472 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -2,7 +2,7 @@ * (C) Copyright 2009 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> * - * (C) Copyright 2007-2010 + * (C) Copyright 2007-2012 * Nobobuhiro Iwamatsu <iwamatsu(a)nigauri.org> * * (C) Copyright 2003 @@ -32,6 +32,9 @@ #include <asm/processor.h> #include <asm/clk.h> #include <asm/io.h> +#include <sh_tmu.h> + +static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE; #define TMU_MAX_COUNTER (~0UL) @@ -55,21 +58,21 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) return usec; } -static void tmu_timer_start (unsigned int timer) +static void tmu_timer_start(unsigned int timer) { if (timer > 2) return; - writeb(readb(TSTR) | (1 << timer), TSTR); + writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr); } -static void tmu_timer_stop (unsigned int timer) +static void tmu_timer_stop(unsigned int timer) { if (timer > 2) return; - writeb(readb(TSTR) & ~(1 << timer), TSTR); + writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr); } -int timer_init (void) +int timer_init(void) { /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */ u16 bit = 0; @@ -91,7 +94,7 @@ int timer_init (void) default: break; } - writew(readw(TCR0) | bit, TCR0); + writew(readw(&tmu->tcr0) | bit, &tmu->tcr0); /* Calc clock rate */ timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2); @@ -105,9 +108,9 @@ int timer_init (void) return 0; } -unsigned long long get_ticks (void) +unsigned long long get_ticks(void) { - unsigned long tcnt = 0 - readl(TCNT0); + unsigned long tcnt = 0 - readl(&tmu->tcnt0); if (last_tcnt > tcnt) /* overflow */ overflow_ticks++; @@ -116,7 +119,7 @@ unsigned long long get_ticks (void) return (overflow_ticks << 32) | tcnt; } -void __udelay (unsigned long usec) +void __udelay(unsigned long usec) { unsigned long long tmp; ulong tmo; @@ -128,13 +131,13 @@ void __udelay (unsigned long usec) /*NOP*/; } -unsigned long get_timer (unsigned long base) +unsigned long get_timer(unsigned long base) { /* return msec */ return tick_to_time(get_ticks()) - base; } -unsigned long get_tbclk (void) +unsigned long get_tbclk(void) { return timer_freq; } diff --git a/include/sh_tmu.h b/include/sh_tmu.h new file mode 100644 index 0000000..a55d141 --- /dev/null +++ b/include/sh_tmu.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SH_TMU_H +#define __SH_TMU_H + +#include <asm/types.h> + +#if defined(CONFIG_SH3) +struct tmu_regs { + u8 tocr; + u8 reserved0; + u8 tstr; + u8 reserved1; + u32 tcor0; + u32 tcnt0; + u16 tcr0; + u16 reserved2; + u32 tcor1; + u32 tcnt1; + u16 tcr1; + u16 reserved3; + u32 tcor2; + u32 tcnt2; + u16 tcr2; + u16 reserved4; + u32 tcpr2; +}; +#endif /* CONFIG_SH3 */ + +#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) +struct tmu_regs { + u32 reserved; + u8 tstr; + u8 reserved2[3]; + u32 tcor0; + u32 tcnt0; + u16 tcr0; + u16 reserved3; + u32 tcor1; + u32 tcnt1; + u16 tcr1; + u16 reserved4; + u32 tcor2; + u32 tcnt2; + u16 tcr2; + u16 reserved5; +}; +#endif /* CONFIG_SH4 */ + +static inline unsigned long get_tmu0_clk_rate(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +#endif /* __SH_TMU_H */ -- 1.7.10

1 2

[U-Boot] [PATCH] MX: Set a common gpio.h for all i.MX
by Stefano Babic 21 Aug '12

21 Aug '12

Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Matt Sealey <matt(a)genesi-usa.com> CC: Marek Vasut <marex(a)denx.de> CC: Benoit Thebaudeau <benoit.thebaudeau(a)advansee.com> CC: Jason Liu <jason.hui(a)linaro.org> --- arch/arm/include/asm/arch-mx25/gpio.h | 12 +-------- arch/arm/include/asm/arch-mx31/gpio.h | 7 +----- arch/arm/include/asm/arch-mx35/gpio.h | 12 +-------- arch/arm/include/asm/arch-mx5/gpio.h | 7 +----- arch/arm/include/asm/arch-mx6/gpio.h | 7 +----- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 -- arch/arm/include/asm/imx-common/gpio.h | 39 ++++++++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 1 + 8 files changed, 45 insertions(+), 42 deletions(-) create mode 100644 arch/arm/include/asm/imx-common/gpio.h diff --git a/arch/arm/include/asm/arch-mx25/gpio.h b/arch/arm/include/asm/arch-mx25/gpio.h index dc6edc7..5ab1f6d 100644 --- a/arch/arm/include/asm/arch-mx25/gpio.h +++ b/arch/arm/include/asm/arch-mx25/gpio.h @@ -30,16 +30,6 @@ */ #define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; /* data */ - u32 gpio_dir; /* direction */ - u32 psr; /* pad satus */ - u32 icr1; /* interrupt config 1 */ - u32 icr2; /* interrupt config 2 */ - u32 imr; /* interrupt mask */ - u32 isr; /* interrupt status */ - u32 edge_sel; /* edge select */ -}; +#include <asm/imx-common/gpio.h> #endif diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h index 95b73bf..55c0afa 100644 --- a/arch/arm/include/asm/arch-mx31/gpio.h +++ b/arch/arm/include/asm/arch-mx31/gpio.h @@ -25,11 +25,6 @@ #ifndef __ASM_ARCH_MX31_GPIO_H #define __ASM_ARCH_MX31_GPIO_H -/* GPIO Registers */ -struct gpio_regs { - u32 gpio_dr; - u32 gpio_dir; - u32 gpio_psr; -}; +#include <asm/imx-common/gpio.h> #endif diff --git a/arch/arm/include/asm/arch-mx35/gpio.h b/arch/arm/include/asm/arch-mx35/gpio.h index 7bcc3e8..1deb292 100644 --- a/arch/arm/include/asm/arch-mx35/gpio.h +++ b/arch/arm/include/asm/arch-mx35/gpio.h @@ -25,16 +25,6 @@ #ifndef __ASM_ARCH_MX35_GPIO_H #define __ASM_ARCH_MX35_GPIO_H -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; /* data */ - u32 gpio_dir; /* direction */ - u32 psr; /* pad satus */ - u32 icr1; /* interrupt config 1 */ - u32 icr2; /* interrupt config 2 */ - u32 imr; /* interrupt mask */ - u32 isr; /* interrupt status */ - u32 edge_sel; /* edge select */ -}; +#include <asm/imx-common/gpio.h> #endif diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h index 1dc34e9..b1b1218 100644 --- a/arch/arm/include/asm/arch-mx5/gpio.h +++ b/arch/arm/include/asm/arch-mx5/gpio.h @@ -25,11 +25,6 @@ #ifndef __ASM_ARCH_MX5_GPIO_H #define __ASM_ARCH_MX5_GPIO_H -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; - u32 gpio_dir; - u32 gpio_psr; -}; +#include <asm/imx-common/gpio.h> #endif diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h index 20c4e57..24c10f8 100644 --- a/arch/arm/include/asm/arch-mx6/gpio.h +++ b/arch/arm/include/asm/arch-mx6/gpio.h @@ -25,11 +25,6 @@ #ifndef __ASM_ARCH_MX6_GPIO_H #define __ASM_ARCH_MX6_GPIO_H -/* GPIO registers */ -struct gpio_regs { - u32 gpio_dr; - u32 gpio_dir; - u32 gpio_psr; -}; +#include <asm/imx-common/gpio.h> #endif /* __ASM_ARCH_MX6_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d77603..f3e58b5 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -172,8 +172,6 @@ #define IMX_IIM_BASE OCOTP_BASE_ADDR #define FEC_QUIRK_ENET_MAC -#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) - #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/imx-common/gpio.h b/arch/arm/include/asm/imx-common/gpio.h new file mode 100644 index 0000000..fcc25e8 --- /dev/null +++ b/arch/arm/include/asm/imx-common/gpio.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, <sbabic(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_IMX_GPIO_H +#define __ASM_ARCH_IMX_GPIO_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +/* GPIO registers */ +struct gpio_regs { + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ + u32 psr; /* pad satus */ +}; +#endif + +#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31)) + +#endif diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 0d376ba..700268e 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -31,6 +31,7 @@ #define CONFIG_MACH_TYPE 3769 #include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -- 1.7.9.5

6 17