July 2010 - U-Boot

[U-Boot] [PATCH 2/2] ppc4xx: DDR/ECC: Use correct macros to clear error status
by Stefan Roese 23 Jul '10

23 Jul '10

Use the correct macro instead of the hardcoded 0x4c to clear the ECC status in the 440/460 DDR(2) error status register after ECC initialization. Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants (440GX) use a different registers to clear this error status. Use the correct ones. Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/powerpc/cpu/ppc4xx/ecc.c | 21 ++++++++++++++++++++- arch/powerpc/include/asm/ppc4xx-sdram.h | 2 ++ 2 files changed, 22 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c index f105605..49f28d9 100644 --- a/arch/powerpc/cpu/ppc4xx/ecc.c +++ b/arch/powerpc/cpu/ppc4xx/ecc.c @@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address, /* clear ECC error repoting registers */ mtsdram(SDRAM_ECCES, 0xffffffff); - mtdcr(0x4c, 0xffffffff); +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) + /* + * IBM DDR(1) core (440GX): + * Clear Mx bits in SDRAM0_BESR0/1 + */ + mtsdram(SDRAM0_BESR0, 0xffffffff); + mtsdram(SDRAM0_BESR1, 0xffffffff); +#elif defined(CONFIG_440) + /* + * 440/460 DDR2 core: + * Clear EMID (Error PLB Master ID) in MQ0_ESL + */ + mtdcr(SDRAM_ERRSTATLL, 0xfff00000); +#else + /* + * 405EX(r) DDR2 core: + * Clear M0ID (Error PLB Master ID) in SDRAM_BESR + */ + mtsdram(SDRAM_BESR, 0xf0000000); +#endif mtsdram(SDRAM_MCOPT1, (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 42eac45..4ec1ef8 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -63,6 +63,8 @@ #define SDRAM_CFG0 0x20 /* memory controller options 0 */ #define SDRAM_CFG1 0x21 /* memory controller options 1 */ +#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */ +#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */ #define SDRAM0_BEAR 0x0010 /* bus error address reg */ #define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */ #define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */ -- 1.7.1.1

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[U-Boot] [PATCH 1/2] ppc4xx: Only define DDR2 registers for the correct PowerPC variants
by Stefan Roese 23 Jul '10

23 Jul '10

Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/powerpc/include/asm/ppc4xx-sdram.h | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index d9506e2..42eac45 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -363,6 +363,7 @@ /* * Memory controller registers */ +#ifdef CONFIG_405EX #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -371,11 +372,10 @@ #define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ -#ifndef CONFIG_405EX -#define SDRAM_MCSTAT 0x14 /* memory controller status */ -#else #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#endif +#else /* CONFIG_405EX */ +#define SDRAM_MCSTAT 0x14 /* memory controller status */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ -- 1.7.1.1

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[U-Boot] [PATCH v2] ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values
by Stefan Roese 23 Jul '10

23 Jul '10

Using this define, a board can define an opimized RFDC value and use the auto calibration code to "tune" the remaining DDR2 controller calibration register. Signed-off-by: Stefan Roese <sr(a)denx.de> --- v2: - Added comment to #else and #endif to better see where it belongs to arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 0f69ef9..5e35c61 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -767,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) debug("\n\n"); +#if defined(CONFIG_DDR_RFDC_FIXED) + mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED); + size = 512; + rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK; + mfsdram(SDRAM_RDCC, rdcc); /* record this value */ + cal->rdcc = rdcc; +#else /* CONFIG_DDR_RFDC_FIXED */ in_window = 0; rdcc = 0; @@ -830,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) rffd_average = SDRAM_RFDC_RFFD_MAX; mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); +#endif /* CONFIG_DDR_RFDC_FIXED */ rffd = rffd_average; in_window = 0; @@ -1211,10 +1219,14 @@ u32 DQS_autocalibration(void) debug("*** best_result: read value SDRAM_RQDC 0x%08x\n", rqdc_reg); +#if defined(CONFIG_DDR_RFDC_FIXED) + mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED); +#else /* CONFIG_DDR_RFDC_FIXED */ mfsdram(SDRAM_RFDC, rfdc_reg); rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd)); +#endif /* CONFIG_DDR_RFDC_FIXED */ mfsdram(SDRAM_RFDC, rfdc_reg); debug("*** best_result: read value SDRAM_RFDC 0x%08x\n", -- 1.7.1.1

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[U-Boot] [PATCH] ppc4xx: T3CORP fixes and updates
by Stefan Roese 23 Jul '10

23 Jul '10

This patch fixes some problems for the T3CORP board. Here the list of the changes: - Add 600-67 and 677 CPU frequency setting to chip_config command - Define CONFIG_DDR_RFDC_FIXED on t3corp: While using the "normal" auto calibration code, sometimes values for RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang upon relocation, while running from SDRAM). With this optimized RFDC value we can force this register and use the auto-calibration code to setup the remaining calibration registers. - Increase sizes of FPGA chips selects - EBC timing updated OEN=3 for 66 MHz EBC speed - Change ext. IRQ2 setup to level-low active - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the chip busy status. This is now used instead of the data toggle method which is used historically by default in the common CFI driver. With this change a problem with not written data is solved on this board, where a 32 byte block of data is still erased instead of filled with the correct content after these commands: => erase 0xfc100000 +0x1000000 ..................................................................... done Erased 128 sectors => cp.b 0x100000 0xfc100000 0x1000000 Copy to Flash... done => cmp.b 0x100000 0xfc100000 0x1000000 byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff) Total of 12637888 bytes were the same Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/t3corp/chip_config.c | 16 +++++++++++++++- board/t3corp/init.S | 8 +++++--- board/t3corp/t3corp.c | 2 +- include/configs/t3corp.h | 27 +++++++++++++-------------- 4 files changed, 34 insertions(+), 19 deletions(-) diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c index c00bf16..98ab49f 100644 --- a/board/t3corp/chip_config.c +++ b/board/t3corp/chip_config.c @@ -27,13 +27,27 @@ struct ppc4xx_config ppc4xx_config_val[] = { { - "600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100", + "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67", + { + 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0, + 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100", { 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 } }, { + "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", + { + 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0, + 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + } + }, + { "800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100", { 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, diff --git a/board/t3corp/init.S b/board/t3corp/init.S index 4a4217f..ecd35ff 100644 --- a/board/t3corp/init.S +++ b/board/t3corp/init.S @@ -81,11 +81,13 @@ tlbtab: tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG) /* TLB-entry for FPGA(s) */ - tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4, + tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4, + tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M, + CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG) + tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4, + tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4, AC_RW | SA_IG) /* TLB-entry for OCM */ diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c index 8ffa321..ddf5897 100644 --- a/board/t3corp/t3corp.c +++ b/board/t3corp/t3corp.c @@ -45,7 +45,7 @@ int board_early_init_f(void) mtdcr(UIC1SR, 0xffffffff); /* clear all */ mtdcr(UIC1ER, 0x00000000); /* disable all */ mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC1SR, 0xffffffff); /* clear all */ diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 0ecc5b1..7b88601 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -74,8 +74,8 @@ #define CONFIG_SYS_FLASH_SIZE (64 << 20) #define CONFIG_SYS_FPGA1_BASE 0xe0000000 -#define CONFIG_SYS_FPGA2_BASE 0xe0100000 -#define CONFIG_SYS_FPGA3_BASE 0xe0200000 +#define CONFIG_SYS_FPGA2_BASE 0xe2000000 +#define CONFIG_SYS_FPGA3_BASE 0xe4000000 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 @@ -84,14 +84,12 @@ (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ - /* * Initial RAM & stack pointer (placed in OCM) */ @@ -121,6 +119,7 @@ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ @@ -144,10 +143,13 @@ /* * DDR2 SDRAM */ +#define CONFIG_SYS_MBYTES_SDRAM 256 +#define CONFIG_DDR_ECC #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A +#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */ /* DDR1/2 SDRAM Device Control Register Data Values */ /* Memory Queue */ @@ -162,9 +164,6 @@ #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 -#define CONFIG_DDR_ECC -#define CONFIG_SYS_MBYTES_SDRAM 256 - #define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK /* DDR1/2 SDRAM Device Control Register Data Values */ @@ -417,7 +416,7 @@ #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -426,7 +425,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_32MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -434,7 +433,7 @@ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -443,7 +442,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -451,7 +450,7 @@ #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -460,7 +459,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) -- 1.7.1.1

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[U-Boot] [PATCH v3]ppc4xx/Canyonlands added USB board callbacks
by Rupjyoti Sarmah 23 Jul '10

23 Jul '10

Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell <dmitchell(a)appliedmicro.com> Signed-off-by: Rupjyoti Sarmah <rsarmah(a)appliedmicro.com> --- This patch incorporates the changes advised. The description of the Macros changed in the header file. Structure name changed. Unused Macros removed. board/amcc/canyonlands/canyonlands.c | 64 +++++++++++++++++++++++++++++----- include/configs/canyonlands.h | 8 ++++ 2 files changed, 63 insertions(+), 9 deletions(-) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 23874d2..158f7bb 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch DECLARE_GLOBAL_DATA_PTR; -#define CONFIG_SYS_BCSR3_PCIE 0x10 + struct board_bcsr { + u8 board_id; + u8 cpld_rev; + u8 led_user; + u8 board_status; + u8 reset_ctrl; + u8 flash_ctrl; + u8 eth_ctrl; + u8 usb_ctrl; + u8 irq_ctrl; +}; #define BOARD_CANYONLANDS_PCIE 1 #define BOARD_CANYONLANDS_SATA 2 @@ -112,6 +122,9 @@ int board_early_init_f(void) { #if !defined(CONFIG_ARCHES) u32 sdr0_cust0; + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; + #endif /* @@ -172,14 +185,10 @@ int board_early_init_f(void) #if !defined(CONFIG_ARCHES) /* Enable ethernet and take out of reset */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0); + out_8(&bcsr_data->eth_ctrl, 0) ; /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0); - - /* Enable USB host & USB-OTG */ - out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0); - + out_8(&bcsr_data->flash_ctrl, 0) ; mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ /* Setup PLB4-AHB bridge based on the system address map */ @@ -201,6 +210,41 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; + u8 val; + + /* Enable USB host & USB-OTG */ + val = in_8(&bcsr_data->usb_ctrl); + val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); + out_8(&bcsr_data->usb_ctrl, val); + + return 0; +} + +int usb_board_stop(void) +{ + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; + u8 val; + + /* Disable USB host & USB-OTG */ + val = in_8(&bcsr_data->usb_ctrl); + val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); + out_8(&bcsr_data->usb_ctrl, val); + + return 0; +} + +int usb_board_init_fail(void) +{ + return usb_board_stop(); +} +#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */ + #if !defined(CONFIG_ARCHES) static void canyonlands_sata_init(int board_type) { @@ -244,11 +288,13 @@ int get_cpu_num(void) #if !defined(CONFIG_ARCHES) int checkboard(void) { + struct board_bcsr *bcsr_data = + (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; char *s = getenv("serial#"); if (pvr_460ex()) { printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) + if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE) gd->board_type = BOARD_CANYONLANDS_PCIE; else gd->board_type = BOARD_CANYONLANDS_SATA; @@ -268,7 +314,7 @@ int checkboard(void) break; } - printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0))); + printf(", Rev. %X", in_8(&bcsr_data->cpld_rev)); if (s != NULL) { puts(", serial# "); diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ac9b3c5..6fe7639 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -77,6 +77,13 @@ #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +/* + * BCSR bits as defined in the Canyonlands board user manual. + */ +#define BCSR_USBCTRL_OTG_RST 0x32 +#define BCSR_USBCTRL_HOST_RST 0x01 +#define BCSR_SELECT_PCIE 0x10 + #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */ /* base address of inbound PCIe window */ @@ -417,6 +424,7 @@ #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_BOARD_INIT #endif /* -- 1.5.6.3

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[U-Boot] [PATCH 01/11] sh: Update lowlevel_init.S of rsk7203
by Nobuhiro Iwamatsu 22 Jul '10

22 Jul '10

Update data address size and fix typo of register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- board/renesas/rsk7203/lowlevel_init.S | 85 ++++++++++++++++++-------------- 1 files changed, 48 insertions(+), 37 deletions(-) diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index 7b9ecd8..30ef5ab 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -73,7 +73,7 @@ init_bsc_cs0: write32 CMNCR_A, CMNCR_D - write32 SC0BCR_A, SC0BCR_D + write32 CS0BCR_A, CS0BCR_D write32 CS0WCR_A, CS0WCR_D @@ -122,63 +122,82 @@ repeat0: CCR1_A: .long CCR1 CCR1_D: .long 0x0000090B PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 +PCCRL4_D0: .word 0x0000 +.align 2 PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 +PECRL4_D0: .word 0x0000 +.align 2 PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 +PECRL3_D: .word 0x0000 +.align 2 PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 +PCIORL_D: .word 0x4000 +.align 2 PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 +PFCRH2_D: .word 0x0000 +.align 2 PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 +PFCRH3_D: .word 0x0000 +.align 2 PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 +PFCRH1_D: .word 0x0000 +.align 2 PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 +PFIORH_D: .word 0x0729 +.align 2 PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 +PECRL1_D0: .word 0x0033 +.align 2 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 +WTCNT_D: .word 0x5A84 +.align 2 FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 +FRQCR_D: .word 0x0104 +.align 2 -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 CMNCR_A: .long 0xFFFC0000 CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 CS0WCR_A: .long 0xFFFC0028 CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 +PECRL4_D1: .word 0x0100 +.align 2 CS1WCR_A: .long 0xFFFC002C CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 +PCCRL4_D2: .word 0x0011 +.align 2 PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 +PCCRL3_D: .word 0x0011 +.align 2 PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 +PCCRL2_D: .word 0x1111 +.align 2 PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 +PCCRL1_D: .word 0x1010 PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 +PDCRL4_D: .word 0x0011 +.align 2 PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 +PDCRL3_D: .word 0x00011 +.align 2 PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 +PDCRL2_D: .word 0x1111 +.align 2 PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 +PDCRL1_D: .word 0x1000 +.align 2 CS3BCR_A: .long 0xFFFC0010 CS3BCR_D: .long 0x00004400 CS3WCR_A: .long 0xFFFC0034 @@ -190,13 +209,5 @@ RTCOR_D: .long 0xA55A0041 RTCSR_A: .long 0xFFFC0050 RTCSR_D: .long 0xa55a0010 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 -- 1.7.1

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[U-Boot] [PATCH] i2c: fix SDA contention in read_byte()
by Thomas Chou 22 Jul '10

22 Jul '10

We should not set SDA after TRISTATE, as it results in contention. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/i2c/soft_i2c.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 847db76..344b7f8 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -305,8 +305,8 @@ static uchar read_byte(int ack) /* * Read 8 bits, MSB first. */ - I2C_TRISTATE; I2C_SDA(1); + I2C_TRISTATE; data = 0; for(j = 0; j < 8; j++) { I2C_SCL(0); -- 1.7.1

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[U-Boot] [PATCH] p1022ds: add audclk hwconfig setting enable codec reference clock
by Timur Tabi 22 Jul '10

22 Jul '10

The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference clock for the audio codec, but by default both are disabled. Add a 'audclk' hwconfig option that allows the user to choose which clock he wants. The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48, 64, and 96KHz. The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and 88200Hz. Also configure a pin muxing to select some SSI signals, which will disable I2C1. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/p1022ds/p1022ds.c | 67 ++++++++++++++++++++++++++++++++----- include/configs/P1022DS.h | 1 + 2 files changed, 59 insertions(+), 9 deletions(-) diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index be692cb..e75f864 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -27,6 +27,7 @@ #include <asm/mp.h> #include <netdev.h> #include <i2c.h> +#include <hwconfig.h> #include "../common/ngpixis.h" @@ -90,34 +91,58 @@ phys_size_t initdram(int board_type) #define CONFIG_TFP410_I2C_ADDR 0x38 +/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 + +/* Route the I2C1 pins to the SSI port instead. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 + +/* Choose the 12.288Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 + +/* Choose the 11.2896Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 + int misc_init_r(void) { u8 temp; + const char *audclk; + size_t arglen; - /* Enable the TFP410 Encoder */ + /* For DVI, enable the TFP410 Encoder. */ temp = 0xBF; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n", temp); temp = 0x10; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n",temp); + /* + * Enable the reference clock for the WM8776 codec, and route the MUX + * pins for SSI. The default is the 12.288 MHz clock + */ + + temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | + CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); + temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; + + audclk = hwconfig_arg("audclk", &arglen); + /* Check the first two chars only */ + if (audclk && (strncmp(audclk, "11", 2) == 0)) + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; + else + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; + out_8(&pixis->brdcfg1, temp); + return 0; } @@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_OF_BOARD_SETUP +/** + * ft_codec_setup - fix up the clock-frequency property of the codec node + * + * Update the clock-frequency property based on the value of the 'audclk' + * hwconfig option. If audclk is not specified, then default to 12.288MHz. + */ +static void ft_codec_setup(void *blob, const char *compatible) +{ + const char *audclk; + size_t arglen; + u32 freq; + + audclk = hwconfig_arg("audclk", &arglen); + if (audclk && (strncmp(audclk, "11", 2) == 0)) + freq = 11289600; + else + freq = 12288000; + + do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); +} + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -343,6 +389,9 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + /* Update the WM8776 node's clock frequency property */ + ft_codec_setup(blob, "wlf,wm8776"); } #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index b42b5d0..0f7aca2 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -137,6 +137,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -- 1.7.0.1

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[U-Boot] Booting Linux on a Custom 460EX Board
by Chris Colicino 21 Jul '10

21 Jul '10

I've been trying to get u-boot to load the Linux operating system on a custom board based on the Canyonlands evaluation board. The custom board does not have a EEPROM, so I had to modify the memory initialization section of u-boot (specifically the initdram function in 44x_spd_ddr2.c). Once modified, u-boot loaded without error. I then wrote the kernel, filesystem, JFFS2 filesystem, and FDT images to flash memory. I then tried to boot the operating system using the command: run ramargs setip addip addtty; bootm 0xfc000000 0xfc200000 0xfc1e0000 On the evaluation board, the operating system loads without issue. On the custom board, it hangs with the last statement being: Booting using OF flat tree... One of the main differences is the absence of the EEPROM in the custom board. What are the contents of the EEPROM? Is the EEPROM used in booting the operating system? Is there any other way to boot the operating system (such as booting without an FDT image)?

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[U-Boot] uboot redundancy.
by Sagar Heroorkar 21 Jul '10

21 Jul '10

Hi All, I am planning to implement uboot redundancy. This means having the following idea which we thought. Golden-Uboot which is flashed in the NOR-FLASH. This is not field upgradable. This golden uboot is going to have logic to pick the other uboot based on certain flags or env vriables As i mentioned i wanted the uboot to be redundant. So i will have 2 copies of uboot now. Uboot1 Uboot2 Golden uboot will pick either of one uboots mentioned above. If the uboot1 which is picked fails to boot, then we will have uboot2 as back up to boot. vice versa. Golden uboot recides in the address fffa0000 (start.s). There is a relocation code which copies the code from flash to ram. if the uboot which i have picked addressess will change , hence how can i do the relocation? Any pointers will help me if any one already did this kind of approach making uboot redundant. -Sagar

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