July 2010 - U-Boot

[U-Boot] [PATCH 1/2] i2c: soft_i2c: add simple GPIO implementation
by Mike Frysinger 24 Jul '10

24 Jul '10

Since the vast majority of GPIO I2C implementations behave the same way, support the common GPIO framework with default settings. This adds two new defines CONFIG_SOFT_I2C_GPIO_{SCL,SDA} so that boards which want GPIO I2C support need only define these. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- README | 10 ++++++++++ drivers/i2c/soft_i2c.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 0 deletions(-) diff --git a/README b/README index a9c98f2..c9fb284 100644 --- a/README +++ b/README @@ -1495,6 +1495,16 @@ The following options need to be configured: #define I2C_DELAY udelay(2) + CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA + + If your arch supports the generic GPIO framework (asm/gpio.h), + then you may alternatively define the two GPIOs that are to be + used as SCL / SDA. Any of the previous I2C_xxx macros will + have GPIO-based defaults assigned to them as appropriate. + + You should define these to the GPIO value as given directly to + the generic GPIO functions. + CONFIG_SYS_I2C_INIT_BOARD When a board is reset during an i2c bus transfer diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index e0cf1e1..847db76 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -51,6 +51,48 @@ #endif #include <i2c.h> +#if defined(CONFIG_SOFT_I2C_GPIO_SCL) +# include <asm/gpio.h> + +# ifndef I2C_GPIO_SYNC +# define I2C_GPIO_SYNC +# endif + +# ifndef I2C_INIT +# define I2C_INIT \ + do { \ + gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, "soft_i2c"); \ + gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SCL, 0); \ + gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, "soft_i2c"); \ + } while (0) +# endif + +# ifndef I2C_ACTIVE +# define I2C_ACTIVE gpio_direction_output(CONFIG_SOFT_I2C_GPIO_SDA, 0) +# endif + +# ifndef I2C_TRISTATE +# define I2C_TRISTATE gpio_direction_input(CONFIG_SOFT_I2C_GPIO_SDA) +# endif + +# ifndef I2C_READ +# define I2C_READ (gpio_get_value(CONFIG_SOFT_I2C_GPIO_SDA) != 0) +# endif + +# ifndef I2C_SDA +# define I2C_SDA(bit) gpio_set_value(CONFIG_SOFT_I2C_GPIO_SDA, bit) +# endif + +# ifndef I2C_SCL +# define I2C_SCL(bit) gpio_set_value(CONFIG_SOFT_I2C_GPIO_SCL, bit) +# endif + +# ifndef I2C_DELAY +# define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +# endif + +#endif + /* #define DEBUG_I2C */ #ifdef DEBUG_I2C -- 1.7.1.1

3 8

[U-Boot] [PATCH V6 1/4] ide: add configuration CONFIG_IDE_SWAP_IO
by Albert Aribaud 24 Jul '10

24 Jul '10

This configuration option replaces a complex conditional in cmd_ide.c with an explicit define to be added to SoC or board configs. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- This patch set introduces CONFIG_IDE_SWAP_IO as suggested by Wolfgang Denk, adds orion5x support to cmd_ide.c and adds IDE support to edminiv2. Patchset history: V1: Initial 4-patch set -- not cleanly submitted (does not appear on gmane for instance) and contained some unrelated changes. V2: Slimmed down to 3 patches and removed unrelated changes. V3: Back to 4 patches (cmd_ide improvement, driver addition, cmd_ide support for orion, edminiv2 support for sata); made initialization code reuseable as a block driver ; moved to C structures; commented some constants. V4: Reordered objects alphabetically in drivers/block/Makefile. Shortened mv_sata to mvsata. Removed volatile qualifier in mvsata port structure. Moved port pointer definition from SoC to board code. Removed unrelated changes. V5: Fixed typo in mvsata_ide driver (IMP, should have been IPM). V6: Fixed case in ide register struct. Fixed warning in deminiv2.c Put IDE configuration under condition. arch/powerpc/include/asm/config.h | 3 +++ common/cmd_ide.c | 18 +++++++++--------- doc/README.PXA_CF | 8 ++++++++ include/configs/ap325rxa.h | 1 + include/configs/ms7720se.h | 1 + include/configs/r2dplus.h | 1 + include/configs/r7780mp.h | 1 + 7 files changed, 24 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index fc3facb..371989d 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -76,4 +76,7 @@ /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS +/* All PPC boards must swap IDE bytes */ +#define CONFIG_IDE_SWAP_IO + #endif /* _ASM_CONFIG_H_ */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index d486697..9292a5b 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -853,7 +853,7 @@ input_swap_data(int dev, ulong *sect_buf, int words) #endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) +#if defined(CONFIG_IDE_SWAP_IO) static void output_data(int dev, ulong *sect_buf, int words) { @@ -897,15 +897,15 @@ output_data(int dev, ulong *sect_buf, int words) } #endif } -#else /* ! __PPC__ */ +#else /* ! CONFIG_IDE_SWAP_IO */ static void output_data(int dev, ulong *sect_buf, int words) { outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1); } -#endif /* __PPC__ */ +#endif /* CONFIG_IDE_SWAP_IO */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) +#if defined(CONFIG_IDE_SWAP_IO) static void input_data(int dev, ulong *sect_buf, int words) { @@ -955,14 +955,14 @@ input_data(int dev, ulong *sect_buf, int words) } #endif } -#else /* ! __PPC__ */ +#else /* ! CONFIG_IDE_SWAP_IO */ static void input_data(int dev, ulong *sect_buf, int words) { insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1); } -#endif /* __PPC__ */ +#endif /* CONFIG_IDE_SWAP_IO */ /* ------------------------------------------------------------------------- */ @@ -1579,7 +1579,7 @@ int ide_device_present(int dev) * ATAPI Support */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +#if defined(CONFIG_IDE_SWAP_IO) /* since ATAPI may use commands with not 4 bytes alligned length * we have our own transfer functions, 2 bytes alligned */ static void @@ -1646,7 +1646,7 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts) #endif } -#else /* ! __PPC__ */ +#else /* ! CONFIG_IDE_SWAP_IO */ static void output_data_shorts(int dev, ushort *sect_buf, int shorts) { @@ -1659,7 +1659,7 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts) insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts); } -#endif /* __PPC__ */ +#endif /* CONFIG_IDE_SWAP_IO */ /* * Wait until (Status & mask) == res, or timeout (in ms) diff --git a/doc/README.PXA_CF b/doc/README.PXA_CF index 6a0f236..1d76b32 100644 --- a/doc/README.PXA_CF +++ b/doc/README.PXA_CF @@ -6,6 +6,14 @@ follow the connections of the standard lubbock. Anyway just the block marked memory configuration should be touched since the other parameters are imposed by the PXA architecture. +EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined +would cause looping on inw()/outw() rather than using insw()/outsw(), +thus making sure IDE / ATA bytes are properly swapped. This behaviour +is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with +PCMCIA should #define CONFIG_IDE_SWAP_IO. + +#define CONFIG_IDE_SWAP_IO + #define CONFIG_PXA_PCMCIA 1 #define CONFIG_PXA_IDE 1 diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 70dd47e..80a5797 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -138,6 +138,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */ #define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */ +#define CONFIG_IDE_SWAP_IO /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index ba0a3f8..0ea3527 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -122,5 +122,6 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ +#define CONFIG_IDE_SWAP_IO #endif /* __MS7720SE_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 8931b97..955f3ff 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -96,6 +96,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ +#define CONFIG_IDE_SWAP_IO /* * SuperH PCI Bridge Configration diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 71c570e..3afe93a 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -171,6 +171,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ +#define CONFIG_IDE_SWAP_IO #endif /* CONFIG_CMD_IDE */ #endif /* __R7780RP_H */ -- 1.6.4.4

1 3

[U-Boot] [PATCH] NAND: add Samsung K9LBG08UXD identifier
by Lei Wen 23 Jul '10

23 Jul '10

The Samsung K9LBG08UXD parts are 32Gbytes x 8 bits 3.3V parts with the 0xD7 identifier. Add this to the list of known devices IDs. Signed-off-by: Lei Wen <leiwen(a)marvell.com> --- drivers/mtd/nand/nand_ids.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 25b22ec..3d958d8 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -111,6 +111,9 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + /* 32 Gigabit */ + {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS16}, + /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is

3 6

[U-Boot] [PATCH 0/8] ARMV7: Enhance support for OMAP4
by Steve Sakoman 23 Jul '10

23 Jul '10

This patch series adds support for: - pad mux initialization - OMAP4 TWL6030 companion chip initialization - usb driver and gadget support It also fixes issues in the udelay implementation and the OMAP I2C driver as well as tweaks the default environment. These patches were tested on Panda and OMAP4430 SDP as well as on the Gumstix Overo to verify that there were no regressions on OMAP3. Steve Sakoman (9): ARMV7: Add pad mux support for OMAP4 ARMV7: Fix udelay for OMAP4 ARMV7: Modify i2c driver for more reliable operation on OMAP4 ARMV7: Add support for the TWL6030 I2C power chip used in OMAP4 systems ARMV7: Restructure omap3 musb driver to allow code sharing between OMAP3 and OMAP4 ARMV7: Enable musb driver and usbtty on OMAP4430 SDP ARMV7: Enable musb driver and usbtty on OMAP4 Panda ARMV7: Update default environment for OMAP4 boards arch/arm/cpu/armv7/omap-common/timer.c | 9 - arch/arm/cpu/armv7/omap4/board.c | 11 + arch/arm/include/asm/arch-omap3/cpu.h | 3 + arch/arm/include/asm/arch-omap3/i2c.h | 4 +- arch/arm/include/asm/arch-omap4/cpu.h | 3 + arch/arm/include/asm/arch-omap4/mux_omap4.h | 344 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/omap4.h | 2 + board/ti/panda/panda.c | 27 ++ board/ti/panda/panda.h | 265 +++++++++++++++++++++ board/ti/sdp4430/sdp.c | 27 ++ board/ti/sdp4430/sdp.h | 265 +++++++++++++++++++++ drivers/i2c/omap24xx_i2c.c | 37 ++- drivers/i2c/omap24xx_i2c.h | 4 + drivers/power/Makefile | 1 + drivers/power/twl6030.c | 77 ++++++ drivers/usb/musb/omap3.c | 16 ++ drivers/usb/musb/omap3.h | 3 +- include/configs/omap4_panda.h | 28 ++- include/configs/omap4_sdp4430.h | 28 ++- include/twl6030.h | 90 +++++++ 20 files changed, 1215 insertions(+), 29 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap4/mux_omap4.h create mode 100644 board/ti/panda/panda.h create mode 100644 board/ti/sdp4430/sdp.h create mode 100644 drivers/power/twl6030.c create mode 100644 include/twl6030.h

3 14

Re: [U-Boot] Supporting two boards which are almost similar
by Detlev Zundel 23 Jul '10

23 Jul '10

Hi Sudhakar, > On Fri, Jun 25, 2010 at 16:40:19, Sudhakar Rajashekhara wrote: >> Hi, >> >> Spectrum digital has two versions of DM6467 EVM, DM6467 and DM6467T. >> Though there are some video related differences between these two boards, >> from U-Boot perspective the only difference the developer need to worry >> is the different oscillator frequency. DM6467 has 27MHz crystal but >> DM6467T has 33MHz crystal. Both these EVMs are registered as two different >> boards in mach-types.h. Existing U-Boot has support DM6467 EVM which has >> 27MHz crystal. How should I go about adding support for DM6467T EVM which >> has 33MHz crystal? Do I need to add a new configuration file for this or >> can I make use of the existing configuration file in any way? >> >> One method I was aware of was, using some scripting from the top level >> Makefile but I believe this is not recommended. >> > > Any other method of achieving this? Actually I'm just in the process of answering your question. My immediate response would have been "use -t for mkconfig" but this does not (yet) work for boards.cfg versions. So I'm just in the process of testing a mkconfig extension to allow for similar handling of "BOARD_OPTION1_OPTION2" configurations which will be split into 'CONFIG_MK_{BOARD,OPTION1,OPTION2}' defines. When we have this, we can use a common config file and use #ifdefs for these CONFIG_MK defines. Stay tuned Detlev -- A foolish consistency is the hobgoblin of little minds. -- Ralph Waldo Emerson -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu(a)denx.de

2 1

[U-Boot] spi utility command support
by shashikiran.bevenkatti＠wipro.com 23 Jul '10

23 Jul '10

Hi, I'm using u-boot-2009.11, please help in enabling sspi utility command for MPC8569MDS board. I included the macro "#define CONFIG_CMD_SPI" in the file "include/configs/MPC8569MDS.h". following is the error when i done make. common/libcommon.a(cmd_spi.o): In function `do_spi': /home/shashi/u-boot-2009.11/common/cmd_spi.c:111: undefined reference to `spi_setup_slave' /home/shashi/u-boot-2009.11/common/cmd_spi.c:120: undefined reference to `spi_claim_bus' /home/shashi/u-boot-2009.11/common/cmd_spi.c:121: undefined reference to `spi_xfer' /home/shashi/u-boot-2009.11/common/cmd_spi.c:131: undefined reference to `spi_release_bus' /home/shashi/u-boot-2009.11/common/cmd_spi.c:132: undefined reference to `spi_free_slave' common/libcommon.a(exports.o):(.got2+0x3c): undefined reference to `spi_init' common/libcommon.a(exports.o):(.got2+0x40): undefined reference to `spi_setup_slave' common/libcommon.a(exports.o):(.got2+0x44): undefined reference to `spi_free_slave' common/libcommon.a(exports.o):(.got2+0x48): undefined reference to `spi_claim_bus' common/libcommon.a(exports.o):(.got2+0x4c): undefined reference to `spi_release_bus' common/libcommon.a(exports.o):(.got2+0x50): undefined reference to `spi_xfer' make: *** [u-boot] Error 1 Thanks & Regards, Shashikiran Please do not print this email unless it is absolutely necessary. The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com

2 1

[U-Boot] [PATCH] ppc4xx: Enable "ecctest" command on t3corp
by Stefan Roese 23 Jul '10

23 Jul '10

Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/t3corp.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 0ecc5b1..3647272 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -360,6 +360,7 @@ * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM -- 1.7.1.1

1 1

[U-Boot] [PATCH] ppc4xx: Enable "ecctest" command on katmai
by Stefan Roese 23 Jul '10

23 Jul '10

Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/katmai.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index fb8ccae..76e9a76 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -202,6 +202,7 @@ */ #define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DATE +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_PCI -- 1.7.1.1

1 1

[U-Boot] [PATCH] ppc4xx: Add ECC status info to machine-check exception for IBM DDR2 core
by Stefan Roese 23 Jul '10

23 Jul '10

Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/powerpc/cpu/ppc4xx/traps.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c index 1616772..b5562ad 100644 --- a/arch/powerpc/cpu/ppc4xx/traps.c +++ b/arch/powerpc/cpu/ppc4xx/traps.c @@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs) /* Clear MCSR */ mtspr(SPRN_MCSR, val); } + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) + /* + * Read and print ECC status register/info: + * The faulting address is only known upon uncorrectable ECC + * errors. + */ + mfsdram(SDRAM_ECCES, val); + if (val & SDRAM_ECCES_CE) + printf("ECC: Correctable error\n"); + if (val & SDRAM_ECCES_UE) { + printf("ECC: Uncorrectable error at 0x%02x%08x\n", + mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL)); + } +#endif /* CONFIG_DDR_ECC ... */ + #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) mfsdram(DDR0_00, val) ; printf("DDR0: DDR0_00 %lx\n", val); -- 1.7.1.1

1 1

[U-Boot] [PATCH] ppc4xx: Add "ecctest" command to test/simulate ECC errors
by Stefan Roese 23 Jul '10

23 Jul '10

This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/powerpc/cpu/ppc4xx/Makefile | 3 + arch/powerpc/cpu/ppc4xx/cmd_ecctest.c | 284 +++++++++++++++++++++++++++++++++ 2 files changed, 287 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/ppc4xx/cmd_ecctest.c diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index 88d53fb..c9c1a33 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -51,6 +51,9 @@ COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o COBJS += ecc.o +ifdef CONFIG_CMD_ECCTEST +COBJS += cmd_ecctest.o +endif COBJS += fdt.o COBJS += interrupts.o COBJS += iop480_uart.o diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c new file mode 100644 index 0000000..b4eac40 --- /dev/null +++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c @@ -0,0 +1,284 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/cache.h> + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ + defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) + +#if defined(CONFIG_405EX) +/* + * Currently only 405EX uses 16bit data bus width as an alternative + * option to 32bit data width (SDRAM0_MCOPT1_WDTH) + */ +#define SDRAM_DATA_ALT_WIDTH 2 +#else +#define SDRAM_DATA_ALT_WIDTH 8 +#endif + +#if defined(CONFIG_SYS_OCM_BASE) +#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE +#endif + +#if defined(CONFIG_SYS_ISRAM_BASE) +#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE +#endif + +#if !defined(CONFIG_FUNC_ISRAM_ADDR) +#error "No internal SRAM/OCM provided!" +#endif + +#define force_inline inline __attribute__ ((always_inline)) + +static inline void machine_check_disable(void) +{ + mtmsr(mfmsr() & ~MSR_ME); +} + +static inline void machine_check_enable(void) +{ + mtmsr(mfmsr() | MSR_ME); +} + +/* + * These helper functions need to be inlined, since they + * are called from the functions running from internal SRAM. + * SDRAM operation is forbidden at that time, so calling + * functions in SDRAM has to be avoided. + */ +static force_inline void wait_ddr_idle(void) +{ + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); +} + +static force_inline void recalibrate_ddr(void) +{ + u32 val; + + /* + * Rewrite RQDC & RFDC to calibrate again. If this is not + * done, the SDRAM controller is working correctly after + * changing the MCOPT1_MCHK bits. + */ + mfsdram(SDRAM_RQDC, val); + mtsdram(SDRAM_RQDC, val); + mfsdram(SDRAM_RFDC, val); + mtsdram(SDRAM_RFDC, val); +} + +static force_inline void set_mcopt1_mchk(u32 bits) +{ + u32 val; + + wait_ddr_idle(); + mfsdram(SDRAM_MCOPT1, val); + mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits); + recalibrate_ddr(); +} + +/* + * The next 2 functions are copied to internal SRAM/OCM and run + * there. No function calls allowed here. No SDRAM acitivity should + * be done here. + */ +static void inject_ecc_error(void *ptr, int par) +{ + u32 val; + + /* + * Taken from PPC460EX/EXr/GT users manual (Rev 1.21) + * 22.2.17.13 ECC Diagnostics + * + * Items 1 ... 5 are already done by now, running from RAM + * with ECC enabled + */ + + out_be32(ptr, 0x00000000); + val = in_be32(ptr); + + /* 6. Set memory controller to no error checking */ + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON); + + /* 7. Modify one or two bits for error simulation */ + if (par == 1) + out_be32(ptr, in_be32(ptr) ^ 0x00000001); + else + out_be32(ptr, in_be32(ptr) ^ 0x00000003); + + /* 8. Wait for SDRAM idle */ + val = in_be32(ptr); + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); + + /* Wait for SDRAM idle */ + wait_ddr_idle(); + + /* Continue with 9. in calling function... */ +} + +static void rewrite_ecc_parity(void *ptr, int par) +{ + u32 current_address = (u32)ptr; + u32 end_address; + u32 address_increment; + u32 mcopt1; + u32 val; + + /* + * Fill ECC parity byte again. Otherwise further accesses to + * the failure address will result in exceptions. + */ + + /* Wait for SDRAM idle */ + val = in_be32(0x00000000); + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN); + + /* ECC bit set method for non-cached memory */ + mfsdram(SDRAM_MCOPT1, mcopt1); + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) + address_increment = 4; + else + address_increment = SDRAM_DATA_ALT_WIDTH; + end_address = current_address + CONFIG_SYS_CACHELINE_SIZE; + + while (current_address < end_address) { + *((unsigned long *)current_address) = 0; + current_address += address_increment; + } + + set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); + + /* Wait for SDRAM idle */ + wait_ddr_idle(); +} + +static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 old_val; + u32 val; + u32 *ptr; + void (*sram_func)(u32 *, int); + int error; + + if (argc < 3) { + cmd_usage(cmdtp); + return 1; + } + + ptr = (u32 *)simple_strtoul(argv[1], NULL, 16); + error = simple_strtoul(argv[2], NULL, 16); + if ((error < 1) || (error > 2)) { + cmd_usage(cmdtp); + return 1; + } + + printf("Using address %p for %d bit ECC error injection\n", + ptr, error); + + /* + * Save value to restore it later on + */ + old_val = in_be32(ptr); + + /* + * Copy ECC injection function into internal SRAM/OCM + */ + sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR; + memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000); + + /* + * Disable interrupts and exceptions before calling this + * function in internal SRAM/OCM + */ + disable_interrupts(); + machine_check_disable(); + eieio(); + + /* + * Jump to ECC simulation function in internal SRAM/OCM + */ + (*sram_func)(ptr, error); + + /* 10. Read the corresponding address */ + val = in_be32(ptr); + + /* + * Read and print ECC status register/info: + * The faulting address is only known upon uncorrectable ECC + * errors. + */ + mfsdram(SDRAM_ECCES, val); + if (val & SDRAM_ECCES_CE) + printf("ECC: Correctable error\n"); + if (val & SDRAM_ECCES_UE) { + printf("ECC: Uncorrectable error at 0x%02x%08x\n", + mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL)); + } + + /* + * Clear pending interrupts/exceptions + */ + mtsdram(SDRAM_ECCES, 0xffffffff); + mtdcr(SDRAM_ERRSTATLL, 0xff000000); + set_mcsr(get_mcsr()); + + /* Now enable interrupts and exceptions again */ + eieio(); + machine_check_enable(); + enable_interrupts(); + + /* + * The ECC parity byte need to be re-written for the + * corresponding address. Otherwise future accesses to it + * will result in exceptions. + * + * Jump to ECC parity generation function + */ + memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000); + (*sram_func)(ptr, 0); + + /* + * Restore value in corresponding address + */ + out_be32(ptr, old_val); + + return 0; +} + +U_BOOT_CMD( + ecctest, 3, 0, do_ecctest, + "Test ECC by single and double error bit injection", + "address 1/2" +); + +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ -- 1.7.1.1

1 1