July 2010 - U-Boot

[U-Boot] [PATCH] [mips] add $(ENDIANNESS) option when link hello_world example
by Xiangfu Liu 27 Jul '10

27 Jul '10

Hi form the document about OUTPUT_FORMAT(default, big, little) If neither -EB nor -EL are used, output format will be the first argument. If -EB is used, the output format will be the second argument. If -EL is used, the output format will be the third argument. so change the mips.lds third argument to little and add $(ENDIANNESS) to linker args. this patch have tested with "./MAKEALL mips mips_el" Signed-off-by: Xiangfu Liu <xiangfu(a)openmobilefree.net> --- arch/mips/config.mk | 2 +- examples/standalone/mips.lds | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index aa06761..cc3719f 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= mips_4KC- -STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds +STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds $(ENDIANNESS) PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds index 717b201..63a1c92 100644 --- a/examples/standalone/mips.lds +++ b/examples/standalone/mips.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) SECTIONS { -- 1.7.0.4

2 3

[U-Boot] [PATCH] fdt: Add function to alloc phandle values
by Kumar Gala 26 Jul '10

26 Jul '10

If we are creating reference (handles) to nodes in a device tree we need to first create a new phandle in node and this needs a new phandle value. So we search through the whole dtb to find the max phandle value and return the next greater value for a new phandle allocation. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- common/fdt_support.c | 16 ++++++++++++++++ include/fdt_support.h | 1 + 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 718b635..30c662a 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1151,4 +1151,20 @@ int fdt_node_offset_by_compat_reg(void *blob, const char *compat, return -FDT_ERR_NOTFOUND; } +/** + * fdt_alloc_phandle: Return next free phandle value + * + * @blob: ptr to device tree + */ +int fdt_alloc_phandle(void *blob) +{ + int offset, len, phandle = 0; + const u32 *val; + for (offset = fdt_next_node(blob, -1, NULL); offset >= 0; + offset = fdt_next_node(blob, offset, NULL)) { + val = fdt_getprop(blob, offset, "linux,phandle", &len); + if (val) phandle = max(*val, phandle); + } + return phandle + 1; +} diff --git a/include/fdt_support.h b/include/fdt_support.h index 54af9fe..871ef45 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -86,6 +86,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias); u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr); int fdt_node_offset_by_compat_reg(void *blob, const char *compat, phys_addr_t compat_off); +int fdt_alloc_phandle(void *blob); #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ -- 1.6.0.6

4 8

[U-Boot] [PATCH] powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platforms
by Kumar Gala 26 Jul '10

26 Jul '10

The CoreNet style platforms can have a L3 cache that fronts the memory controllers. Enable that cache as well as add information into the device tree about it. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> Signed-off-by: Dave Liu <daveliu(a)freescale.com> Signed-off-by: Becky Bruce <beckyb(a)kernel.crashing.org> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Timur Tabi <timur(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 45 ++++++++++++++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/fdt.c | 24 ++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e957677..b257a0f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -127,6 +127,44 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif +#ifdef CONFIG_SYS_FSL_CPC +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + + out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); + /* Read back to sync write */ + in_be32(&cpc->cpccsr0); + + } + + printf("Corenet Platform Cache: %d KB enabled\n", size); +} + +void invalidate_cpc(void) +{ + int i; + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* Flash invalidate the CPC and clear all the locks */ + out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); + while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) + ; + } +} +#else +#define enable_cpc() +#define invalidate_cpc() +#endif /* CONFIG_SYS_FSL_CPC */ + /* * Breathe some life into the CPU... * @@ -242,6 +280,9 @@ void cpu_init_f (void) corenet_tb_init(); #endif init_used_tlb_cams(); + + /* Invalidate the CPC before DDR gets enabled */ + invalidate_cpc(); } @@ -252,7 +293,6 @@ void cpu_init_f (void) * use the same bit-encoding as the older 8555, etc, parts. * */ - int cpu_init_r(void) { #ifdef CONFIG_SYS_LBC_LCRR @@ -373,6 +413,9 @@ int cpu_init_r(void) #else puts("disabled\n"); #endif + + enable_cpc(); + #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ qe_init(qe_base); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 932466e..6c5fb36 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/processor.h> #include <linux/ctype.h> +#include <asm/io.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif @@ -80,7 +81,30 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_SYS_FSL_CPC +static inline void ft_fixup_l3cache(void *blob, int off) +{ + u32 line_size, num_ways, size, num_sets; + cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; + u32 cfg0 = in_be32(&cpc->cpccfg0); + + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + num_ways = CPC_CFG0_NUM_WAYS(cfg0); + line_size = CPC_CFG0_LINE_SZ(cfg0); + num_sets = size / (line_size * num_ways); + + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 3); +#ifdef CONFIG_SYS_CACHE_STASHING + fdt_setprop_cell(blob, off, "cache-stash-id", 1); +#endif +} +#else #define ft_fixup_l3cache(x, y) +#endif #if defined(CONFIG_L2_CACHE) /* return size in kilobytes */ -- 1.6.0.6

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[U-Boot] [PATCH] powerpc/85xx: Add support to initialize LIODN registers and portals
by Kumar Gala 26 Jul '10

26 Jul '10

On the new QorIQ/CoreNet based platforms we need to initialize the "portals" as access into the Data Path subystem as well as Logical IO Device Numbers (LIODN) that are used for the IOMMU (PAMU). Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> Signed-off-by: Scott Wood <scottwood(a)freescale.com> Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/Makefile | 6 + arch/powerpc/cpu/mpc85xx/fdt.c | 15 ++ arch/powerpc/cpu/mpc85xx/liodn.c | 187 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p4080_ids.c | 115 +++++++++++++++ arch/powerpc/cpu/mpc85xx/portals.c | 238 ++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_liodn.h | 142 +++++++++++++++++++ arch/powerpc/include/asm/fsl_portals.h | 59 ++++++++ 7 files changed, 762 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/liodn.c create mode 100644 arch/powerpc/cpu/mpc85xx/p4080_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/portals.c create mode 100644 arch/powerpc/include/asm/fsl_liodn.h create mode 100644 arch/powerpc/include/asm/fsl_portals.h diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4d52ebe..b6456fc 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -64,9 +64,15 @@ COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_FSL_CORENET) += portals.o + +# various SoC specific assignments +COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o + COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6c5fb36..8e7b827 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/fsl_portals.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif @@ -446,4 +447,18 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif ft_fixup_dpaa_clks(blob); + +#if defined(CONFIG_SYS_BMAN_MEM_PHYS) + fdt_portal(blob, "fsl,bman-portal", "bman-portals", + (u64)CONFIG_SYS_BMAN_MEM_PHYS, + CONFIG_SYS_BMAN_MEM_SIZE); +#endif + +#if defined(CONFIG_SYS_QMAN_MEM_PHYS) + fdt_portal(blob, "fsl,qman-portal", "qman-portals", + (u64)CONFIG_SYS_QMAN_MEM_PHYS, + CONFIG_SYS_QMAN_MEM_SIZE); + + fdt_fixup_qportals(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c new file mode 100644 index 0000000..bd19094 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -0,0 +1,187 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset) +{ + liodns[0] = liodn_bases[dpaa_dev].id[0] + liodn_offset; + + if (liodn_bases[dpaa_dev].num_ids == 2) + liodns[1] = liodn_bases[dpaa_dev].id[1] + liodn_offset; + + return liodn_bases[dpaa_dev].num_ids; +} + +static void set_liodn(struct liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + u32 liodn; + if (tbl[i].num_ids == 2) { + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + } else { + liodn = tbl[i].id[0]; + } + + out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); + } +} + +static void setup_sec_liodn_base(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + u32 base; + + if (!IS_E_PROCESSOR(get_svr())) + return; + + /* QILCR[QSLOM] */ + out_be32(&sec->qilcr_ms, 0x3ff<<16); + + base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_SEC].id[1]; + + out_be32(&sec->qilcr_ls, base); +} + +#ifdef CONFIG_SYS_DPAA_FMAN +static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, + struct liodn_id_table *tbl, int size) +{ + int i; + ccsr_fman_t *fm; + u32 base; + + switch(dev) { + case FSL_HW_PORTAL_FMAN1: + fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; + break; + +#if (CONFIG_SYS_NUM_FMAN == 2) + case FSL_HW_PORTAL_FMAN2: + fm = (void *)CONFIG_SYS_FSL_FM2_ADDR; + break; +#endif + default: + printf("Error: Invalid device type to %s\n", __FUNCTION__); + return ; + } + + base = (liodn_bases[dev].id[0] << 16) | liodn_bases[dev].id[0]; + + /* setup all bases the same */ + for (i = 0; i < 32; i++) { + out_be32(&fm->fm_dma.fmdmplr[i], base); + } + + /* update tbl to ... */ + for (i = 0; i < size; i++) + tbl[i].id[0] += liodn_bases[dev].id[0]; +} +#endif + +static void setup_pme_liodn_base(void) +{ +#ifdef CONFIG_SYS_DPAA_PME + ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_PME].id[1]; + + out_be32(&pme->liodnbr, base); +#endif +} + +void set_liodns(void) +{ + /* setup general liodn offsets */ + set_liodn(liodn_tbl, liodn_tbl_sz); + + /* setup SEC block liodn bases & offsets if we have one */ + if (IS_E_PROCESSOR(get_svr())) { + set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz); + setup_sec_liodn_base(); + } + + /* setup FMAN block(s) liodn bases & offsets if we have one */ +#ifdef CONFIG_SYS_DPAA_FMAN + set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); + setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, + fman1_liodn_tbl_sz); + +#if (CONFIG_SYS_NUM_FMAN == 2) + set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); + setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, + fman2_liodn_tbl_sz); +#endif +#endif + /* setup PME liodn base */ + setup_pme_liodn_base(); +} + +static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) +{ + int i; + + for (i = 0; i < sz; i++) { + int off; + + if (tbl[i].compat == NULL) + continue; + + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat, tbl[i].compat_offset); + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for " + "%s: %s\n", + tbl[i].compat, fdt_strerror(off)); + } else { + debug("WARNING: could not set fsl,liodn for %s: %s.\n", + tbl[i].compat, fdt_strerror(off)); + } + } +} + +void fdt_fixup_liodn(void *blob) +{ + fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); +#if (CONFIG_SYS_NUM_FMAN == 2) + fdt_fixup_liodn_tbl(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); +#endif +#endif + fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); +} diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c new file mode 100644 index 0000000..3861146 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -0,0 +1,115 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO(11, 12, 6, 5), + SET_QP_INFO(13, 14, 7, 6), + SET_QP_INFO(15, 16, 8, 7), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_USB_LIODN(1, "fsl-usb2-mph", 127), + SET_USB_LIODN(2, "fsl-usb2-dr", 157), + + SET_SDHC_LIODN(1, 156), + + SET_PCI_LIODN(1, 193), + SET_PCI_LIODN(2, 194), + SET_PCI_LIODN(3, 195), + + SET_DMA_LIODN(1, 196), + SET_DMA_LIODN(2, 197), + + SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), + + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + SET_PME_LIODN(128), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 1, 12), + SET_FMAN_RX_1G_LIODN(1, 2, 13), + SET_FMAN_RX_1G_LIODN(1, 3, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; + +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 16), + SET_FMAN_RX_1G_LIODN(2, 1, 17), + SET_FMAN_RX_1G_LIODN(2, 2, 18), + SET_FMAN_RX_1G_LIODN(2, 3, 19), + SET_FMAN_RX_10G_LIODN(2, 0, 20), +}; +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JQ_LIODN_ENTRY(0, 146, 154), + SET_SEC_JQ_LIODN_ENTRY(1, 147, 155), + SET_SEC_JQ_LIODN_ENTRY(2, 178, 186), + SET_SEC_JQ_LIODN_ENTRY(3, 179, 187), + SET_SEC_RTIC_LIODN_ENTRY(a, 144), + SET_SEC_RTIC_LIODN_ENTRY(b, 145), + SET_SEC_RTIC_LIODN_ENTRY(c, 176), + SET_SEC_RTIC_LIODN_ENTRY(d, 177), + SET_SEC_DECO_LIODN_ENTRY(0, 129, 161), + SET_SEC_DECO_LIODN_ENTRY(1, 130, 162), + SET_SEC_DECO_LIODN_ENTRY(2, 131, 163), + SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), + SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c new file mode 100644 index 0000000..01aec6e --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -0,0 +1,238 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include <asm/processor.h> +#include <asm/io.h> + +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; + +void setup_portals(void) +{ + int i; + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + u8 sdest = qp_info[i].sdest; + u16 fliodn = qp_info[i].fliodn; + u16 dliodn = qp_info[i].dliodn; + u16 liodn_off = qp_info[i].liodn_offset; + + out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) | + dliodn); + /* set frame liodn */ + out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); + } +} + +/* Update portal containter to match LAW setup of portal in phy map */ +void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size) +{ + int off; + + off = fdt_node_offset_by_compatible(blob, -1, compat); + if (off < 0) + return ; + + off = fdt_parent_offset(blob, off); + /* if non-zero assume we have a container */ + if (off > 0) { + char buf[60]; + const char *p, *name; + u32 *range; + int len; + + /* fixup ranges */ + range = fdt_getprop_w(blob, off, "ranges", &len); + if (range == NULL) { + printf("ERROR: container for %s has no ranges", compat); + return ; + } + + range[0] = 0; + if (len == 16) { + range[1] = addr >> 32; + range[2] = addr & 0xffffffff; + range[3] = size; + } else { + range[1] = addr & 0xffffffff; + range[2] = size; + } + fdt_setprop_inplace(blob, off, "ranges", range, len); + + /* fixup the name */ + name = fdt_get_name(blob, off, &len); + p = memchr(name, '@', len); + + if (p) + len = p - name; + + /* if we are given a container name check it + * against what we found, if it doesnt match exit out */ + if (container && (memcmp(container, name, len))) { + printf("WARNING: container names didn't match %s %s\n", + container, name); + return ; + } + + memcpy(&buf, name, len); + len += sprintf(&buf[len], "@%llx", addr); + fdt_set_name(blob, off, buf); + return ; + } + + printf("ERROR: %s isn't in a container. Not supported\n", compat); +} + +static int fdt_qportal(void *blob, int off, int id, char *name, + enum fsl_dpaa_dev dev, int create) +{ + int childoff, dev_off, num, ret = 0; + uint32_t dev_handle; + u32 liodns[2]; + + childoff = fdt_subnode_offset(blob, off, name); + if (create) { + if (childoff <= 0) + childoff = fdt_add_subnode(blob, off, name); + + if (childoff > 0) { + char handle[64], *p; + + strncpy(handle, name, sizeof(handle)); + p = strchr(handle, '@'); + if (!strncmp(name, "fman", 4)) { + *p = *(p + 1); + p++; + } + *p = '\0'; + + dev_off = fdt_path_offset(blob, handle); + if (dev_off < 0) + return dev_off; + + dev_handle = fdt_get_phandle(blob, dev_off); + if (dev_handle <= 0) { + dev_handle = fdt_alloc_phandle(blob); + fdt_setprop_cell(blob, dev_off, + "linux,phandle", dev_handle); + } + + ret = fdt_setprop(blob, childoff, "dev-handle", + &dev_handle, sizeof(dev_handle)); + if (ret < 0) + return ret; + + num = get_dpaa_liodn(dev, &liodns[0], id); + ret = fdt_setprop(blob, childoff, "fsl,liodn", + &liodns[0], sizeof(u32) * num); + } else { + return childoff; + } + } else { + if (childoff > 0) + ret = fdt_del_node(blob, childoff); + } + + return ret; +} + +void fdt_fixup_qportals(void *blob) +{ + int off, err; + unsigned int maj, min; + u32 rev_1 = in_be32(&qman->ip_rev_1); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1; + compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + u32 liodns[2]; + const int *ci = fdt_getprop(blob, off, "cell-index", NULL); + int j, i = *ci; + + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) + goto err; + + liodns[0] = qp_info[i].dliodn; + liodns[1] = qp_info[i].fliodn; + + err = fdt_setprop(blob, off, "fsl,liodn", + &liodns, sizeof(u32) * 2); + if (err < 0) + goto err; + + i++; + + err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC, + IS_E_PROCESSOR(get_svr())); + if (err < 0) + goto err; + +#ifdef CONFIG_SYS_DPAA_PME + err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); + if (err < 0) + goto err; +#else + fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); +#endif +#ifdef CONFIG_SYS_DPAA_FMAN + for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { + char name[] = "fman@0"; + + name[sizeof(name) - 2] = '0' + j; + err = fdt_qportal(blob, off, i, name, + FSL_HW_PORTAL_FMAN1 + j, 1); + if (err < 0) + goto err; + } +#endif + +err: + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal"); + } +} diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h new file mode 100644 index 0000000..acdc99a --- /dev/null +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -0,0 +1,142 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_LIODN_H_ +#define _FSL_LIODN_H_ + +#include <asm/types.h> + +struct liodn_id_table { + const char * compat; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + +extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid); +extern void set_liodns(void); +extern void fdt_fixup_liodn(void *blob); + +#define SET_LIODN_BASE_1(idA) \ + { .id = { idA }, .num_ids = 1, } + +#define SET_LIODN_BASE_2(idA, idB) \ + { .id = { idA, idB }, .num_ids = 2 } + +#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ + { .compat = name, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ + { .compat = name, \ + .id = { idA, idB }, .num_ids = 2, \ + .reg_offset = off + CONFIG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ + SET_LIODN_ENTRY_1(compat, liodn, \ + offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \ + compatoff) + +#define SET_USB_LIODN(usbNum, compat, liodn) \ + SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\ + CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET) + +#define SET_SATA_LIODN(sataNum, liodn) \ + SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ + CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) + +#define SET_PCI_LIODN(pciNum, liodn) \ + SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\ + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + +/* reg nodes for DMA start @ 0x300 */ +#define SET_DMA_LIODN(dmaNum, liodn) \ + SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\ + CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) + +#define SET_SDHC_LIODN(sdhcNum, liodn) \ + SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) + +#define SET_QMAN_LIODN(liodn) \ + SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \ + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) + +#define SET_BMAN_LIODN(liodn) \ + SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \ + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \ + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) + +#define SET_PME_LIODN(liodn) \ + SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ + CONFIG_SYS_FSL_CORENET_PME_OFFSET, \ + CONFIG_SYS_FSL_CORENET_PME_OFFSET) + +/* -1 from portID due to how immap has the registers */ +#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \ + CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ + offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) + +/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \ + FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + +/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ + FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ + +#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum) + +/* This is a bit evil since we treat rtic param as both a string & hex value */ +#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ + SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + +#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ + SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ + offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, 0) + +extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; +extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; +extern int liodn_tbl_sz, sec_liodn_tbl_sz; +extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; + +#endif diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h new file mode 100644 index 0000000..cb32927 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -0,0 +1,59 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_PORTALS_H_ +#define _FSL_PORTALS_H_ + +/* entries must be in order and contiguous */ +enum fsl_dpaa_dev { + FSL_HW_PORTAL_SEC, +#ifdef CONFIG_SYS_DPAA_FMAN + FSL_HW_PORTAL_FMAN1, +#if (CONFIG_SYS_NUM_FMAN == 2) + FSL_HW_PORTAL_FMAN2, +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + FSL_HW_PORTAL_PME, +#endif +}; + +struct qportal_info { + u16 dliodn; /* DQRR LIODN */ + u16 fliodn; /* frame data LIODN */ + u16 liodn_offset; + u8 sdest; +}; + +#define SET_QP_INFO(dqrr, fdata, off, dest) \ + { .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest } + +extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, + u32 *liodns, int liodn_offset); +extern void setup_portals(void); +extern void fdt_fixup_qportals(void *blob); + +extern struct qportal_info qp_info[]; +extern void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size); + +#endif -- 1.6.0.6

1 1

[U-Boot] [PATCH] powerpc/85xx: Move INIT_RAM_ADDR physical address to 36-bit space
by Kumar Gala 26 Jul '10

26 Jul '10

From: york <yorksun(a)freescale.com> If 36-bit physical address is used, move the INIT_RAM_ADDR to higher address. This frees the low 4GB address space for better use. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/start.S | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index b3cb56a..aaf7838 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -330,8 +330,15 @@ _start_e500: lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l +#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH + mtspr MAS7,r10 +#else lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif mtspr MAS0,r6 mtspr MAS1,r7 -- 1.6.0.6

1 3

[U-Boot] A Beautiful Summer
by Couture Brands Inc. 26 Jul '10

26 Jul '10

Your email client cannot read this email. To view it online, please go here: http://www.entourage-group.com/EmailMarketing/display.php?M=79672&C=f7eec6b… PRESENTS SUMMER MADNESS SALE RIGHT NOW CHOOSE FROM A LARGE VARIETY OF OUR FAMOUS FASHION ARMS SLINGS DISCOUNTED AT 25% OFF REGULAR PRICE & RECEIVE A F R E E MATCHING FASHION CAST COVER! COUTURE BRANDS INC. IS CAUSING A BUZZ! SLING COUTURE TM Fashion Face Masks - As Seen On NBC New York (July 2010)! C.B. Fashion Face Masks Featured In South Florida Business Journal! Check Out What Lady Gaga Is Wearing During Her Performance On The Today Show! SkyMAll Monday: SLING COUTURE Fashion Face Mask www.SlingCouture.com www.FashionCarCouture.com Unsubscribe me from this list To stop receiving these emails:http://www.entourage-group.com/EmailMarketing/unsubscribe.php?M=7967…

1 0

[U-Boot] Hello,
by Joy Hasler 26 Jul '10

26 Jul '10

Hello, my name is Joy,Nice to meet you on internet. i am searching for a nice person who understand the meaning of relationship as trust and faith in each other, After reading your profile today i pick interest in you.I believe age or distance have noting to do with relationship.When you respond to me, i will send you my pictures and i will also like to see your pictures too, i am waiting for your respond. with faith and trust. Joy.

1 0

[U-Boot] did anyone use flash_utils on dm355 platform?i cannot write flash!
by yaojin liu 26 Jul '10

26 Jul '10

hi: i use the GUN tools. flash_utils.tar.gz now I can read the flash ID,(K9F1208U0C):ID = 0x000000EC0x000000760x000000A50x000000C0 but i cannot write data to page, so i cannot use UBOOT! Therefor i doubt that uboot also has the same problem? i have tried several days, but cannot figure it out yet! help! regards!

2 1

[U-Boot] [PATCH] powerpc/85xx: Add additional p4080 platform related defines/structs
by Kumar Gala 26 Jul '10

26 Jul '10

* Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/immap_85xx.h | 172 +++++++++++++++++++++++++++++---- 1 files changed, 154 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e65d665..a5e56d8 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1646,6 +1646,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_DDR2 0x00080000 #define FSL_CORENET_DEVDISR_DBG 0x00010000 #define FSL_CORENET_DEVDISR_NAL 0x00008000 +#define FSL_CORENET_DEVDISR_SATA1 0x00004000 +#define FSL_CORENET_DEVDISR_SATA2 0x00002000 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 #define FSL_CORENET_DEVDISR_USB1 0x00000800 #define FSL_CORENET_DEVDISR_USB2 0x00000400 @@ -1666,12 +1668,14 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 +#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 +#define FSL_CORENET_NUM_DEVDISR 2 u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ u8 res8[12]; @@ -1700,9 +1704,18 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 +#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ +#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 +#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 +#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 +#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 +#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 +#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res19[240]; @@ -1726,10 +1739,15 @@ typedef struct ccsr_gur { u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ - u32 rmuliodnr; /* RIO Message Unit LIODN */ - u32 rduliodnr; /* RIO Doorbell Unit LIODN */ - u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ - u8 res22[52]; + u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ + u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ + u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ + u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ + u32 sata1liodnr; /* SATA 1 LIODN */ + u32 sata2liodnr; /* SATA 2 LIODN */ + u32 sata3liodnr; /* SATA 3 LIODN */ + u32 sata4liodnr; /* SATA 4 LIODN */ + u8 res22[32]; u32 dma1liodnr; /* DMA 1 LIODN */ u32 dma2liodnr; /* DMA 2 LIODN */ u32 dma3liodnr; /* DMA 3 LIODN */ @@ -1764,6 +1782,12 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +/* + * On p4080 we have an LIODN for msg unit (rmu) but not maintenance + * everything after has RMan thus msg unit LIODN is used for maintenance + */ +#define rmuliodnr rio1maintliodnr + typedef struct ccsr_clk { u32 clkc0csr; /* Core 0 Clock control/status */ u8 res1[0x1c]; @@ -2032,38 +2056,125 @@ enum { /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 typedef struct ccsr_sec { - u8 res1[0xfa0]; + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x8]; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jqliodnr[4]; + u8 res2[0x30]; + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[5]; + u8 res4[0x58]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0xe78]; u32 crnr_ms; /* CHA Revision Number Register, MS */ u32 crnr_ls; /* CHA Revision Number Register, LS */ u32 ctpr_ms; /* Compile Time Parameters Register, MS */ -#define SEC_CTPR_MS_AXI_LIODN 0x08000000 -#define SEC_CTPR_MS_QI 0x02000000 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ - u8 res2[0x10]; + u8 res6[0x10]; u32 far_ms; /* Fault Address Register, MS */ u32 far_ls; /* Fault Address Register, LS */ u32 falr; /* Fault Address LIODN Register */ u32 fadr; /* Fault Address Detail Register */ - u8 res3[0x4]; + u8 res7[0x4]; u32 csta; /* CAAM Status Register */ - u8 res4[0x8]; + u8 res8[0x8]; u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ -#define SEC_RVID_MA 0x0f000000 u32 ccbvid; /* CHA Cluster Block Version ID Register */ u32 chavid_ms; /* CHA Version ID Register, MS */ u32 chavid_ls; /* CHA Version ID Register, LS */ u32 chanum_ms; /* CHA Number Register, MS */ + u32 chanum_ls; /* CHA Number Register, LS */ + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ + u8 res9[0x6020]; + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ + u8 res10[0x8fd8]; +} ccsr_sec_t; + +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 +#define SEC_RVID_MA 0x0f000000 #define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 #define SEC_CHANUM_MS_JQNUM_SHIFT 28 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 - u32 chanum_ls; /* CHA Number Register, LS */ - u32 caamvid_ms; /* CAAM Version ID Register, MS */ - u32 caamvid_ls; /* CAAM Version ID Register, LS */ - u8 res5[0xf000]; -} ccsr_sec_t; #endif +typedef struct ccsr_qman { + struct { + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ + u32 res; + u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ + } qcsp[32]; + + /* Not actually reserved, but irrelevant to u-boot */ + u8 res[0xbf8 - 0x200]; + u32 ip_rev_1; + u32 ip_rev_2; + u32 fqd_bare; /* FQD Extended Base Addr Register */ + u32 fqd_bar; /* FQD Base Addr Register */ + u8 res1[0x8]; + u32 fqd_ar; /* FQD Attributes Register */ + u8 res2[0xc]; + u32 pfdr_bare; /* PFDR Extended Base Addr Register */ + u32 pfdr_bar; /* PFDR Base Addr Register */ + u8 res3[0x8]; + u32 pfdr_ar; /* PFDR Attributes Register */ + u8 res4[0x4c]; + u32 qcsp_bare; /* QCSP Extended Base Addr Register */ + u32 qcsp_bar; /* QCSP Base Addr Register */ + u8 res5[0x78]; + u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ + u32 srcidr; /* Source ID Register */ + u32 liodnr; /* LIODN Register */ + u8 res6[4]; + u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ + u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ + u8 res7[0x2e8]; +} ccsr_qman_t; + +typedef struct ccsr_bman { + /* Not actually reserved, but irrelevant to u-boot */ + u8 res[0xbf8]; + u32 ip_rev_1; + u32 ip_rev_2; + u32 fbpr_bare; /* FBPR Extended Base Addr Register */ + u32 fbpr_bar; /* FBPR Base Addr Register */ + u8 res1[0x8]; + u32 fbpr_ar; /* FBPR Attributes Register */ + u8 res2[0xf0]; + u32 srcidr; /* Source ID Register */ + u32 liodnr; /* LIODN Register */ + u8 res7[0x2f4]; +} ccsr_bman_t; + +typedef struct ccsr_pme { + u8 res0[0x804]; + u32 liodnbr; /* LIODN Base Register */ + u8 res1[0x1f8]; + u32 srcidr; /* Source ID Register */ + u8 res2[8]; + u32 liodnr; /* LIODN Register */ + u8 res3[0x1e8]; + u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ + u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ + u8 res4[0x400]; +} ccsr_pme_t; + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2072,20 +2183,41 @@ typedef struct ccsr_sec { #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 -#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 +#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 +#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 +#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 +#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 +#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 +#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 +#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 +#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 +#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 +#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 +#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 +#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 +#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 +#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 @@ -2130,6 +2262,8 @@ typedef struct ccsr_sec { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_FSL_CORENET_PME_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ @@ -2195,6 +2329,8 @@ typedef struct ccsr_sec { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) #define CONFIG_SYS_PCIE3_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) +#define CONFIG_SYS_PCIE4_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) -- 1.6.0.6

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[U-Boot] Webmail Update Account
by Mail Administrator 26 Jul '10

26 Jul '10

Caro utilizador Webmail, Esta mensagem é a partir do Webmail IT Service centro de mensagens para todos os assinantes de usuários / webmail. Estamos atualizando nossa base de dados e e-mail devido a um centro de atividades incomuns identificado em nosso sistema de e-mail. Nós estamos apagando todos os não utilizados Webmail Contas. Você é obrigado a verificar a sua conta de webmail, confirmando sua identidade Webmail. Isto irá prevenir a sua conta de Webmail foram encerradas durante o exercício. A fim de confirmar se a identidade Web-Mail, você deve fornecer os seguintes dados; Nome: Sobrenome: Nome de usuário / ID: Senha: Redigite sua senha: E-mail: * Importante Favor fornecer todas essas informações corretamente e completamente contrário devido a razões de segurança, vamos ter de fechar a sua conta temporariamente. Agradecemos por sua pronta atenção a este assunto. Por favor, entendam que esta é uma medida de segurança destinadas a ajudar a proteger você e seu webmail. Pedimos desculpas por qualquer inconveniente. Atenciosamente, Webmail IT Service _________________________________________________________ This mail sent using V-webmail - http://www.v-webmail.org

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