September 2009 - U-Boot

[U-Boot] [PATCH] TI: DaVinci: Adding GIO addresses to header file
by s-paulraj＠ti.com 22 Sep '09

22 Sep '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> This patch adds GIO definitions to the hardware.h header file Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- include/asm-arm/arch-davinci/hardware.h | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 313b3f3..3d31d24 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -181,6 +181,29 @@ void davinci_errata_workarounds(void); #define PSC_SILVER_BULLET (0x01c41a20) +/* GIO registers */ +#define GIO_BINTEN 0x01C67008 +#define GIO_DIR01 0x01C67010 +#define GIO_OUT_DATA01 0x01C67014 +#define GIO_SET_DATA01 0x01C67018 +#define GIO_CLR_DATA01 0x01C6701C +#define GIO_SET_RIS_TRIG01 0x01C67024 + +#define GIO_DIR23 0x01C67038 +#define GIO_OUT_DATA23 0x01C6703c +#define GIO_SET_DATA23 0x01C67040 +#define GIO_CLR_DATA23 0x01C67044 + +#define GIO_DIR45 0x01C67060 +#define GIO_OUT_DATA45 0x01C67064 +#define GIO_SET_DATA45 0x01C67068 +#define GIO_CLR_DATA45 0x01C6706C + +#define GIO_DIR06 0x01C67088 +#define GIO_OUT_DATA06 0x01C6708C +#define GIO_SET_DATA06 0x01C67090 +#define GIO_CLR_DATA06 0x01C67094 + /* Miscellania... */ #define VBPR (0x20000020) -- 1.6.0.4

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[U-Boot] [PATCH] TI: DaVinci: DM355 Leopard board support
by s-paulraj＠ti.com 22 Sep '09

22 Sep '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> This patch adds support for the leopard board which is based on the DM355 SOC. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- Makefile | 3 + board/davinci/dm355leopard/Makefile | 52 +++++++++ board/davinci/dm355leopard/config.mk | 6 + board/davinci/dm355leopard/dm355leopard.c | 84 +++++++++++++++ include/configs/davinci_dm355leopard.h | 162 +++++++++++++++++++++++++++++ 5 files changed, 307 insertions(+), 0 deletions(-) create mode 100644 board/davinci/dm355leopard/Makefile create mode 100644 board/davinci/dm355leopard/config.mk create mode 100644 board/davinci/dm355leopard/dm355leopard.c create mode 100644 include/configs/davinci_dm355leopard.h diff --git a/Makefile b/Makefile index 0449a5b..5a4a109 100644 --- a/Makefile +++ b/Makefile @@ -2958,6 +2958,9 @@ davinci_dm355evm_config : unconfig davinci_dm365evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm365evm davinci davinci +davinci_dm355leopard_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355leopard davinci davinci + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile new file mode 100644 index 0000000..26b0705 --- /dev/null +++ b/board/davinci/dm355leopard/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk new file mode 100644 index 0000000..d67df02 --- /dev/null +++ b/board/davinci/dm355leopard/config.mk @@ -0,0 +1,6 @@ +# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c new file mode 100644 index 0000000..ba3adc6 --- /dev/null +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include "../common/misc.h" +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* GIO 9 & 10 are used for IO */ + writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3); + + /* Interrupt set GIO 9 */ + writel((readl(GIO_BINTEN) | 0x01), GIO_BINTEN); + + /* set GIO 9 input */ + writel((readl(GIO_DIR01) | (1 << 9)), GIO_DIR01); + + /* Both edge trigger GIO 9 */ + writel((readl(GIO_SET_RIS_TRIG01) | (1 << 9)), GIO_SET_RIS_TRIG01); + writel((readl(GIO_DIR01) & ~(1 << 5)), GIO_DIR01); + + /* output low */ + writel((readl(GIO_SET_DATA01) & ~(1 << 5)), GIO_SET_DATA01); + + /* set GIO 10 output */ + writel((readl(GIO_DIR01) & ~(1 << 10)), GIO_DIR01); + + /* output high */ + writel((readl(GIO_SET_DATA01) | (1 << 10)), GIO_SET_DATA01); + + /* set GIO 32 output */ + writel((readl(GIO_DIR23) & ~(1 << 0)), GIO_DIR23); + + /* output High */ + writel((readl(GIO_SET_DATA23) | (1 << 0)), GIO_SET_DATA23); + + /* Enable UART1 MUX Lines */ + writel((readl(PINMUX0) & ~3), PINMUX0); + writel((readl(GIO_DIR06) & ~(1 << 6)), GIO_DIR06); + writel((readl(GIO_SET_DATA06) | (1 << 6)), GIO_SET_DATA06); + + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif + +#ifdef CONFIG_NAND_DAVINCI +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + + return 0; +} +#endif diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h new file mode 100644 index 0000000..39450cd --- /dev/null +++ b/include/configs/davinci_dm355leopard.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DAVINCI_DM355LEOPARD + +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_DISPLAY_CPUINFO + +/* SoC Configuration */ +#define CONFIG_ARM926EJS /* arm926ejs CPU */ +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM355 /* DM355 based board */ + +/* Memory Info */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ + +/* Serial Driver info: UART0 for console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0x01c20000 +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Ethernet: external DM9000 */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x04000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 16) +#define CONFIG_NET_MULTI + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x10 + +/* NAND */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_HW_ECC + +#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +/* U-Boot command configuration */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES + +#ifdef CONFIG_NAND_DAVINCI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#endif + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* U-Boot general configuration */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DM355 LEOPARD # " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP + +#ifdef CONFIG_NAND_DAVINCI +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x3C0000 +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#endif + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND \ + "dhcp;bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200n8 " \ + "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +#define CONFIG_NET_RETRY_COUNT 10 + +/* U-Boot memory configuration */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ +#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ +#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ + +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" + +#ifdef CONFIG_SYS_NAND_LARGEPAGE +#define PART_BOOT "2m(bootloader)ro," +#else +/* Assume 16K erase blocks; allow a few bad ones. */ +#define PART_BOOT "512k(bootloader)ro," +#endif + +#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ +#define PART_REST "-(filesystem)" + +#define MTDPARTS_DEFAULT \ + "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST + +#endif /* __CONFIG_H */ -- 1.6.0.4

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[U-Boot] [PATCH] Support for Calao USB A9263 board based on AT91SAM9263 CPU
by Thomas Petazzoni 22 Sep '09

22 Sep '09

The Calao USB A9263 board is a board manufactured and sold by Calao Systems <http://www.calao-systems.com>. Its components are very similar to the AT91SAM9263EK board, so its configuration is based on the configuration of this board. There are however some differences: different clocks, no LCD, etc. Signed-off-by: Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/calao/usb-a9263/Makefile | 58 +++++++++++ board/calao/usb-a9263/config.mk | 24 +++++ board/calao/usb-a9263/partition.c | 38 +++++++ board/calao/usb-a9263/usb-a9263.c | 198 +++++++++++++++++++++++++++++++++++++ include/configs/usb-a9263.h | 184 ++++++++++++++++++++++++++++++++++ 8 files changed, 510 insertions(+), 0 deletions(-) create mode 100644 board/calao/usb-a9263/Makefile create mode 100644 board/calao/usb-a9263/config.mk create mode 100644 board/calao/usb-a9263/partition.c create mode 100644 board/calao/usb-a9263/usb-a9263.c create mode 100644 include/configs/usb-a9263.h diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..28fe0ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -643,6 +643,10 @@ Peter Pearse <peter.pearse(a)arm.com> versatile ARM926EJ-S versatile ARM926EJ-S +Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> + + usb-a9263 ARM926EJS (AT91SAM9263 SoC) + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/MAKEALL b/MAKEALL index f0ed8ea..c0200a9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -617,6 +617,7 @@ LIST_at91=" \ SBC35_A9G20 \ TNY_A9260 \ TNY_A9G20 \ + usb9263 \ " ######################################################################### diff --git a/Makefile b/Makefile index 0449a5b..087c592 100644 --- a/Makefile +++ b/Makefile @@ -2914,6 +2914,9 @@ TNY_A9260_config : unconfig @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h @$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91 +usb_a9263_config : unconfig + @$(MKCONFIG) -a usb-a9263 arm arm926ejs usb-a9263 calao at91 + ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/calao/usb-a9263/Makefile b/board/calao/usb-a9263/Makefile new file mode 100644 index 0000000..ec79872 --- /dev/null +++ b/board/calao/usb-a9263/Makefile @@ -0,0 +1,58 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2009 +# Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += usb-a9263.o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/calao/usb-a9263/config.mk b/board/calao/usb-a9263/config.mk new file mode 100644 index 0000000..2724a7d --- /dev/null +++ b/board/calao/usb-a9263/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2009 +# Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x23f00000 diff --git a/board/calao/usb-a9263/partition.c b/board/calao/usb-a9263/partition.c new file mode 100644 index 0000000..614ef0d --- /dev/null +++ b/board/calao/usb-a9263/partition.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2008-2009 + * Ulf Samuelsson <ulf(a)atmel.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/board/calao/usb-a9263/usb-a9263.c b/board/calao/usb-a9263/usb-a9263.c new file mode 100644 index 0000000..a4b7882 --- /dev/null +++ b/board/calao/usb-a9263/usb-a9263.c @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2007-2009 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9263_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void usb_a9263_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOCDE); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void usb_a9263_macb_hw_init(void) +{ + unsigned long rstc; + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUER); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of USB-A9263-Board */ + gd->bd->bi_arch_number = MACH_TYPE_USB_A9263; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + usb_a9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + usb_a9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = get_ram_size((long*) PHYS_SDRAM, + PHYS_SDRAM_SIZE); + if (gd->bd->bi_dram[0].size != PHYS_SDRAM_SIZE) + return -1; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/include/configs/usb-a9263.h b/include/configs/usb-a9263.h new file mode 100644 index 0000000..2424058 --- /dev/null +++ b/include/configs/usb-a9263.h @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2007-2009 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * + * Configuration settings for the Calao USB-A9263 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/at91sam9263.h> + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_CALAO_USB_A9263 1 /* on an Calao USB A 9263 Board */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#undef CONFIG_LCD + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define AT91_SPI_CLK 8000000 +#define DATAFLASH_TCSS (0x1c << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MACB_SEARCH_PHY 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91SAM9263_UHP_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0) +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=atmel_nand:2m(kernel)ro,-(root) "\ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, \ + 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- 1.6.3.3

2 1

[U-Boot] [PATCH v3] at91: Update MEESC board support
by Daniel Gorsulowski 22 Sep '09

22 Sep '09

This patch implements several updates: -disable CONFIG_ENV_OVERWRITE -add new hardware style variants and set the arch numbers appropriate (autodet.) -pass the serial# and hardware revision to the kernel -removed unused macros from include/configs/meesc.h Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski(a)esd.eu> --- v2: - don't write the ethernet address to the EMAC module anymore v3: - removed function meesc_set_arch_number and moved code to checkboard() - reworked function get_board_serial() - removed unused macros from include/configs/meesc.h board/esd/meesc/meesc.c | 62 +++++++++++++++++++++++++++++++++++++++++++---- include/configs/meesc.h | 25 ++++++------------- 2 files changed, 65 insertions(+), 22 deletions(-) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 636d0ed..045fbe2 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -156,8 +156,35 @@ int board_eth_init(bd_t *bis) int checkboard(void) { char str[32]; - - puts("Board: esd CAN-EtherCAT Gateway"); + u_char hw_type; /* hardware type */ + + /* read the "Type" register of the ET1100 controller */ + hw_type = readb(CONFIG_ET1100_BASE); + + switch (hw_type) { + case 0x11: + case 0x3F: + /* ET1100 present, + arch number of MEESC-Board */ + gd->bd->bi_arch_number = MACH_TYPE_MEESC; + puts("Board: CAN-EtherCAT Gateway"); + break; + case 0xFF: + /* no ET1100 present, + arch number of EtherCAN/2-Board */ + gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; + puts("Board: EtherCAN/2 Gateway"); + /* switch on LED1D */ + at91_set_gpio_output(AT91_PIN_PB12, 1); + break; + default: + /* assume, no ET1100 present, + arch number of EtherCAN/2-Board */ + gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; + printf("FATAL! Read invalid hw_type: %02X\n", hw_type); + puts("Board: EtherCAN/2 Gateway"); + break; + } if (getenv_r("serial#", str, sizeof(str)) > 0) { puts(", serial# "); puts(str); @@ -167,6 +194,32 @@ int checkboard(void) return 0; } +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *str; + + char *serial = getenv("serial#"); + if (serial) { + str = strchr(serial, '_'); + if (str && (strlen(str) >= 4)) { + serialnr->high = (*(str + 1) << 8) | *(str + 2); + serialnr->low = simple_strtoul(str + 3, NULL, 16); + } + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + return hw_rev | 0x100; +} +#endif + int board_init(void) { /* Peripheral Clock Enable Register */ @@ -174,8 +227,8 @@ int board_init(void) 1 << AT91SAM9263_ID_PIOB | 1 << AT91SAM9263_ID_PIOCDE); - /* arch number of MEESC-Board */ - gd->bd->bi_arch_number = MACH_TYPE_MEESC; + /* initialize ET1100 Controller */ + meesc_ethercat_hw_init(); /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; @@ -184,7 +237,6 @@ int board_init(void) #ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); #endif - meesc_ethercat_hw_init(); #ifdef CONFIG_HAS_DATAFLASH at91_spi0_hw_init(1 << 0); #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 8253172..b996854 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -36,13 +36,14 @@ #define CONFIG_MEESC 1 /* Board is esd MEESC */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ -#define CONFIG_ENV_OVERWRITE 1 /* necessary on prototypes */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#define CONFIG_SERIAL_TAG 1 +#define CONFIG_REVISION_TAG 1 #undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -138,12 +139,13 @@ #define CONFIG_SYS_USE_DATAFLASH 1 #undef CONFIG_SYS_USE_NANDFLASH -#ifdef CONFIG_SYS_USE_DATAFLASH - /* CAN */ #define CONFIG_AT91_CAN 1 -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +/* hw-controller addresses */ +#define CONFIG_ET1100_BASE 0x70000000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ #define CONFIG_ENV_IS_IN_DATAFLASH 1 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ 0x8400) @@ -151,18 +153,6 @@ #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b C0042000 22000000 210000; bootm" - -#else /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 22000000 A0000 200000; bootm" - -#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } @@ -178,7 +168,8 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN 0x2D000 +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128*1024, 0x1000) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ -- 1.5.3

3 4

[U-Boot] [PATCH][v1] FDT: remove obsolete OF_CPU and OF_SOC macros.
by Marcel Ziswiler 22 Sep '09

22 Sep '09

Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> --- README | 6 ++++-- include/configs/IDS8247.h | 2 -- include/configs/MPC8260ADS.h | 1 - include/configs/linkstation.h | 2 -- include/configs/mgcoge.h | 2 -- include/configs/mpc7448hpc2.h | 1 - include/configs/muas3001.h | 2 -- include/configs/stxxtc.h | 1 - 8 files changed, 4 insertions(+), 13 deletions(-) diff --git a/README b/README index ff4ed8b..3cb7786 100644 --- a/README +++ b/README @@ -368,8 +368,10 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - OF_CPU - The proper name of the cpus node. - OF_SOC - The proper name of the soc node. + OF_CPU - The proper name of the cpus node (only required for + MPC512X and MPC5xxx based boards). + OF_SOC - The proper name of the soc node (only required for + MPC512X and MPC5xxx based boards). OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 4c4af05..147a8b2 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -125,8 +125,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 942a4cc..677a143 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -209,7 +209,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "cpu@0" #define OF_TBCLK (bd->bi_busfreq / 4) #endif diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 2feb3ae..16b464c 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -96,8 +96,6 @@ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,603e" -#define OF_SOC "soc10x@80000000" #define OF_STDOUT_PATH "/soc10x/serial@80004600" /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index ea14948..99ac8c1 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -346,8 +346,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4f98ba4..be12186 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -79,7 +79,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index f031a17..f2d117c 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -404,8 +404,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8270@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #if defined(CONFIG_MUAS_DEV_BOARD) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index d16262b..5854366 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -509,7 +509,6 @@ typedef unsigned int led_id_t; /* pass open firmware flattened device tree */ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ -- 1.6.0.4

3 9

[U-Boot] [PATCH MAKEALL coldfire] : Fix start.S:Error: Conversion of PC relative displacement to absolute
by Philippe De Muyter 22 Sep '09

22 Sep '09

Hi all, This fixes the following errors when running MAKEALL for coldfire : start.S: Assembler messages: start.S:320: Error: Conversion of PC relative displacement to absolute Signed-off-by: Philippe De Muyter <phdm(a)macqel.be> diff -ru a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S --- a/cpu/mcf523x/start.S 2009-09-17 23:28:31.000000000 +0200 +++ b/cpu/mcf523x/start.S 2009-09-21 19:58:34.000000000 +0200 @@ -246,7 +246,7 @@ /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler: diff -ru a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S --- a/cpu/mcf52x2/start.S 2009-09-17 23:28:31.000000000 +0200 +++ b/cpu/mcf52x2/start.S 2009-09-21 19:47:40.000000000 +0200 @@ -317,7 +317,7 @@ /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler: diff -ru a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S --- a/cpu/mcf532x/start.S 2009-09-17 23:28:31.000000000 +0200 +++ b/cpu/mcf532x/start.S 2009-09-21 19:50:36.000000000 +0200 @@ -256,7 +256,7 @@ /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler:

3 7

[U-Boot] Subject: [PATCH v3] mx27ads: add support for iMX27ADS board from Freescale
by Alan Carvalho de Assis 22 Sep '09

22 Sep '09

This patch adds support to iMX27ADS development board. This board has 128MB RAM, 32MB NOR Flash and 128MB NAND Flash. Currently only booting from NOR is supported. Signed-off-by: Alan Carvalho de Assis <acassis(a)gmail.com> --- MAINTAINERS | 3 + MAKEALL | 1 + Makefile | 3 + board/freescale/mx27ads/Makefile | 51 ++++++++ board/freescale/mx27ads/config.mk | 1 + board/freescale/mx27ads/lowlevel_init.S | 127 +++++++++++++++++++ board/freescale/mx27ads/mx27ads.c | 93 ++++++++++++++ board/freescale/mx27ads/u-boot.lds | 56 +++++++++ include/configs/mx27ads.h | 202 +++++++++++++++++++++++++++++++ 9 files changed, 537 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx27ads/Makefile create mode 100644 board/freescale/mx27ads/config.mk create mode 100644 board/freescale/mx27ads/lowlevel_init.S create mode 100644 board/freescale/mx27ads/mx27ads.c create mode 100644 board/freescale/mx27ads/u-boot.lds create mode 100644 include/configs/mx27ads.h diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..7ff3160 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -512,6 +512,9 @@ Unknown / orphaned boards: # Board CPU # ######################################################################### +Alan Carvalho de Assis <acassis(a)gmail.com> + mx27ads i.MX27 + Rowel Atienza <rowel(a)diwalabs.com> armadillo ARM720T diff --git a/MAKEALL b/MAKEALL index f0ed8ea..56b4446 100755 --- a/MAKEALL +++ b/MAKEALL @@ -525,6 +525,7 @@ LIST_ARM9=" \ mv88f6281gtw_ge \ mx1ads \ mx1fs2 \ + mx27ads \ netstar \ nhk8815 \ nhk8815_onenand \ diff --git a/Makefile b/Makefile index 9764cea..4f2dcef 100644 --- a/Makefile +++ b/Makefile @@ -2965,6 +2965,9 @@ davinci_dm365evm_config : unconfig imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 +mx27ads_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs mx27ads freescale mx27 + lpd7a400_config \ lpd7a404_config: unconfig @$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x diff --git a/board/freescale/mx27ads/Makefile b/board/freescale/mx27ads/Makefile new file mode 100644 index 0000000..d142a9e --- /dev/null +++ b/board/freescale/mx27ads/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx27ads.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/freescale/mx27ads/config.mk b/board/freescale/mx27ads/config.mk new file mode 100644 index 0000000..a2e7768 --- /dev/null +++ b/board/freescale/mx27ads/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xA7F00000 diff --git a/board/freescale/mx27ads/lowlevel_init.S b/board/freescale/mx27ads/lowlevel_init.S new file mode 100644 index 0000000..dc62a93 --- /dev/null +++ b/board/freescale/mx27ads/lowlevel_init.S @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include <config.h> +#include <asm/macro.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +.macro sdram_init + /* + * DDR on CSD0 + */ + write32 0xD8001010, 0x00000008 + write32 0x10027828, 0x55555555 + write32 0x10027830, 0x55555555 + write32 0x10027834, 0x55555555 + write32 0x10027838, 0x00005005 + write32 0x1002783C, 0x15555555 + write32 0xD8001010, 0x00000004 + write32 0xD8001004, 0x006ac73a + write32 0xD8001000, 0x92100000 + write32 0xA0000F00, 0x00000000 + write32 0xD8001000, 0xA2100000 + write32 0xA0000F00, 0x00000000 + write32 0xA0000F00, 0x00000000 + write32 0xA0000F00, 0x00000000 + write32 0xA0000F00, 0x00000000 + write32 0xD8001000, 0xA2200000 + write32 0xA0000F00, 0x00000000 + write32 0xA0000F00, 0x00000000 + write32 0xA0000F00, 0x00000000 + write32 0xA0000F00, 0x00000000 + write32 0xD8001000, 0xb2100000 + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + write32 0xD8001000, 0x82226080 +.endm + +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + + /* ahb lite ip interface */ + write32 AIPI1_PSR0, 0x20040304 + write32 AIPI1_PSR1, 0xDFFBFCFB + write32 AIPI2_PSR0, 0x00000000 + write32 AIPI2_PSR1, 0xFFFFFFFF + + /* disable mpll/spll */ + ldr r0, =CSCR + ldr r1, [r0] + bic r1, r1, #0x03 + str r1, [r0] + + /* + * pll clock initialization - see section 3.4.3 of the i.MX27 manual + * + * FIXME: Using the 399*2 MHz values from table 3-8 doens't work + * with 1.2 V core voltage! Find out if this is + * documented somewhere. + */ + write32 MPCTL0, 0x1EF15D5 /* MPLL = 199.5*2 MHz */ + write32 SPCTL0, 0x043A1C09 /* SPLL = FIXME (needs review) */ + + /* + * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz + * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz + * System clock (HCLK) = 133 MHz + */ + write32 CSCR, (0x33F08107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART) + + /* add some delay here */ + mov r1, #0x1000 +1: subs r1, r1, #0x1 + bne 1b + + /* clock gating enable */ + write32 0x10027818, 0x00050f08 + + /* peripheral clock divider */ + write32 PCDR0, 0x120470C3 /* FIXME */ + write32 PCDR1, 0x03030303 /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz */ + + /* Configure PCCR0 and PCCR1*/ + write32 PCCR0, 0xFFFFFFFF + write32 PCCR1, 0xFFFFFFFC + + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + mov pc,r10 +1: + sdram_init + + mov pc,r10 + diff --git a/board/freescale/mx27ads/mx27ads.c b/board/freescale/mx27ads/mx27ads.c new file mode 100644 index 0000000..4def923 --- /dev/null +++ b/board/freescale/mx27ads/mx27ads.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2008,2009 Eric Jarrige <jorasse(a)users.sourceforge.net> + * Copyright (C) 2009 Ilya Yanok <yanok(a)emcraft.com> + * Copyright (C) 2009 Alan Carvalho de Assis <alan(a)maxtrack.com.br> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/macro.h> +#include <asm/arch/imx-regs.h> + +# define __REG(x) (*((volatile u32 *)(x))) + +#define IMX_CS4_BASE 0xD4000000 +#define CS4U __REG(IMX_WEIM_BASE + 0x40) /* Chip Select 4 Upper Register */ +#define CS4L __REG(IMX_WEIM_BASE + 0x44) /* Chip Select 4 Lower Register */ +#define CS4A __REG(IMX_WEIM_BASE + 0x48) /* Chip Select 4 Addition Register */ + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; + + gd->bd->bi_arch_number = MACH_TYPE_MX27ADS; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + +#ifdef CONFIG_MXC_UART + mx27_uart_init_pins(); +#endif +#ifdef CONFIG_FEC_MXC + mx27_fec_init_pins(); + imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31)); + writel(readl(&regs->port[PORTC].dr) | (1 << 31), + &regs->port[PORTC].dr); + + /* Configure CPLD on CS4 */ + CS4U = 0x0000DCF6; + CS4L = 0x444A4541; + CS4A = 0x44443302; + + /* Select FEC data through data path */ + writew(0x0020, IMX_CS4_BASE + 0x10); + + /* Enable CPLD FEC data path */ + writew(0x0010, IMX_CS4_BASE + 0x14); +#endif +#ifdef CONFIG_MXC_MMC + mx27_sd2_init_pins(); +#endif + + return 0; +} + +int dram_init(void) +{ + +#if CONFIG_NR_DRAM_BANKS > 0 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#endif +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("Freescale i.MX27ADS\n"); + return 0; +} diff --git a/board/freescale/mx27ads/u-boot.lds b/board/freescale/mx27ads/u-boot.lds new file mode 100644 index 0000000..f66f20e --- /dev/null +++ b/board/freescale/mx27ads/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} + diff --git a/include/configs/mx27ads.h b/include/configs/mx27ads.h new file mode 100644 index 0000000..3360d76 --- /dev/null +++ b/include/configs/mx27ads.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2009 Ilya Yanok <yanok(a)emcraft.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX27 +#define CONFIG_IMX27ADS +#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/*=============*/ +/* Memory Info */ +/*=============*/ +/* malloc() len */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) +/* reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +/* memtest start address */ +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ + +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX27_UART1 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_FLASH_CFI + +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */ +/* end of flash */ +#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000) +/* CS2 Base address */ +#define PHYS_FLASH_1 0xc0000000 +/* Flash Base for U-Boot */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +/* Flash size 32MB */ +#define PHYS_FLASH_SIZE 0x2000000 +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ + CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x1f +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/*#define CONFIG_DRIVER_CS8900 1 +#define CS8900_BASE 0xD4020300 +#define CS8900_BUS16 1*/ +#define CONFIG_ETHADDR 02:80:ad:20:31:e8 + +/* + * NAND + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_MXC_NAND_HWECC + +/* + * SD/MMC + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 +#define CONFIG_DOS_PARTITION + +/* + * MTD partitions + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:256k(U-Boot),3968k(kernel),28416k(user),64k(env1),64k(env2)" + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer sz */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "u-boot=imx27/u-boot.bin\0" \ + "kernel_addr_r=a0800000\0" \ + "hostname=imx27\0" \ + "bootfile=imx27/uImage\0" \ + "rootpath=/opt/eldk-4.2-arm/arm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run net_nfs\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#endif /* __CONFIG_H */ -- 1.6.0.4

3 3

[U-Boot] [PATCH] Add support for Eukrea CPU9260/CPU9G20 SBC
by Eric Benard 22 Sep '09

22 Sep '09

these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric(a)eukrea.com> --- MAINTAINERS | 5 + MAKEALL | 2 + Makefile | 8 + board/eukrea/cpu9260/Makefile | 59 +++++ board/eukrea/cpu9260/config.mk | 1 + board/eukrea/cpu9260/cpu9260.c | 218 +++++++++++++++++ board/eukrea/cpu9260/led.c | 153 ++++++++++++ cpu/arm926ejs/at91/lowlevel_init.S | 3 +- include/configs/cpu9260.h | 453 ++++++++++++++++++++++++++++++++++++ 9 files changed, 901 insertions(+), 1 deletions(-) create mode 100644 board/eukrea/cpu9260/Makefile create mode 100644 board/eukrea/cpu9260/config.mk create mode 100644 board/eukrea/cpu9260/cpu9260.c create mode 100644 board/eukrea/cpu9260/led.c create mode 100644 include/configs/cpu9260.h diff --git a/MAINTAINERS b/MAINTAINERS index d674753..4b961b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -525,6 +525,11 @@ Dirk Behme <dirk.behme(a)gmail.com> omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC) +Eric Benard <eric(a)eukrea.com> + + cpu9260 ARM926EJS (AT91SAM9260 SoC) + cpu9G20 ARM926EJS (AT91SAM9G20 SoC) + Rishi Bhattacharya <rishi(a)ti.com> omap5912osk ARM926EJS diff --git a/MAKEALL b/MAKEALL index 85f99ef..7a438f7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -605,6 +605,8 @@ LIST_at91=" \ at91sam9m10g45ek \ at91sam9rlek \ cmc_pu2 \ + CPU9260 \ + CPU9G20 \ csb637 \ kb9202 \ meesc \ diff --git a/Makefile b/Makefile index dd01b66..1d1ded4 100644 --- a/Makefile +++ b/Makefile @@ -2863,6 +2863,14 @@ at91sam9rlek_config : unconfig fi; @$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91 +CPU9G20_128M_config \ +CPU9G20_config \ +CPU9260_128M_config \ +CPU9260_config : unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h + @$(MKCONFIG) -a cpu9260 arm arm926ejs cpu9260 eukrea at91 + meesc_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91 diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile new file mode 100644 index 0000000..a718014 --- /dev/null +++ b/board/eukrea/cpu9260/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# Ilko Iliev <www.ronetix.at> +# +# (C) Copyright 2009 +# Eric Benard <eric(a)eukrea.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += led.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/eukrea/cpu9260/config.mk b/board/eukrea/cpu9260/config.mk new file mode 100644 index 0000000..9ce161e --- /dev/null +++ b/board/eukrea/cpu9260/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c new file mode 100644 index 0000000..cff4a63 --- /dev/null +++ b/board/eukrea/cpu9260/cpu9260.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * (C) Copyright 2009 + * Eric Benard <eric(a)eukrea.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void cpu9260_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ +#if defined(CONFIG_CPU9G20) + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_DBW_8 | + AT91_SMC_TDF_(3)); +#elif defined(CONFIG_CPU9260) + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_DBW_8 | + AT91_SMC_TDF_(2)); +#endif + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void cpu9260_macb_hw_init(void) +{ + unsigned long rstc; + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of the board */ +#if defined(CONFIG_CPU9G20) + gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; +#elif defined(CONFIG_CPU9260) + gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; +#endif + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + cpu9260_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + cpu9260_macb_hw_init(); +#endif +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) + return -1; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/eukrea/cpu9260/led.c b/board/eukrea/cpu9260/led.c new file mode 100644 index 0000000..76b67c4 --- /dev/null +++ b/board/eukrea/cpu9260/led.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * (C) Copyright 2009 + * Eric Benard <eric(a)eukrea.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <status_led.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF, + STATUS_LED_OFF, STATUS_LED_OFF}; + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + at91_set_gpio_output(CONFIG_BLUE_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 1); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + at91_set_gpio_value(CONFIG_BLUE_LED, 1); +} + +void red_LED_off (void) +{ + at91_set_gpio_value(CONFIG_RED_LED, 1); + saved_state[STATUS_LED_RED] = STATUS_LED_OFF; +} + +void green_LED_off (void) +{ + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF; +} + +void yellow_LED_off (void) +{ + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); + saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF; +} + +void blue_LED_off (void) +{ + at91_set_gpio_value(CONFIG_BLUE_LED, 1); + saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; +} + +void red_LED_on (void) +{ + at91_set_gpio_value(CONFIG_RED_LED, 0); + saved_state[STATUS_LED_RED] = STATUS_LED_ON; +} + +void green_LED_on (void) +{ + at91_set_gpio_value(CONFIG_GREEN_LED, 0); + saved_state[STATUS_LED_GREEN] = STATUS_LED_ON; +} + +void yellow_LED_on (void) +{ + at91_set_gpio_value(CONFIG_YELLOW_LED, 0); + saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON; +} + +void blue_LED_on (void) +{ + at91_set_gpio_value(CONFIG_BLUE_LED, 0); + saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; +} + +void __led_init (led_id_t mask, int state) +{ + __led_set (mask, state); +} + +void __led_toggle (led_id_t mask) +{ + if (STATUS_LED_BLUE == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) + blue_LED_off(); + else + blue_LED_on(); + } else if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) + red_LED_off(); + else + red_LED_on(); + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN]) + green_LED_off(); + else + green_LED_on(); + } else if (STATUS_LED_YELLOW == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW]) + yellow_LED_off(); + else + yellow_LED_on(); + } +} + +void __led_set (led_id_t mask, int state) +{ + if (STATUS_LED_BLUE == mask) { + if (STATUS_LED_ON == state) + blue_LED_on(); + else + blue_LED_off(); + } else if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == state) + red_LED_on(); + else + red_LED_off(); + } else if (STATUS_LED_GREEN == mask) { + if (STATUS_LED_ON == state) + green_LED_on(); + else + green_LED_off(); + } else if (STATUS_LED_YELLOW == mask) { + if (STATUS_LED_ON == state) + yellow_LED_on(); + else + yellow_LED_off(); + } +} diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index 9962ae9..f11ebc6 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -194,7 +194,8 @@ SMRDATA: .word CONFIG_SYS_PIOD_PPUDR_VAL .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) .word CONFIG_SYS_PIOD_PPUDR_VAL -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ + || defined(CONFIG_AT91SAM9G20) .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) .word CONFIG_SYS_PIOC_PDR_VAL1 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h new file mode 100644 index 0000000..4ef8566 --- /dev/null +++ b/include/configs/cpu9260.h @@ -0,0 +1,453 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * (C) Copyright 2009 + * Eric Benard <eric(a)eukrea.com> + * + * Configuration settings for the Eukrea CPU9260 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_DISPLAY_CPUINFO 1 + +#define AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 + +#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260) +#define CONFIG_CPU9260 1 +#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20) +#define CONFIG_CPU9G20 1 +#endif + +#if defined(CONFIG_CPU9G20) +#define CONFIG_AT91SAM9G20 1 +#elif defined(CONFIG_CPU9260) +#define CONFIG_AT91SAM9260 1 +#else +#error "Unknown board" +#endif + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* clocks */ +#if defined(CONFIG_CPU9G20) +#define MASTER_PLL_DIV 0x01 +#define MASTER_PLL_MUL 0x2B +#elif defined(CONFIG_CPU9260) +#define MASTER_PLL_DIV 0x09 +#define MASTER_PLL_MUL 0x61 +#endif + +/* CKGR_MOR - enable main osc. */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +#endif + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_6 | \ + AT91_PMC_PDIV_2) +#define CONFIG_SYS_MCKR2_VAL \ + CONFIG_SYS_MCKR1_VAL +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +#endif + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 + +/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\ + AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x287 +/* SDRAMC_CR - Configuration register*/ +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_SDRC_CR_VAL_64MB \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (9 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (3 << 20) | /* Row to Column Delay */ \ + (6 << 24) | /* Active to Precharge Delay */ \ + (10 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_CR_VAL_128MB \ + (AT91_SDRAMC_NC_10 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (9 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (3 << 20) | /* Row to Column Delay */ \ + (6 << 24) | /* Active to Precharge Delay */ \ + (10 << 28)) /* Exit Self Refresh to Active Delay */ +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_SDRC_CR_VAL_64MB \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_CR_VAL_128MB \ + (AT91_SDRAMC_NC_10 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ +#endif + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit */ +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \ + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \ + AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(3)) +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \ + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \ + AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(2)) +#endif + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_FAT 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M) +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB +#else +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB +#endif + +/* NAND flash */ +#define CONFIG_NAND_ATMEL 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) + +/* NOR flash */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_2 0x12000000 +#define CONFIG_SYS_FLASH_BANKS_LIST \ + { PHYS_FLASH_1, PHYS_FLASH_2 } +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT (255+4) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY 1 + +/* LEDS */ +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_RED 0 +#define STATUS_LED_GREEN 1 +#define STATUS_LED_YELLOW 2 +#define STATUS_LED_BLUE 3 +/* Red */ +#define STATUS_LED_BIT STATUS_LED_RED +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Green */ +#define STATUS_LED_BIT1 STATUS_LED_GREEN +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Yellow */ +#define STATUS_LED_BIT2 STATUS_LED_YELLOW +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) +/* Blue */ +#define STATUS_LED_BIT3 STATUS_LED_BLUE +#define STATUS_LED_STATE3 STATUS_LED_ON +#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +#define CONFIG_RED_LED AT91_PIN_PC11 +#define CONFIG_GREEN_LED AT91_PIN_PC12 +#define CONFIG_YELLOW_LED AT91_PIN_PC7 +#define CONFIG_BLUE_LED AT91_PIN_PC9 + +/* USB */ +#define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_FLASH 1 + +#if defined(CONFIG_SYS_USE_FLASH) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "256k(u-boot)ro," \ + "128k(u-boot-env)ro," \ + "1792k(kernel)," \ + "-(rootfs);" \ + "atmel_nand:-(nand)" + +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 " + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_BASEDIR "cpu9G20" +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_BASEDIR "cpu9260" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \ + "run ramargs;bootm 22000000\0" \ + "flashboot=run ramargs;bootm 0x10060000\0" \ + "basedir=" CONFIG_SYS_BASEDIR "\0" \ + "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \ + "off 0x10000000 0x1003ffff;erase 0x10000000 " \ + "0x1003ffff;cp.b 0x24000000 0x10000000 " \ + "$(filesize)\0" \ + "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \ + " 0x10060000 0x1021ffff;erase 0x10060000 " \ + "0x1021ffff;cp.b 0x24000000 0x10060000 " \ + "$(filesize)\0" \ + "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \ + "protect off 0x10220000 0x13ffffff;erase " \ + "0x10220000 0x13ffffff;cp.b 0x24000000 " \ + "0x10220000 $(filesize)\0" \ + "" +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_PROMPT "CPU9G20=> " +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_PROMPT "CPU9260=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_NETCONSOLE 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_STACKSIZE (32 * 1024) + +#if defined(CONFIG_USE_IRQ) +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- 1.6.0.4

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[U-Boot] [PATCH 0/3 v2] New MIIPHYBB implementation with multi-bus support
by Luigi 'Comio' Mantellini 22 Sep '09

22 Sep '09

From: Luigi 'Comio' Mantellini <luigi.mantellini(a)idf-hit.com> This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to support an arbitrary number of buses. This feature is useful when your board uses different mii buses for different phys and all (or a part) of these buses are implemented via bit-banging mode. The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver CONFIG_BITBANGMII_MULTI - Enable the multi bus support If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs to define the following macros: MII_INIT - Generic cod to enable the MII bus (like gpios setup) MDIO_DECLARE - Declaration needed to access to the MDIO pin MDIO_ACTIVE - Activate the MDIO pin as out pin MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin MDIO_READ - Read the MDIO pin MDIO(v) - Write v on the MDIO pin MDC_DECLARE - Declaration needed to access to the MDC pin MDC(v) - Write v on the MDC pin The previous macros make the driver compatible with the previous version (that didn't support the multi-bus). When the CONFIG_BITBANGMII_MULTI is defined, the board code needs to fill the bbmiibusses[] array with a record for each required bus. The record (struct bbmiibus) has the following fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name int (*init)() - Initialization function called at startup time (just before the Ethernet initialization) int (*mdio_active)() - Activate the MDIO pin as output int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin int (*set_mdio)() - Write the MDIO pin int (*get_mdio)() - Read the MDIO pin int (*set_mdc)() - Write the MDC pin int (*delay)() - Delay function void *priv - Private data used by board specific code The board code will look like: struct bbmiibus bbmiibusses[] = { { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... }, { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... }, ... }; Patch Changelog: v1 -- First (broken) release v2 -- Fix some typos and disable callbacks pointers relacation (if CONFIG_RELOC_FIXUP_WORKS is not defined) Luigi 'Comio' Mantellini (3): Bit-banged MII driver with multi-bus support. Add bb_miiphy_init call before any ethernet bring-up code. Update all board to support new bbmiiphy driver (with multibus support) drivers/net/phy/miiphybb.c | 322 +++++++++++++++++++++++++++++------------- include/configs/ISPAN.h | 3 + include/configs/MPC8260ADS.h | 2 + include/configs/MPC8266ADS.h | 3 + include/configs/MPC8560ADS.h | 3 + include/configs/Rattler.h | 3 + include/configs/SBC8540.h | 3 + include/configs/TQM8272.h | 2 + include/configs/VoVPN-GW.h | 3 + include/configs/ZPC1900.h | 3 + include/configs/ep8248.h | 3 + include/configs/ep82xxm.h | 3 + include/configs/gw8260.h | 3 + include/configs/hymod.h | 9 ++ include/configs/muas3001.h | 3 + include/configs/ppmc8260.h | 3 + include/configs/sacsng.h | 3 + include/configs/sbc8260.h | 3 + include/configs/sbc8560.h | 3 + include/miiphy.h | 22 +++ lib_arm/board.c | 3 + lib_avr32/board.c | 3 + lib_blackfin/board.c | 3 + lib_i386/board.c | 3 + lib_m68k/board.c | 3 + lib_mips/board.c | 3 + lib_ppc/board.c | 4 +- lib_sh/board.c | 3 + lib_sparc/board.c | 3 + 29 files changed, 333 insertions(+), 97 deletions(-)

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[U-Boot] [PATCH] ppc/85xx: add cpu init config file for boot from NAND
by Mingkai Hu 22 Sep '09

22 Sep '09

When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> --- ChangeLog: - move the board specific config for br/or to board init file, i.e. nand_spl/board/freescale/mpc8536ds/nand_boot.c, which make it common for 85xx platform. cpu/mpc85xx/cpu_init_nand.c | 63 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 63 insertions(+), 0 deletions(-) create mode 100644 cpu/mpc85xx/cpu_init_nand.c diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c new file mode 100644 index 0000000..184cca4 --- /dev/null +++ b/cpu/mpc85xx/cpu_init_nand.c @@ -0,0 +1,63 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +void cpu_init_f(void) +{ + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + + /* + * LCRR - Clock Ratio Register - set up local bus timing + * when needed + */ + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); + +#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); +#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + char *l2srbar; + int i; + + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* Initialize L2 SRAM to zero */ + l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; + for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) + l2srbar[i] = 0; +#endif +} -- 1.6.4

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