September 2009 - U-Boot

Re: [U-Boot] [PATCH] MCI support for AT91 family processors.
by Sami Kantoluoto 01 Sep '09

01 Sep '09

On Sun, Aug 30, 2009 at 01:08:27AM +0200, Albin Tonnerre wrote: > On Sat, Aug 29, 2009 at 08:18:32PM +0300, Sami Kantoluoto wrote : > > Fixed to parse CSD correctly on little endian processors as gcc orders > > bitfields differently between big and little endian ones. > > Please also see this patch, which will fix those bugs as weel, while switching > to the new GENRIC_MMC API: > http://lists.denx.de/pipermail/u-boot/2009-August/059456.html > I'd highly appreciate if you could test it, to get some feedback Thanks, I'll test when I get some time later this week but I think (by reading the patch so I probably missed something) it won't solve the CSD problem. The real reason of the "CSD problem" of course is that how the mmc_csd structure is defined (host byte order not taken in account or at least how gcc handles bitfields). [snip] > the configuration for the MCI controller, which should be done in the > at91sam*_devices.c files. See the attached patch (relying on the patch > mentionned above) that adds such support. It's not complete yet either: it > partially lacks support for models which have 2 MCI controllers, but > that's not the case of the 9G20 anyway (that's just a matter of putting > proper ifdefs before defining AT91_BASE_MCI). > If what I've done in this patch is not the way to go, I'd appreciate > guidance on how to do it correctly. It seems ok to me except one comment about the interface: > diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h > > +void at91_mci0_hw_init(int); > +void at91_mci1_hw_init(int); I'm just wondering if the bus width should be configurable. It's probably quite unusual to use just one data bit but not impossible though. So maybe the interface call could be: void at91_mci0_hw_init(int bwForSlotA, bwForSlotB) Where the bwForSlot<X> is either 0 (which means slot is not used), 1 or 4. -sk

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[U-Boot] [PATCH] AT91: Add SD/MMC controller support
by Albin Tonnerre 01 Sep '09

01 Sep '09

This patch allows to use the atmel_mci SD/MMC driver on the at91 architecture. It contains: - initialization code for the MCI controller for all the supported AT91. It allows the use of only one controller even if a SoC has two controllers (anyway there's no support for it in atmel_mci as of now) - the necessary get_mci_clk_rate function - definition of MMCI_BASE for use in atmel_mci - the cpu_mmc_init function. As of now this is not used, but will be required when atmel_mci is ported to the new generic mmc API. Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- cpu/arm926ejs/at91/at91cap9_devices.c | 36 ++++++++++++++++++ cpu/arm926ejs/at91/at91sam9260_devices.c | 27 +++++++++++++ cpu/arm926ejs/at91/at91sam9261_devices.c | 18 +++++++++ cpu/arm926ejs/at91/at91sam9263_devices.c | 54 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 54 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9rl_devices.c | 22 +++++++++++ cpu/arm926ejs/at91/cpu.c | 7 +++ include/asm-arm/arch-at91/at91_common.h | 2 + include/asm-arm/arch-at91/clk.h | 5 ++ include/asm-arm/arch-at91/hardware.h | 18 +++++++++ include/asm-arm/arch-at91/memory-map.h | 1 + 11 files changed, 244 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..4486cbb 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -79,6 +79,42 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } +} +#elif defined(CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI); + at91_set_A_periph(AT91_PIN_PA16, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA17, 1); + at91_set_A_periph(AT91_PIN_PA18, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + at91_set_A_periph(AT91_PIN_PA21, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index f86cb99..ea22030 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -75,6 +75,33 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_set_A_periph(AT91_PIN_PA8, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_A_periph(AT91_PIN_PA7, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + } +} +#endif /* ATMEL_MCI */ + #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..7ee573c 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -75,6 +75,24 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_MCI); + at91_set_B_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_B_periph(AT91_PIN_PA6, 1); + } + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..40e36a4 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -79,6 +79,60 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA12, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } + if (mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA16, 1); + at91_set_A_periph(AT91_PIN_PA17, 1); + if (mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + } +} +#elif defined(CONFIG_AT91_MCI1) +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI); + at91_set_A_periph(AT91_PIN_PA6, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA21, 1); + at91_set_B_periph(AT91_PIN_PA22, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA23, 1); + at91_set_B_periph(AT91_PIN_PA24, 1); + at91_set_B_periph(AT91_PIN_PA25, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..647306a 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -75,6 +75,60 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA12, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } + if (mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA16, 1); + at91_set_A_periph(AT91_PIN_PA17, 1); + if (mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + } +} +#elif defined(CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI); + at91_set_A_periph(AT91_PIN_PA6, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..41ae4a8 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -75,6 +75,28 @@ void at91_serial_hw_init(void) #endif } +/* + * The AT91SAM9RL64 is said to have 2 slots, but the datasheet doesn't + * seem to mention to what pins the second slot is assigned + */ +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_set_A_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..f96b715 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -52,3 +52,10 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_GENERIC_MMC +int cpu_mmc_init(bd_t *bis) +{ + atmel_mci_init(bis); +} +#endif /* GENERIC_MMC */ diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h index 01840ee..01fcdd6 100644 --- a/include/asm-arm/arch-at91/at91_common.h +++ b/include/asm-arm/arch-at91/at91_common.h @@ -32,6 +32,8 @@ void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); void at91_serial2_hw_init(void); void at91_serial3_hw_init(void); +void at91_mci0_hw_init(unsigned long mask); +void at91_mci1_hw_init(unsigned long mask); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); void at91_uhp_hw_init(void); diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index f642dd9..457e6c9 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index de06a10..ca4af37 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -20,31 +20,49 @@ #include <asm/arch/at91rm9200.h> #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) #include <asm/arch/at91sam9260.h> +#define AT91_BASE_MCI AT91SAM9260_BASE_MCI #define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 #define AT91_ID_UHP AT91SAM9260_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) #include <asm/arch/at91sam9261.h> +#define AT91_BASE_MCI AT91SAM9261_BASE_MCI #define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 #define AT91_ID_UHP AT91SAM9261_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9263) #include <asm/arch/at91sam9263.h> +#ifdef CONFIG_AT91_MCI1 + #define AT91_BASE_MCI AT91SAM9263_BASE_MCI1 +#else + #define AT91_BASE_MCI AT91SAM9263_BASE_MCI0 +#endif #define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 #define AT91_ID_UHP AT91SAM9263_ID_UHP #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91SAM9RL) #include <asm/arch/at91sam9rl.h> +#define AT91_BASE_MCI AT91SAM9RL_BASE_MCI #define AT91_BASE_SPI AT91SAM9RL_BASE_SPI #define AT91_ID_UHP AT91SAM9RL_ID_UHP #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) #include <asm/arch/at91sam9g45.h> +#ifdef CONFIG_AT91_MCI1 + #define AT91_BASE_MCI AT91SAM9G45_BASE_MCI1 +#else + #define AT91_BASE_MCI AT91SAM9G45_BASE_MCI0 +#endif #define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC #define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0 #define AT91_ID_UHP AT91SAM9G45_ID_UHPHS #define AT91_PMC_UHP AT91SAM926x_PMC_UHP #elif defined(CONFIG_AT91CAP9) #include <asm/arch/at91cap9.h> +#ifdef CONFIG_AT91_MCI1 + #define AT91_BASE_MCI AT91CAP9_BASE_MCI1 +#else + #define AT91_BASE_MCI AT91CAP9_BASE_MCI0 +#endif #define AT91_BASE_SPI AT91CAP9_BASE_SPI0 #define AT91_ID_UHP AT91CAP9_ID_UHP #define AT91_PMC_UHP AT91CAP9_PMC_UHP diff --git a/include/asm-arm/arch-at91/memory-map.h b/include/asm-arm/arch-at91/memory-map.h index f605f37..300b61d 100644 --- a/include/asm-arm/arch-at91/memory-map.h +++ b/include/asm-arm/arch-at91/memory-map.h @@ -31,5 +31,6 @@ #define USART2_BASE AT91_USART2 #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) #define SPI0_BASE AT91_BASE_SPI +#define MMCI_BASE AT91_BASE_MCI #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ -- 1.6.3.3

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[U-Boot] [PATCH] Support for Micrel/Kendin KS899xM managed switches.
by Sami Kantoluoto 01 Sep '09

01 Sep '09

This patch adds simple support for KS8993M and KS8995MA managed switches. It uses SPI interface for configuration (as everything cannot be configured through MII). Switch can be configured to either regular switch or to "router mode" so that every port (except the host port) has it's own VLAN ("port based VLAN"). Signed-off-by: Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/ks899xm.c | 189 +++++++++++++++++++++++++++++++++ drivers/net/phy/ks899xm.h | 255 +++++++++++++++++++++++++++++++++++++++++++++ include/netdev.h | 15 +++ 4 files changed, 460 insertions(+), 0 deletions(-) create mode 100644 drivers/net/phy/ks899xm.c create mode 100644 drivers/net/phy/ks899xm.h diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 3b92614..d91244c 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libphy.a COBJS-$(CONFIG_BITBANGMII) += miiphybb.o +COBJS-$(CONFIG_KS899XM_SWITCH) += ks899xm.o COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS := $(COBJS-y) diff --git a/drivers/net/phy/ks899xm.c b/drivers/net/phy/ks899xm.c new file mode 100644 index 0000000..87e47c7 --- /dev/null +++ b/drivers/net/phy/ks899xm.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <spi.h> +#include "ks899xm.h" + +static unsigned int ks_cmd (struct spi_slave *ss, + unsigned rdwr, unsigned reg, unsigned value, + unsigned *retvalue) +{ + unsigned char cmd[4] = { rdwr, reg, value }, rsp[4]; + int ret; + + ret = spi_xfer(ss, 32, cmd, rsp, SPI_XFER_BEGIN | SPI_XFER_END); + + if (ret != 0) { + return KS_ERROR; + } + + if (retvalue) { + *retvalue = rsp[2]; + } + + return KS_OK; +} + +static unsigned int ks_write_reg (struct spi_slave *ss, + unsigned reg, unsigned value) +{ + /*printf("%s: reg=%02x, value=%02x\n", __FUNCTION__, reg, value); */ + return ks_cmd (ss, KS_WR_DATA, reg, value, 0); +} + +static unsigned int ks_read_reg (struct spi_slave *ss, + unsigned reg, unsigned *value) +{ + int ret = ks_cmd (ss, KS_RD_DATA, reg, 0, value); + /*printf("%s: reg=%02x, value=%02x, ret=%d\n", __FUNCTION__, reg, *value, ret); */ + return ret; +} + +static unsigned int ks_ind_wr (struct spi_slave *ss, + unsigned table, unsigned addr, + const unsigned char *data, int dlen) +{ + int i, ret; + + for (ret = KS_OK, i = 9 - dlen; ret == KS_OK && (i <= 8); i++) { + ret = ks_write_reg (ss, KS_IDR8 + i, *data++); + } + + if (ret == KS_OK) { + ret = + ks_write_reg (ss, KS_IAC0, + (table & KS_IAC0_TBL) | ((addr >> 8) & + KS_IAC0_ADDR_HIGH)); + } + + if (ret == KS_OK) { + ret = ks_write_reg (ss, KS_IAC1, addr & 0xff); + } + + return ret; +} + +static int ks_write_vtab (struct spi_slave *ss, + unsigned ndx, unsigned vid, unsigned fid, + unsigned members) +{ + unsigned char buf[3] = { + 0x20 | (members & 0x1F), + (fid << 4) | ((vid >> 8) & 0xF), + vid & 0xFF + }; + return ks_ind_wr (ss, KS_IAC0_TBL_VLAN, ndx, buf, 3); +} + +int ks899xm_switch_initialize(const struct ks899xm_config *swconfig) +{ + struct spi_slave *ss; + int ret = -1, i, nports = -1; + unsigned id0, id1; + + /* check arguments */ + if (swconfig->vlancfg != KS899XM_VLANCFG_DEFAULT + && swconfig->vlancfg != KS899XM_VLANCFG_ROUTER) + goto done; + + /* prepare spi */ + ss = spi_setup_slave(swconfig->spibus, swconfig->spics, + 10000000, SPI_MODE_0); + if (!ss) + goto done; + if (spi_claim_bus(ss) != 0) + goto done_2; + + /* get chip id */ + if (ks_read_reg (ss, KS_ID0, &id0) != KS_OK + || ks_read_reg (ss, KS_ID1, &id1) != KS_OK) + goto done_3; + + /* check chip id */ + switch (id0) { + case 0x93: + case 0x95: + if (!(id1 & 0xF0)) { + nports = id0 & 0xf; + printf ("Micrel %s detected, revision: 0x%X\n", + nports == 5 ? "KS8995MA" : "KS8993M", + (id1 & 0x0e) >> 1); + break; + } + /* fall through: */ + default: + printf ("unknown chip, id0:%02x, id1=%02x\n", id0, id1); + goto done_3; + } + + /* enable flow control */ + if (ks_write_reg(ss, KS_GC3, + swconfig->vlancfg == KS899XM_VLANCFG_ROUTER + ? KS_GC3_802_1Q_VLAN : 0) != KS_OK + || ks_write_reg(ss, KS_GC4, KS_GC4_MII_FLOW_ENA) != KS_OK) + goto done_3; + + if (swconfig->vlancfg == KS899XM_VLANCFG_ROUTER) { + /* configure vlans */ + for (i = 0; i < (nports - 1); i++) { + if (ks_write_vtab (ss, i, i + 1, i + 1, + (1 << (nports - 1)) | (1 << i)) != KS_OK) + goto done_3; + if (ks_write_reg (ss, KS_P1 + 16 * i + KS_P_CR0, + KS_P_CR0_TAG_REMOVAL) != KS_OK || + ks_write_reg (ss, KS_P1 + 16 * i + KS_P_CR1, + 1 << (nports - 1)) != KS_OK || + ks_write_reg (ss, KS_P1 + 16 * i + KS_P_CR2, + KS_P_CR2_VLAN_FILTERING | + KS_P_CR2_TRANSMIT_ENA | + KS_P_CR2_RECEIVE_ENA) != KS_OK) + goto done_3; + } + /* configure host port too */ + if (ks_write_reg (ss, KS_P1 + 16 * i + KS_P_CR0, + KS_P_CR0_TAG_INSERTION) != KS_OK || + ks_write_reg (ss, KS_P1 + 16 * i + KS_P_CR1, + (1 << i) - 1) != KS_OK || + ks_write_reg (ss, KS_P1 + 16 * i + KS_P_CR2, + KS_P_CR2_TRANSMIT_ENA | + KS_P_CR2_RECEIVE_ENA) != KS_OK) + goto done_3; + } + if (ks_write_reg (ss, KS_GC9, 0) != KS_OK) + goto done_3; + + /* finally start the switch */ + if (ks_write_reg (ss, KS_ID1, KS_ID1_START_SWITCH) == KS_OK) { + ret = 0; + } + +done_3: + spi_release_bus(ss); +done_2: + spi_free_slave(ss); +done: + return ret; +} diff --git a/drivers/net/phy/ks899xm.h b/drivers/net/phy/ks899xm.h new file mode 100644 index 0000000..d3d6591 --- /dev/null +++ b/drivers/net/phy/ks899xm.h @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _KS899XMA_H +#define _KS899XMA_H 1 + +#define KS_OK 0 +#define KS_ERROR -1 + +#define KS_RD_DATA 0x03 +#define KS_WR_DATA 0x02 + +enum { + KS_ID0 = 0, + KS_ID1, + KS_GC0, + KS_GC1, + KS_GC2, + KS_GC3, + KS_GC4, + KS_GC5, + KS_GC6, + KS_GC7, + KS_GC8, + KS_GC9, + + KS_P_CR0 = 0, + KS_P_CR1, + KS_P_CR2, + KS_P_CR3, + KS_P_CR4, + KS_P_CR5, + KS_P_CR6, + KS_P_CR7, + KS_P_CR8, + KS_P_CR9, + KS_P_CR10, + KS_P_CR11, + KS_P_CR12, + KS_P_CR13, + KS_P_SR0, + KS_P_CR14, + + KS_P1 = 16, + KS_P2 = 32, + KS_P3 = 48, + KS_P4 = 64, + KS_P5 = 80, + + KS_TOS_PCR0 = 96, + KS_TOS_PCR1, + KS_TOS_PCR2, + KS_TOS_PCR3, + KS_TOS_PCR4, + KS_TOS_PCR5, + KS_TOS_PCR6, + KS_TOS_PCR7, + + KS_TOS_MAC0, + KS_TOS_MAC1, + KS_TOS_MAC2, + KS_TOS_MAC3, + KS_TOS_MAC4, + KS_TOS_MAC5, + + KS_IAC0, + KS_IAC1, + KS_IDR8, + KS_IDR7, + KS_IDR6, + KS_IDR5, + KS_IDR4, + KS_IDR3, + KS_IDR2, + KS_IDR1, + KS_IDR0, + + KS_DTS0, + KS_DTS1, + KS_DTC0, + KS_DTC1, + KS_ATC0, + KS_ATC1, + KS_ATS, +}; + +#define KS_ID0_FAMILY_ID 0xFF + +#define KS_ID1_CHIP_ID 0xF0 +#define KS_ID1_CHIP_ID_B 4 +#define KS_ID1_REV_ID 0x0E +#define KS_ID1_START_SWITCH 0x01 + +#define KS_GC0_802_1P_PRIO 0x70 +#define KS_GC0_802_1P_PRIO_B 4 +#define KS_GC0_ENABLE_PHY_MII 0x08 +#define KS_GC0_SHARED_BUFFER 0x04 +#define KS_GC0_UNH_MODE 0x02 +#define KS_GC0_LINK_CHANGE_AGE 0x01 + +#define KS_GC1_PASS_ALL 0x80 +#define KS_GC1_PROMISCUOUS GC1_PASS_ALL +#define KS_GC1_TX_FLOW_CTL_DISABLE 0x20 +#define KS_GC1_RX_FLOW_CTL_DISABLE 0x10 +#define KS_GC1_FRAME_LENGTH_CHK 0x08 +#define KS_GC1_AGING 0x04 +#define KS_GC1_FAST_AGING 0x02 +#define KS_GC1_AGGRESSIVE_BACK_OFF 0x01 + +#define KS_GC2_UNICAST_VLAN_DISC 0x80 +#define KS_GC2_MULTICAST_STORM_DIS 0x40 +#define KS_GC2_BACK_PRESSURE_MODE 0x20 +#define KS_GC2_FAIR_MODE 0x10 +#define KS_GC2_NO_EXCESSIVE_DROP 0x08 +#define KS_GC2_HUGE_PACKET 0x04 +#define KS_GC2_DISABLE_LENGTH_CHK 0x02 +#define KS_GC2_PRIORITY_BUF 0x01 + +#define KS_GC3_802_1Q_VLAN 0x80 +#define KS_GC3_IGMP_SNOOP 0x40 +#define KS_GC3_MII_DIRECT_MODE 0x20 +#define KS_GC3_MII_PRE_TAG 0x10 +#define KS_GC3_PRIO_SCHEME_SEL 0x0C +#define KS_GC3_PRIO_SCHEME_HIGH 0x00 +#define KS_GC3_PRIO_SCHEME_10_1 0x04 +#define KS_GC3_PRIO_SCHEME_5_1 0x08 +#define KS_GC3_PRIO_SCHEME_2_1 0x0C +#define KS_GC3_TAG_MASK 0x02 +#define KS_GC3_RX_AND_TX_SNIFF 0x01 + +#define KS_GC4_MII_BACK_PRESSURE 0x80 +#define KS_GC4_MII_HALF_DUPLEX 0x40 +#define KS_GC4_MII_FLOW_ENA 0x20 +#define KS_GC4_MII_10_MBPS 0x10 +#define KS_GC4_NULL_VID_REPLACE 0x08 +#define KS_GC4_BCAST_STORM_PROT 0x07 +#define KS_GC4_BCAST_STORM_PROT_B 0 + +#define KS_GC5_BCAST_STORM_PROT 0xFF +#define KS_GC5_BCAST_STORM_PROT_B 0 + +#define KS_GC9_PHY_PWR_SAVE 0x08 +#define KS_GC9_PHY_LED_MODE 0x02 +#define KS_GC9_TPID_MODE 0x01 + +#define KS_P_CR0_BCAST_STORM_PROT_ENA 0x80 +#define KS_P_CR0_DIFFSERV_PRIO_ENA 0x40 +#define KS_P_CR0_802_1P_PRIO_ENA 0x20 +#define KS_P_CR0_CLASSIFICATION_ENA 0x10 +#define KS_P_CR0_TAG_INSERTION 0x04 +#define KS_P_CR0_TAG_REMOVAL 0x02 +#define KS_P_CR0_PRIO_ENA 0x01 + +#define KS_P_CR1_SNIFFER_PORT 0x80 +#define KS_P_CR1_RECEIVE_SNIFF 0x40 +#define KS_P_CR1_TRANSMIT_SNIFF 0x20 +#define KS_P_CR1_PORT_VLAN_MASK 0x1F + +#define KS_P_CR2_VLAN_FILTERING 0x40 +#define KS_P_CR2_DISCARD_NON_PVID 0x20 +#define KS_P_CR2_FORCE_FLOW_CTL 0x10 +#define KS_P_CR2_BACK_PRESURE_ENA 0x08 +#define KS_P_CR2_TRANSMIT_ENA 0x04 +#define KS_P_CR2_RECEIVE_ENA 0x02 +#define KS_P_CR2_LEARNING_DIS 0x01 + +#define KS_P_CR7_TX_LOW_PRIO_RATE 0xF0 +#define KS_P_CR7_TX_HIGH_PRIO_RATE 0x0F + +#define KS_P_CR10_RX_LOW_PRIO_RATE 0xF0 +#define KS_P_CR10_RX_HIGH_PRIO_RATE 0x0F + +#define KS_P_CR11_RX_DIFF_PRIO_ENA 0x80 +#define KS_P_CR11_RX_LOW_PRIO_RATE_ENA 0x40 +#define KS_P_CR11_RX_HIGH_PRIO_RATE_ENA 0x20 +#define KS_P_CR11_RX_LOW_PRIO_RATE_FLOW 0x10 +#define KS_P_CR11_RX_HIGH_PRIO_RATE_FLOW 0x08 +#define KS_P_CR11_TX_DIFF_PRIO_ENA 0x04 +#define KS_P_CR11_TX_LOW_PRIO_RATE_ENA 0x02 +#define KS_P_CR11_TX_HIGH_PRIO_RATE_ENA 0x01 + +#define KS_P_CR12_AUTO_NEG_DIS 0x80 +#define KS_P_CR12_100_MBPS 0x40 +#define KS_P_CR12_FULL_DUPLEX 0x20 +#define KS_P_CR12_ADVERTISED_FLOW_CTL 0x10 +#define KS_P_CR12_ADVERTISED_100_FD 0x08 +#define KS_P_CR12_ADVERTISED_100_HD 0x04 +#define KS_P_CR12_ADVERTISED_10_FD 0x02 +#define KS_P_CR12_ADVERTISED_10_HD 0x01 + +#define KS_P_CR13_LED_OFF 0x80 +#define KS_P_CR13_TX_DIS 0x40 +#define KS_P_CR13_RESTART_AN 0x20 +#define KS_P_CR13_FAR_END_DIS 0x10 +#define KS_P_CR13_PWR_DOWN 0x08 +#define KS_P_CR13_AUTO_MDI_MDI_X_DIS 0x04 +#define KS_P_CR13_FORCED_MDI 0x02 +#define KS_P_CR13_MAC_LOOPBACK 0x01 + +#define KS_P_PS0_MDI 0x80 +#define KS_P_PS0_AN_DONE 0x40 +#define KS_P_PS0_LINK_GOOD 0x20 +#define KS_P_PS0_PARTNER_FLOW_CTL_CAP 0x10 +#define KS_P_PS0_PARTNER_100BT_FD_CAP 0x08 +#define KS_P_PS0_PARTNER_100BT_HD_CAP 0x04 +#define KS_P_PS0_PARTNER_10BT_FD_CAP 0x02 +#define KS_P_PS0_PARTNER_10BT_HD_CAP 0x01 + +#define KS_P_CR14_PHY_LOOPBACK 0x80 +#define KS_P_CR14_REMOTE_LOOPBACK 0x40 +#define KS_P_CR14_PHY_ISOLATE 0x20 +#define KS_P_CR14_SOFT_RESET 0x10 +#define KS_P_CR14_FORCE_LINK 0x08 +#define KS_P_CR14_FAR_END_FAULT 0x01 + +#define KS_IAC0_RD 0x10 +#define KS_IAC0_TBL 0x0C +#define KS_IAC0_TBL_STATIC_MAC 0x00 +#define KS_IAC0_TBL_VLAN 0x04 +#define KS_IAC0_TBL_DYNAMIC_MAC 0x08 +#define KS_IAC0_TBL_MIB_COUNTER 0x0C +#define KS_IAC0_ADDR_HIGH 0x03 + +typedef union ks_ind_data { + u_int8_t Buf[9]; + struct { + u_int8_t _reserved[(72 - 21) / 8]; + u_int8_t Membership; +#define KS_MEMB_VALID 0x20 + u_int16_t VID; + } __attribute__ ((packed)) VLAN; +} ks_ind_data_t; + +#endif /* !_KS899XMA_H */ diff --git a/include/netdev.h b/include/netdev.h index a50ec67..628de38 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -171,4 +171,19 @@ struct mv88e61xx_config { int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ +#ifdef CONFIG_KS899XM_SWITCH +enum ks899xm_cfg_vlan { + KS899XM_VLANCFG_DEFAULT, + KS899XM_VLANCFG_ROUTER +}; + +struct ks899xm_config { + unsigned spibus, spics; + enum ks899xm_cfg_vlan vlancfg; +}; + +int ks899xm_switch_initialize(const struct ks899xm_config *swconfig); + +#endif /* CONFIG_KS899XM_SWITCH */ + #endif /* _NETDEV_H_ */ -- 1.6.0.4

1 0

[U-Boot] ARM preprocessor error generating assembly dependencies
by Dirk Behme 01 Sep '09

01 Sep '09

Hi, for ARM I'm including include/asm-arm/assembler.h in an assembly file. Doing this, I get preprocessor error message include/asm/assembler.h:17:2: error: #error "Only include this from assembly code" This is due to __ASSEMBLY__ not defined, but It seems to me that this message comes from *dependency* generation, not from compilation. For compilation, -D__ASSEMBLY__ is set and it compiles fine. Doing #define __ASSEMBLY__ #include <asm/assembler.h> in assembly file fixes the error while generating dependencies, but results in __ASSEMBLY__ redefined message while compilation. Any expert here could have look to which options are taken for ARM's assembly dependency generation? It seems to me that -D__ASSEMBLY__ is missing there? Many thanks and best regards Dirk

2 8

[U-Boot] [PATCH] Add common code dir for Matrix Vision boards.
by Andre Schwarz 01 Sep '09

01 Sep '09

This fixes current build failure. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- board/matrix_vision/common/Makefile | 54 ++++++++++++++ board/matrix_vision/common/mv_common.c | 126 ++++++++++++++++++++++++++++++++ board/matrix_vision/common/mv_common.h | 25 ++++++ 3 files changed, 205 insertions(+), 0 deletions(-) create mode 100644 board/matrix_vision/common/Makefile create mode 100644 board/matrix_vision/common/mv_common.c create mode 100644 board/matrix_vision/common/mv_common.h diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile new file mode 100644 index 0000000..b496258 --- /dev/null +++ b/board/matrix_vision/common/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-y = mv_common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c new file mode 100644 index 0000000..ed23e56 --- /dev/null +++ b/board/matrix_vision/common/mv_common.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz(a)matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <environment.h> +#include <fpga.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +static char* entries_to_keep[] = { + "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt", + "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr", + "static_ipaddr", "static_netmask", "static_gateway", + "syslog", "watchdog", "netboot", "evo8serialnumber" }; + +#define MV_MAX_ENV_ENTRY_LENGTH 64 +#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) + +void mv_reset_environment(void) +{ + int i; + char *s[MV_KEEP_ENTRIES]; + char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH]; + + printf("\n*** RESET ENVIRONMENT ***\n"); + + memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH); + for (i = 0; i < MV_KEEP_ENTRIES; i++) { + s[i] = getenv(entries_to_keep[i]); + if (s[i]) { + printf("save '%s' : %s\n", entries_to_keep[i], s[i]); + strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH); + } + } + + gd->env_valid = 0; + env_relocate(); + + for (i = 0; i < MV_KEEP_ENTRIES; i++) { + if (s[i]) { + printf("restore '%s' : %s\n", entries_to_keep[i], s[i]); + setenv(entries_to_keep[i], s[i]); + } + } + + saveenv(); +} + +int mv_load_fpga(void) +{ + int result; + size_t data_size = 0; + void *fpga_data = NULL; + char *datastr = getenv("fpgadata"); + char *sizestr = getenv("fpgadatasize"); + + if (getenv("skip_fpga")) { + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); + return -1; + } + printf("loading FPGA\n"); + + if (datastr) + fpga_data = (void *)simple_strtoul(datastr, NULL, 16); + if (sizestr) + data_size = (size_t)simple_strtoul(sizestr, NULL, 16); + if (!data_size) { + printf("fpgadatasize invalid -> FPGA _not_ loaded !\n"); + return -1; + } + + result = fpga_load(0, fpga_data, data_size); + if (!result) + show_boot_progress(0); + + return result; +} + +u8 *dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + if ((ptr = getenv("dhcp_vendor-class-identifier"))) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv("dhcp_client_id"))) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} diff --git a/board/matrix_vision/common/mv_common.h b/board/matrix_vision/common/mv_common.h new file mode 100644 index 0000000..046c038 --- /dev/null +++ b/board/matrix_vision/common/mv_common.h @@ -0,0 +1,25 @@ +/* + * Copyright 2008 Matrix Vision GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +extern int mv_load_fpga(void); +extern void mv_reset_environment(void); -- 1.6.0.4 MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

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[U-Boot] [PATCH] fix broken matrix vision boards
by Andre Schwarz 01 Sep '09

01 Sep '09

boards are currently broken due to missing common dir inside board dir. MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

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