September 2009 - U-Boot

[U-Boot] [PATCH] Support for the Calao TNY-A9260 board
by Albin Tonnerre 01 Sep '09

01 Sep '09

The Calao TNY-A9260 board is a board manufactured and sold by Calao Systems <http://www.calao-systems.com>. Its components are very similar to the AT91SAM9260EK board, so its configuration is based on the configuration of this board. There are however some differences: different clocks, no LCD, no ethernet. It also uses SPI EEPROM to store the environment. The SPI chip is a STM95080, and as it's used in a number of CALAO boards which should be supported soon, the corresponding spi_read and spi_write functions have been put in drivers/spi/eeprom_m95xxx.c --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 12 +++ board/calao/tny_a9260/Makefile | 55 ++++++++++ board/calao/tny_a9260/config.mk | 1 + board/calao/tny_a9260/spi.c | 49 +++++++++ board/calao/tny_a9260/tny_a9260.c | 102 +++++++++++++++++++ cpu/arm926ejs/at91/at91sam9260_devices.c | 2 +- drivers/spi/Makefile | 1 + drivers/spi/eeprom_m95xxx.c | 114 +++++++++++++++++++++ include/configs/tny_a9260.h | 158 ++++++++++++++++++++++++++++++ 11 files changed, 498 insertions(+), 1 deletions(-) create mode 100644 board/calao/tny_a9260/Makefile create mode 100644 board/calao/tny_a9260/config.mk create mode 100644 board/calao/tny_a9260/spi.c create mode 100644 board/calao/tny_a9260/tny_a9260.c create mode 100644 drivers/spi/eeprom_m95xxx.c create mode 100644 include/configs/tny_a9260.h diff --git a/MAINTAINERS b/MAINTAINERS index 575a7ec..1ba1921 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,6 +624,10 @@ Peter Pearse <peter.pearse(a)arm.com> versatile ARM926EJ-S versatile ARM926EJ-S +Albin Tonnerre <albin.tonnerre(a)free-electrons.com> + + tny_a9260 ARM926EJS (AT91SAM9260 SoC) + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/MAKEALL b/MAKEALL index 020ff73..59b65d2 100755 --- a/MAKEALL +++ b/MAKEALL @@ -599,6 +599,7 @@ LIST_at91=" \ m501sk \ pm9261 \ pm9263 \ + tny_a9260 \ " ######################################################################### diff --git a/Makefile b/Makefile index 25a6254..d05abd9 100644 --- a/Makefile +++ b/Makefile @@ -2807,6 +2807,18 @@ at91sam9g45ekes_config : unconfig pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 +tny_a9260_nandflash_config \ +tny_a9260_eeprom_config \ +tny_a9260_config : unconfig + @if [ "$(findstring _nandflash,$@)" ] ; then \ + $(XECHO) "#define CONFIG_ENV_IS_IN_NAND" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in NAND FLASH" ; \ + else \ + $(XECHO) "#define CONFIG_ENV_IS_IN_EEPROM" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI EEPROM CS1" ; \ + fi; + @$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91 + ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile new file mode 100644 index 0000000..21f5ed1 --- /dev/null +++ b/board/calao/tny_a9260/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += tny_a9260.o +COBJS-$(CONFIG_ATMEL_SPI) += spi.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/calao/tny_a9260/config.mk b/board/calao/tny_a9260/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/calao/tny_a9260/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/calao/tny_a9260/spi.c b/board/calao/tny_a9260/spi.c new file mode 100644 index 0000000..e02955f --- /dev/null +++ b/board/calao/tny_a9260/spi.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2009 Albin Tonnerre <albin.tonnerre(a)free-electrons.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <spi.h> + +#define TNY_A9260_CS_PIN AT91_PIN_PC11 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + at91_set_gpio_value(TNY_A9260_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + at91_set_gpio_value(TNY_A9260_CS_PIN, 1); +} + +void spi_init_f(void) +{ + /* everything done in board_init */ +} diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c new file mode 100644 index 0000000..cedcdbd --- /dev/null +++ b/board/calao/tny_a9260/tny_a9260.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Copyright (C) 2009 Albin Tonnerre <albin.tonnerre(a)free-electrons.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void tny_a9260_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_TNY_A9260; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); + tny_a9260_nand_hw_init(); + at91_spi0_hw_init(1 << 5 | 1 << 1); + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM, PHYS_SDRAM_SIZE); + return 0; +} diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index 5309ba2..f86cb99 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -75,7 +75,7 @@ void at91_serial_hw_init(void) #endif } -#ifdef CONFIG_HAS_DATAFLASH +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index a9f67a0..35c9e02 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o +COBJS-$(CONFIG_M95XXX_SPI) += eeprom_m95xxx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/eeprom_m95xxx.c b/drivers/spi/eeprom_m95xxx.c new file mode 100644 index 0000000..0b9f983 --- /dev/null +++ b/drivers/spi/eeprom_m95xxx.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2009 Albin Tonnerre <albin.tonnerre(a)free-electrons.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> + +#define SPI_EEPROM_WREN 0x06 +#define SPI_EEPROM_RDSR 0x05 +#define SPI_EEPROM_READ 0x03 +#define SPI_EEPROM_WRITE 0x02 + +#ifndef CONFIG_DEFAULT_SPI_BUS +#define CONFIG_DEFAULT_SPI_BUS 0 +#endif + +#ifndef CONFIG_DEFAULT_SPI_MODE +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 +#endif + +ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) +{ + struct spi_slave *slave; + u8 cmd = SPI_EEPROM_READ; + + slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, + CONFIG_DEFAULT_SPI_MODE); + spi_claim_bus(slave); + + /* command */ + if(spi_xfer(slave, 8, &cmd, NULL, SPI_XFER_BEGIN)) + return -1; + + /* if alen == 3, addr[0] is the block number, we never use it here. All we + * need are the lower 16 bits*/ + if (alen == 3) + addr++; + + /* address, and data */ + if(spi_xfer(slave, 16, addr, NULL, 0)) + return -1; + if(spi_xfer(slave, 8*len, NULL, buffer, SPI_XFER_END)) + return -1; + + spi_release_bus(slave); + spi_free_slave(slave); + return len; +} + +ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len) +{ + struct spi_slave *slave; + int i; + char buf[3]; + + slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000, + CONFIG_DEFAULT_SPI_MODE); + spi_claim_bus(slave); + + buf[0] = SPI_EEPROM_WREN; + if(spi_xfer(slave, 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END)) + return -1; + + buf[0] = SPI_EEPROM_WRITE; + + /* As for reading, drop addr[0] if alen is 3 */ + if (alen == 3) { + alen--; + addr++; + } + + memcpy(buf+1, addr, alen); + /* command + addr, then data */ + if(spi_xfer(slave, 24, buf, NULL, SPI_XFER_BEGIN)) + return -1; + if(spi_xfer(slave, len*8, buffer, NULL, SPI_XFER_END)) + return -1; + + for (i = 0; i < 1000; i++) { + buf[0] = SPI_EEPROM_RDSR; + buf[1] = 0; + spi_xfer(slave, 16, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END); + + if (!(buf[1] & 1)) { + break; + } + udelay(1000); + } + if (i >= 1000) { + printf ("*** spi_write: Time out while writing!\n"); + } + + spi_release_bus(slave); + spi_free_slave(slave); + return len; +} diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h new file mode 100644 index 0000000..1dcbb97 --- /dev/null +++ b/include/configs/tny_a9260.h @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Copyright (C) 2009 Albin Tonnerre <albin.tonnerre(a)free-electrons.com> + * + * Configuation settings for the Calao TNY-A9260 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ + +#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_USB + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_ATMEL_SPI +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define AT91_SPI_CLK 15000000 + +#define CONFIG_CMD_EEPROM +#define CONFIG_M95XXX_SPI +#define CONFIG_SYS_EEPROM_SIZE 0x10000 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 + +/* NAND flash */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 + +/* NOR flash - no real flash on this board */ +#define CONFIG_SYS_NO_FLASH 1 + +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* Env in EEPROM, bootstrap + u-boot in NAND*/ +#ifdef CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_OFFSET 0x20 +#define CONFIG_ENV_SIZE 0x1000 +#endif + +/* Env, bootstrap and u-boot in NAND */ +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=atmel_nand:16M(kernel)ro," \ + "120M(rootfs),-(other) " \ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- 1.6.0.4

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[U-Boot] [PATCH v3] arm: Kirkwood: add SYSRSTn Duration Counter Support
by Prafulla Wadaskar 01 Sep '09

01 Sep '09

This feature can be used to trigger special command "sysrstcmd" using reset key long press event and environment variable "sysrstdelay" is set (useful for reset to factory or manufacturing mode execution) Kirkwood SoC implements a hardware-based SYSRSTn duration counter. When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter value is stored in the SYSRSTn Length Counter Register The counter is based on the 25-MHz reference clock (40ns) It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, it remains at this value until counter reset is triggered by setting bit 31 of KW_REG_SYSRST_CNT Implementation: Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be executed if pre-defined in environment variables. This feature will be disabled if "sysrstdelay" variable is unset. for-ex. setenv sysrst_cmd "echo starting factory reset; nand erase 0xa0000 0x20000; echo finish ed sysrst command;" will erase particular nand sector if triggered by this event Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log: v2: updated as per review feedback for v1 bug fix in the previous post (V2) fixed v2 repost: I am sorry for previous post v2, pls ignore it, this is the right patch for the same v3: updated as per review feedback for v2 all possible messages termed as debug cpu/arm926ejs/kirkwood/cpu.c | 75 +++++++++++++++++++++++++++++++++++ include/asm-arm/arch-kirkwood/cpu.h | 2 + 2 files changed, 77 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c index 795a739..3b978e2 100644 --- a/cpu/arm926ejs/kirkwood/cpu.c +++ b/cpu/arm926ejs/kirkwood/cpu.c @@ -195,6 +195,78 @@ int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31, return 0; } +/* + * SYSRSTn Duration Counter Support + * + * Kirkwood SoC implements a hardware-based SYSRSTn duration counter. + * When SYSRSTn is asserted low, a SYSRSTn duration counter is running. + * The SYSRSTn duration counter is useful for implementing a manufacturer + * or factory reset. Upon a long reset assertion that is greater than a + * pre-configured environment variable value for sysrstdelay, + * The counter value is stored in the SYSRSTn Length Counter Register + * The counter is based on the 25-MHz reference clock (40ns) + * It is a 29-bit counter, yielding a maximum counting duration of + * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, + * it remains at this value until counter reset is triggered by setting + * bit 31 of KW_REG_SYSRST_CNT + */ +static void kw_sysrst_action(void) +{ + int ret; + char *s = getenv("sysrstcmd"); + + if (!s) { + debug("Error.. %s failed, check sysrstcmd\n", + __FUNCTION__); + return; + } + + debug("Starting %s process...\n", __FUNCTION__); +#if !defined(CONFIG_SYS_HUSH_PARSER) + ret = run_command (s, 0); +#else + ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON + | FLAG_EXIT_FROM_LOOP); +#endif + if (ret < 0) + debug("Error.. %s failed\n", __FUNCTION__); + else + debug("%s process finished\n", __FUNCTION__); +} + +static void kw_sysrst_check(void) +{ + u32 sysrst_cnt, sysrst_dly; + char *s; + + /* + * no action if sysrstdelay environment variable is not defined + */ + s = getenv("sysrstdelay"); + if (s == NULL) + return; + + /* read sysrstdelay value */ + sysrst_dly = (u32) simple_strtoul(s, NULL, 10); + + /* read SysRst Length counter register (bits 28:0) */ + sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT)); + debug("H/w Rst hold time: %d.%d secs\n", + sysrst_cnt / SYSRST_CNT_1SEC_VAL, + sysrst_cnt % SYSRST_CNT_1SEC_VAL); + + /* clear the counter for next valid read*/ + writel(1 << 31, KW_REG_SYSRST_CNT); + + /* + * sysrst_action: + * if H/w Reset key is pressed and hold for time + * more than sysrst_dly in seconds + */ + if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly) + kw_sysrst_action(); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -298,6 +370,9 @@ int arch_misc_init(void) temp = get_cr(); set_cr(temp & ~CR_V); + /* checks and execute resset to factory event */ + kw_sysrst_check(); + return 0; } #endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/include/asm-arm/arch-kirkwood/cpu.h b/include/asm-arm/arch-kirkwood/cpu.h index d1440af..b3022a3 100644 --- a/include/asm-arm/arch-kirkwood/cpu.h +++ b/include/asm-arm/arch-kirkwood/cpu.h @@ -36,6 +36,8 @@ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) +#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) +#define SYSRST_CNT_1SEC_VAL (25*1000000) #define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) enum memory_bank { -- 1.5.3.3

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[U-Boot] [PATCH 0/7][v3] Support for LogicPD i.MX27-LITEKIT development board
by Ilya Yanok 01 Sep '09

01 Sep '09

This patch set adds support for LogicPD i.MX27-LITEKIT development board. It contains support for i.MX27 CPU, support for serial console, FEC ethernet controller, NFC NAND controller and SDHC controller. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com>

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Re: [U-Boot] [PATCH 2/2] MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST
by John Rigby 01 Sep '09

01 Sep '09

Sorry for the late comments. We have been trying to use this code with the associated davinci 4-bit ecc patches and have some questions (inline). ..... > + uint8_t *ecc_code = chip->buffers->ecccode; > + uint32_t *eccpos = chip->ecc.layout->eccpos; > + uint8_t *ecc_calc = chip->buffers->ecccalc; > + > + /* Read the OOB area first */ > + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); > What about chips that do not support the NAND_CMD_READOOB? Do I need to provide my own read routine for that case? + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); > + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); > + > + for (i = 0; i < chip->ecc.total; i++) > + ecc_code[i] = chip->oob_poi[eccpos[i]]; > + > + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { > + int stat; > + > + chip->ecc.hwctl(mtd, NAND_ECC_READ); > + chip->read_buf(mtd, p, eccsize); > + chip->ecc.calculate(mtd, p, &ecc_calc[i]); > Here you calculate ecc then never use the result? + > + stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); > + if (stat < 0) > + mtd->ecc_stats.failed++; > + else > + mtd->ecc_stats.corrected += stat; > + } > + return 0; > +} > + >

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[U-Boot] Large Block USB Flash Drive Problem
by Barnes, Clifton A. 01 Sep '09

01 Sep '09

I have been trying out loading the Linux kernel using a USB flash drive in the u-boot-2009.06-rc2 release and ran into a problem with one of my flash drives. This particular drive has a block size of 2048 while the other drives have block sizes of 512. The drives with a block size of 512 work perfectly. However, the flash drive with a block size of 2048 fails during the 'usb start' command. I traced this issue to the Part_dos.c file and the function test_part_dos. The buffer allocated there is only 512 bytes. When I changed it to 2048, the 'usb start' command worked correctly and found the one storage device connected. This had no adverse affect with the flash drives that were 512 bytes. Should the macro DEFAULT_SECTOR_SIZE be changed to accommodate larger block size usb flash drives? The second problem came when I tried to use the FAT utilities. When I ran 'fatls usb 0', it failed the same way as when the 'usb start' failed before. Naturally, I guessed that it was a buffer size problem again. I was able to trace the issue to the macro SECTOR_SIZE in fat.h. I tried changing it to 2048, however, there is a check right below it that fails if SECTOR_SIZE != FS_BLOCK_SIZE. So, I assume that the support isn't written to handle sector sizes that are different than the FAT block size. However, I went ahead and changed them both to 2048. This fixed the issues with the FAT utilities partly. I was able to run 'fatls usb 0' and it listed the files but also some junk. I'm guessing it was grabbing junk after the files since the block size is too big. I was also able to run 'fatload usb 0 0x22000000 uImage' successfully and boot the kernel successfully. So, I think the fix has to be in the SECTOR_SIZE macro in the fat.h file. Can anyone with expertise in the FAT implementation take a look at supporting different sector sizes for larger block size flash drives? I can send a large block flash drive to someone if they're willing to take a look at this issue and they don't have one of these drives. Thanks, Clifton A Barnes INDesign, LLC cabarnes(a)indesign-llc.com

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[U-Boot] API License Terms
by Daniel Sherwood 01 Sep '09

01 Sep '09

Hi Please can someone clarify the following points regarding the 'Consumer API' which we wish to use to access the environment from the core application of a commercial closed source product. 1) Is it true that the so called 'consumer application' can use this API and remain closed source - if so, where in the license information is this made clear? 2) Who has agreed (or has to agree) that this is acceptable use? It's all very well Rafal adding the code and a 'public' header file with a BSD license - but surely all of the authors that have contributed to code accessed through this API would have to consent to these terms. 3) If presume that we cannot use the GPLv2 glue files in a closed source application. We need to understand these points before we can proceed with code that interacts with this API. Also, following on from these points, how would we go about extending the API? Specifically, we would like to add a saveenv function to the API - is it legitimate for us to simply extend the API to add this functionality - provided we publish our changes to u-boot as per the GPL - without compromising our core application code as closed source? Cheers Daniel Sherwood Software Engineer Sepura PLC Radio House, St Andrew's Road Cambridge, CB4 1GR, UK T: +44 (0) 1223 694637 F: +44 (0) 1223 879000 www.sepura.com <http://www.sepura.com> The information in this email is confidential. It is intended solely for the addressee. Access to this email by anyone else is unauthorised. If you are not the intended recipient, any disclosure, copying, or distribution is prohibited and may be unlawful. If you have received this email in error please delete it immediately and contact commercial(a)sepura.com. Sepura plc. Registered Office: Radio House, St Andrew’s Road, Cambridge, CB4 1GR, England. Registered in England and Wales. Registration Number 4353801

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Re: [U-Boot] API License Terms
by Daniel Sherwood 01 Sep '09

01 Sep '09

Wolfgang > > Please can someone clarify the following points regarding the 'Consumer > > API' which we wish to use to access the environment from the core > > application of a commercial closed source product. > > There is no such thing as a "consumer API". > > > 1) Is it true that the so called 'consumer application' can use > > this API and remain closed source - if so, where in the license > > information is this made clear? > > I guess you might be referring to standalone applications here. And > the licensing for these is described right at the beginning of the > license file "COPYING". [Daniel Sherwood] No, I am referring to the code contributed by Rafel under api/* and examples/api/* (although these directories may have been renamed more recently). > The API code implemented by Rafal (abi/* and examples/abi/*) is *not* > part of the exception for standalone programs; instead, it is > licensed under GPL. The source code makes this pretty clear. [Daniel Sherwood] The include/api_public.h header file is clearly dual licensed as GPLv2/BSD implying that it can be used as a public API from non-GPL code - indeed I believe there are examples around of this being accessed from BSD. Surely this is already effectively an exception (as BSD is not released under GPLv2 but can link with this API). > Of course you can always reconsider and release your code under GPL - > that would be the most natural thing given the fact that you are > taking man-years worth of source code for free. [Daniel Sherwood] We will be releasing the changes and improvements we have made to u-Boot itself as part of our project (the main one being support for digital signature checking in the boot code), however we are not in a position to release our core application - the only link we have with u-Boot code is that we also wish to access the environment variables. If we have no other option, we will write clean versions of getenv, setenv and saveenv for our application. > > Also, following on from these points, how would we go about extending > > the API? Specifically, we would like to add a saveenv function to the > > API - is it legitimate for us to simply extend the API to add this > > functionality - provided we publish our changes to u-boot as per the GPL > > - without compromising our core application code as closed source? > > Most probably you will need to include header files in addition to > those explicitly allowed in the "COPYING" file. This would require > you to release your code under GPL. Indeed, we would need to include api_public.h (which we can do under the BSD license), therefore it becomes an issue of a) the legitimacy of locating and calling the syscall function from our application and b) extending the available syscall within u-Boot (which of course would be released under our GPL obligations). Cheers Daniel The information in this email is confidential. It is intended solely for the addressee. Access to this email by anyone else is unauthorised. If you are not the intended recipient, any disclosure, copying, or distribution is prohibited and may be unlawful. If you have received this email in error please delete it immediately and contact commercial(a)sepura.com. Sepura plc. Registered Office: Radio House, St Andrew’s Road, Cambridge, CB4 1GR, England. Registered in England and Wales. Registration Number 4353801

1 0

Re: [U-Boot] [PATCH 2/2] MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST
by John Rigby 01 Sep '09

01 Sep '09

Thanks for the info. On Tue, Sep 1, 2009 at 10:33 AM, Paulraj, Sandeep <s-paulraj(a)ti.com> wrote: > This patch is fine. > > I'll send an updated NAND Davinci driver patch soon which adds to what is > already there. I have made a mistake and testing did not show it. > > Have you noticed that not all e-mails reach the mailing list in the correct > order? This is true for the conversation you two were having. > > Thanks, > Sandeep > > > -----Original Message----- > > From: Paulraj, Sandeep > > Sent: Tuesday, September 01, 2009 12:04 PM > > To: Scott Wood; John Rigby > > Cc: u-boot(a)lists.denx.de; Paulraj, Sandeep; Narnakaje, Snehaprabha > > Subject: RE: [U-Boot] [PATCH 2/2] MTD:NAND: ADD new ECC mode > > NAND_ECC_HW_OOB_FIRST > > > > > > > John Rigby wrote: > > > > Sorry for the late comments. We have been trying to use this code > > with > > > > the associated davinci 4-bit ecc patches and have some questions > > We use this internally and it works. Are you having any issues because we > > don't see any!! > > J-C has to apply a patch and you will need that for this to work > properly. > > That patch updates the DM355 Config > > > (inline). > > > > > > > > ..... > > > > + uint8_t *ecc_code = chip->buffers->ecccode; > > > > + uint32_t *eccpos = chip->ecc.layout->eccpos; > > > > + uint8_t *ecc_calc = chip->buffers->ecccalc; > > > > + > > > > + /* Read the OOB area first */ > > > > + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); > > > > > > > > > > > > What about chips that do not support the NAND_CMD_READOOB? Do I > need > > > > to provide my own read routine for that case? > > > > > > cmdfunc is supposed to fix that up. This is already the case with > > > existing code. > > > > > > > + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); > > > > + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); > > > > + > > > > + for (i = 0; i < chip->ecc.total; i++) > > > > + ecc_code[i] = chip->oob_poi[eccpos[i]]; > > > > + > > > > + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += > > > eccsize) { > > > > + int stat; > > > > + > > > > + chip->ecc.hwctl(mtd, NAND_ECC_READ); > > > > + chip->read_buf(mtd, p, eccsize); > > > > + chip->ecc.calculate(mtd, p, &ecc_calc[i]); > > > > > > > > > > > > Here you calculate ecc then never use the result? > > > > > > Hmm, that looks wrong, both here and in the davinci driver. Are the > two > > > calls to nand_davinci_4bit_readecc reading different things? Does the > > > calculate function have any side effects beyond producing data that is > > > never used? > > Have you reads the patch description. Maybe that might help a bit > > > > This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to > > support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND > > chips. This ECC mode is similar to NAND_ECC_HW, with the exception of > > read_page API that first reads the OOB area, reads the data in chunks, > > feeds the ECC from OOB area to the ECC hw engine and perform any > > correction on the data as per the ECC status reported by the engine. > > > > > > > > -Scott > > > _______________________________________________ > > > U-Boot mailing list > > > U-Boot(a)lists.denx.de > > > http://lists.denx.de/mailman/listinfo/u-boot > >

1 0

[U-Boot] Obtaining board specific phy diagnostics
by Matthew Lear 01 Sep '09

01 Sep '09

Hi all, Is there a common mechanism to hook in board specific ethernet phy commands? For example, I'd like to hook in the ability to read the TDR characteristics of the ethernet cable connected to my board. I know the phy on my board supports this so I was planning on hooking it into the mii command set somehow. Currently, the ethernet set up code registers phy read and write routines, but that is all. Is there a recognised method / approach to add such board specific commands/features into an existing 'common' command? Cheers, -- Matt

1 1

[U-Boot] [PATCH v6 2/2] arm: A320: Add support for Faraday A320 evaluation board
by ratbert.chuang＠gmail.com 01 Sep '09

01 Sep '09

From: Po-Yu Chuang <ratbert(a)faraday-tech.com> This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/faraday/a320evb/Makefile | 51 ++++++++ board/faraday/a320evb/a320evb.c | 73 +++++++++++ board/faraday/a320evb/config.mk | 35 +++++ board/faraday/a320evb/lowlevel_init.S | 118 +++++++++++++++++ cpu/arm920t/a320/Makefile | 47 +++++++ cpu/arm920t/a320/ftsmc020.c | 51 ++++++++ cpu/arm920t/a320/reset.S | 22 ++++ cpu/arm920t/a320/timer.c | 193 ++++++++++++++++++++++++++++ include/asm-arm/arch-a320/a320.h | 35 +++++ include/asm-arm/arch-a320/ftpmu010.h | 190 ++++++++++++++++++++++++++++ include/asm-arm/arch-a320/ftsdmc020.h | 103 +++++++++++++++ include/asm-arm/arch-a320/ftsmc020.h | 79 ++++++++++++ include/asm-arm/arch-a320/fttmr010.h | 73 +++++++++++ include/configs/a320evb.h | 222 +++++++++++++++++++++++++++++++++ 17 files changed, 1300 insertions(+), 0 deletions(-) create mode 100644 board/faraday/a320evb/Makefile create mode 100644 board/faraday/a320evb/a320evb.c create mode 100644 board/faraday/a320evb/config.mk create mode 100644 board/faraday/a320evb/lowlevel_init.S create mode 100644 cpu/arm920t/a320/Makefile create mode 100644 cpu/arm920t/a320/ftsmc020.c create mode 100644 cpu/arm920t/a320/reset.S create mode 100644 cpu/arm920t/a320/timer.c create mode 100644 include/asm-arm/arch-a320/a320.h create mode 100644 include/asm-arm/arch-a320/ftpmu010.h create mode 100644 include/asm-arm/arch-a320/ftsdmc020.h create mode 100644 include/asm-arm/arch-a320/ftsmc020.h create mode 100644 include/asm-arm/arch-a320/fttmr010.h create mode 100644 include/configs/a320evb.h diff --git a/MAINTAINERS b/MAINTAINERS index 79873f3..aa54bdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -533,6 +533,10 @@ Rick Bronson <rick(a)efn.org> AT91RM9200DK at91rm9200 +Po-Yu Chuang <ratbert(a)faraday-tech.com> + + a320evb FA526 (ARM920T-like) (a320 SoC) + George G. Davis <gdavis(a)mvista.com> assabet SA1100 diff --git a/MAKEALL b/MAKEALL index 5882ceb..7c742b6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -505,6 +505,7 @@ LIST_ARM7=" \ ######################################################################### LIST_ARM9=" \ + a320evb \ ap920t \ ap922_XA10 \ ap926ejs \ diff --git a/Makefile b/Makefile index c9d315a..a3fb0b8 100644 --- a/Makefile +++ b/Makefile @@ -2661,6 +2661,9 @@ shannon_config : unconfig ## ARM92xT Systems ######################################################################### +a320evb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320 + ######################################################################### ## Atmel AT91RM9200 Systems ######################################################################### diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile new file mode 100644 index 0000000..74f660d --- /dev/null +++ b/board/faraday/a320evb/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := a320evb.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c new file mode 100644 index 0000000..2aaa7a7 --- /dev/null +++ b/board/faraday/a320evb/a320evb.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <asm/arch/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + ftsmc020_init (); /* initialize Flash */ + return 0; +} + +int dram_init (void) +{ + void *sdram_base = PHYS_SDRAM_1; + unsigned long expected_size = PHYS_SDRAM_1_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size(sdram_base, expected_size); + + gd->bd->bi_dram[0].start = sdram_base; + gd->bd->bi_dram[0].size = actual_size; + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return 0; +} + +int board_eth_init (bd_t *bd) +{ + return ftmac100_initialize (bd); +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/faraday/a320evb/config.mk b/board/faraday/a320evb/config.mk new file mode 100644 index 0000000..aa25b98 --- /dev/null +++ b/board/faraday/a320evb/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2009 Faraday Technology +# Po-Yu Chuang <ratbert(a)faraday-tech.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information + +# A320 has 1 bank of 64 MB DRAM +# +# 1000'0000 to 1400'0000 +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# +# we load ourself to 13f8'0000 +# +# download area is 1200'0000 + +TEXT_BASE = 0x13f80000 diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S new file mode 100644 index 0000000..97718c0 --- /dev/null +++ b/board/faraday/a320evb/lowlevel_init.S @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <version.h> + +#include <asm/macro.h> +#include <asm/arch/ftsdmc020.h> + +/* + * parameters for the SDRAM controller + */ +#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0) +#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1) +#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR) +#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR) +#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR) + +#define TP0_D CONFIG_SYS_FTSDMC020_TP0 +#define TP1_D CONFIG_SYS_FTSDMC020_TP1 +#define CR_D1 FTSDMC020_CR_IPREC +#define CR_D2 FTSDMC020_CR_ISMR +#define CR_D3 FTSDMC020_CR_IREF + +#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(PHYS_SDRAM_1)) +#define ACR_D FTSDMC020_ACR_TOC(0x18) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + ldr r0, =CONFIG_FTSDMC020_BASE +1: + ldr r1, [r0, #FTSDMC020_OFFSET_CR] + cmp r1, #0 + bne 1b +.endm + +.globl lowlevel_init +lowlevel_init: + mov r11, lr + + led 0x0 + + bl init_sdmc + + led 0x1 + + /* everything is fine now */ + mov lr, r11 + mov pc, lr + +/* + * memory initialization + */ +init_sdmc: + led 0x10 + + /* set SDRAM register */ + + write32 TP0_A, TP0_D + led 0x11 + + write32 TP1_A, TP1_D + led 0x12 + + /* set to precharge */ + write32 CR_A, CR_D1 + led 0x13 + + wait_sdram + led 0x14 + + /* set mode register */ + write32 CR_A, CR_D2 + led 0x15 + + wait_sdram + led 0x16 + + /* set to refresh */ + write32 CR_A, CR_D3 + led 0x17 + + wait_sdram + led 0x18 + + write32 B0_BSR_A, B0_BSR_D + led 0x19 + + write32 ACR_A, ACR_D + led 0x1a + + mov pc, lr diff --git a/cpu/arm920t/a320/Makefile b/cpu/arm920t/a320/Makefile new file mode 100644 index 0000000..f030c53 --- /dev/null +++ b/cpu/arm920t/a320/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS += reset.o +COBJS += timer.o +COBJS += ftsmc020.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/a320/ftsmc020.c b/cpu/arm920t/a320/ftsmc020.c new file mode 100644 index 0000000..3d00fa8 --- /dev/null +++ b/cpu/arm920t/a320/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftsmc020.h> + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; + +static void ftsmc020_setup_bank (unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf ("bank # %u invalid\n", bank); + return; + } + + writel (cfg->config, &smc->bank[bank].cr); + writel (cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init (void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE (config); i++) + ftsmc020_setup_bank (i, &config[i]); +} diff --git a/cpu/arm920t/a320/reset.S b/cpu/arm920t/a320/reset.S new file mode 100644 index 0000000..12ca527 --- /dev/null +++ b/cpu/arm920t/a320/reset.S @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +.global reset_cpu +reset_cpu: + b reset_cpu diff --git a/cpu/arm920t/a320/timer.c b/cpu/arm920t/a320/timer.c new file mode 100644 index 0000000..bc134b6 --- /dev/null +++ b/cpu/arm920t/a320/timer.c @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftpmu010.h> +#include <asm/arch/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + +#define TIMER_CLOCK 32768 +#define TIMER_LOAD_VAL 0xffffffff + +int timer_init (void) +{ + unsigned int oscc; + unsigned int cr; + + debug ("%s()\n", __func__); + + /* disable timers */ + writel (0, &tmr->cr); + + /* + * use 32768Hz oscillator for RTC, WDT, TIMER + */ + + /* enable the 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel (oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl (&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc |= FTPMU010_OSCC_RTCLSEL; + writel (oscc, &pmu->OSCC); + + /* setup timer */ + writel (TIMER_LOAD_VAL, &tmr->timer3_load); + writel (TIMER_LOAD_VAL, &tmr->timer3_counter); + writel (0, &tmr->timer3_match1); + writel (0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel (FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl (&tmr->cr); + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ + cr |= FTTMR010_TM3_ENABLE; + writel (cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked (); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked (void) +{ + /* capure current decrementer value time */ + lastdec = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug ("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer (void) +{ + debug ("%s()\n", __func__); + reset_timer_masked (); +} + +/* + * return timer ticks + */ +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + debug ("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug ("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer (ulong base) +{ + debug ("%s(%lx)\n", __func__, base); + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + debug ("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&tmr->timer3_counter); + + debug ("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks (void) +{ + debug ("%s()\n", __func__); + return get_timer (0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + debug ("%s()\n", __func__); + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h new file mode 100644 index 0000000..5c0a097 --- /dev/null +++ b/include/asm-arm/arch-a320/a320.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __A320_H +#define __A320_H + +/* + * Hardware register bases + */ +#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ +#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ +#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ +#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ +#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ +#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ +#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ + +#endif /* __A320_H */ + diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h new file mode 100644 index 0000000..7044131 --- /dev/null +++ b/include/asm-arm/arch-a320/ftpmu010.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#define FTPMU010_OFFSET_IDNMBR0 0x00 +#define FTPMU010_OFFSET_OSCC 0x08 +#define FTPMU010_OFFSET_PMODE 0x0C +#define FTPMU010_OFFSET_PMCR 0x10 +#define FTPMU010_OFFSET_PED 0x14 +#define FTPMU010_OFFSET_PEDSR 0x18 +#define FTPMU010_OFFSET_PMSR 0x20 +#define FTPMU010_OFFSET_PGSR 0x24 +#define FTPMU010_OFFSET_MFPSR 0x28 +#define FTPMU010_OFFSET_MISC 0x2C +#define FTPMU010_OFFSET_PDLLCR0 0x30 +#define FTPMU010_OFFSET_PDLLCR1 0x34 +#define FTPMU010_OFFSET_AHBMCLKOFF 0x38 +#define FTPMU010_OFFSET_APBMCLKOFF 0x3C +#define FTPMU010_OFFSET_DCSRCR0 0x40 +#define FTPMU010_OFFSET_DCSRCR1 0x44 +#define FTPMU010_OFFSET_DCSRCR2 0x48 +#define FTPMU010_OFFSET_SDRAMHTC 0x4C +#define FTPMU010_OFFSET_PSPR0 0x50 +#define FTPMU010_OFFSET_PSPR1 0x54 +#define FTPMU010_OFFSET_PSPR2 0x58 +#define FTPMU010_OFFSET_PSPR3 0x5C +#define FTPMU010_OFFSET_PSPR4 0x60 +#define FTPMU010_OFFSET_PSPR5 0x64 +#define FTPMU010_OFFSET_PSPR6 0x68 +#define FTPMU010_OFFSET_PSPR7 0x6C +#define FTPMU010_OFFSET_PSPR8 0x70 +#define FTPMU010_OFFSET_PSPR9 0x74 +#define FTPMU010_OFFSET_PSPR10 0x78 +#define FTPMU010_OFFSET_PSPR11 0x7C +#define FTPMU010_OFFSET_PSPR12 0x80 +#define FTPMU010_OFFSET_PSPR13 0x84 +#define FTPMU010_OFFSET_PSPR14 0x88 +#define FTPMU010_OFFSET_PSPR15 0x8C +#define FTPMU010_OFFSET_AHBDMA_RACCS 0x90 +#define FTPMU010_OFFSET_JSS 0x9C +#define FTPMU010_OFFSET_CFC_RACC 0xA0 +#define FTPMU010_OFFSET_SSP1_RACC 0xA4 +#define FTPMU010_OFFSET_UART1TX_RACC 0xA8 +#define FTPMU010_OFFSET_UART1RX_RACC 0xAC +#define FTPMU010_OFFSET_UART2TX_RACC 0xB0 +#define FTPMU010_OFFSET_UART2RX_RACC 0xB4 +#define FTPMU010_OFFSET_SDC_RACC 0xB8 +#define FTPMU010_OFFSET_I2SAC97_RACC 0xBC +#define FTPMU010_OFFSET_IRDATX_RACC 0xC0 +#define FTPMU010_OFFSET_USBD_RACC 0xC8 +#define FTPMU010_OFFSET_IRDARX_RACC 0xCC +#define FTPMU010_OFFSET_IRDA_RACC 0xD0 +#define FTPMU010_OFFSET_ED0_RACC 0xD4 +#define FTPMU010_OFFSET_ED1_RACC 0xD8 + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_PLL1NS(x) (((x) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1NS_VALUEOF(reg) (((reg) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h new file mode 100644 index 0000000..0699772 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h new file mode 100644 index 0000000..43dfa61 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init (void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h new file mode 100644 index 0000000..72abcb3 --- /dev/null +++ b/include/asm-arm/arch-a320/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h new file mode 100644 index 0000000..fcc5563 --- /dev/null +++ b/include/configs/a320evb.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * Configuation settings for the Faraday A320 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/a320.h> + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ + +/*----------------------------------------------------------------------- + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x98200000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 18432000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x13F00000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include <asm/arch/ftsmc020.h> + +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_1M | \ + FTSMC020_BANK_MBW_8) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +/* support JEDEC */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + +#define PHYS_FLASH_1 0x00000000 +#define PHYS_FLASH_2 0x00400000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_EMPTY_INFO + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR 0x00060000 +#define CONFIG_ENV_SIZE 0x20000 + +#endif /* __CONFIG_H */ -- 1.6.3.3

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