September 2009 - U-Boot

[U-Boot] boot linux data aboot for S3C2440A
by fluke56512 04 Sep '09

04 Sep '09

what is wrong with me. [u-boot@S3C2440A]# nand read 0x30008000 0x00040000 0x00200000 NAND read: device 0 offset 0x40000, size 0x200000 2097152 bytes read: OK [u-boot@S3C2440A]# bootm 0x30008000 ## Booting kernel from Legacy Image at 30008000 ... Image Name: linux-2.6.30-5 Created: 2009-09-04 14:22:40 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1958132 Bytes = 1.9 MB Load Address: 30008000 Entry Point: 30008000 Verifying Checksum ... OK XIP Kernel Image ... OK OK Starting kernel ... data abort pc : [<30008008>] lr : [<33fa36b4>] sp : 33f4fcd0 ip : 33f4fce4 fp : 33f60a90 r10: 0000016a r9 : 00000002 r8 : 33f4ffdc r7 : 33f4ffb8 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 30008000 r2 : 30000100 r1 : 0000016a r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... 2009-09-04 fluke56512

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[U-Boot] [PATCH 1/4] s5pc1xx: support Samsung s5pc1xx SoC
by Minkyu Kang 04 Sep '09

04 Sep '09

This patch add support new SoCs that are s5pc100 and s5pc110 s5pc1xx SoC is ARM Cortex A8 processor Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> --- cpu/arm_cortexa8/s5pc1xx/Makefile | 53 ++++++ cpu/arm_cortexa8/s5pc1xx/cache.c | 43 +++++ cpu/arm_cortexa8/s5pc1xx/clock.c | 282 ++++++++++++++++++++++++++++++ cpu/arm_cortexa8/s5pc1xx/cpu_info.c | 71 ++++++++ cpu/arm_cortexa8/s5pc1xx/reset.S | 47 +++++ cpu/arm_cortexa8/s5pc1xx/timer.c | 200 +++++++++++++++++++++ include/asm-arm/arch-s5pc1xx/clk.h | 46 +++++ include/asm-arm/arch-s5pc1xx/clock.h | 79 +++++++++ include/asm-arm/arch-s5pc1xx/cpu.h | 73 ++++++++ include/asm-arm/arch-s5pc1xx/gpio.h | 127 ++++++++++++++ include/asm-arm/arch-s5pc1xx/hardware.h | 63 +++++++ include/asm-arm/arch-s5pc1xx/i2c.h | 43 +++++ include/asm-arm/arch-s5pc1xx/interrupt.h | 40 +++++ include/asm-arm/arch-s5pc1xx/keypad.h | 33 ++++ include/asm-arm/arch-s5pc1xx/mem.h | 58 ++++++ include/asm-arm/arch-s5pc1xx/power.h | 42 +++++ include/asm-arm/arch-s5pc1xx/pwm.h | 65 +++++++ include/asm-arm/arch-s5pc1xx/uart.h | 72 ++++++++ 18 files changed, 1437 insertions(+), 0 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc1xx/Makefile create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/clock.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/cpu_info.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/reset.S create mode 100644 cpu/arm_cortexa8/s5pc1xx/timer.c create mode 100644 include/asm-arm/arch-s5pc1xx/clk.h create mode 100644 include/asm-arm/arch-s5pc1xx/clock.h create mode 100644 include/asm-arm/arch-s5pc1xx/cpu.h create mode 100644 include/asm-arm/arch-s5pc1xx/gpio.h create mode 100644 include/asm-arm/arch-s5pc1xx/hardware.h create mode 100644 include/asm-arm/arch-s5pc1xx/i2c.h create mode 100644 include/asm-arm/arch-s5pc1xx/interrupt.h create mode 100644 include/asm-arm/arch-s5pc1xx/keypad.h create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h create mode 100644 include/asm-arm/arch-s5pc1xx/power.h create mode 100644 include/asm-arm/arch-s5pc1xx/pwm.h create mode 100644 include/asm-arm/arch-s5pc1xx/uart.h diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile new file mode 100644 index 0000000..6ccb09a --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS = reset.o + +COBJS += timer.o +COBJS += clock.o +COBJS += cpu_info.o +COBJS += cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.c b/cpu/arm_cortexa8/s5pc1xx/cache.c new file mode 100644 index 0000000..8652a45 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cache.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/cache.h> + +void l2_cache_enable(void) +{ + unsigned long i; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); +} + +void l2_cache_disable(void) +{ + unsigned long i; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c new file mode 100644 index 0000000..59690d7 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code should work for both the S3C2400 and the S3C2410 + * as they seem to have the same PLL and clock machinery inside. + * The different address mapping is handled by the s3c24xx.h files below. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/clock.h> + +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + +#ifndef CONFIG_SYS_CLK_FREQ_C100 +#define CONFIG_SYS_CLK_FREQ_C100 12000000 +#endif +#ifndef CONFIG_SYS_CLK_FREQ_C110 +#define CONFIG_SYS_CLK_FREQ_C110 24000000 +#endif + +static int s5pc1xx_clock_read_reg(int offset) +{ + return readl(S5PC1XX_CLOCK_BASE + offset); +} + +/* ------------------------------------------------------------------------- */ +/* + * NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +unsigned long get_pll_clk(int pllreg) +{ + unsigned long r, m, p, s, mask, fout; + unsigned int freq; + + switch (pllreg) { + case APLL: + if (cpu_is_s5pc110()) + r = s5pc1xx_clock_read_reg(S5PC110_APLL_CON_OFFSET); + else + r = s5pc1xx_clock_read_reg(S5PC100_APLL_CON_OFFSET); + break; + case MPLL: + if (cpu_is_s5pc110()) + r = s5pc1xx_clock_read_reg(S5PC110_MPLL_CON_OFFSET); + else + r = s5pc1xx_clock_read_reg(S5PC100_MPLL_CON_OFFSET); + break; + case EPLL: + if (cpu_is_s5pc110()) + r = s5pc1xx_clock_read_reg(S5PC110_EPLL_CON_OFFSET); + else + r = s5pc1xx_clock_read_reg(S5PC100_EPLL_CON_OFFSET); + break; + case HPLL: + if (cpu_is_s5pc110()) + hang(); + r = s5pc1xx_clock_read_reg(S5PC100_HPLL_CON_OFFSET); + break; + case VPLL: + if (cpu_is_s5pc100()) + hang(); + r = s5pc1xx_clock_read_reg(S5PC110_VPLL_CON_OFFSET); + break; + default: + hang(); + } + + if (cpu_is_s5pc110()) { + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + } else { + if (pllreg == APLL) + mask = 0x3ff; + else + mask = 0x0ff; + } + + m = (r >> 16) & mask; + p = (r >> 8) & 0x3f; + s = r & 0x7; + + if (cpu_is_s5pc110()) { + freq = CONFIG_SYS_CLK_FREQ_C110; + if (pllreg == APLL) { + if (s < 1) + s = 1; + fout = m * (freq / (p * (1 << (s - 1)))); + } else + fout = m * (freq / (p * (1 << s))); + } else { + freq = CONFIG_SYS_CLK_FREQ_C100; + fout = m * (freq / (p * (1 << s))); + } + + return fout; +} + +/* return ARMCORE frequency */ +unsigned long get_arm_clk(void) +{ + unsigned long div; + unsigned long dout_apll, armclk; + unsigned int apll_ratio, arm_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + if (cpu_is_s5pc110()) { + /* ARM_RATIO: don't use */ + arm_ratio = 0; + /* APLL_RATIO: [2:0] */ + apll_ratio = div & 0x7; + } else { + /* ARM_RATIO: [6:4] */ + arm_ratio = (div >> 4) & 0x7; + /* APLL_RATIO: [0] */ + apll_ratio = div & 0x1; + } + + dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); + armclk = dout_apll / (arm_ratio + 1); + + return armclk; +} + +/* return FCLK frequency */ +unsigned long get_fclk(void) +{ + return get_pll_clk(APLL); +} + +/* return MCLK frequency */ +unsigned long get_mclk(void) +{ + return get_pll_clk(MPLL); +} + +/* s5pc100: return HCLKD0 frequency */ +unsigned long get_hclk(void) +{ + unsigned long hclkd0; + uint div, d0_bus_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + /* D0_BUS_RATIO: [10:8] */ + d0_bus_ratio = (div >> 8) & 0x7; + + hclkd0 = get_arm_clk() / (d0_bus_ratio + 1); + + return hclkd0; +} + +/* s5pc100: return PCLKD0 frequency */ +unsigned long get_pclkd0(void) +{ + unsigned long pclkd0; + uint div, pclkd0_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + /* PCLKD0_RATIO: [14:12] */ + pclkd0_ratio = (div >> 12) & 0x7; + + pclkd0 = get_hclk() / (pclkd0_ratio + 1); + + return pclkd0; +} + +/* s5pc100: return PCLKD1 frequency */ +unsigned long get_pclkd1(void) +{ + unsigned long d1_bus, pclkd1; + uint div, d1_bus_ratio, pclkd1_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV1_OFFSET); + /* D1_BUS_RATIO: [14:12] */ + d1_bus_ratio = (div >> 12) & 0x7; + /* PCLKD1_RATIO: [18:16] */ + pclkd1_ratio = (div >> 16) & 0x7; + + /* ASYNC Mode */ + d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); + pclkd1 = d1_bus / (pclkd1_ratio + 1); + + return pclkd1; +} + +/* s5pc110: return HCLKs frequency */ +unsigned long get_hclk_sys(int clk) +{ + unsigned long hclk; + unsigned int div; + unsigned int offset; + unsigned int hclk_sys_ratio; + + if (clk == CLK_M) + return get_hclk(); + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + + /* HCLK_MSYS_RATIO: [10:8] + * HCLK_DSYS_RATIO: [19:16] + * HCLK_PSYS_RATIO: [27:24] */ + offset = 8 + (clk << 0x3); + + hclk_sys_ratio = (div >> offset) & 0xf; + + hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); + + return hclk; +} + +/* s5pc110: return PCLKs frequency */ +unsigned long get_pclk_sys(int clk) +{ + unsigned long pclk; + unsigned int div; + unsigned int offset; + unsigned int pclk_sys_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + + /* PCLK_MSYS_RATIO: [14:12] + * PCLK_DSYS_RATIO: [22:20] + * PCLK_PSYS_RATIO: [30:28] */ + offset = 12 + (clk << 0x3); + + pclk_sys_ratio = (div >> offset) & 0x7; + + pclk = get_hclk_sys(clk) / (pclk_sys_ratio + 1); + + return pclk; +} + +/* return peripheral clock */ +unsigned long get_pclk(void) +{ + if (cpu_is_s5pc110()) + return get_pclk_sys(CLK_P); + else + return get_pclkd1(); +} + +/* return UCLK frequency */ +unsigned long get_uclk(void) +{ + return get_pll_clk(EPLL); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c new file mode 100644 index 0000000..cd37738 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> + +/* Default is s5pc100 */ +unsigned int s5pc1xx_cpu_id = 0xC100; + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID); + s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12); + + return 0; +} +#endif + +u32 get_device_type(void) +{ + return s5pc1xx_cpu_id; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU:\tS5P%X@%luMHz\n", s5pc1xx_cpu_id, get_arm_clk() / 1000000); + if (cpu_is_s5pc110()) { + printf("\tAPLL = %luMHz, MPLL = %luMHz, EPLL = %luMHz\n", + get_fclk() / 1000000, + get_mclk() / 1000000, + get_uclk() / 1000000); + printf("\tHclk: Msys %luMhz, Dsys %luMhz, Psys %luMhz\n", + get_hclk_sys(CLK_M) / 1000000, + get_hclk_sys(CLK_D) / 1000000, + get_hclk_sys(CLK_P) / 1000000); + printf("\tPclk: Msys %3luMhz, Dsys %3luMhz, Psys %3luMhz\n", + get_pclk_sys(CLK_M) / 1000000, + get_pclk_sys(CLK_D) / 1000000, + get_pclk_sys(CLK_P) / 1000000); + } else { + printf("\tFclk = %luMHz, HclkD0 = %luMHz, PclkD0 = %luMHz," + " PclkD1 = %luMHz\n", + get_fclk() / 1000000, get_hclk() / 1000000, + get_pclkd0() / 1000000, get_pclkd1() / 1000000); + } + + return 0; +} +#endif diff --git a/cpu/arm_cortexa8/s5pc1xx/reset.S b/cpu/arm_cortexa8/s5pc1xx/reset.S new file mode 100644 index 0000000..7f6ff9c --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/reset.S @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2009 Samsung Electronics. + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/cpu.h> + +#define S5PC100_SWRESET 0xE0200000 +#define S5PC110_SWRESET 0xE0102000 + +.globl reset_cpu +reset_cpu: + ldr r1, =S5PC1XX_PRO_ID + ldr r2, [r1] + ldr r4, =0x00010000 + and r4, r2, r4 + cmp r4, #0 + bne 110f + /* S5PC100 */ + ldr r1, =S5PC100_SWRESET + ldr r2, =0xC100 + b 200f +110: /* S5PC110 */ + ldr r1, =S5PC110_SWRESET + mov r2, #1 +200: + str r2, [r1] +_loop_forever: + b _loop_forever diff --git a/cpu/arm_cortexa8/s5pc1xx/timer.c b/cpu/arm_cortexa8/s5pc1xx/timer.c new file mode 100644 index 0000000..de4ebb5 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/timer.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Heungjun Kim <riverful.kim(a)samsung.com> + * Inki Dae <inki.dae(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/pwm.h> +#include <asm/arch/clk.h> + +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ +#define MUX4_DIV_SHIFT 16 + +#define TCON_TIMER4_SHIFT 20 + +static unsigned long count_value; + +/* Internal tick units */ +static unsigned long long timestamp; /* Monotonic incrementing timer */ +static unsigned long lastdec; /* Last decremneter snapshot */ + +/* macro to read the 16 bit timer */ +static inline unsigned long READ_TIMER(void) +{ + s5pc1xx_timers_t *timers; + + if (cpu_is_s5pc110()) + timers = (s5pc1xx_timers_t *) S5PC110_TIMER_BASE; + else + timers = (s5pc1xx_timers_t *) S5PC100_TIMER_BASE; + + return timers->TCNTO4; +} + +int timer_init(void) +{ + s5pc1xx_timers_t *timers; + + if (cpu_is_s5pc110()) + timers = (s5pc1xx_timers_t *) S5PC110_TIMER_BASE; + else + timers = (s5pc1xx_timers_t *) S5PC100_TIMER_BASE; + + /* + * @ PWM Timer 4 + * Timer Freq(HZ) = + * PCLK / { (prescaler_value + 1) * (divider_value) } + */ + + /* set prescaler : 16 */ + /* set divider : 2 */ + timers->TCFG0 = (PRESCALER_1 & 0xff) << 8; + timers->TCFG1 = (MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT; + + if (count_value == 0) { + /* reset initial value */ + /* count_value = 2085937.5(HZ) (per 1 sec)*/ + count_value = get_pclk() / ((PRESCALER_1 + 1) * + (MUX_DIV_2 + 1)); + + /* count_value / 100 = 20859.375(HZ) (per 10 msec) */ + count_value = count_value / 100; + } + + /* set count value */ + timers->TCNTB4 = count_value; + lastdec = count_value; + + /* auto reload & manual update */ + timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) | + S5PC1XX_TCON4_AUTO_RELOAD | S5PC1XX_TCON4_UPDATE; + + /* start PWM timer 4 */ + timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) | + S5PC1XX_TCON4_AUTO_RELOAD | S5PC1XX_TCON4_START; + + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked() - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +/* delay x useconds */ +void udelay(unsigned long usec) +{ + unsigned long tmo, tmp; + + if (usec >= 1000) { + /* + * if "big" number, spread normalization + * to seconds + * 1. start to normalize for usec to ticks per sec + * 2. find number of "ticks" to wait to achieve target + * 3. finish normalize. + */ + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 1000; + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000 * 1000); + } + + /* get current timestamp */ + tmp = get_timer(0); + + /* if setting this fordward will roll time stamp */ + /* reset "advancing" timestamp to 0, set lastdec value */ + /* else, set advancing stamp wake up time */ + if ((tmo + tmp + 1) < tmp) + reset_timer_masked(); + else + tmo += tmp; + + /* loop till event */ + while (get_timer_masked() < tmo) + ; /* nop */ +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +unsigned long get_timer_masked(void) +{ + /* current tick value */ + unsigned long now = READ_TIMER(); + + if (lastdec >= now) + timestamp += lastdec - now; + else + timestamp += lastdec + count_value - now; + + lastdec = now; + + return timestamp; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + /* We overrun in 100s */ + return CONFIG_SYS_HZ * 100; +} diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h new file mode 100644 index 0000000..c0f46d2 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLK_H_ +#define __ASM_ARM_ARCH_CLK_H_ + +unsigned long get_pll_clk(int pllreg); +unsigned long get_arm_clk(void); +unsigned long get_fclk(void); +unsigned long get_mclk(void); +unsigned long get_hclk(void); +unsigned long get_pclk(void); +unsigned long get_uclk(void); + +/*s5pc110 */ +#define CLK_M 0 +#define CLK_D 1 +#define CLK_P 2 + +unsigned long get_hclk_sys(int clk); +unsigned long get_pclk_sys(int clk); + +/* s5pc100 */ +unsigned long get_pclkd0(void); +unsigned long get_pclkd1(void); + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h new file mode 100644 index 0000000..ac28e15 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/clock.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H_ +#define __ASM_ARM_ARCH_CLOCK_H_ + +/* + * Clock control + */ + +/* Clock Register */ +#define S5PC100_APLL_LOCK_OFFSET 0x0 +#define S5PC100_MPLL_LOCK_OFFSET 0x4 +#define S5PC100_EPLL_LOCK_OFFSET 0x8 +#define S5PC100_HPLL_LOCK_OFFSET 0xc + +#define S5PC100_APLL_CON_OFFSET 0x100 +#define S5PC100_MPLL_CON_OFFSET 0x104 +#define S5PC100_EPLL_CON_OFFSET 0x108 +#define S5PC100_HPLL_CON_OFFSET 0x10c + +#define S5PC110_APLL_LOCK_OFFSET 0x00 +#define S5PC110_MPLL_LOCK_OFFSET 0x08 +#define S5PC110_EPLL_LOCK_OFFSET 0x10 +#define S5PC110_VPLL_LOCK_OFFSET 0x20 + +#define S5PC110_APLL_CON_OFFSET 0x100 +#define S5PC110_MPLL_CON_OFFSET 0x108 +#define S5PC110_EPLL_CON_OFFSET 0x110 +#define S5PC110_VPLL_CON_OFFSET 0x120 + +#define S5P_CLK_SRC0_OFFSET 0x200 +#define S5P_CLK_SRC1_OFFSET 0x204 +#define S5P_CLK_SRC2_OFFSET 0x208 +#define S5P_CLK_SRC3_OFFSET 0x20c + +#define S5P_CLK_DIV0_OFFSET 0x300 +#define S5P_CLK_DIV1_OFFSET 0x304 +#define S5P_CLK_DIV2_OFFSET 0x308 +#define S5P_CLK_DIV3_OFFSET 0x30c +#define S5P_CLK_DIV4_OFFSET 0x310 + +#define S5P_CLK_OUT_OFFSET 0x400 + +#define S5P_CLK_GATE_D00_OFFSET 0x500 +#define S5P_CLK_GATE_D01_OFFSET 0x504 +#define S5P_CLK_GATE_D02_OFFSET 0x508 + +#define S5P_CLK_GATE_D10_OFFSET 0x520 +#define S5P_CLK_GATE_D11_OFFSET 0x524 +#define S5P_CLK_GATE_D12_OFFSET 0x528 +#define S5P_CLK_GATE_D13_OFFSET 0x530 +#define S5P_CLK_GATE_D14_OFFSET 0x534 + +#define S5P_CLK_GATE_D20_OFFSET 0x540 + +#define S5P_CLK_GATE_SCLK0_OFFSET 0x560 +#define S5P_CLK_GATE_SCLK1_OFFSET 0x564 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h new file mode 100644 index 0000000..c7d7183 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/cpu.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _S5PC1XX_CPU_H +#define _S5PC1XX_CPU_H + +#include <asm/hardware.h> + +#define S5PC1XX_ADDR_BASE 0xe0000000 +#define S5P_ADDR(x) (S5PC1XX_ADDR_BASE + (x)) + +#define S5PC1XX_CLOCK_BASE 0xE0100000 +#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */ + +/* Note that write the macro by address order */ +#define S5PC100_VIC0_BASE 0xE4000000 +#define S5PC100_VIC1_BASE 0xE4100000 +#define S5PC100_VIC2_BASE 0xE4200000 +#define S5PC100_SROMC_BASE 0xE7000000 +#define S5PC100_ONENAND_BASE 0xE7100000 +#define S5PC100_WATCHDOG_BASE 0xEA200000 + +#define S5PC110_WATCHDOG_BASE 0xE2700000 +#define S5PC110_SROMC_BASE 0xE8000000 +#define S5PC110_VIC0_BASE 0xF2000000 +#define S5PC110_VIC1_BASE 0xF2100000 +#define S5PC110_VIC2_BASE 0xF2200000 +#define S5PC110_VIC3_BASE 0xF2300000 + +/* + * Chip ID + */ +#define S5PC1XX_CHIP_ID(x) (0xE0000000 + (x)) +#define S5PC1XX_PRO_ID S5PC1XX_CHIP_ID(0) +#define S5PC1XX_OMR S5PC1XX_CHIP_ID(4) + +#ifndef __ASSEMBLY__ +/* CPU detection macros */ +extern unsigned int s5pc1xx_cpu_id; + +#define IS_SAMSUNG_TYPE(type, id) \ +static inline int is_##type(void) \ +{ \ + return (s5pc1xx_cpu_id == (id)) ? 1 : 0; \ +} + +IS_SAMSUNG_TYPE(s5pc100, 0xc100) +IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +#define cpu_is_s5pc100() is_s5pc100() +#define cpu_is_s5pc110() is_s5pc110() +#endif + +#endif /* _S5PC1XX_CPU_H */ diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h new file mode 100644 index 0000000..26d0950 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __S5PC1XX_GPIO_H +#define __S5PC1XX_GPIO_H + +/* GPIO Bank Base */ +#define S5PC100_GPIO_BASE(x) (0xE0300000 + (x)) +#define S5PC110_GPIO_BASE(x) (0xE0200000 + (x)) + +/* S5PC100 bank offset */ +#define S5PC100_GPIO_A0_OFFSET 0x000 +#define S5PC100_GPIO_A1_OFFSET 0x020 +#define S5PC100_GPIO_B_OFFSET 0x040 +#define S5PC100_GPIO_C_OFFSET 0x060 +#define S5PC100_GPIO_D_OFFSET 0x080 +#define S5PC100_GPIO_E0_OFFSET 0x0A0 +#define S5PC100_GPIO_E1_OFFSET 0x0C0 +#define S5PC100_GPIO_F0_OFFSET 0x0E0 +#define S5PC100_GPIO_F1_OFFSET 0x100 +#define S5PC100_GPIO_F2_OFFSET 0x120 +#define S5PC100_GPIO_F3_OFFSET 0x140 +#define S5PC100_GPIO_G0_OFFSET 0x160 +#define S5PC100_GPIO_G1_OFFSET 0x180 +#define S5PC100_GPIO_G2_OFFSET 0x1A0 +#define S5PC100_GPIO_G3_OFFSET 0x1C0 +#define S5PC100_GPIO_I_OFFSET 0x1E0 +#define S5PC100_GPIO_J0_OFFSET 0x200 +#define S5PC100_GPIO_J1_OFFSET 0x220 +#define S5PC100_GPIO_J2_OFFSET 0x240 +#define S5PC100_GPIO_J3_OFFSET 0x260 +#define S5PC100_GPIO_J4_OFFSET 0x280 +#define S5PC100_GPIO_K0_OFFSET 0x2A0 +#define S5PC100_GPIO_K1_OFFSET 0x2C0 +#define S5PC100_GPIO_K2_OFFSET 0x2E0 +#define S5PC100_GPIO_K3_OFFSET 0x300 +#define S5PC100_GPIO_L0_OFFSET 0x320 +#define S5PC100_GPIO_L1_OFFSET 0x340 +#define S5PC100_GPIO_L2_OFFSET 0x360 +#define S5PC100_GPIO_L3_OFFSET 0x380 +#define S5PC100_GPIO_L4_OFFSET 0x3A0 +#define S5PC100_GPIO_H0_OFFSET 0xC00 +#define S5PC100_GPIO_H1_OFFSET 0xC20 +#define S5PC100_GPIO_H2_OFFSET 0xC40 +#define S5PC100_GPIO_H3_OFFSET 0xC60 + +/* S5PC110 bank offset */ +#define S5PC110_GPIO_A0_OFFSET 0x000 +#define S5PC110_GPIO_A1_OFFSET 0x020 +#define S5PC110_GPIO_B_OFFSET 0x040 +#define S5PC110_GPIO_C0_OFFSET 0x060 +#define S5PC110_GPIO_C1_OFFSET 0x080 +#define S5PC110_GPIO_D0_OFFSET 0x0A0 +#define S5PC110_GPIO_D1_OFFSET 0x0C0 +#define S5PC110_GPIO_E0_OFFSET 0x0E0 +#define S5PC110_GPIO_E1_OFFSET 0x110 +#define S5PC110_GPIO_F0_OFFSET 0x120 +#define S5PC110_GPIO_F1_OFFSET 0x140 +#define S5PC110_GPIO_F2_OFFSET 0x160 +#define S5PC110_GPIO_F3_OFFSET 0x180 +#define S5PC110_GPIO_G0_OFFSET 0x1A0 +#define S5PC110_GPIO_G1_OFFSET 0x1C0 +#define S5PC110_GPIO_G2_OFFSET 0x1E0 +#define S5PC110_GPIO_G3_OFFSET 0x200 +#define S5PC110_GPIO_I_OFFSET 0x220 +#define S5PC110_GPIO_J0_OFFSET 0x240 +#define S5PC110_GPIO_J1_OFFSET 0x260 +#define S5PC110_GPIO_J2_OFFSET 0x280 +#define S5PC110_GPIO_J3_OFFSET 0x2A0 +#define S5PC110_GPIO_J4_OFFSET 0x2C0 +#define S5PC110_GPIO_MP0_1_OFFSET 0x2E0 +#define S5PC110_GPIO_MP0_2_OFFSET 0x300 +#define S5PC110_GPIO_MP0_3_OFFSET 0x320 +#define S5PC110_GPIO_MP0_4_OFFSET 0x340 +#define S5PC110_GPIO_MP0_5_OFFSET 0x360 +#define S5PC110_GPIO_MP0_6_OFFSET 0x380 +#define S5PC110_GPIO_MP0_7_OFFSET 0x3A0 +#define S5PC110_GPIO_MP1_0_OFFSET 0x3C0 +#define S5PC110_GPIO_MP1_1_OFFSET 0x3E0 +#define S5PC110_GPIO_MP1_2_OFFSET 0x410 +#define S5PC110_GPIO_MP1_3_OFFSET 0x420 +#define S5PC110_GPIO_MP1_4_OFFSET 0x440 +#define S5PC110_GPIO_MP1_5_OFFSET 0x460 +#define S5PC110_GPIO_MP1_6_OFFSET 0x480 +#define S5PC110_GPIO_MP1_7_OFFSET 0x4A0 +#define S5PC110_GPIO_MP1_8_OFFSET 0x4C0 +#define S5PC110_GPIO_MP2_0_OFFSET 0x4E0 +#define S5PC110_GPIO_MP2_1_OFFSET 0x510 +#define S5PC110_GPIO_MP2_2_OFFSET 0x520 +#define S5PC110_GPIO_MP2_3_OFFSET 0x540 +#define S5PC110_GPIO_MP2_4_OFFSET 0x560 +#define S5PC110_GPIO_MP2_5_OFFSET 0x580 +#define S5PC110_GPIO_MP2_6_OFFSET 0x5A0 +#define S5PC110_GPIO_MP2_7_OFFSET 0x5C0 +#define S5PC110_GPIO_MP2_8_OFFSET 0x5E0 +#define S5PC110_GPIO_H0_OFFSET 0xC00 +#define S5PC110_GPIO_H1_OFFSET 0xC20 +#define S5PC110_GPIO_H2_OFFSET 0xC40 +#define S5PC110_GPIO_H3_OFFSET 0xC60 + +/* GPIO bank Offset */ +#define S5PC1XX_GPIO_CON_OFFSET 0x0 +#define S5PC1XX_GPIO_DAT_OFFSET 0x4 +#define S5PC1XX_GPIO_PULL_OFFSET 0x8 +#define S5PC1XX_GPIO_DRV_OFFSET 0xc +#define S5PC1XX_GPIO_PDNCON_OFFSET 0x10 +#define S5PC1XX_GPIO_PDNPULL_OFFSET 0x14 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/hardware.h b/include/asm-arm/arch-s5pc1xx/hardware.h new file mode 100644 index 0000000..ca95c3d --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/hardware.h @@ -0,0 +1,63 @@ +/* + * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ARCH_HARDWARE_H_ +#define _ARCH_HARDWARE_H_ + +#include <asm/sizes.h> + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long)(Data)) + +#define __REG(x) (*(vu_long *)(x)) +#define __REGl(x) (*(vu_long *)(x)) +#define __REGw(x) (*(vu_short *)(x)) +#define __REGb(x) (*(vu_char *)(x)) +#define __REG2(x, y) (*(vu_long *)((x) + (y))) +#else +#define UData(Data) (Data) + +#define __REG(x) (x) +#define __REGl(x) (x) +#define __REGw(x) (x) +#define __REGb(x) (x) +#define __REG2(x, y) ((x) + (y)) +#endif + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData(1) << FSize(Field)) - 1) << FShft(Field)) +#define FAlnMsk(Field) ((UData(1) << FSize(Field)) - 1) +#define F1stBit(Field) (UData(1) << FShft(Field)) + +#define FClrBit(Data, Bit) (Data = (Data & ~(Bit))) +#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field))) + +#define FInsrt(Value, Field) \ + (UData(Value) << FShft(Field)) + +#define FExtr(Data, Field) \ + ((UData(Data) >> FShft(Field)) & FAlnMsk(Field)) + +#endif /* _ARCH_HARDWARE_H_ */ diff --git a/include/asm-arm/arch-s5pc1xx/i2c.h b/include/asm-arm/arch-s5pc1xx/i2c.h new file mode 100644 index 0000000..35a904a --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Kyungnin Park <kyungmin.park(a)samsung.com> + * + * based on s3c24x0_i2c.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_I2C_H_ +#define __ASM_ARCH_I2C_H_ + +/* I2C */ +#define S5PC100_I2C0_BASE 0xEC100000 +#define S5PC100_I2C1_BASE 0xEC200000 +#define S5PC110_I2C0_BASE 0xE1800000 +#define S5PC110_I2C2_BASE 0xE1A00000 + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_i2c { + volatile unsigned long IICCON; + volatile unsigned long IICSTAT; + volatile unsigned long IICADD; + volatile unsigned long IICDS; + volatile unsigned long IICLC; +} s5pc1xx_i2c_t; +#endif + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/interrupt.h b/include/asm-arm/arch-s5pc1xx/interrupt.h new file mode 100644 index 0000000..a3c8680 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/interrupt.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_INTERRUPT_H_ +#define __ASM_ARM_ARCH_INTERRUPT_H_ + +/* Vector Interrupt Offset */ +#define VIC_IRQSTATUS_OFFSET 0x0 +#define VIC_FIQSTATUS_OFFSET 0x4 +#define VIC_RAWINTR_OFFSET 0x8 +#define VIC_INTSELECT_OFFSET 0xc +#define VIC_INTENABLE_OFFSET 0x10 +#define VIC_INTENCLEAR_OFFSET 0x14 +#define VIC_SOFTINT_OFFSET 0x18 +#define VIC_SOFTINTCLEAR_OFFSET 0x1c +#define VIC_PROTECTION_OFFSET 0x20 +#define VIC_SWPRIORITYMASK_OFFSET 0x24 +#define VIC_PRIORITYDAISY_OFFSET 0x28 +#define VIC_INTADDRESS_OFFSET 0xf00 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/keypad.h b/include/asm-arm/arch-s5pc1xx/keypad.h new file mode 100644 index 0000000..0437b5e --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/keypad.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungnin Park <kyungmin.park(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_KEYPAD_H_ +#define __ASM_ARCH_KEYPAD_H_ + +#define S5PC100_KEYPAD_BASE 0xF3100000 +#define S5PC110_KEYPAD_BASE 0xE1600000 + +#define S5PC1XX_KEYIFCON_OFFSET (0x00) +#define S5PC1XX_KEYIFSTSCLR_OFFSET (0x04) +#define S5PC1XX_KEYIFCOL_OFFSET (0x08) +#define S5PC1XX_KEYIFROW_OFFSET (0x0C) +#define S5PC1XX_KEYIFFC_OFFSET (0x10) + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h new file mode 100644 index 0000000..4b06aaf --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/mem.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_MEM_H_ +#define __ASM_ARM_ARCH_MEM_H_ + +/* + * SROMC Controller + */ +/* DRAM Memory Controller */ +#define S5PC100_DMC_BASE 0xE6000000 +#define S5PC110_DMC0_BASE 0xF0000000 +#define S5PC110_DMC1_BASE 0xF1400000 + +/* DMC offset */ +#define CONCONTROL_OFFSET 0x00 +#define MEMCONTROL_OFFSET 0x04 +#define MEMCONFIG0_OFFSET 0x08 +#define MEMCONFIG1_OFFSET 0x0c +#define DIRECTCMD_OFFSET 0x10 +#define PRECHCONFIG_OFFSET 0x14 +#define PHYCONTROL0_OFFSET 0x18 +#define PHYCONTROL1_OFFSET 0x1c +#define PHYCONTROL2_OFFSET 0x20 +#define PWRDNCONFIG_OFFSET 0x28 +#define TIMINGAREF_OFFSET 0x30 +#define TIMINGROW_OFFSET 0x34 +#define TIMINGDATA_OFFSET 0x38 +#define TIMINGPOWER_OFFSET 0x3c +#define PHYSTATUS0_OFFSET 0x40 +#define PHYSTATUS1_OFFSET 0x44 +#define CHIP0STATUS_OFFSET 0x48 +#define CHIP1STATUS_OFFSET 0x4c +#define AREFSTATUS_OFFSET 0x50 +#define MRSTATUS_OFFSET 0x54 +#define PHYTEST0_OFFSET 0x58 +#define PHYTEST1_OFFSET 0x5c + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/include/asm-arm/arch-s5pc1xx/power.h new file mode 100644 index 0000000..57e2a2b --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/power.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_POWER_H_ +#define __ASM_ARM_ARCH_POWER_H_ + +/* + * Power control + */ +#define S5PC100_OTHERS 0xE0108200 +#define S5PC100_RST_STAT 0xE0108300 +#define S5PC100_SLEEP_WAKEUP (1 << 3) +#define S5PC100_WAKEUP_STAT 0xE0108304 +#define S5PC100_INFORM0 0xE0108400 + +#define S5PC110_RST_STAT 0xE010A000 +#define S5PC110_SLEEP_WAKEUP (1 << 3) +#define S5PC110_WAKEUP_STAT 0xE010C200 +#define S5PC110_OTHERS 0xE010E000 +#define S5PC110_USB_PHY_CON 0xE010E80C +#define S5PC110_INFORM0 0xE010F000 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h new file mode 100644 index 0000000..6a6347e --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/pwm.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +/* + * PWM Timer + */ +#define S5PC100_PWMTIMER_BASE 0xEA000000 +#define S5PC110_PWMTIMER_BASE 0xE2500000 + +/* PWM timer addressing */ +#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE +#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE + +/* Interval mode(Auto Reload) of PWM Timer 4 */ +#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) +/* Update TCNTB4 */ +#define S5PC1XX_TCON4_UPDATE (1 << 21) +/* start bit of PWM Timer 4 */ +#define S5PC1XX_TCON4_START (1 << 20) + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_timer { + volatile unsigned long TCFG0; + volatile unsigned long TCFG1; + volatile unsigned long TCON; + volatile unsigned long TCNTB0; + volatile unsigned long TCMPB0; + volatile unsigned long TCNTO0; + volatile unsigned long TCNTB1; + volatile unsigned long TCMPB1; + volatile unsigned long TCNTO1; + volatile unsigned long TCNTB2; + volatile unsigned long TCMPB2; + volatile unsigned long TCNTO2; + volatile unsigned long TCNTB3; + volatile unsigned long res1; + volatile unsigned long TCNTO3; + volatile unsigned long TCNTB4; + volatile unsigned long TCNTO4; + volatile unsigned long TINTCSTAT; +} s5pc1xx_timers_t; +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h new file mode 100644 index 0000000..189bbff --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/uart.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +/* + * UART + */ +/* uart base address */ +#define S5PC100_PA_UART 0xEC000000 +#define S5PC110_PA_UART 0xE2900000 + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_uart { + volatile unsigned long ULCON; + volatile unsigned long UCON; + volatile unsigned long UFCON; + volatile unsigned long UMCON; + volatile unsigned long UTRSTAT; + volatile unsigned long UERSTAT; + volatile unsigned long UFSTAT; + volatile unsigned long UMSTAT; +#ifdef __BIG_ENDIAN + volatile unsigned char res1[3]; + volatile unsigned char UTXH; + volatile unsigned char res2[3]; + volatile unsigned char URXH; +#else /* Little Endian */ + volatile unsigned char UTXH; + volatile unsigned char res1[3]; + volatile unsigned char URXH; + volatile unsigned char res2[3]; +#endif + volatile unsigned long UBRDIV; +#ifdef __BIG_ENDIAN + volatile unsigned char res3[2]; + volatile unsigned short UDIVSLOT; +#else + volatile unsigned short UDIVSLOT; + volatile unsigned char res3[2]; +#endif +} s5pc1xx_uart_t; + +enum s5pc1xx_uarts_nr { + S5PC1XX_UART0, + S5PC1XX_UART1, + S5PC1XX_UART2, + S5PC1XX_UART3, +}; +#endif /* __ASSEMBLY__ */ + +#endif -- 1.5.4.3

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[U-Boot] [PATCH] atngw100: Use virtual address in CONFIG_ENV_ADDR
by Haavard Skinnemoen 04 Sep '09

04 Sep '09

Ever since the CFI driver was rewritten to use virtual addresses, thus eliminating the whole point of the map_physmem() macro, ATNGW100 has been broken like this: U-Boot> saveenv Saving Environment to Flash... Error: start and/or end address not on sector boundary So let's take a different approach and store the virtual address in CONFIG_ENV_ADDR. I personally believe that's rubbish and will break whenever we decide to change the virtual-to-physical mapping in any way, but it looks like it's the direction in which u-boot is currently moving, and it does fix the problem. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- include/configs/atngw100.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 4ed5514..9777ec0 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -155,7 +155,7 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) +#define CONFIG_ENV_ADDR (0xa0000000 + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) -- 1.6.0.4

9 47

[U-Boot] Newest Version U-boot
by Marcos Cunha 04 Sep '09

04 Sep '09

1 0

[U-Boot] TEST
by Wolfgang Denk 03 Sep '09

03 Sep '09

Please ignore. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de The flow chart is a most thoroughly oversold piece of program docu- mentation. -- Frederick Brooks, "The Mythical Man Month"

1 0

[U-Boot] [PATCH 1/2 v2] 85xx: CONFIG_MP Boot Page Translation update
by Peter Tyser 03 Sep '09

03 Sep '09

Previously, when CONFIG_MP was defined Boot Page Translation was unconditionally enabled and secondary cores were put in a spin loop at address 0xfffff000. The 0xfffffxxx address range (ie the Boot Page) was being remapped to SDRAM via the BPTR register. This change puts secondary cores into spin loops at their 'true' address in SDRAM and doesn't require Boot Page Translation to always be enabled. The main advantage of this change is that Boot Page Translation can be disabled after the secondary cores are brought up which allows the memory region at 0xfffffxxx to be used for other peripherals, etc. By default, Boot Page Translation remains enabled while U-Boot executes. A new CONFIG_MPC8xxx_DISABLE_BPTR define has been added which causes Boot Page Translation to be disabled for those boards which wish to use the 0xfffffxxx address range as part of their normal memory map. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- Changes since v1: - Use clrbits_be32() instead of in/out_be32() This is very similar to "85xx: Fix mapping of 0xfffffxxx when CONFIG_MP" The 2 differences are: - Boot page translation is only disabled when CONFIG_MPC8xxx_DISABLT_BPTR is defined. - Instead of zeroing out BPTR when disabling translation, this patch only disables translation, but maintins the translation address. This should make it easier to properly re-enable translation if need be. cpu/mpc85xx/mp.c | 22 ++++++++++++++++++++-- cpu/mpc85xx/release.S | 30 +++++++++++++++++++++++++----- 2 files changed, 45 insertions(+), 7 deletions(-) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 76f02a4..53fc3be 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -129,7 +129,7 @@ ulong get_spin_addr(void) ulong addr = (ulong)&__spin_table - (ulong)&__secondary_start_page; - addr += 0xfffff000; + addr += determine_mp_bootpg(); return addr; } @@ -137,7 +137,8 @@ ulong get_spin_addr(void) static void pq3_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; - u32 *table = (u32 *)get_spin_addr(); + /* The table is at 0xfffffxxx due to boot page translation below */ + u32 *table = (u32 *)(0xfffff000 | get_spin_addr()); volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -146,6 +147,8 @@ static void pq3_mp_up(unsigned long bootpg) int timeout = 10; whoami = in_be32(&pic->whoami); + + /* Translate 0xfffffxxx 'bootpg' address range to SDRAM */ out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); /* disable time base at the platform */ @@ -194,6 +197,17 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); + +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Disabling Boot Page Translation allows the memory region 0xfffff000 + * to 0xffffffff to be used normally. Leaving Boot Page Translation + * enabled remaps 0xfffff000 to SDRAM which makes that memory region + * unusable for normal operation but it does allow OSes to easily + * reset a processor core to put it back into U-Boot's spinloop. + */ + clrbits_be32(&ecm->bptr, 0x80000000); +#endif } void cpu_mp_lmb_reserve(struct lmb *lmb) @@ -206,9 +220,13 @@ void cpu_mp_lmb_reserve(struct lmb *lmb) void setup_mp(void) { extern ulong __secondary_start_page; + extern ulong __bootpg_addr; ulong fixup = (ulong)&__secondary_start_page; u32 bootpg = determine_mp_bootpg(); + /* Store the bootpg's SDRAM address for use by secondary CPU cores */ + __bootpg_addr = bootpg; + memcpy((void *)bootpg, (void *)fixup, 4096); flush_cache(bootpg, 4096); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index fbefc2c..6799633 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -114,23 +114,38 @@ __secondary_start_page: stw r3,ENTRY_R6_UPPER(r10) stw r3,ENTRY_R6_LOWER(r10) + /* load r13 with the address of the 'bootpg' in SDRAM */ + lis r13,toreset(__bootpg_addr)@h + ori r13,r13,toreset(__bootpg_addr)@l + lwz r13,0(r13) + /* setup mapping for AS = 1, and jump there */ lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h mtspr SPRN_MAS0,r11 lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - lis r11,(0xfffff000|MAS2_I)@h - ori r11,r11,(0xfffff000|MAS2_I)@l + oris r11,r13,(MAS2_I)@h + ori r11,r13,(MAS2_I)@l mtspr SPRN_MAS2,r11 - lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h - ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l + oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l mtspr SPRN_MAS3,r11 tlbwe bl 1f 1: mflr r11 - addi r11,r11,28 + /* + * OR in 0xfff to create a mask of the bootpg SDRAM address. We use + * this mask to fixup the cpu spin table and the address that we want + * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the + * bootpg is at 0x7ffff000 in SDRAM. + */ + ori r13,r13,0xfff + and r11, r11, r13 + and r10, r10, r13 + + addi r11,r11,(2f-1b) mfmsr r13 ori r12,r13,MSR_IS|MSR_DS@l @@ -200,6 +215,11 @@ __secondary_start_page: mtspr SPRN_SRR1,r13 rfi + /* Allocate some space for the SDRAM address of the bootpg */ + .globl __bootpg_addr +__bootpg_addr: + .long 0 + .align L1_CACHE_SHIFT .globl __spin_table __spin_table: -- 1.6.2.1

2 5

[U-Boot] Request to mailing list U-Boot-Users
by Tien Guo 03 Sep '09

03 Sep '09

*Subscribing to U-Boot* Subscribe to U-Boot by filling out the following form. You will be sent email requesting confirmation, to prevent others from gratuitously subscribing you. This is a private list, which means that the list of members is not available to non-members. Your email address: Your name (optional): You may enter a privacy password below. This provides only mild security, but should prevent others from messing with your subscription. *Do not use a valuable password* as it will occasionally be emailed back to you in cleartext. If you choose not to enter a password, one will be automatically generated for you, and it will be sent to you once you've confirmed your subscription. You can always request a mail-back of your password when you edit your personal options. Pick a password: Reenter password to confirm: Which language do you prefer to display your messages? English (USA) Would you like to receive list mail batched in a daily digest? No Yes

1 0

[U-Boot] HP Jornada flashrom doesnt boot
by Kristoffer Ericson 03 Sep '09

03 Sep '09

Greetings, Im at the state where it compiles nicely (thanks wolfgang!) but doesnt do anything. I am working with an old blob code that I know works and tried to move all the data from there into u-boot. Currently I get no output at all on serial and the handheld itself makes a small humming noise. ANY ideas would be greatly appreciated. According to blob it should use the serial3, do I need to initialize it somehow or is it handled already? The only value I couldnt extract from blob was the MDREFR value, currenyl Im using the value used by assabet. How can I calculate this? I know that the memory/flash size settings arent correct. For example its set for 32MB when Im using 128MB but thought that it wouldnt matter much initially? As Ive said, any suggestions would help alot since Im basicly stuck. Best wishes Kristoffer diff --git a/MAKEALL b/MAKEALL index c8a1f37..f4a52bd 100755 --- a/MAKEALL +++ b/MAKEALL @@ -485,6 +485,7 @@ LIST_SA=" \ gcplus \ lart \ shannon \ + jornada \ " ######################################################################### diff --git a/Makefile b/Makefile index c9727f8..4c1bce5 100644 --- a/Makefile +++ b/Makefile @@ -2716,6 +2716,9 @@ lart_config : unconfig shannon_config : unconfig @$(MKCONFIG) $(@:_config=) arm sa1100 shannon +jornada_config : unconfig + @$(MKCONFIG) $(@:_config=) arm sa1100 jornada + ######################################################################### ## ARM92xT Systems ######################################################################### diff --git a/board/jornada/Makefile b/board/jornada/Makefile new file mode 100644 index 0000000..1b4e192 --- /dev/null +++ b/board/jornada/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# 2004 (c) MontaVista Software, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := jornada.o +SOBJS := setup.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/jornada/config.mk b/board/jornada/config.mk new file mode 100644 index 0000000..c9d9109 --- /dev/null +++ b/board/jornada/config.mk @@ -0,0 +1,7 @@ +# +# SA-1110 based HP Jornada board +# +# The Intel Jornada 1 bank of 32 MiB SDRAM +# + +TEXT_BASE = 0xc1f00000 diff --git a/board/jornada/jornada.c b/board/jornada/jornada.c new file mode 100644 index 0000000..3c30b80 --- /dev/null +++ b/board/jornada/jornada.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <SA-1100.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +static inline u8 +readb(volatile u8 * p) +{ + return *p; +} + +static inline void +writeb(u8 v, volatile u8 * p) +{ + *p = v; +} + +static void jornada_init(void) +{ +} + +int board_init(void) +{ + gd->bd->bi_arch_number = 48; + gd->bd->bi_boot_params = 0xc0000100; + + jornada_init(); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/jornada/setup.S b/board/jornada/setup.S new file mode 100644 index 0000000..a78d1b8 --- /dev/null +++ b/board/jornada/setup.S @@ -0,0 +1,164 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include "config.h" +#include "version.h" + + +/*----------------------------------------------------------------------- + * Board defines: + */ + +#define MDCNFG 0x00 +#define MDCAS00 0x04 +#define MDCAS01 0x08 +#define MDCAS02 0x0C +#define MSC0 0x10 +#define MSC1 0x14 +#define MECR 0x18 +#define MDREFR 0x1C +#define MDCAS20 0x20 +#define MDCAS21 0x24 +#define MDCAS22 0x28 +#define MSC2 0x2C +#define SMCNFG 0x30 + +#define MDCNFG_BANK0_ENABLE (1 << 0) +#define MDCNFG_DTIM0_SDRAM (1 << 2) +#define MDCNFG_DWID0_32B (0 << 3) +#define MDCNFG_DRAC0(n_) (((n_) & 7) << 4) +#define MDCNFG_TRP0(n_) (((n_) & 0xF) << 8) +#define MDCNFG_TDL0(n_) (((n_) & 3) << 12) +#define MDCNFG_TWR0(n_) (((n_) & 3) << 14) +#define MSC_RT_ROMFLASH 0 +#define MSC_RBW32 (0 << 2) +#define MSC_RDF(n_) (((n_) & 0x1f) << 3) +#define MSC_RDN(n_) (((n_) & 0x1f) << 8) +#define MSC_RRR(n_) (((n_) & 0x07) << 13) +#define MSC_RT_VARLAT_345 1 + +#define mdcnfg_1 (MDCNFG_BANK0_ENABLE|MDCNFG_DTIM0_SDRAM|MDCNFG_DWID0_32B|MDCNFG_DRAC0(6)|MDCNFG_TRP0(2)|MDCNFG_TDL0(3)|MDCNFG_TWR0(1)) +#define cs0_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(15)|MSC_RDN(15)|MSC_RRR(2)) +#define cs1_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7)) +#define cs2_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(30)|MSC_RDN(31)|MSC_RRR(7)) +#define cs3_1 (MSC_RT_ROMFLASH|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7)) +#define cs4_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(11)|MSC_RDN(9)|MSC_RRR(1)) +#define cs5_1 (MSC_RT_VARLAT_345|MSC_RBW32|MSC_RDF(3)|MSC_RDN(0)|MSC_RRR(1)) +#define msc0_1 (cs0_1|(cs1_1 << 16)) +#define msc1_1 (cs2_1|(cs3_1 << 16)) +#define msc2_1 (cs4_1|(cs5_1 << 16)) + + + +#define JORNADA_BCR (0x12000000) +#define JORNADA_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) +#define JORNADA_SCR_nNEPONSET (1 << 9) +#define JORNADA_LEDS (0x10000010) + + +/*----------------------------------------------------------------------- + * Setup parameters for the board: + */ + + +MEM_BASE: .long 0xa0000000 +MEM_START: .long 0xc0000000 + +/* calculated from old blob bootloader */ +mdcnfg: .long mdcnfg_1 /* 0x00007265 */ +mdcas00: .long 0x5555557f /* 0x5555557f */ +mdcas01: .long 0x55555555 /* 0x55555555 */ +mdcas02: .long 0x55555555 /* 0x55555555 */ +msc0: .long msc0_1 /* 0xfff04f78 */ +msc1: .long msc1_1 /* 0xfff8fff0 */ +mecr: .long 0x98c698c6 /* 0x98c698c6 */ +mdrefr: .long /* 0x04340327 */ +mdcas20: .long 0xd1284142 /* 0xd1284142 */ +mdcas21: .long 0x72249529 /* 0x72249529 */ +mdcas22: .long 0x78414351 /* 0x78414351 */ +msc2: .long msc2_1 /* 0x201d2959 */ +smcnfg: .long 0x00000000 /* 0x00000000 */ + +BCR: .long JORNADA_BCR +BCR_DB1110: .long JORNADA_BCR_DB1110 +LEDS: .long JORNADA_LEDS + + + .globl lowlevel_init +lowlevel_init: + + /* Setting up the memory and stuff */ + + ldr r0, MEM_BASE + ldr r1, mdcas00 + str r1, [r0, #MDCAS00] + ldr r1, mdcas01 + str r1, [r0, #MDCAS01] + ldr r1, mdcas02 + str r1, [r0, #MDCAS02] + ldr r1, mdcas20 + str r1, [r0, #MDCAS20] + ldr r1, mdcas21 + str r1, [r0, #MDCAS21] + ldr r1, mdcas22 + str r1, [r0, #MDCAS22] + ldr r1, mdrefr + str r1, [r0, #MDREFR] + ldr r1, mecr + str r1, [r0, #MECR] + ldr r1, msc0 + str r1, [r0, #MSC0] + ldr r1, msc1 + str r1, [r0, #MSC1] + ldr r1, msc2 + str r1, [r0, #MSC2] + ldr r1, smcnfg + str r1, [r0, #SMCNFG] + + ldr r1, mdcnfg + str r1, [r0, #MDCNFG] + + /* Load something to activate bank */ + ldr r2, MEM_START +.rept 8 + ldr r3, [r2] +.endr + + /* Enable SDRAM */ + orr r1, r1, #0x00000001 + str r1, [r0, #MDCNFG] + + ldr r1, BCR + ldr r2, BCR_DB1110 + str r2, [r1] + + ldr r1, LEDS + mov r0, #0x3 + str r0, [r1] + + /* All done... */ + mov pc, lr diff --git a/board/jornada/u-boot.lds b/board/jornada/u-boot.lds new file mode 100644 index 0000000..de6101e --- /dev/null +++ b/board/jornada/u-boot.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * 2004 (c) MontaVista Software, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/sa1100/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/include/configs/jornada.h b/include/configs/jornada.h new file mode 100644 index 0000000..76c9020 --- /dev/null +++ b/include/configs/jornada.h @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * 2004 (c) MontaVista Software, Inc. + * + * Configuation settings for the Intel Assabet board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SA1110 1 /* This is an SA1100 CPU */ +#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 */ + +#undef CONFIG_USE_IRQ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ + +/* + * select serial console configuration + */ +#define CONFIG_SA1100_SERIAL +#define CONFIG_SERIAL3 1 /* needed? */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 19200 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" +#define CONFIG_BOOTCOMMAND "bootp;bootm" +#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "HP Jornada # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */ + +#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */ + + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_RAMSTART +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE +#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ +#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ +#undef CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_ENV_IS_IN_FLASH 1 + +#if defined(CONFIG_ENV_IS_IN_FLASH) +#define CONFIG_ENV_IN_OWN_SECTOR 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) +#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#endif + +#endif /* __CONFIG_H */ -- Kristoffer Ericson <kristoffer.ericson(a)gmail.com>

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[U-Boot] RTLWS11 / XUM-2009, 28-30 September, TU-Dresden - Call for Participation
by Wolfgang Denk 03 Sep '09

03 Sep '09

Hello, I apologize in advance if you should consider this message off topic; please feel free to ignore it. I'm reposting it here as a number af U-Boot developers happen to be present at XUM-2009 (including myself), so just in case you don't have anything better to do... ------- Forwarded Message Date: Thu, 03 Sep 2009 12:58:07 +0200 From: Wolfgang Denk <wd(a)denx.de> To: Xenomai Help <xenomai-help(a)gna.org>, Xenomai Core <xenomai-core(a)gna.org> cc: Nicholas Mc Guire <mcguire(a)lzu.edu.cn> Subject: RTLWS11 / XUM-2009, 28-30 September, TU-Dresden - Call for Participation CALL FOR PARTICIPATION The 11th Real Time Linux Workshop Xenomai User Meeting 2009 September 28 to 30, 2009 Technische Universitaet Dresden Faculty of Computer Science Chair of Operating Systems (TUDOS) Dresden, Germany http://www.realtimelinuxfoundation.org/events/rtlws-2009/ws.html The 11th Real Time Linux Workshop, held at the Technische Universitaet Dresden, Germany, from September 28-30 this year will bring together many of the Real Time Linux developers from all of the Real Time Linux Variants. This workshop will feature a RT-Preempt track held by key RT-preempt developers, a broad spectrum of presentation on existing Real Time Linux variants as well as applications utilizing Embedded and Real Time Linux Further we plan hands-on sessions on key Real Time Linux systems. RTLWS Agenda: http://www.osadl.org/RTLWS-Agenda.rtlws11-agenda.0.html Registration: http://www.osadl.org/RTLWS11-Registration.form.0.html Hotel Infos: http://www.osadl.org/RTLWS-Hotels.rtlws11-hotels.0.html -- Nicholas Mc Guire <mcguire(a)lzu.edu.cn> At the same time the Xenomai User Meeting 2009 will be held in close proximity to RTLWS11 - details can be found at: General Infos: http://www.denx.de/en/News/XenomaiUserMeeting2009 XUM-2009 Agenda: http://www.denx.de/en/view/News/XenomaiUserMeeting2009#Agenda XUM-2009 Abstracts: http://www.denx.de/en-edit/News/Xum2009Abstracts Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Computers are not intelligent. They only think they are. ------- End of Forwarded Message Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Imagination is more important than knowledge. -- Albert Einstein

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[U-Boot] HP Jornada 720 flashrom
by Kristoffer Ericson 03 Sep '09

03 Sep '09

Greetings, Trying to get my Flashrom working (previously used blob with it). I get this now : c -Map u-boot.map -o u-boot net/libnet.a(net.o)(.text+0x1cc): In function `ArpRequest': /home/kristoffer/work/projects/u-boot.git/net/net.c:250: undefined reference to `eth_send' net/libnet.a(net.o)(.text+0x29c): In function `NetStartAgain': /home/kristoffer/work/projects/u-boot.git/net/net.c:568: undefined reference to `eth_halt' net/libnet.a(net.o)(.text+0x370): In function `NetSendPacket': /home/kristoffer/work/projects/u-boot.git/net/net.c:623: undefined reference to `eth_send' net/libnet.a(net.o)(.text+0x634): In function `NetSendUDPPacket': /home/kristoffer/work/projects/u-boot.git/net/net.c:668: undefined reference to `eth_send' net/libnet.a(net.o)(.text+0x910): In function `NetReceive': /home/kristoffer/work/projects/u-boot.git/net/net.c:1263: undefined reference to `eth_send' net/libnet.a(net.o)(.text+0x98c):/home/kristoffer/work/projects/u-boot.git/net/net.c:1295: undefined reference to `eth_send' net/libnet.a(net.o)(.text+0xf04): In function `NetLoop': /home/kristoffer/work/projects/u-boot.git/net/net.c:342: undefined reference to `eth_halt' net/libnet.a(net.o)(.text+0xf0c):/home/kristoffer/work/projects/u-boot.git/net/net.c:346: undefined reference to `eth_init' net/libnet.a(net.o)(.text+0x101c):/home/kristoffer/work/projects/u-boot.git/net/net.c:370: undefined reference to `eth_halt' net/libnet.a(net.o)(.text+0x10ac):/home/kristoffer/work/projects/u-boot.git/net/net.c:481: undefined reference to `eth_halt' net/libnet.a(net.o)(.text+0x10cc):/home/kristoffer/work/projects/u-boot.git/net/net.c:475: undefined reference to `eth_rx' net/libnet.a(net.o)(.text+0x11a4):/home/kristoffer/work/projects/u-boot.git/net/net.c:535: undefined reference to `eth_halt' make: *** [u-boot] Fel 1 My device shouldnt be using those at all so its no wonder that they are undefined, but the question is how I should get rid of those messages. Best wishes Kristoffer -- Kristoffer Ericson <kristoffer.ericson(a)gmail.com>

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