February 2009 - U-Boot

[U-Boot] [PATCH] 5/12 Multiadapter/multibus I2C, drivers part 2, fixed
by ksi＠koi8.net 13 Feb '09

13 Feb '09

Initial multiadapter/multibus I2C support. Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/drivers/i2c/omap1510_i2c.c u-boot-i2c/drivers/i2c/omap1510_i2c.c --- u-boot-i2c.orig/drivers/i2c/omap1510_i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/drivers/i2c/omap1510_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -1,4 +1,8 @@ /* + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * * Basic I2C functions * * Copyright (c) 2003 Texas Instruments @@ -19,11 +23,51 @@ */ #include <common.h> +#include <i2c.h> + +i2c_adap_t omap1510_i2c_adap; + +DECLARE_GLOBAL_DATA_PTR; + +static void wait_for_bb (void) +{ + int timeout = 10; + + while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { + inw (I2C_IV); + udelay (1000); + } + + if (timeout <= 0) { + printf ("timed out in wait_for_bb: I2C_STAT=%x\n", + inw (I2C_STAT)); + } +} + +static u16 wait_for_pin (void) +{ + u16 status, iv; + int timeout = 10; + + do { + udelay (1000); + status = inw (I2C_STAT); + iv = inw (I2C_IV); + } while (!iv && + !(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf ("timed out in wait_for_pin: I2C_STAT=%x\n", + inw (I2C_STAT)); + } -static void wait_for_bb (void); -static u16 wait_for_pin (void); + return status; +} -void i2c_init (int speed, int slaveadd) +static void omap1510_i2c_init (int speed, int slaveadd) { u16 scl; @@ -46,6 +90,10 @@ void i2c_init (int speed, int slaveadd) outw (slaveadd, I2C_OA); outw (0, I2C_CNT); udelay (1000); + + if (gd->flags & GD_FLG_RELOC) { + omap1510_i2c_adap.init_done = 1; + } } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -158,7 +206,7 @@ static int i2c_write_byte (u8 devaddr, u return i2c_error; } -int i2c_probe (uchar chip) +static int omap1510_i2c_probe (uchar chip) { int res = 1; @@ -188,24 +236,24 @@ int i2c_probe (uchar chip) return res; } -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +static int omap1510_i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("%s: address out of range\n", __FUNCTION__); return 1; } for (i = 0; i < len; i++) { if (i2c_read_byte (chip, addr + i, &buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + printf ("%s: I/O error\n", __FUNCTION__); + i2c_init (CONFIG_SYS_OMAP1510_I2C_SPEED, CONFIG_SYS_OMAP1510_I2C_SLAVE); return 1; } } @@ -213,24 +261,24 @@ int i2c_read (uchar chip, uint addr, int return 0; } -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +static int omap1510_i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("%s: address out of range\n", __FUNCTION__); return 1; } for (i = 0; i < len; i++) { if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + printf ("%s: I/O error\n", __FUNCTION__); + i2c_init (CONFIG_SYS_OMAP1510_I2C_SPEED, CONFIG_SYS_OMAP1510_I2C_SLAVE); return 1; } } @@ -238,40 +286,25 @@ int i2c_write (uchar chip, uint addr, in return 0; } -static void wait_for_bb (void) +static unsigned int omap1510_i2c_set_bus_speed(unsigned int speed) { - int timeout = 10; - - while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - inw (I2C_IV); - udelay (1000); - } - - if (timeout <= 0) { - printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - inw (I2C_STAT)); - } + return(omap1510_i2c_adap.speed); } -static u16 wait_for_pin (void) +static unsigned int omap1510_i2c_get_bus_speed(void) { - u16 status, iv; - int timeout = 10; - - do { - udelay (1000); - status = inw (I2C_STAT); - iv = inw (I2C_IV); - } while (!iv && - !(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); - - if (timeout <= 0) { - printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - inw (I2C_STAT)); - } - - return status; + return(omap1510_i2c_adap.speed); } + +i2c_adap_t omap1510_i2c_adap = { + .init = omap1510_i2c_init, + .probe = omap1510_i2c_probe, + .read = omap1510_i2c_read, + .write = omap1510_i2c_write, + .set_bus_speed = omap1510_i2c_set_bus_speed, + .get_bus_speed = omap1510_i2c_get_bus_speed, + .speed = CONFIG_SYS_OMAP1510_I2C_SPEED, + .slaveaddr = CONFIG_SYS_OMAP1510_I2C_SLAVE, + .init_done = 0, + .name = "omap1510_i2c" +}; diff -purN u-boot-i2c.orig/drivers/i2c/omap24xx_i2c.c u-boot-i2c/drivers/i2c/omap24xx_i2c.c --- u-boot-i2c.orig/drivers/i2c/omap24xx_i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/drivers/i2c/omap24xx_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -1,4 +1,8 @@ /* + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * * Basic I2C functions * * Copyright (c) 2004 Texas Instruments @@ -24,65 +28,134 @@ #include <asm/arch/i2c.h> #include <asm/io.h> +#include <i2c.h> -static void wait_for_bb (void); -static u16 wait_for_pin (void); -static void flush_fifo(void); +#define OMAP24XX_NAME(arg) "omap24xx_i2c@" MK_NAME(arg) +#define MK_NAME(arg) #arg + +#ifndef CONFIG_SYS_OMAP24XX_I2C_BASE +#define CONFIG_SYS_OMAP24XX_I2C_BASE I2C_BASE1 +#endif -void i2c_init (int speed, int slaveadd) +i2c_adap_t omap24xx_i2c_adap[]; + +DECLARE_GLOBAL_DATA_PTR; + +static void flush_fifo(ulong base) +{ + u16 stat; + + /* note: if you try and read data when its not there or ready + * you get a bus error + */ + while(1){ + stat = readw(base + I2C_STAT); + if(stat == I2C_STAT_RRDY){ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + readb(base + I2C_DATA); +#else + readw(base + I2C_DATA); +#endif + writew(I2C_STAT_RRDY, base + I2C_STAT); + udelay(1000); + }else + break; + } +} + +static void wait_for_bb (ulong base) +{ + int timeout = 10; + u16 stat; + + writew(0xFFFF, base + I2C_STAT); /* clear current interruts...*/ + while ((stat = readw (base + I2C_STAT) & I2C_STAT_BB) && timeout--) { + writew (stat, base + I2C_STAT); + udelay (50000); + } + + if (timeout <= 0) { + printf ("timed out in wait_for_bb: I2C_STAT=%x\n", + readw (base + I2C_STAT)); + } + writew(0xFFFF, base + I2C_STAT); /* clear delayed stuff*/ +} + +static u16 wait_for_pin (ulong base) +{ + u16 status; + int timeout = 10; + + do { + udelay (1000); + status = readw (base + I2C_STAT); + } while ( !(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf ("timed out in wait_for_pin: I2C_STAT=%x\n", + readw (base + I2C_STAT)); + writew(0xFFFF, base + I2C_STAT); + } + return status; +} + +static void _i2c_init (int speed, int slaveadd, ulong base) { u16 scl; - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, base + I2C_SYSC); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, base + I2C_SYSC); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); + if (readw (base + I2C_CON) & I2C_CON_EN) { + writew (0, base + I2C_CON); udelay (50000); } /* 12MHz I2C module clock */ - writew (0, I2C_PSC); + writew (0, base + I2C_PSC); speed = speed/1000; /* 100 or 400 */ scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - writew (scl, I2C_SCLL); - writew (scl, I2C_SCLH); + writew (scl, base + I2C_SCLL); + writew (scl, base + I2C_SCLH); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, base + I2C_OA); + writew (I2C_CON_EN, base + I2C_CON); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, base + I2C_IE); udelay (1000); - flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + flush_fifo(base); + writew (0xFFFF, base + I2C_STAT); + writew (0, base + I2C_CNT); } -static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) +static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value, ulong base) { int i2c_error = 0; u16 status; /* wait until bus not busy */ - wait_for_bb (); + wait_for_bb (base); /* one byte only */ - writew (1, I2C_CNT); + writew (1, base + I2C_CNT); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, base + I2C_SA); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, base + I2C_CON); - status = wait_for_pin (); + status = wait_for_pin (base); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, base + I2C_DATA); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (base + I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -91,28 +164,29 @@ static int i2c_read_byte (u8 devaddr, u8 if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, base + I2C_CON); + while (readw (base + I2C_STAT) || + (readw (base + I2C_CON) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, base + I2C_STAT); } - wait_for_bb (); + wait_for_bb (base); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, base + I2C_SA); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, base + I2C_CNT); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + base + I2C_CON); - status = wait_for_pin (); + status = wait_for_pin (base); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (base + I2C_DATA); #else - *value = readw (I2C_DATA); + *value = readw (base + I2C_DATA); #endif udelay (20000); } else { @@ -120,60 +194,60 @@ static int i2c_read_byte (u8 devaddr, u8 } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, base + I2C_CON); + while (readw (base + I2C_STAT) + || (readw (base + I2C_CON) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, base + I2C_STAT); } } } - flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + flush_fifo(base); + writew (0xFFFF, base + I2C_STAT); + writew (0, base + I2C_CNT); return i2c_error; } -static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) +static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value, ulong base) { int i2c_error = 0; u16 status, stat; /* wait until bus not busy */ - wait_for_bb (); + wait_for_bb (base); /* two bytes */ - writew (2, I2C_CNT); + writew (2, base + I2C_CNT); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, base + I2C_SA); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, base + I2C_CON); /* wait until state change */ - status = wait_for_pin (); + status = wait_for_pin (base); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, base + I2C_DATA); + writew (I2C_STAT_XRDY, base + I2C_STAT); - status = wait_for_pin (); + status = wait_for_pin (base); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, base + I2C_DATA); + writew (I2C_STAT_XRDY, base + I2C_STAT); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, base + I2C_DATA); #endif /* must have enough delay to allow BB bit to go low */ udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (base + I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -183,96 +257,96 @@ static int i2c_write_byte (u8 devaddr, u if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, base + I2C_CON); + while ((stat = readw (base + I2C_STAT)) || + (readw (base + I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, base + I2C_STAT); if(--eout == 0) /* better leave with error than hang */ break; } } - flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + flush_fifo(base); + writew (0xFFFF, base + I2C_STAT); + writew (0, base + I2C_CNT); return i2c_error; } -static void flush_fifo(void) -{ u16 stat; - - /* note: if you try and read data when its not there or ready - * you get a bus error - */ - while(1){ - stat = readw(I2C_STAT); - if(stat == I2C_STAT_RRDY){ -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); -#else - readw(I2C_DATA); -#endif - writew(I2C_STAT_RRDY,I2C_STAT); - udelay(1000); - }else - break; - } -} -int i2c_probe (uchar chip) +static int _i2c_probe (uchar chip, ulong base) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (base + I2C_OA)) { return res; } /* wait until bus not busy */ - wait_for_bb (); + wait_for_bb (base); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, base + I2C_CNT); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, base + I2C_SA); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, base + I2C_CON); /* enough delay for the NACK bit set */ udelay (50000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (base + I2C_STAT) & I2C_STAT_NACK)) { res = 0; /* success case */ - flush_fifo(); - writew(0xFFFF, I2C_STAT); + flush_fifo(base); + writew(0xFFFF, base + I2C_STAT); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, base + I2C_STAT); /* failure, clear sources*/ + writew (readw (base + I2C_CON) | I2C_CON_STP, base + I2C_CON); /* finish up xfer */ udelay(20000); - wait_for_bb (); + wait_for_bb (base); } - flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + flush_fifo(base); + writew (0, base + I2C_CNT); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, base + I2C_STAT); return res; } -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) + +static void omap24xx_i2c_init (int speed, int slaveadd) +{ + _i2c_init(speed, slaveadd, CONFIG_SYS_OMAP24XX_I2C_BASE); + + if (gd->flags & GD_FLG_RELOC) { + omap24xx_i2c_adap[0].speed = speed; + omap24xx_i2c_adap[0].slaveaddr = slaveadd; + omap24xx_i2c_adap[0].init_done = 1; + } +} + +static int omap24xx_i2c_probe (uchar chip) +{ + return(_i2c_probe(chip, CONFIG_SYS_OMAP24XX_I2C_BASE)); +} + +static int omap24xx_i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("%s: address out of range\n", __FUNCTION__); return 1; } for (i = 0; i < len; i++) { - if (i2c_read_byte (chip, addr + i, &buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (i2c_read_byte (chip, addr + i, &buffer[i], CONFIG_SYS_OMAP24XX_I2C_BASE)) { + printf ("%s: I/O error\n", __FUNCTION__); + _i2c_init (CONFIG_SYS_OMAP24XX_I2C_SPEED, + CONFIG_SYS_OMAP24XX_I2C_SLAVE, + CONFIG_SYS_OMAP24XX_I2C_BASE); return 1; } } @@ -280,24 +354,26 @@ int i2c_read (uchar chip, uint addr, int return 0; } -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +static int omap24xx_i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("%s: address out of range\n", __FUNCTION__); return 1; } for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (i2c_write_byte (chip, addr + i, buffer[i], CONFIG_SYS_OMAP24XX_I2C_BASE)) { + printf ("%s: I/O error\n", __FUNCTION__); + _i2c_init (CONFIG_SYS_OMAP24XX_I2C_SPEED, + CONFIG_SYS_OMAP24XX_I2C_SLAVE, + CONFIG_SYS_OMAP24XX_I2C_BASE); return 1; } } @@ -305,41 +381,219 @@ int i2c_write (uchar chip, uint addr, in return 0; } -static void wait_for_bb (void) +static unsigned int omap24xx_i2c_set_bus_speed(unsigned int speed) { - int timeout = 10; - u16 stat; + return(omap24xx_i2c_adap[0].speed); +} - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); - udelay (50000); +static unsigned int omap24xx_i2c_get_bus_speed(void) +{ + return(omap24xx_i2c_adap[0].speed); +} + +#ifdef CONFIG_SYS_OMAP24XX_I2C2_BASE +static void omap24xx_i2c2_init (int speed, int slaveadd) +{ + _i2c_init(speed, slaveadd, CONFIG_SYS_OMAP24XX_I2C2_BASE); + + if (gd->flags & GD_FLG_RELOC) { + omap24xx_i2c_adap[1].speed = speed; + omap24xx_i2c_adap[1].slaveaddr = slaveadd; + omap24xx_i2c_adap[1].init_done = 1; + } +} + +static int omap24xx_i2c2_probe (uchar chip) +{ + return(_i2c_probe(chip, CONFIG_SYS_OMAP24XX_I2C2_BASE)); +} + +static int omap24xx_i2c2_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); + return 1; } - if (timeout <= 0) { - printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + if (addr + len > 256) { + printf ("%s: address out of range\n", __FUNCTION__); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte (chip, addr + i, &buffer[i], CONFIG_SYS_OMAP24XX_I2C2_BASE)) { + printf ("%s: I/O error\n", __FUNCTION__); + _i2c_init (CONFIG_SYS_OMAP24XX_I2C2_SPEED, + CONFIG_SYS_OMAP24XX_I2C2_SLAVE, + CONFIG_SYS_OMAP24XX_I2C2_BASE); + return 1; + } } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + + return 0; } -static u16 wait_for_pin (void) +static int omap24xx_i2c2_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { - u16 status; - int timeout = 10; + int i; - do { - udelay (1000); - status = readw (I2C_STAT); - } while ( !(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); + if (alen > 1) { + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); + return 1; + } - if (timeout <= 0) { - printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + if (addr + len > 256) { + printf ("%s: address out of range\n", __FUNCTION__); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte (chip, addr + i, buffer[i], CONFIG_SYS_OMAP24XX_I2C2_BASE)) { + printf ("%s: I/O error\n", __FUNCTION__); + _i2c_init (CONFIG_SYS_OMAP24XX_I2C2_SPEED, + CONFIG_SYS_OMAP24XX_I2C2_SLAVE, + CONFIG_SYS_OMAP24XX_I2C2_BASE); + return 1; + } + } + + return 0; } - return status; + +static unsigned int omap24xx_i2c2_set_bus_speed(unsigned int speed) +{ + return(omap24xx_i2c_adap[1].speed); +} + +static unsigned int omap24xx_i2c2_get_bus_speed(void) +{ + return(omap24xx_i2c_adap[1].speed); +} +#endif + +#ifdef CONFIG_SYS_OMAP24XX_I2C3_BASE +static void omap24xx_i2c3_init (int speed, int slaveadd) +{ + _i2c_init(speed, slaveadd, CONFIG_SYS_OMAP24XX_I2C3_BASE); + + if (gd->flags & GD_FLG_RELOC) { + omap24xx_i2c_adap[2].speed = speed; + omap24xx_i2c_adap[2].slaveaddr = slaveadd; + omap24xx_i2c_adap[2].init_done = 1; + } +} + +static int omap24xx_i2c3_probe (uchar chip) +{ + return(_i2c_probe(chip, CONFIG_SYS_OMAP24XX_I2C3_BASE)); } + +static int omap24xx_i2c3_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); + return 1; + } + + if (addr + len > 256) { + printf ("%s: address out of range\n", __FUNCTION__); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte (chip, addr + i, &buffer[i], CONFIG_SYS_OMAP24XX_I2C3_BASE)) { + printf ("%s: I/O error\n", __FUNCTION__); + _i2c_init (CONFIG_SYS_OMAP24XX_I2C3_SPEED, + CONFIG_SYS_OMAP24XX_I2C3_SLAVE, + CONFIG_SYS_OMAP24XX_I2C3_BASE); + return 1; + } + } + + return 0; +} + +static int omap24xx_i2c3_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("%s: addr len %d not supported\n", __FUNCTION__, alen); + return 1; + } + + if (addr + len > 256) { + printf ("%s: address out of range\n", __FUNCTION__); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte (chip, addr + i, buffer[i], CONFIG_SYS_OMAP24XX_I2C3_BASE)) { + printf ("%s: I/O error\n", __FUNCTION__); + _i2c_init (CONFIG_SYS_OMAP24XX_I2C3_SPEED, + CONFIG_SYS_OMAP24XX_I2C3_SLAVE, + CONFIG_SYS_OMAP24XX_I2C3_BASE); + return 1; + } + } + + return 0; +} + +static unsigned int omap24xx_i2c3_set_bus_speed(unsigned int speed) +{ + return(omap24xx_i2c_adap[2].speed); +} + +static unsigned int omap24xx_i2c3_get_bus_speed(void) +{ + return(omap24xx_i2c_adap[2].speed); +} +#endif + +i2c_adap_t omap24xx_i2c_adap[3] = { + { + .init = omap24xx_i2c_init, + .probe = omap24xx_i2c_probe, + .read = omap24xx_i2c_read, + .write = omap24xx_i2c_write, + .set_bus_speed = omap24xx_i2c_set_bus_speed, + .get_bus_speed = omap24xx_i2c_get_bus_speed, + .speed = CONFIG_SYS_OMAP24XX_I2C_SPEED, + .slaveaddr = CONFIG_SYS_OMAP24XX_I2C_SLAVE, + .init_done = 0, + .name = OMAP24XX_NAME(CONFIG_SYS_OMAP24XX_I2C_BASE) + }, +#ifdef CONFIG_SYS_OMAP24XX_I2C2_BASE + { + .init = omap24xx_i2c2_init, + .probe = omap24xx_i2c2_probe, + .read = omap24xx_i2c2_read, + .write = omap24xx_i2c2_write, + .set_bus_speed = omap24xx_i2c2_set_bus_speed, + .get_bus_speed = omap24xx_i2c2_get_bus_speed, + .speed = CONFIG_SYS_OMAP24XX_I2C2_SPEED, + .slaveaddr = CONFIG_SYS_OMAP24XX_I2C2_SLAVE, + .init_done = 0, + .name = OMAP24XX_NAME(CONFIG_SYS_OMAP24XX_I2C2_BASE) + }, +#endif +#ifdef CONFIG_SYS_OMAP24XX_I2C3_BASE + { + .init = omap24xx_i2c3_init, + .probe = omap24xx_i2c3_probe, + .read = omap24xx_i2c3_read, + .write = omap24xx_i2c3_write, + .set_bus_speed = omap24xx_i2c3_set_bus_speed, + .get_bus_speed = omap24xx_i2c3_get_bus_speed, + .speed = CONFIG_SYS_OMAP24XX_I2C3_SPEED, + .slaveaddr = CONFIG_SYS_OMAP24XX_I2C3_SLAVE, + .init_done = 0, + .name = OMAP24XX_NAME(CONFIG_SYS_OMAP24XX_I2C3_BASE) + } +#endif +}; diff -purN u-boot-i2c.orig/drivers/i2c/tsi108_i2c.c u-boot-i2c/drivers/i2c/tsi108_i2c.c --- u-boot-i2c.orig/drivers/i2c/tsi108_i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/drivers/i2c/tsi108_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -1,4 +1,8 @@ /* + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * * (C) Copyright 2004 Tundra Semiconductor Corp. * Author: Alex Bounine * @@ -26,8 +30,7 @@ #include <common.h> #include <tsi108.h> - -#if defined(CONFIG_CMD_I2C) +#include <i2c.h> #define I2C_DELAY 100000 #undef DEBUG_I2C @@ -38,6 +41,8 @@ #define DPRINT(x) #endif +i2c_adap_t tsi108_i2c_adap; + /* All functions assume that Tsi108 I2C block is the only master on the bus */ /* I2C read helper function */ @@ -132,7 +137,7 @@ static int i2c_read_byte ( * Returns: 0 on success, not 0 on failure */ -int i2c_read (uchar chip_addr, uint byte_addr, int alen, +static int tsi108_i2c_read (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) { u32 op_status = TSI108_I2C_PARAM_ERR; @@ -238,7 +243,7 @@ static int i2c_write_byte (uchar chip_ad * Returns: 0 on success, not 0 on failure */ -int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, +static int tsi108_i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len) { u32 op_status = TSI108_I2C_PARAM_ERR; @@ -266,7 +271,7 @@ int i2c_write (uchar chip_addr, uint byt * Returns 0 if a chip responded, not 0 on failure. */ -int i2c_probe (uchar chip) +static int tsi108_i2c_probe (uchar chip) { u32 tmp; @@ -278,4 +283,31 @@ int i2c_probe (uchar chip) return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); } -#endif +static unsigned int tsi108_i2c_set_bus_speed(unsigned int speed) +{ + return(tsi108_i2c_adap.speed); +} + +static unsigned int tsi108_i2c_get_bus_speed(void) +{ + return(tsi108_i2c_adap.speed); +} + +static void tsi108_i2c_init(int speed, int slaveaddr) +{ + /* Dummy */ +} + +i2c_adap_t tsi108_i2c_adap = { + .init = tsi108_i2c_init, + .probe = tsi108_i2c_probe, + .read = tsi108_i2c_read, + .write = tsi108_i2c_write, + .set_bus_speed = tsi108_i2c_set_bus_speed, + .get_bus_speed = tsi108_i2c_get_bus_speed, + .speed = CONFIG_SYS_TSI108_I2C_SPEED, + .slaveaddr = CONFIG_SYS_TSI108_I2C_SLAVE, + .init_done = 0, + .name = "tsi108_i2c" +}; + diff -purN u-boot-i2c.orig/include/asm-arm/arch-omap24xx/i2c.h u-boot-i2c/include/asm-arm/arch-omap24xx/i2c.h --- u-boot-i2c.orig/include/asm-arm/arch-omap24xx/i2c.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/asm-arm/arch-omap24xx/i2c.h 2009-02-12 10:46:00.000000000 -0800 @@ -23,24 +23,24 @@ #ifndef _OMAP24XX_I2C_H_ #define _OMAP24XX_I2C_H_ -#define I2C_BASE 0x48070000 +#define I2C_BASE1 0x48070000 #define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_SYSC (I2C_BASE + 0x20) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) +#define I2C_REV (0x00) +#define I2C_IE (0x04) +#define I2C_STAT (0x08) +#define I2C_IV (0x0c) +#define I2C_BUF (0x14) +#define I2C_CNT (0x18) +#define I2C_DATA (0x1c) +#define I2C_SYSC (0x20) +#define I2C_CON (0x24) +#define I2C_OA (0x28) +#define I2C_SA (0x2c) +#define I2C_PSC (0x30) +#define I2C_SCLL (0x34) +#define I2C_SCLH (0x38) +#define I2C_SYSTEST (0x3c) /* I2C masks */ diff -purN u-boot-i2c.orig/include/asm-arm/arch-omap3/i2c.h u-boot-i2c/include/asm-arm/arch-omap3/i2c.h --- u-boot-i2c.orig/include/asm-arm/arch-omap3/i2c.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/asm-arm/arch-omap3/i2c.h 2009-02-12 10:46:00.000000000 -0800 @@ -20,26 +20,24 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _I2C_H_ -#define _I2C_H_ +#ifndef _OMAP3_I2C_H_ +#define _OMAP3_I2C_H_ -#define I2C_DEFAULT_BASE I2C_BASE1 - -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) +#define I2C_REV (0x00) +#define I2C_IE (0x04) +#define I2C_STAT (0x08) +#define I2C_IV (0x0c) +#define I2C_BUF (0x14) +#define I2C_CNT (0x18) +#define I2C_DATA (0x1c) +#define I2C_SYSC (0x20) +#define I2C_CON (0x24) +#define I2C_OA (0x28) +#define I2C_SA (0x2c) +#define I2C_PSC (0x30) +#define I2C_SCLL (0x34) +#define I2C_SCLH (0x38) +#define I2C_SYSTEST (0x3c) /* I2C masks */ @@ -125,4 +123,4 @@ #define I2C_PSC_MAX 0x0f #define I2C_PSC_MIN 0x00 -#endif /* _I2C_H_ */ +#endif /* _OMAP3_I2C_H_ */

1 0

[U-Boot] [PATCH v2 0/5] Add multi-chips support for NAND, FSL-UPM and TQM8548
by Wolfgang Grandegger 13 Feb '09

13 Feb '09

The following patch series intends to support the Micron multi-chip NAND device MT29F8G08FAB on the TQM8548 modules from TQ-Components. To offer this multi-chip device as one single device to the user, multi-chip device has been added to the MTD NAND layer and the FSL-UPM-NAND driver. The TQM8548 support is based on the following patch series sent a few minutes ago: [PATCH 0/8] MPC85xx: Support for TQM8548-AG and TQM8548-BE Wolfgang.

2 10

[U-Boot] NAND issues
by Derek Ou 13 Feb '09

13 Feb '09

I have a few issues/questions regarding the NAND commands in the latest git main tree. 1) The nand_util.c does not have WATCHDOG_RESET() in the nand_read_skip_bad() and nand_write_skip_bad() while the original nand_write_opts() and nand_read_opts() do. Is there a special reason this is removed? It's likely that watchdog will fail when trying to read/write large files from NAND. 2) "nand write.jffs2" used to allow writing non page-aligned data. So we can have scripts like "tftp 0x22000000 u-boot.bin" and "nand write.jffs2 0x22000000 0x20000 $(filesize)" to automate downloading files to NAND. Now, "nand write(.jffs2)" and nand_write_skip_bad() rejects non page-aligned write. I think we have to either pad the binary file to page-aligned or re-write nand_write_skip_bad(). Is there another way/parameter to write non page-aligned data? 3) In common/cmd_nand.c, nand_load_image() starting at at line 492 call nand_read() at line 514 and line 547. Does it mean that nand_load_image() will read NAND bad blocks? Should they be nand_read_skip_bad() instead? Especially, line 546 has this comment /* FIXME: skip bad blocks */ Thanks, Derek

2 1

[U-Boot] address of boot_params and kernel entry point
by Iram Shahzad 13 Feb '09

13 Feb '09

Hi Why does most of the existing configurations use such addresses as: For passing boot_params gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; Why + 0x100 and not just PHYS_SDRAM? Similarly for Linux kernel load address PHYS_SDRAM + 0x8000 Why + 0x8000? I think by doing this the following areas are unused, please correct me if I am wrong. PHYS_SDRAM to PHYS_SDRAM+0x100 PHYS_SDRAM+0x100+boot_param_len to PHYS_SDRAM+0x8000 Just want to make sure if I am missing something. Best regards Iram

1 0

[U-Boot] [U-BOOT][PATCH 0/3] mflash u-boot support
by unsik Kim 13 Feb '09

13 Feb '09

Hello? The following patch series support mflash for u-boot. [U-BOOT][PATCH 1/3] Initial mflash support [U-BOOT][PATCH 2/3] Change CONFIG_MG_DISK_RES unit to KB [U-BOOT][PATCH 3/3] Fix miscalculated total sectors Previous patches I posted were wrong(line wrapped, not rebased and so on). Please ignore all the mflash related previous patches. <57afda040901052341g3b00f741r445c0ce8d33b7b71(a)mail.gmail.com> <57afda040902020032h760174adja5ecba853ef6863b(a)mail.gmail.com> <57afda040902092222l2bb9027bvbebf67795a7add3a(a)mail.gmail.com> Signed-off-by: unsik Kim <donari75(a)gmail.com> unsik Kim

1 0

[U-Boot] git setlocalversion
by Derek Ou 13 Feb '09

13 Feb '09

Our company uses svn for the source code management but I use git locally to track my development. When I build U-boot, it always complains about "fatal: cannot describe" the SHA1 # of HEAD. It goes back to line 16 of tools/setlocalversion. I know that the error will go away when I tag my git HEAD. But what is the philosophy of this setlocalversion? Should I always tag the top commit of my git tree to maintain a clean U_BOOT_VERSION define? Derek

2 1

[U-Boot] 12/12 Multiadapter/multibus I2C, configs part 5
by ksi＠koi8.net 12 Feb '09

12 Feb '09

Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/include/configs/mgcoge.h u-boot-i2c/include/configs/mgcoge.h --- u-boot-i2c.orig/include/configs/mgcoge.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/mgcoge.h 2009-02-12 10:46:00.000000000 -0800 @@ -62,6 +62,7 @@ * must be unset. */ #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ +#define CONFIG_NET_MULTI /* ether_scc.c won't compile otherwise */ #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ @@ -142,14 +143,21 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 1 +#define CONFIG_SYS_NUM_I2C_BUSSES 3 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} +#define CONFIG_SYS_I2C_BUSSES { {0, {I2C_NULL_HOP}}, \ + {0, {{I2C_MUX_PCA9542, 0x70, 0}}}, \ + {0, {{I2C_MUX_PCA9542, 0x70, 1}}}} /* * Software (bit-bang) I2C driver configuration */ - #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) @@ -160,11 +168,10 @@ else iop->pdat &= ~0x00020000 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_CMD_TREE 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 +/* I2C_INIT_BOARD specific... */ #define CONFIG_SYS_I2C_INIT_BOARD 1 -#define CONFIG_I2C_MUX 1 +#define SOFT_I2C_INIT_BOARD i2c_init_board() +#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_SOFT_I2C_SPEED /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 @@ -174,6 +181,7 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* Support the IVM EEprom */ +#define CONFIG_SYS_IVM_EEPROM_BUS_NUM 1 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100 @@ -184,7 +192,7 @@ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) +#define CONFIG_SYS_DTT_BUS_NUM 2 #define CONFIG_SYS_IMMR 0xF0000000 diff -purN u-boot-i2c.orig/include/configs/mgsuvd.h u-boot-i2c/include/configs/mgsuvd.h --- u-boot-i2c.orig/include/configs/mgsuvd.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/mgsuvd.h 2009-02-12 10:46:00.000000000 -0800 @@ -265,11 +265,18 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS - +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 1 +#define CONFIG_SYS_NUM_I2C_BUSSES 3 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} +#define CONFIG_SYS_I2C_BUSSES { {0, {I2C_NULL_HOP}}, \ + {0, {{I2C_MUX_PCA9542, 0x70, 0}}}, \ + {0, {{I2C_MUX_PCA9542, 0x70, 1}}}} /* * Software (bit-bang) I2C driver configuration */ @@ -298,11 +305,10 @@ } #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */ -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_CMD_TREE 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 +/* I2C_INIT_BOARD specific... */ #define CONFIG_SYS_I2C_INIT_BOARD 1 -#define CONFIG_I2C_MUX 1 +#define SOFT_I2C_INIT_BOARD i2c_init_board() +#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_SOFT_I2C_SPEED /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 @@ -312,6 +318,7 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* Support the IVM EEprom */ +#define CONFIG_SYS_IVM_EEPROM_BUS_NUM 1 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100 @@ -322,6 +329,6 @@ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) +#define CONFIG_SYS_DTT_BUS_NUM 2 #endif /* __CONFIG_H */ diff -purN u-boot-i2c.orig/include/configs/mpc7448hpc2.h u-boot-i2c/include/configs/mpc7448hpc2.h --- u-boot-i2c.orig/include/configs/mpc7448hpc2.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/mpc7448hpc2.h 2009-02-12 10:46:00.000000000 -0800 @@ -178,7 +178,12 @@ * Miscellaneous configurable options */ #define CONFIG_VERSION_VARIABLE 1 + +#define CONFIG_NEW_I2C #define CONFIG_TSI108_I2C +#define CONFIG_SYS_TSI108_I2C_SPEED 100000 /* Bogus */ +#define CONFIG_SYS_TSI108_I2C_SLAVE 1 /* Bogus */ +#define CONFIG_SYS_I2C_ADAPTERS {&tsi108_i2c_adap} #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ diff -purN u-boot-i2c.orig/include/configs/omap2420h4.h u-boot-i2c/include/configs/omap2420h4.h --- u-boot-i2c.orig/include/configs/omap2420h4.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/omap2420h4.h 2009-02-12 10:46:00.000000000 -0800 @@ -108,10 +108,11 @@ /* * I2C configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_NEW_I2C +#define CONFIG_OMAP24XX_I2C +#define CONFIG_SYS_OMAP24XX_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP24XX_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap24xx_i2c_adap[0]} /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff -purN u-boot-i2c.orig/include/configs/omap3_beagle.h u-boot-i2c/include/configs/omap3_beagle.h --- u-boot-i2c.orig/include/configs/omap3_beagle.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/omap3_beagle.h 2009-02-12 10:46:00.000000000 -0800 @@ -111,11 +111,12 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +#define CONFIG_NEW_I2C +#define CONFIG_OMAP24XX_I2C +#define CONFIG_SYS_OMAP24XX_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP24XX_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap24xx_i2c_adap[0]} /* * Board NAND Info. diff -purN u-boot-i2c.orig/include/configs/omap3_evm.h u-boot-i2c/include/configs/omap3_evm.h --- u-boot-i2c.orig/include/configs/omap3_evm.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/omap3_evm.h 2009-02-12 10:46:00.000000000 -0800 @@ -116,11 +116,12 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +#define CONFIG_NEW_I2C +#define CONFIG_OMAP24XX_I2C +#define CONFIG_SYS_OMAP24XX_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP24XX_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap24xx_i2c_adap[0]} /* * Board NAND Info. diff -purN u-boot-i2c.orig/include/configs/omap3_overo.h u-boot-i2c/include/configs/omap3_overo.h --- u-boot-i2c.orig/include/configs/omap3_overo.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/omap3_overo.h 2009-02-12 10:46:00.000000000 -0800 @@ -103,11 +103,11 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_NEW_I2C +#define CONFIG_OMAP24XX_I2C +#define CONFIG_SYS_OMAP24XX_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP24XX_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap24xx_i2c_adap[0]} /* * Board NAND Info. diff -purN u-boot-i2c.orig/include/configs/omap3_pandora.h u-boot-i2c/include/configs/omap3_pandora.h --- u-boot-i2c.orig/include/configs/omap3_pandora.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/omap3_pandora.h 2009-02-12 10:46:00.000000000 -0800 @@ -106,11 +106,11 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_NEW_I2C +#define CONFIG_OMAP24XX_I2C +#define CONFIG_SYS_OMAP24XX_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP24XX_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap24xx_i2c_adap[0]} /* * Board NAND Info. diff -purN u-boot-i2c.orig/include/configs/omap3_zoom1.h u-boot-i2c/include/configs/omap3_zoom1.h --- u-boot-i2c.orig/include/configs/omap3_zoom1.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/omap3_zoom1.h 2009-02-12 10:46:00.000000000 -0800 @@ -112,11 +112,11 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_NEW_I2C +#define CONFIG_OMAP24XX_I2C +#define CONFIG_SYS_OMAP24XX_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP24XX_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap24xx_i2c_adap[0]} /* * Board NAND Info. diff -purN u-boot-i2c.orig/include/configs/pdnb3.h u-boot-i2c/include/configs/pdnb3.h --- u-boot-i2c.orig/include/configs/pdnb3.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/pdnb3.h 2009-02-12 10:46:00.000000000 -0800 @@ -296,11 +296,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 83000 /* 83 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ diff -purN u-boot-i2c.orig/include/configs/rmu.h u-boot-i2c/include/configs/rmu.h --- u-boot-i2c.orig/include/configs/rmu.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/rmu.h 2009-02-12 10:46:00.000000000 -0800 @@ -61,11 +61,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 40000 /* 40 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* Software (bit-bang) I2C driver configuration */ #define PB_SCL 0x00000020 /* PB 26 */ #define PB_SDA 0x00000010 /* PB 27 */ diff -purN u-boot-i2c.orig/include/configs/sacsng.h u-boot-i2c/include/configs/sacsng.h --- u-boot-i2c.orig/include/configs/sacsng.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/sacsng.h 2009-02-12 10:46:00.000000000 -0800 @@ -292,14 +292,15 @@ * configuration items that the driver uses to drive the port pins. */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 400000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ -#ifdef CONFIG_SOFT_I2C #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) @@ -309,7 +310,6 @@ #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ else iop->pdat &= ~0x00020000 #define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ /* Define this to reserve an entire FLASH sector for * environment variables. Otherwise, the environment will be diff -purN u-boot-i2c.orig/include/configs/sbc8260.h u-boot-i2c/include/configs/sbc8260.h --- u-boot-i2c.orig/include/configs/sbc8260.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/sbc8260.h 2009-02-12 10:46:00.000000000 -0800 @@ -250,14 +250,15 @@ * configuration items that the driver uses to drive the port pins. */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 400000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ -#ifdef CONFIG_SOFT_I2C #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) @@ -267,7 +268,6 @@ #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ else iop->pdat &= ~0x00020000 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ /* Define this to reserve an entire FLASH sector (256 KB) for diff -purN u-boot-i2c.orig/include/configs/sbc8349.h u-boot-i2c/include/configs/sbc8349.h --- u-boot-i2c.orig/include/configs/sbc8349.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/sbc8349.h 2009-02-12 10:46:00.000000000 -0800 @@ -312,17 +312,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C1_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* TSEC */ #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff -purN u-boot-i2c.orig/include/configs/sbc8548.h u-boot-i2c/include/configs/sbc8548.h --- u-boot-i2c.orig/include/configs/sbc8548.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/sbc8548.h 2009-02-12 10:46:00.000000000 -0800 @@ -320,13 +320,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 /* * General PCI diff -purN u-boot-i2c.orig/include/configs/sbc8560.h u-boot-i2c/include/configs/sbc8560.h --- u-boot-i2c.orig/include/configs/sbc8560.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/sbc8560.h 2009-02-12 10:46:00.000000000 -0800 @@ -222,13 +222,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 diff -purN u-boot-i2c.orig/include/configs/sbc8641d.h u-boot-i2c/include/configs/sbc8641d.h --- u-boot-i2c.orig/include/configs/sbc8641d.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/sbc8641d.h 2009-02-12 10:46:00.000000000 -0800 @@ -292,13 +292,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3100 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* * RapidIO MMU diff -purN u-boot-i2c.orig/include/configs/socrates.h u-boot-i2c/include/configs/socrates.h --- u-boot-i2c.orig/include/configs/socrates.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/socrates.h 2009-02-12 10:46:00.000000000 -0800 @@ -235,16 +235,16 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 102124 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 102124 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} /* I2C RTC */ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ diff -purN u-boot-i2c.orig/include/configs/spc1920.h u-boot-i2c/include/configs/spc1920.h --- u-boot-i2c.orig/include/configs/spc1920.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/spc1920.h 2009-02-12 10:46:00.000000000 -0800 @@ -208,12 +208,12 @@ #if defined(CONFIG_CMD_I2C) /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -229,7 +229,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ #endif /*----------------------------------------------------------------------- diff -purN u-boot-i2c.orig/include/configs/stxgp3.h u-boot-i2c/include/configs/stxgp3.h --- u-boot-i2c.orig/include/configs/stxgp3.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/stxgp3.h 2009-02-12 10:46:00.000000000 -0800 @@ -180,18 +180,12 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#if 0 -#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ -#else -/* I did the 'if 0' so we could keep the syntax above if ever needed. */ -#undef CONFIG_SYS_I2C_NOPROBES -#endif -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} /* RapdIO Map configuration, mapped 1:1. */ diff -purN u-boot-i2c.orig/include/configs/stxssa.h u-boot-i2c/include/configs/stxssa.h --- u-boot-i2c.orig/include/configs/stxssa.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/stxssa.h 2009-02-12 10:46:00.000000000 -0800 @@ -197,13 +197,12 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#undef CONFIG_SYS_I2C_NOPROBES -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} /* I2C RTC */ #define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */ diff -purN u-boot-i2c.orig/include/configs/uc100.h u-boot-i2c/include/configs/uc100.h --- u-boot-i2c.orig/include/configs/uc100.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/uc100.h 2009-02-12 10:46:00.000000000 -0800 @@ -468,12 +468,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -489,7 +489,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ /*----------------------------------------------------------------------- * I2C EEPROM (24C164) diff -purN u-boot-i2c.orig/include/configs/vct.h u-boot-i2c/include/configs/vct.h --- u-boot-i2c.orig/include/configs/vct.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/vct.h 2009-02-12 10:46:00.000000000 -0800 @@ -235,11 +235,14 @@ * I2C/EEPROM */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 83000 /* 83 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} +#define CONFIG_SOFT_I2C /* I2C bit-banged */ /* * Software (bit-bang) I2C driver configuration */ diff -purN u-boot-i2c.orig/include/configs/voiceblue.h u-boot-i2c/include/configs/voiceblue.h --- u-boot-i2c.orig/include/configs/voiceblue.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/voiceblue.h 2009-02-12 10:46:00.000000000 -0800 @@ -97,10 +97,11 @@ #define CONFIG_DRIVER_SMC91111 #define CONFIG_SMC91111_BASE 0x08000300 -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C +#define CONFIG_NEW_I2C +#define CONFIG_OMAP1510_I2C +#define CONFIG_SYS_OMAP1510_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP1510_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap1510_i2c_adap} #define CONFIG_RTC_DS1307 #define CONFIG_SYS_I2C_RTC_ADDR 0x68

1 0

[U-Boot] 11/12 Multiadapter/multibus I2C, configs part 4
by ksi＠koi8.net 12 Feb '09

12 Feb '09

Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/include/configs/barco.h u-boot-i2c/include/configs/barco.h --- u-boot-i2c.orig/include/configs/barco.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/barco.h 2009-02-12 10:46:00.000000000 -0800 @@ -197,6 +197,11 @@ #ifdef CONFIG_SOFT_I2C #error "Soft I2C is not configured properly. Please review!" +#define CONFIG_NEW_I2C +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) diff -purN u-boot-i2c.orig/include/configs/bf533-ezkit.h u-boot-i2c/include/configs/bf533-ezkit.h --- u-boot-i2c.orig/include/configs/bf533-ezkit.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/bf533-ezkit.h 2009-02-12 10:46:00.000000000 -0800 @@ -168,7 +168,12 @@ * I2C settings * By default PF1 is used as SDA and PF0 as SCL on the Stamp board */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -197,9 +202,6 @@ } #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - #define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ #define CONFIG_EBIU_SDRRC_VAL 0x398 diff -purN u-boot-i2c.orig/include/configs/bf533-stamp.h u-boot-i2c/include/configs/bf533-stamp.h --- u-boot-i2c.orig/include/configs/bf533-stamp.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/bf533-stamp.h 2009-02-12 10:46:00.000000000 -0800 @@ -27,14 +27,6 @@ /* FLASH/ETHERNET uses the same address range */ #define SHARED_RESOURCES 1 -/* Is I2C bit-banged? */ -#define CONFIG_SOFT_I2C 1 - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF3 -#define PF_SDA PF2 /* * Video splash screen support @@ -178,6 +170,41 @@ #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ #endif +/* I2C */ +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF3 +#define PF_SDA PF2 +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + + /* * Command settings */ @@ -213,13 +240,6 @@ "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ "" -#ifdef CONFIG_SOFT_I2C -#if (!CONFIG_SOFT_I2C) -#undef CONFIG_SOFT_I2C -#endif -#endif - - /* * BOOTP options */ @@ -244,7 +264,7 @@ #define CONFIG_CMD_PING #endif -#if (CONFIG_SOFT_I2C) +#if defined(CONFIG_SOFT_I2C) #define CONFIG_CMD_I2C #endif @@ -271,37 +291,6 @@ #define CONFIG_LOADS_ECHO 1 -/* - * I2C settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board - */ -#if (CONFIG_SOFT_I2C) - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 -#endif /* CONFIG_SOFT_I2C */ /* * Compact Flash settings diff -purN u-boot-i2c.orig/include/configs/bf537-stamp.h u-boot-i2c/include/configs/bf537-stamp.h --- u-boot-i2c.orig/include/configs/bf537-stamp.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/bf537-stamp.h 2009-02-12 10:46:00.000000000 -0800 @@ -306,10 +306,11 @@ /* * I2C settings */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_BFIN_TWI_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0 +#define CONFIG_NEW_I2C +#define CONFIG_BFIN_TWI_I2C +#define CONFIG_SYS_BFIN_TWI_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CONFIG_SYS_BFIN_TWI_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_ADAPTERS {&bfin_twi_i2c_adap} #define CONFIG_EBIU_SDRRC_VAL 0x306 #define CONFIG_EBIU_SDGCTL_VAL 0x91114d diff -purN u-boot-i2c.orig/include/configs/debris.h u-boot-i2c/include/configs/debris.h --- u-boot-i2c.orig/include/configs/debris.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/debris.h 2009-02-12 10:46:00.000000000 -0800 @@ -280,6 +280,11 @@ #ifdef CONFIG_SOFT_I2C #error "Soft I2C is not configured properly. Please review!" +#define CONFIG_NEW_I2C +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) diff -purN u-boot-i2c.orig/include/configs/ep8260.h u-boot-i2c/include/configs/ep8260.h --- u-boot-i2c.orig/include/configs/ep8260.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/ep8260.h 2009-02-12 10:46:00.000000000 -0800 @@ -226,14 +226,20 @@ * configuration items that the driver uses to drive the port pins. */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ + #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */ /* * Software (bit-bang) I2C driver configuration */ #ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) diff -purN u-boot-i2c.orig/include/configs/imx31_phycore.h u-boot-i2c/include/configs/imx31_phycore.h --- u-boot-i2c.orig/include/configs/imx31_phycore.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/imx31_phycore.h 2009-02-12 10:46:00.000000000 -0800 @@ -58,11 +58,19 @@ * Hardware drivers */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MXC 1 -#define CONFIG_SYS_I2C_MX31_PORT2 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe +/* + * CONFIG_SYS_MXC_I2C_BASE for the port used: + * + * 1: 0x43f80000 + * 2: 0x43f98000 + * 3: 0x43f84000 + */ +#define CONFIG_NEW_I2C +#define CONFIG_MXC_I2C +#define CONFIG_SYS_MXC_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_MXC_I2C_SLAVE 0xfe +#define CONFIG_SYS_MXC_I2C_BASE 0x43f98000 +#define CONFIG_SYS_I2C_ADAPTERS {&mxc_i2c_adap[0]} #define CONFIG_MX31_UART 1 #define CONFIG_SYS_MX31_UART1 1 diff -purN u-boot-i2c.orig/include/configs/lwmon.h u-boot-i2c/include/configs/lwmon.h --- u-boot-i2c.orig/include/configs/lwmon.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/lwmon.h 2009-02-12 10:46:00.000000000 -0800 @@ -144,12 +144,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -165,7 +165,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ diff -purN u-boot-i2c.orig/include/configs/TASREG.h u-boot-i2c/include/configs/TASREG.h --- u-boot-i2c.orig/include/configs/TASREG.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TASREG.h 2009-02-12 10:46:00.000000000 -0800 @@ -137,19 +137,13 @@ /*----------------------------------------------------------------------- * I2C */ -#define CONFIG_SOFT_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 100000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} -#if defined (CONFIG_SOFT_I2C) #if 0 /* push-pull */ #define SDA 0x00800000 #define SCL 0x00000008 @@ -183,7 +177,15 @@ #define I2C_ACTIVE {DIR1|=SDA;} #define I2C_TRISTATE {DIR1&=~SDA;} #endif -#endif + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) diff -purN u-boot-i2c.orig/include/configs/TK885D.h u-boot-i2c/include/configs/TK885D.h --- u-boot-i2c.orig/include/configs/TK885D.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TK885D.h 2009-02-12 10:46:00.000000000 -0800 @@ -102,12 +102,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -123,7 +123,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ diff -purN u-boot-i2c.orig/include/configs/TOP5200.h u-boot-i2c/include/configs/TOP5200.h --- u-boot-i2c.orig/include/configs/TOP5200.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TOP5200.h 2009-02-12 10:46:00.000000000 -0800 @@ -196,9 +196,15 @@ #define CONFIG_MISC_INIT_R #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ #if defined (CONFIG_SOFT_I2C) +# define CONFIG_NEW_I2C +# define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +# define CONFIG_SYS_SOFT_I2C_SPEED 100000 +# define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +# define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} +/**/ # define SDA0 0x40 # define SCL0 0x80 # define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00)) @@ -213,8 +219,7 @@ # define I2C_DELAY {udelay(5);} # define I2C_ACTIVE {DDR0|=SDA0;} # define I2C_TRISTATE {DDR0&=~SDA0;} -# define CONFIG_SYS_I2C_SPEED 100000 -# define CONFIG_SYS_I2C_SLAVE 0x7F + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 #define CONFIG_SYS_I2C_FACT_ADDR 0x57 #endif diff -purN u-boot-i2c.orig/include/configs/TOP860.h u-boot-i2c/include/configs/TOP860.h --- u-boot-i2c.orig/include/configs/TOP860.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TOP860.h 2009-02-12 10:46:00.000000000 -0800 @@ -159,7 +159,6 @@ * Environment handler * only the first 6k in EEPROM are available for user. Of that we use 256b */ -#define CONFIG_SOFT_I2C #define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ #define CONFIG_ENV_OFFSET 0x1000 #define CONFIG_ENV_SIZE 0x0700 @@ -170,13 +169,17 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_SIZE 0x2000 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xFE #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 #define CONFIG_ENV_OVERWRITE #define CONFIG_MISC_INIT_R -#if defined (CONFIG_SOFT_I2C) +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 100000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} +/**/ #define SDA 0x00010 #define SCL 0x00020 #define __I2C_DIR immr->im_cpm.cp_pbdir @@ -193,7 +196,6 @@ #define I2C_DELAY { udelay(5); } #define I2C_ACTIVE { __I2C_DIR |= SDA; } #define I2C_TRISTATE { __I2C_DIR &= ~SDA; } -#endif #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } diff -purN u-boot-i2c.orig/include/configs/TQM8260.h u-boot-i2c/include/configs/TQM8260.h --- u-boot-i2c.orig/include/configs/TQM8260.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM8260.h 2009-02-12 10:46:00.000000000 -0800 @@ -88,9 +88,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 400000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration diff -purN u-boot-i2c.orig/include/configs/TQM8272.h u-boot-i2c/include/configs/TQM8272.h --- u-boot-i2c.orig/include/configs/TQM8272.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM8272.h 2009-02-12 10:46:00.000000000 -0800 @@ -96,10 +96,12 @@ #if CONFIG_I2C /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 400000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ diff -purN u-boot-i2c.orig/include/configs/TQM834x.h u-boot-i2c/include/configs/TQM834x.h --- u-boot-i2c.orig/include/configs/TQM834x.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM834x.h 2009-02-12 10:46:00.000000000 -0800 @@ -201,12 +201,12 @@ extern int tqm834x_num_flash_banks; /* * I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ diff -purN u-boot-i2c.orig/include/configs/TQM855M.h u-boot-i2c/include/configs/TQM855M.h --- u-boot-i2c.orig/include/configs/TQM855M.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM855M.h 2009-02-12 10:46:00.000000000 -0800 @@ -93,12 +93,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -114,7 +114,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ diff -purN u-boot-i2c.orig/include/configs/TQM85xx.h u-boot-i2c/include/configs/TQM85xx.h --- u-boot-i2c.orig/include/configs/TQM85xx.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM85xx.h 2009-02-12 10:46:00.000000000 -0800 @@ -302,13 +302,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */ /* I2C RTC */ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ diff -purN u-boot-i2c.orig/include/configs/TQM866M.h u-boot-i2c/include/configs/TQM866M.h --- u-boot-i2c.orig/include/configs/TQM866M.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM866M.h 2009-02-12 10:46:00.000000000 -0800 @@ -105,12 +105,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -126,7 +126,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ diff -purN u-boot-i2c.orig/include/configs/TQM885D.h u-boot-i2c/include/configs/TQM885D.h --- u-boot-i2c.orig/include/configs/TQM885D.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/TQM885D.h 2009-02-12 10:46:00.000000000 -0800 @@ -99,12 +99,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -120,7 +120,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ diff -purN u-boot-i2c.orig/include/configs/XPEDITE5200.h u-boot-i2c/include/configs/XPEDITE5200.h --- u-boot-i2c.orig/include/configs/XPEDITE5200.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/XPEDITE5200.h 2009-02-12 10:46:00.000000000 -0800 @@ -219,14 +219,16 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} /* I2C EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 diff -purN u-boot-i2c.orig/include/configs/XPEDITE5370.h u-boot-i2c/include/configs/XPEDITE5370.h --- u-boot-i2c.orig/include/configs/XPEDITE5370.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/XPEDITE5370.h 2009-02-12 10:46:00.000000000 -0800 @@ -237,14 +237,16 @@ extern unsigned long get_board_ddr_clk(u /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} /* PEX8518 slave I2C interface */ #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70

1 0

[U-Boot] [PATCH] 10/12 Multiadapter/multibus I2C, configs part 3
by ksi＠koi8.net 12 Feb '09

12 Feb '09

Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/include/configs/MPC8555CDS.h u-boot-i2c/include/configs/MPC8555CDS.h --- u-boot-i2c.orig/include/configs/MPC8555CDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8555CDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -320,13 +320,13 @@ extern unsigned long get_clock_freq(void /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* EEPROM */ #define CONFIG_ID_EEPROM diff -purN u-boot-i2c.orig/include/configs/MPC8560ADS.h u-boot-i2c/include/configs/MPC8560ADS.h --- u-boot-i2c.orig/include/configs/MPC8560ADS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8560ADS.h 2009-02-12 10:46:00.000000000 -0800 @@ -291,13 +291,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* RapidIO MMU */ #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ diff -purN u-boot-i2c.orig/include/configs/MPC8568MDS.h u-boot-i2c/include/configs/MPC8568MDS.h --- u-boot-i2c.orig/include/configs/MPC8568MDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8568MDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -306,17 +306,18 @@ extern unsigned long get_clock_freq(void /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* * General PCI diff -purN u-boot-i2c.orig/include/configs/MPC8572DS.h u-boot-i2c/include/configs/MPC8572DS.h --- u-boot-i2c.orig/include/configs/MPC8572DS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8572DS.h 2009-02-12 10:46:00.000000000 -0800 @@ -373,17 +373,18 @@ extern unsigned long get_board_ddr_clk(u #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ /* I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* * I2C2 EEPROM diff -purN u-boot-i2c.orig/include/configs/MPC8610HPCD.h u-boot-i2c/include/configs/MPC8610HPCD.h --- u-boot-i2c.orig/include/configs/MPC8610HPCD.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8610HPCD.h 2009-02-12 10:46:00.000000000 -0800 @@ -261,13 +261,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* * General PCI diff -purN u-boot-i2c.orig/include/configs/MPC8641HPCN.h u-boot-i2c/include/configs/MPC8641HPCN.h --- u-boot-i2c.orig/include/configs/MPC8641HPCN.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8641HPCN.h 2009-02-12 10:46:00.000000000 -0800 @@ -310,13 +310,13 @@ extern unsigned long get_board_sys_clk(u /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3100 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* * RapidIO MMU diff -purN u-boot-i2c.orig/include/configs/MVBLM7.h u-boot-i2c/include/configs/MVBLM7.h --- u-boot-i2c.orig/include/configs/MVBLM7.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MVBLM7.h 2009-02-12 10:46:00.000000000 -0800 @@ -42,23 +42,22 @@ #define CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI #define CONFIG_PCI_SKIP_HOST_BRIDGE -#define CONFIG_HARD_I2C #define CONFIG_TSEC_ENET #define CONFIG_MPC8XXX_SPI #define CONFIG_HARD_SPI #define MVBLM7_MMC_CS 0x04000000 /* I2C */ -#undef CONFIG_SOFT_I2C - +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 #define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} /* * DDR Setup diff -purN u-boot-i2c.orig/include/configs/NC650.h u-boot-i2c/include/configs/NC650.h --- u-boot-i2c.orig/include/configs/NC650.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/NC650.h 2009-02-12 10:46:00.000000000 -0800 @@ -104,10 +104,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7f - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 100000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ diff -purN u-boot-i2c.orig/include/configs/PM826.h u-boot-i2c/include/configs/PM826.h --- u-boot-i2c.orig/include/configs/PM826.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/PM826.h 2009-02-12 10:46:00.000000000 -0800 @@ -54,9 +54,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ diff -purN u-boot-i2c.orig/include/configs/PM828.h u-boot-i2c/include/configs/PM828.h --- u-boot-i2c.orig/include/configs/PM828.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/PM828.h 2009-02-12 10:46:00.000000000 -0800 @@ -54,9 +54,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ diff -purN u-boot-i2c.orig/include/configs/PM854.h u-boot-i2c/include/configs/PM854.h --- u-boot-i2c.orig/include/configs/PM854.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/PM854.h 2009-02-12 10:46:00.000000000 -0800 @@ -194,13 +194,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* * EEPROM configuration diff -purN u-boot-i2c.orig/include/configs/PM856.h u-boot-i2c/include/configs/PM856.h --- u-boot-i2c.orig/include/configs/PM856.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/PM856.h 2009-02-12 10:46:00.000000000 -0800 @@ -191,13 +191,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* * EEPROM configuration diff -purN u-boot-i2c.orig/include/configs/RRvision.h u-boot-i2c/include/configs/RRvision.h --- u-boot-i2c.orig/include/configs/RRvision.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/RRvision.h 2009-02-12 10:46:00.000000000 -0800 @@ -119,12 +119,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ - -# define CONFIG_SYS_I2C_SPEED 50000 /* 50 kHz is supposed to work */ -# define CONFIG_SYS_I2C_SLAVE 0xFE - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -140,7 +140,6 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ /* diff -purN u-boot-i2c.orig/include/configs/Sandpoint8240.h u-boot-i2c/include/configs/Sandpoint8240.h --- u-boot-i2c.orig/include/configs/Sandpoint8240.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/Sandpoint8240.h 2009-02-12 10:46:00.000000000 -0800 @@ -209,6 +209,11 @@ #ifdef CONFIG_SOFT_I2C #error "Soft I2C is not configured properly. Please review!" +#define CONFIG_NEW_I2C +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) diff -purN u-boot-i2c.orig/include/configs/Sandpoint8245.h u-boot-i2c/include/configs/Sandpoint8245.h --- u-boot-i2c.orig/include/configs/Sandpoint8245.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/Sandpoint8245.h 2009-02-12 10:46:00.000000000 -0800 @@ -179,6 +179,11 @@ #ifdef CONFIG_SOFT_I2C #error "Soft I2C is not configured properly. Please review!" +#define CONFIG_NEW_I2C +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) diff -purN u-boot-i2c.orig/include/configs/SBC8540.h u-boot-i2c/include/configs/SBC8540.h --- u-boot-i2c.orig/include/configs/SBC8540.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/SBC8540.h 2009-02-12 10:46:00.000000000 -0800 @@ -234,13 +234,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 diff -purN u-boot-i2c.orig/include/configs/SCM.h u-boot-i2c/include/configs/SCM.h --- u-boot-i2c.orig/include/configs/SCM.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/SCM.h 2009-02-12 10:46:00.000000000 -0800 @@ -74,14 +74,15 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 400000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ - #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) diff -purN u-boot-i2c.orig/include/configs/SIMPC8313.h u-boot-i2c/include/configs/SIMPC8313.h --- u-boot-i2c.orig/include/configs/SIMPC8313.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/SIMPC8313.h 2009-02-12 10:46:00.000000000 -0800 @@ -217,15 +217,17 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 #define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* * General PCI diff -purN u-boot-i2c.orig/include/configs/SMN42.h u-boot-i2c/include/configs/SMN42.h --- u-boot-i2c.orig/include/configs/SMN42.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/SMN42.h 2009-02-12 10:46:00.000000000 -0800 @@ -78,17 +78,13 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 10000 /* this would be 0xAE if E0, E1 and E2 were pulled high */ -#define CONFIG_SYS_I2C_SLAVE 0xA0 -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA0 >> 1) -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -/* not used but required by devices.c */ -#define CONFIG_SYS_I2C_SPEED 10000 - -#ifdef CONFIG_SOFT_I2C +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xA0 +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -107,7 +103,11 @@ i2ctmp = GET32(IO0DIR); \ i2ctmp &= ~SDA; \ PUT32(IO0DIR, i2ctmp); } -#endif /* CONFIG_SOFT_I2C */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA0 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 /* diff -purN u-boot-i2c.orig/include/configs/SX1.h u-boot-i2c/include/configs/SX1.h --- u-boot-i2c.orig/include/configs/SX1.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/SX1.h 2009-02-12 10:46:00.000000000 -0800 @@ -81,10 +81,11 @@ /* * I2C configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C +#define CONFIG_NEW_I2C +#define CONFIG_OMAP1510_I2C +#define CONFIG_SYS_OMAP1510_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_OMAP1510_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&omap1510_i2c_adap} #define CONFIG_ENV_OVERWRITE diff -purN u-boot-i2c.orig/include/configs/SXNI855T.h u-boot-i2c/include/configs/SXNI855T.h --- u-boot-i2c.orig/include/configs/SXNI855T.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/SXNI855T.h 2009-02-12 10:46:00.000000000 -0800 @@ -119,7 +119,12 @@ #define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -136,8 +141,6 @@ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xFE # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */ # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */

1 0

[U-Boot] [PATCH] 4/12 Multiadapter/multibus I2C, drivers part 1
by ksi＠koi8.net 12 Feb '09

12 Feb '09

Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/drivers/i2c/bfin-twi_i2c.c u-boot-i2c/drivers/i2c/bfin-twi_i2c.c --- u-boot-i2c.orig/drivers/i2c/bfin-twi_i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/drivers/i2c/bfin-twi_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -1,4 +1,8 @@ /* + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * * i2c.c - driver for Blackfin on-chip TWI/I2C * * Copyright (c) 2006-2008 Analog Devices Inc. @@ -44,7 +48,7 @@ #ifdef CONFIG_TWICLK_KHZ # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED #endif -#if CONFIG_SYS_I2C_SPEED > 400000 +#if CONFIG_SYS_BFIN_TWI_I2C_SPEED > 400000 # error The Blackfin I2C hardware can only operate at 400KHz max #endif @@ -60,6 +64,10 @@ struct i2c_msg { u8 *abuf; /* addr buffer */ }; +i2c_adap_t bfin_twi_i2c_adap; + +DECLARE_GLOBAL_DATA_PTR; + /** * wait_for_completion - manage the actual i2c transfer * @msg: the i2c msg @@ -205,14 +213,14 @@ static int i2c_transfer(uchar chip, uint } /* - * i2c_init - initialize the i2c bus + * bfin_twi_i2c_init - initialize the i2c bus * @speed: bus speed (in HZ) * @slaveaddr: address of device in slave mode (0 - not slave) * * Slave mode isn't actually implemented. It'll stay that way until * we get a real request for it. */ -void i2c_init(int speed, int slaveaddr) +static void bfin_twi_i2c_init(int speed, int slaveaddr) { uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; @@ -235,7 +243,7 @@ void i2c_init(int speed, int slaveaddr) debugi("CONTROL:0x%04x CLKDIV:0x%04x", bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV()); -#if CONFIG_SYS_I2C_SLAVE +#if CONFIG_SYS_BFIN_TWI_I2C_SLAVE # error I2C slave support not tested/supported /* If they want us as a slave, do it */ if (slaveaddr) { @@ -243,21 +251,13 @@ void i2c_init(int speed, int slaveaddr) bfin_write_TWI_SLAVE_CTL(SEN); } #endif + if (gd->flags & GD_FLG_RELOC) { + bfin_twi_i2c_adap.init_done = 1; + } } /** - * i2c_probe - test if a chip exists at a given i2c address - * @chip: i2c chip addr to search for - * @return: 0 if found, non-0 if not found - */ -int i2c_probe(uchar chip) -{ - u8 byte; - return i2c_read(chip, 0, 0, &byte, 1); -} - -/** - * i2c_read - read data from an i2c device + * bfin_twi_i2c_read - read data from an i2c device * @chip: i2c chip addr * @addr: memory (register) address in the chip * @alen: byte size of address @@ -265,13 +265,24 @@ int i2c_probe(uchar chip) * @len: how many bytes to read * @return: 0 on success, non-0 on failure */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int bfin_twi_i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ)); } /** - * i2c_write - write data to an i2c device + * bfin_twi_i2c_probe - test if a chip exists at a given i2c address + * @chip: i2c chip addr to search for + * @return: 0 if found, non-0 if not found + */ +static int bfin_twi_i2c_probe(uchar chip) +{ + u8 byte; + return bfin_twi_i2c_read(chip, 0, 0, &byte, 1); +} + +/** + * bfin_twi_i2c_write - write data to an i2c device * @chip: i2c chip addr * @addr: memory (register) address in the chip * @alen: byte size of address @@ -279,7 +290,30 @@ int i2c_read(uchar chip, uint addr, int * @len: how many bytes to write * @return: 0 on success, non-0 on failure */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int bfin_twi_i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { return i2c_transfer(chip, addr, alen, buffer, len, 0); } + +static unsigned int bfin_twi_i2c_set_bus_speed(unsigned int speed) +{ + return(bfin_twi_i2c_adap.speed); +} + +static unsigned int bfin_twi_i2c_get_bus_speed(void) +{ + return(bfin_twi_i2c_adap.speed); +} + +i2c_adap_t bfin_twi_i2c_adap = { + .init = bfin_twi_i2c_init, + .probe = bfin_twi_i2c_probe, + .read = bfin_twi_i2c_read, + .write = bfin_twi_i2c_write, + .set_bus_speed = bfin_twi_i2c_set_bus_speed, + .get_bus_speed = bfin_twi_i2c_get_bus_speed, + .speed = CONFIG_SYS_BFIN_TWI_I2C_SPEED, + .slaveaddr = CONFIG_SYS_BFIN_TWI_I2C_SLAVE, + .init_done = 0, + .name = "bfin_twi_i2c" +}; diff -purN u-boot-i2c.orig/drivers/i2c/fsl_i2c.c u-boot-i2c/drivers/i2c/fsl_i2c.c --- u-boot-i2c.orig/drivers/i2c/fsl_i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/drivers/i2c/fsl_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -1,4 +1,8 @@ /* + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * * Copyright 2006 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or @@ -18,8 +22,6 @@ #include <common.h> -#ifdef CONFIG_HARD_I2C - #include <command.h> #include <i2c.h> /* Functional interface */ @@ -31,24 +33,15 @@ #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 -DECLARE_GLOBAL_DATA_PTR; - -/* Initialize the bus pointer to whatever one the SPD EEPROM is on. - * Default is bus 0. This is necessary because the DDR initialization - * runs from ROM, and we can't switch buses because we can't modify - * the global variables. - */ -#ifndef CONFIG_SYS_SPD_BUS_NUM -#define CONFIG_SYS_SPD_BUS_NUM 0 -#endif -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; +#define FSL_NAME(arg) "fsl_i2c@" MK_NAME(arg) +#define MK_NAME(arg) #arg -static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; +DECLARE_GLOBAL_DATA_PTR; static const struct fsl_i2c *i2c_dev[2] = { - (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), -#ifdef CONFIG_SYS_I2C2_OFFSET - (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) + (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET), +#ifdef CONFIG_SYS_FSL_I2C2_OFFSET + (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET) #endif }; @@ -126,6 +119,8 @@ static const struct { #endif }; +i2c_adap_t fsl_i2c_adap[]; + /** * Set the I2C bus speed for a given I2C device * @@ -169,43 +164,32 @@ static unsigned int set_i2c_bus_speed(co return speed; } -void -i2c_init(int speed, int slaveadd) + +static void __i2c_init(int adap_no, int speed, int slaveadd) { struct fsl_i2c *dev; unsigned int temp; - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); + dev = i2c_dev[adap_no]; writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); - if (gd->flags & GD_FLG_RELOC) - i2c_bus_speed[0] = temp; - writeb(slaveadd << 1, &dev->adr); /* write slave address */ - writeb(0x0, &dev->sr); /* clear status register */ - writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ - -#ifdef CONFIG_SYS_I2C2_OFFSET - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); - - writeb(0, &dev->cr); /* stop I2C controller */ - udelay(5); /* let it shutdown in peace */ - temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); - if (gd->flags & GD_FLG_RELOC) - i2c_bus_speed[1] = temp; + if (gd->flags & GD_FLG_RELOC) { + fsl_i2c_adap[adap_no].speed = temp; + fsl_i2c_adap[adap_no].slaveaddr = slaveadd; + } writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -#endif } -static __inline__ int -i2c_wait4bus(void) + +static __inline__ int i2c_wait4bus(int adap_no) { unsigned long long timeval = get_ticks(); - while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { + while (readb(&i2c_dev[adap_no]->sr) & I2C_SR_MBB) { if ((get_ticks() - timeval) > usec2ticks(I2C_TIMEOUT)) return -1; } @@ -213,18 +197,18 @@ i2c_wait4bus(void) return 0; } -static __inline__ int -i2c_wait(int write) + +static __inline__ int i2c_wait(int adap_no, int write) { u32 csr; unsigned long long timeval = get_ticks(); do { - csr = readb(&i2c_dev[i2c_bus_num]->sr); + csr = readb(&i2c_dev[adap_no]->sr); if (!(csr & I2C_SR_MIF)) continue; - writeb(0x0, &i2c_dev[i2c_bus_num]->sr); + writeb(0x0, &i2c_dev[adap_no]->sr); if (csr & I2C_SR_MAL) { debug("i2c_wait: MAL\n"); @@ -248,85 +232,85 @@ i2c_wait(int write) return -1; } -static __inline__ int -i2c_write_addr (u8 dev, u8 dir, int rsta) + +static __inline__ int i2c_write_addr (int adap_no, u8 dev, u8 dir, int rsta) { writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | (rsta ? I2C_CR_RSTA : 0), - &i2c_dev[i2c_bus_num]->cr); + &i2c_dev[adap_no]->cr); - writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); + writeb((dev << 1) | dir, &i2c_dev[adap_no]->dr); - if (i2c_wait(I2C_WRITE_BIT) < 0) + if (i2c_wait(adap_no, I2C_WRITE_BIT) < 0) return 0; return 1; } -static __inline__ int -__i2c_write(u8 *data, int length) + +static __inline__ int i2c_write_data(int adap_no, u8 *data, int length) { int i; writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, - &i2c_dev[i2c_bus_num]->cr); + &i2c_dev[adap_no]->cr); for (i = 0; i < length; i++) { - writeb(data[i], &i2c_dev[i2c_bus_num]->dr); + writeb(data[i], &i2c_dev[adap_no]->dr); - if (i2c_wait(I2C_WRITE_BIT) < 0) + if (i2c_wait(adap_no, I2C_WRITE_BIT) < 0) break; } return i; } -static __inline__ int -__i2c_read(u8 *data, int length) + +static __inline__ int i2c_read_data(int adap_no, u8 *data, int length) { int i; writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), - &i2c_dev[i2c_bus_num]->cr); + &i2c_dev[adap_no]->cr); /* dummy read */ - readb(&i2c_dev[i2c_bus_num]->dr); + readb(&i2c_dev[adap_no]->dr); for (i = 0; i < length; i++) { - if (i2c_wait(I2C_READ_BIT) < 0) + if (i2c_wait(adap_no, I2C_READ_BIT) < 0) break; /* Generate ack on last next to last byte */ if (i == length - 2) writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, - &i2c_dev[i2c_bus_num]->cr); + &i2c_dev[adap_no]->cr); /* Generate stop on last byte */ if (i == length - 1) - writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); + writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[adap_no]->cr); - data[i] = readb(&i2c_dev[i2c_bus_num]->dr); + data[i] = readb(&i2c_dev[adap_no]->dr); } return i; } -int -i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) + +static int __i2c_read(int adap_no, u8 dev, uint addr, int alen, u8 *data, int length) { int i = -1; /* signal error */ u8 *a = (u8*)&addr; - if (i2c_wait4bus() >= 0 - && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 - && __i2c_write(&a[4 - alen], alen) == alen) + if (i2c_wait4bus(adap_no) >= 0 + && i2c_write_addr(adap_no, dev, I2C_WRITE_BIT, 0) != 0 + && i2c_write_data(adap_no, &a[4 - alen], alen) == alen) i = 0; /* No error so far */ if (length - && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) - i = __i2c_read(data, length); + && i2c_write_addr(adap_no, dev, I2C_READ_BIT, 1) != 0) + i = i2c_read_data(adap_no, data, length); - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + writeb(I2C_CR_MEN, &i2c_dev[adap_no]->cr); if (i == length) return 0; @@ -334,19 +318,19 @@ i2c_read(u8 dev, uint addr, int alen, u8 return -1; } -int -i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) + +static int __i2c_write(int adap_no, u8 dev, uint addr, int alen, u8 *data, int length) { int i = -1; /* signal error */ u8 *a = (u8*)&addr; - if (i2c_wait4bus() >= 0 - && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 - && __i2c_write(&a[4 - alen], alen) == alen) { - i = __i2c_write(data, length); + if (i2c_wait4bus(adap_no) >= 0 + && i2c_write_addr(adap_no, dev, I2C_WRITE_BIT, 0) != 0 + && i2c_write_data(adap_no, &a[4 - alen], alen) == alen) { + i = i2c_write_data(adap_no, data, length); } - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + writeb(I2C_CR_MEN, &i2c_dev[adap_no]->cr); if (i == length) return 0; @@ -354,54 +338,123 @@ i2c_write(u8 dev, uint addr, int alen, u return -1; } -int -i2c_probe(uchar chip) + +static int __i2c_probe(int adap_no, uchar chip) { /* For unknow reason the controller will ACK when * probing for a slave with the same address, so skip * it. */ - if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) + if (chip == (readb(&i2c_dev[adap_no]->adr) >> 1)) return -1; - return i2c_read(chip, 0, 0, NULL, 0); + return __i2c_read(adap_no, chip, 0, 0, NULL, 0); } -int i2c_set_bus_num(unsigned int bus) + +static int __i2c_set_bus_speed(int adap_no, unsigned int speed) { -#ifdef CONFIG_SYS_I2C2_OFFSET - if (bus > 1) { -#else - if (bus > 0) { -#endif - return -1; - } + unsigned int i2c_clk = (adap_no == 1) ? gd->i2c2_clk : gd->i2c1_clk; - i2c_bus_num = bus; + writeb(0, &i2c_dev[adap_no]->cr); /* stop controller */ + fsl_i2c_adap[adap_no].speed = + set_i2c_bus_speed(i2c_dev[adap_no], i2c_clk, speed); + writeb(I2C_CR_MEN, &i2c_dev[adap_no]->cr); /* start controller */ return 0; } -int i2c_set_bus_speed(unsigned int speed) + +/* Wrappers for the first controller */ +static void fsl_i2c1_init(int speed, int slaveadd) +{ + __i2c_init(0, speed, slaveadd); +} + +static int fsl_i2c1_read(u8 dev, uint addr, int alen, u8 *data, int length) { - unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; + return(__i2c_read(0, dev, addr, alen, data, length)); +} - writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ - i2c_bus_speed[i2c_bus_num] = - set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); - writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ +static int fsl_i2c1_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + return(__i2c_write(0, dev, addr, alen, data, length)); +} - return 0; +static int fsl_i2c1_probe(uchar chip) +{ + return(__i2c_probe(0, chip)); +} + +static unsigned int fsl_i2c1_set_bus_speed(unsigned int speed) +{ + return(__i2c_set_bus_speed(0, speed)); } -unsigned int i2c_get_bus_num(void) +static unsigned int fsl_i2c1_get_bus_speed(void) +{ + return(fsl_i2c_adap[0].speed); +} + + +/* Second controller */ +#ifdef CONFIG_SYS_FSL_I2C2_OFFSET +static void fsl_i2c2_init(int speed, int slaveadd) { - return i2c_bus_num; + __i2c_init(1, speed, slaveadd); } -unsigned int i2c_get_bus_speed(void) +static int fsl_i2c2_read(u8 dev, uint addr, int alen, u8 *data, int length) { - return i2c_bus_speed[i2c_bus_num]; + return(__i2c_read(1, dev, addr, alen, data, length)); } -#endif /* CONFIG_HARD_I2C */ +static int fsl_i2c2_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + return(__i2c_write(1, dev, addr, alen, data, length)); +} + +static int fsl_i2c2_probe(uchar chip) +{ + return(__i2c_probe(1, chip)); +} + +static unsigned int fsl_i2c2_set_bus_speed(unsigned int speed) +{ + return(__i2c_set_bus_speed(1, speed)); +} + +static unsigned int fsl_i2c2_get_bus_speed(void) +{ + return(fsl_i2c_adap[1].speed); +} +#endif + +i2c_adap_t fsl_i2c_adap[] = { + { + .init = fsl_i2c1_init, + .probe = fsl_i2c1_probe, + .read = fsl_i2c1_read, + .write = fsl_i2c1_write, + .set_bus_speed = fsl_i2c1_set_bus_speed, + .get_bus_speed = fsl_i2c1_get_bus_speed, + .speed = CONFIG_SYS_FSL_I2C_SPEED, + .slaveaddr = CONFIG_SYS_FSL_I2C_SLAVE, + .init_done = 0, + .name = FSL_NAME(CONFIG_SYS_FSL_I2C_OFFSET) + }, +#ifdef CONFIG_SYS_FSL_I2C2_OFFSET + { + .init = fsl_i2c2_init, + .probe = fsl_i2c2_probe, + .read = fsl_i2c2_read, + .write = fsl_i2c2_write, + .set_bus_speed = fsl_i2c2_set_bus_speed, + .get_bus_speed = fsl_i2c2_get_bus_speed, + .speed = CONFIG_SYS_FSL_I2C2_SPEED, + .slaveaddr = CONFIG_SYS_FSL_I2C2_SLAVE, + .init_done = 0, + .name = FSL_NAME(CONFIG_SYS_FSL_I2C2_OFFSET) + }, +#endif +}; diff -purN u-boot-i2c.orig/drivers/i2c/mxc_i2c.c u-boot-i2c/drivers/i2c/mxc_i2c.c --- u-boot-i2c.orig/drivers/i2c/mxc_i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/drivers/i2c/mxc_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -1,6 +1,10 @@ /* * i2c driver for Freescale mx31 * + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> * * See file CREDITS for list of people who contributed to this @@ -24,11 +28,11 @@ #include <common.h> -#if defined(CONFIG_HARD_I2C) - #include <asm/arch/mx31.h> #include <asm/arch/mx31-regs.h> +#include <i2c.h> + #define IADR 0x00 #define IFDR 0x04 #define I2CR 0x08 @@ -47,15 +51,8 @@ #define I2SR_IIF (1 << 1) #define I2SR_RX_NO_AK (1 << 0) -#ifdef CONFIG_SYS_I2C_MX31_PORT1 -#define I2C_BASE 0x43f80000 -#elif defined (CONFIG_SYS_I2C_MX31_PORT2) -#define I2C_BASE 0x43f98000 -#elif defined (CONFIG_SYS_I2C_MX31_PORT3) -#define I2C_BASE 0x43f84000 -#else -#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver" -#endif +#define MXC_NAME(arg) "mxc_i2c@" MK_NAME(arg) +#define MK_NAME(arg) #arg #ifdef DEBUG #define DPRINTF(args...) printf(args) @@ -63,11 +60,15 @@ #define DPRINTF(args...) #endif +i2c_adap_t mxc_i2c_adap[]; + static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; -void i2c_init(int speed, int unused) +DECLARE_GLOBAL_DATA_PTR; + +static void _i2c_init(int speed, int unused, ulong base) { int freq = mx31_get_ipg_clk(); int i; @@ -78,125 +79,278 @@ void i2c_init(int speed, int unused) DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + IFDR) = i; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - __REG16(I2C_BASE + I2SR) = 0; + __REG16(base + I2CR) = 0; /* Reset module */ + __REG16(base + IFDR) = i; + __REG16(base + I2CR) = I2CR_IEN; + __REG16(base + I2SR) = 0; } -static int wait_busy(void) +static int wait_busy(ulong base) { int timeout = 10000; - while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + while (!(__REG16(base + I2SR) & I2SR_IIF) && --timeout) udelay(1); - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + __REG16(base + I2SR) = 0; /* clear interrupt */ return timeout; } -static int tx_byte(u8 byte) +static int tx_byte(u8 byte, ulong base) { - __REG16(I2C_BASE + I2DR) = byte; + __REG16(base + I2DR) = byte; - if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + if (!wait_busy(base) || __REG16(base + I2SR) & I2SR_RX_NO_AK) return -1; return 0; } -static int rx_byte(void) +static int rx_byte(ulong base) { - if (!wait_busy()) + if (!wait_busy(base)) return -1; - return __REG16(I2C_BASE + I2DR); + return __REG16(base + I2DR); } -int i2c_probe(uchar chip) +static int _i2c_probe(uchar chip, ulong base) { int ret; - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + __REG16(base + I2CR) = 0; /* Reset module */ + __REG16(base + I2CR) = I2CR_IEN; - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; - ret = tx_byte(chip << 1); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; + __REG16(base + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + ret = tx_byte(chip << 1, base); + __REG16(base + I2CR) = I2CR_IEN | I2CR_MTX; return ret; } -static int i2c_addr(uchar chip, uint addr, int alen) +static int i2c_addr(uchar chip, uint addr, int alen, ulong base) { - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + __REG16(base + I2SR) = 0; /* clear interrupt */ + __REG16(base + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; - if (tx_byte(chip << 1)) + if (tx_byte(chip << 1, base)) return -1; while (alen--) - if (tx_byte((addr >> (alen * 8)) & 0xff)) + if (tx_byte((addr >> (alen * 8)) & 0xff, base)) return -1; return 0; } -int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +static int _i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len, ulong base) { int timeout = 10000; int ret; DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); - if (i2c_addr(chip, addr, alen)) { + if (i2c_addr(chip, addr, alen, base)) { printf("i2c_addr failed\n"); return -1; } - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; + __REG16(base + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; - if (tx_byte(chip << 1 | 1)) + if (tx_byte(chip << 1 | 1, base)) return -1; - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); + __REG16(base + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); - ret = __REG16(I2C_BASE + I2DR); + ret = __REG16(base + I2DR); while (len--) { - if ((ret = rx_byte()) < 0) + if ((ret = rx_byte(base)) < 0) return -1; *buf++ = ret; if (len <= 1) - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; + __REG16(base + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; } - wait_busy(); + wait_busy(base); - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + __REG16(base + I2CR) = I2CR_IEN; - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + while (__REG16(base + I2SR) & I2SR_IBB && --timeout) udelay(1); return 0; } -int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +static int _i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len, ulong base) { int timeout = 10000; DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); - if (i2c_addr(chip, addr, alen)) + if (i2c_addr(chip, addr, alen, base)) return -1; while (len--) - if (tx_byte(*buf++)) + if (tx_byte(*buf++, base)) return -1; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; + __REG16(base + I2CR) = I2CR_IEN; - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + while (__REG16(base + I2SR) & I2SR_IBB && --timeout) udelay(1); return 0; } -#endif /* CONFIG_HARD_I2C */ +static void mxc_i2c_init(int speed, int slaveaddr) +{ + _i2c_init(speed, slaveaddr, CONFIG_SYS_MXC_I2C_BASE); + + if (gd->flags & GD_FLG_RELOC) { + mxc_i2c_adap[0].init_done = 1; + mxc_i2c_adap[0].speed = speed; + mxc_i2c_adap[0].slaveaddr = slaveaddr; + } +} + +static int mxc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + return(_i2c_read(chip, addr, alen, buf, len, CONFIG_SYS_MXC_I2C_BASE)); +} + +static int mxc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + return(_i2c_write(chip, addr, alen, buf, len, CONFIG_SYS_MXC_I2C_BASE)); +} + +static int mxc_i2c_probe(uchar chip) +{ + return(_i2c_probe(chip, CONFIG_SYS_MXC_I2C_BASE)); +} + +static unsigned int mxc_i2c_set_bus_speed(unsigned int speed) +{ + return(mxc_i2c_adap[0].speed); +} + +static unsigned int mxc_i2c_get_bus_speed(void) +{ + return(mxc_i2c_adap[0].speed); +} + +#ifdef CONFIG_SYS_MXC_I2C2_BASE +static void mxc_i2c2_init(int speed, int slaveaddr) +{ + _i2c_init(speed, slaveaddr, CONFIG_SYS_MXC_I2C2_BASE); + + if (gd->flags & GD_FLG_RELOC) { + mxc_i2c_adap[1].init_done = 1; + mxc_i2c_adap[1].speed = speed; + mxc_i2c_adap[1].slaveaddr = slaveaddr; + } +} + +static int mxc_i2c2_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + return(_i2c_read(chip, addr, alen, buf, len, CONFIG_SYS_MXC_I2C2_BASE)); +} + +static int mxc_i2c2_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + return(_i2c_write(chip, addr, alen, buf, len, CONFIG_SYS_MXC_I2C2_BASE)); +} + +static int mxc_i2c2_probe(uchar chip) +{ + return(_i2c_probe(chip, CONFIG_SYS_MXC_I2C2_BASE)); +} + +static unsigned int mxc_i2c2_set_bus_speed(unsigned int speed) +{ + return(mxc_i2c_adap[1].speed); +} + +static unsigned int mxc_i2c2_get_bus_speed(void) +{ + return(mxc_i2c_adap[1].speed); +} +#endif + +#ifdef CONFIG_SYS_MXC_I2C3_BASE +static void mxc_i2c3_init(int speed, int slaveaddr) +{ + _i2c_init(speed, slaveaddr, CONFIG_SYS_MXC_I2C3_BASE); + + if (gd->flags & GD_FLG_RELOC) { + mxc_i2c_adap[2].init_done = 1; + mxc_i2c_adap[2].speed = speed; + mxc_i2c_adap[2].slaveaddr = slaveaddr; + } +} + +static int mxc_i2c3_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + return(_i2c_read(chip, addr, alen, buf, len, CONFIG_SYS_MXC_I2C3_BASE)); +} + +static int mxc_i2c3_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + return(_i2c_write(chip, addr, alen, buf, len, CONFIG_SYS_MXC_I2C3_BASE)); +} + +static int mxc_i2c_probe(uchar chip) +{ + return(_i2c_probe(chip, CONFIG_SYS_MXC_I2C3_BASE)); +} + +static unsigned int mxc_i2c3_set_bus_speed(unsigned int speed) +{ + return(mxc_i2c_adap[2].speed); +} + +static unsigned int mxc_i2c3_get_bus_speed(void) +{ + return(mxc_i2c_adap[2].speed); +} +#endif + +i2c_adap_t mxc_i2c_adap[] = { + { + .init = mxc_i2c_init, + .probe = mxc_i2c_probe, + .read = mxc_i2c_read, + .write = mxc_i2c_write, + .set_bus_speed = mxc_i2c_set_bus_speed, + .get_bus_speed = mxc_i2c_get_bus_speed, + .speed = CONFIG_SYS_MXC_I2C_SPEED, + .slaveaddr = CONFIG_SYS_MXC_I2C_SLAVE, + .init_done = 0, + .name = MXC_NAME(CONFIG_SYS_MXC_I2C_BASE) + }, +#ifdef CONFIG_SYS_MXC_I2C2_BASE + { + .init = mxc_i2c2_init, + .probe = mxc_i2c2_probe, + .read = mxc_i2c2_read, + .write = mxc_i2c2_write, + .set_bus_speed = mxc_i2c2_set_bus_speed, + .get_bus_speed = mxc_i2c2_get_bus_speed, + .speed = CONFIG_SYS_MXC_I2C2_SPEED, + .slaveaddr = CONFIG_SYS_MXC_I2C2_SLAVE, + .init_done = 0, + .name = MXC_NAME(CONFIG_SYS_MXC_I2C2_BASE) + }, +#endif +#ifdef CONFIG_SYS_MXC_I2C3_BASE + { + .init = mxc_i2c3_init, + .probe = mxc_i2c3_probe, + .read = mxc_i2c3_read, + .write = mxc_i2c3_write, + .set_bus_speed = mxc_i2c3_set_bus_speed, + .get_bus_speed = mxc_i2c3_get_bus_speed, + .speed = CONFIG_SYS_MXC_I2C3_SPEED, + .slaveaddr = CONFIG_SYS_MXC_I2C3_SLAVE, + .init_done = 0, + .name = MXC_NAME(CONFIG_SYS_MXC_I2C3_BASE) + }, +#endif +};

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