February 2009 - U-Boot

[U-Boot] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git
by Stefan Roese 12 Feb '09

12 Feb '09

The following changes since commit f15c6515fc23f83c51f3de272ca23d86b80e81b1: Wolfgang Denk (1): Coding style cleanup; update CHANGELOG are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Adam Graham (1): ppc4xx: Autocalibration can set RDCC to over aggressive value. Carolyn Smith (1): ppc4xx: Fix initialization of the SDRAM_CODT register Dirk Eibach (1): ppc4xx: Add README entry for CONFIG_PCI_DISABLE_PCIE Stefan Roese (2): ppc4xx: Fix problem with CONFIG_MAX_MEM_MAPPED in include/asm-ppc/config.h ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boards README | 4 ++ board/amcc/katmai/katmai.c | 1 + board/amcc/taihu/taihu.c | 1 + board/amcc/taishan/taishan.c | 1 + board/amcc/yucca/yucca.c | 1 + cpu/ppc4xx/44x_spd_ddr2.c | 7 +-- cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 74 +++++++++++++++++++++-------------- include/asm-ppc/config.h | 4 +- include/asm-ppc/ppc4xx-sdram.h | 2 + include/configs/katmai.h | 1 - include/configs/kilauea.h | 7 --- 11 files changed, 59 insertions(+), 44 deletions(-)

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[U-Boot] [PATCH] 82xx, mgcoge: fix compile error
by Heiko Schocher 12 Feb '09

12 Feb '09

With actual u-boot compiling the mgcoge port fails, because since commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56 it is necessary to define CONFIG_NET_MULTI. [hs@pollux u-boot]$ ./MAKEALL mgcoge Configuring for mgcoge board... ether_scc.c:47:2: error: #error "CONFIG_NET_MULTI must be defined." ether_scc.c:47:2: error: #error "CONFIG_NET_MULTI must be defined." make[1]: *** [ether_scc.o] Fehler 1 make: *** [cpu/mpc8260/libmpc8260.a] Fehler 2 make: *** Warte auf noch nicht beendete Prozesse... ppc_82xx-size: './u-boot': No such file [hs@pollux u-boot]$ Seems to me the mgcoge port is the only actual existing 8260 port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed to be fixed. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- include/configs/mgcoge.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 233bee0..b5d12c6 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -64,6 +64,7 @@ #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ +#define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 -- 1.6.0.6 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] [PATCH] ppc4xx: Add README entry for CONFIG_PCI_DISABLE_PCIE
by Dirk Eibach 12 Feb '09

12 Feb '09

Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- README | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/README b/README index 132650e..96aece4 100644 --- a/README +++ b/README @@ -2579,6 +2579,10 @@ Low Level (hardware related) configuration options: CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. +- CONFIG_PCI_DISABLE_PCIE: + Disable PCI-Express on systems where it is supported but not + required. + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs -- 1.5.6.5

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[U-Boot] [PATCH 1/1 v3] ppc4xx: Autocalibration can set RDCC to over aggressive value.
by Adam Graham 12 Feb '09

12 Feb '09

The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham(a)amcc.com> --- v2: - Shortened the maximum patch comment line lengths - Correct coding indentions by using TABS - Correct coding style by removing deep nested if statements v3: - Remove debug changes from v2 patch which had nothing to do with the fix for this patch cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 74 +++++++++++++++++++++-------------- include/asm-ppc/ppc4xx-sdram.h | 2 + include/configs/kilauea.h | 7 --- 3 files changed, 47 insertions(+), 36 deletions(-) diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 1e3e20d..91bf582 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -61,6 +61,8 @@ #define NUMLOOPS 1 /* configure as you deem approporiate */ #define NUMMEMWORDS 16 +#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n)) + /* Private Structure Definitions */ struct autocal_regs { @@ -147,6 +149,13 @@ ulong __ddr_scan_option(ulong default_val) } ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option"))); +u32 __ddr_rdss_opt(u32 default_val) +{ + return default_val; +} +u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt"))); + + static u32 *get_membase(int bxcr_num) { ulong bxcf; @@ -341,6 +350,7 @@ static int short_mem_test(u32 *base_address) ppcDcbf((ulong)&(base_address[j])); } sync(); + iobarrier_rw(); for (l = 0; l < NUMLOOPS; l++) { for (j = 0; j < NUMMEMWORDS; j++) { if (base_address[j] != test[i][j]) { @@ -355,6 +365,7 @@ static int short_mem_test(u32 *base_address) ppcDcbf((u32)&(base_address[j])); } /* for (j = 0; j < NUMMEMWORDS; j++) */ sync(); + iobarrier_rw(); } /* for (l=0; l<NUMLOOPS; l++) */ } @@ -447,7 +458,8 @@ static u32 DQS_calibration_methodA(struct ddrautocal *cal) * Program RDCC register * Read sample cycle auto-update enable */ - mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE); + mtsdram(SDRAM_RDCC, + ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); #ifdef DEBUG mfsdram(SDRAM_RDCC, temp); @@ -633,7 +645,8 @@ static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal) * Program RDCC register * Read sample cycle auto-update enable */ - mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE); + mtsdram(SDRAM_RDCC, + ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); #ifdef DEBUG mfsdram(SDRAM_RDCC, temp); @@ -1091,32 +1104,36 @@ u32 DQS_autocalibration(void) * if no passing window was found, or is the * size of the RFFD passing window. */ - if (result != 0) { - tcal.autocal.flags = 1; - debug("*** (%d)(%d) result passed window size: 0x%08x, " - "rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n", - wdtr, clkp, result, ddrcal.rqfd, - ddrcal.rffd, ddrcal.rdcc); - /* - * Save the SDRAM_WRDTR and SDRAM_CLKTR - * settings for the largest returned - * RFFD passing window size. - */ - if (result > best_result) { + /* + * want the lowest Read Sample Cycle Select + */ + val = SDRAM_RDCC_RDSS_DECODE(val); + debug("*** (%d) (%d) current_rdcc, best_rdcc\n", + val, best_rdcc); + + if ((result != 0) && + (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) { + if (((result == best_result) && (val < best_rdcc)) || + ((result > best_result) && (val <= best_rdcc))) { + tcal.autocal.flags = 1; + debug("*** (%d)(%d) result passed window " + "size: 0x%08x, rqfd = 0x%08x, " + "rffd = 0x%08x, rdcc = 0x%08x\n", + wdtr, clkp, result, ddrcal.rqfd, + ddrcal.rffd, ddrcal.rdcc); + /* - * want the lowest Read Sample Cycle Select + * Save the SDRAM_WRDTR and SDRAM_CLKTR + * settings for the largest returned + * RFFD passing window size. */ - val = (val & SDRAM_RDCC_RDSS_MASK) >> 30; - debug("*** (%d) (%d) current_rdcc, best_rdcc\n", - val, best_rdcc); - if (val <= best_rdcc) { - best_rdcc = val; - tcal.clocks.wrdtr = wdtr; - tcal.clocks.clktr = clkp; - tcal.clocks.rdcc = (val << 30); - tcal.autocal.rqfd = ddrcal.rqfd; - tcal.autocal.rffd = ddrcal.rffd; - best_result = result; + best_rdcc = val; + tcal.clocks.wrdtr = wdtr; + tcal.clocks.clktr = clkp; + tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val); + tcal.autocal.rqfd = ddrcal.rqfd; + tcal.autocal.rffd = ddrcal.rffd; + best_result = result; if (verbose_lvl > 2) { printf("** (%d)(%d) " @@ -1152,9 +1169,8 @@ u32 DQS_autocalibration(void) "loop FCSR: 0x%08x\n", wdtr, clkp, val); } - } /* if (val <= best_rdcc) */ - } /* if (result >= best_result) */ - } /* if (result != 0) */ + } + } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */ scan_list++; } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 98faced..992a3d2 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -566,6 +566,8 @@ #define SDRAM_RDCC_RSAE_MASK 0x00000001 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 +#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30) +#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03) /* * SDRAM Read Feedback Delay Control Register diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 4d3ccf5..26cb854 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -234,16 +234,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if 0 -/* - * Needs FIX!!! - * Disable autocalibration for now, because of the unresolved problem - * with kilauea board using 200MHz PLB/DDR2 frequency - */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) -- 1.5.5

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[U-Boot] [PATCH v2] ppc4xx: Fix initialization of the SDRAM_CODT register
by Stefan Roese 12 Feb '09

12 Feb '09

From: Carolyn Smith <carolyn.smith(a)tektronix.com> This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith(a)tektronix.com> Signed-off-by: Stefan Roese <sr(a)denx.de> --- v2: - Generated by Stefan using git tools - Minor coding style cleanup cpu/ppc4xx/44x_spd_ddr2.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 1e49571..33788cc 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1101,11 +1101,8 @@ static void program_codt(unsigned long *dimm_populated, * Set the SDRAM Controller On Die Termination Register *-----------------------------------------------------------------*/ mfsdram(SDRAM_CODT, codt); - codt |= (SDRAM_CODT_IO_NMODE - & (~SDRAM_CODT_DQS_SINGLE_END - & ~SDRAM_CODT_CKSE_SINGLE_END - & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END - & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END)); + codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END); + codt |= SDRAM_CODT_IO_NMODE; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { if (dimm_populated[dimm_num] != SDRAM_NONE) { -- 1.6.1.3

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[U-Boot] [PATCH 00/40] Blackfin updates for 2009.03
by Mike Frysinger 12 Feb '09

12 Feb '09

Nothing terribly interesting here. Normal smatterings of bug fixes and minor updates as we fold the external Blackfin fork back into mainline. Everything can be found in the "next" branch of the Blackfin git tree: git://www.denx.de/git/u-boot-blackfin.git next Mike Frysinger (40): Blackfin: add defines to describe active bootrom behavior Blackfin: add bit defines for DDR parts Blackfin: convert CMD_LINE_ADDR to CONFIG_LINUX_CMDLINE_{ADDR,SIZE} Blackfin: set more sane default board config values Blackfin: rename bootm.c to boot.c Blackfin: abort dma_memcpy() for L1 scratchpad Blackfin: split cache handling out of dma_memcpy() Blackfin: minimize time cache is turned off when replacing cplb entries Blackfin: pass --bmode/--initcode when creating ldr Blackfin: dont generate ldrs with --force Blackfin: fix dcache handling when doing dma memcpy's Blackfin: bfin_mac: update port muxing Blackfin: do not init i2c in Blackfin board init Blackfin: implement general support for CONFIG_STATUS_LED Blackfin: respect/check CONFIG_SYS_GBL_DATA_SIZE Blackfin: respect CONFIG_SYS_MONITOR_LEN for default flash protection Blackfin: overhaul i2c driver Blackfin: bf533-ezkit: shuffle flash defines a little Blackfin: drop dead/wrong debug code in initdram() Blackfin: bf537-stamp nand: fix more style errors in previous commit Blackfin: tighten up post memory coding style Blackfin: resurrect BF533-STAMP video splash driver Blackfin: punt unused BF533-STAMP definitions Blackfin: set default boot SPI CS for BF538/BF539 Blackfin: use common memcpy routine during init Blackfin: respect CONFIG_CLKIN_HALF Blackfin: add portmuxing for UARTs on the BF51x Blackfin: just set SP register directly during init Blackfin: clarify relocation comment during init Blackfin: pass RETX to Linux Blackfin: handle new anomalies with reset Blackfin: support console-over-JTAG Blackfin: allow serial console to be disabled Blackfin: update on-chip ROM API Blackfin: implement real write support for OTP Blackfin: bootldr: implement BF53x/BF56x LDR loader smc91111_eeprom: move board-specific init into SMC91111_EEPROM_INIT() Blackfin: bf533-stamp: rewrite resource swap logic Blackfin: convert old boards to use COBJS-y Makefile style Blackfin: fixup misc warnings such as printf's and missing casts Makefile | 2 +- blackfin_config.mk | 4 + board/bf533-ezkit/Makefile | 8 +- board/bf533-ezkit/bf533-ezkit.c | 23 +- board/bf533-ezkit/flash-defines.h | 4 +- board/bf533-ezkit/flash.c | 10 +- board/bf533-stamp/Makefile | 12 +- board/bf533-stamp/bf533-stamp.c | 50 +-- board/bf533-stamp/bf533-stamp.h | 3 - board/bf533-stamp/video.c | 167 +++++++++ board/bf533-stamp/video.h | 25 ++ board/bf537-stamp/Makefile | 10 +- board/bf537-stamp/bf537-stamp.c | 14 +- board/bf537-stamp/nand.c | 9 +- board/bf537-stamp/post-memory.c | 23 +- board/bf537-stamp/spi_flash.c | 8 +- board/bf561-ezkit/Makefile | 8 +- board/bf561-ezkit/bf561-ezkit.c | 14 +- common/cmd_bootldr.c | 135 +++++++- common/cmd_cplbinfo.c | 4 +- common/cmd_otp.c | 163 +++++++--- common/devices.c | 3 + cpu/blackfin/Makefile | 9 +- cpu/blackfin/cache.S | 4 +- cpu/blackfin/cpu.c | 6 + cpu/blackfin/i2c.c | 428 ----------------------- cpu/blackfin/initcode.c | 2 +- cpu/blackfin/jtag-console.c | 125 +++++++ cpu/blackfin/reset.c | 20 +- cpu/blackfin/serial.c | 4 + cpu/blackfin/serial.h | 15 +- cpu/blackfin/start.S | 41 +-- cpu/blackfin/traps.c | 52 +-- drivers/i2c/Makefile | 1 + drivers/i2c/bfin-twi_i2c.c | 285 +++++++++++++++ drivers/net/bfin_mac.c | 47 ++- examples/smc91111_eeprom.c | 15 +- include/asm-blackfin/blackfin-config-post.h | 84 ++++- include/asm-blackfin/blackfin_local.h | 2 +- include/asm-blackfin/mach-common/bits/bootrom.h | 72 +++-- include/asm-blackfin/mach-common/bits/ebiu.h | 21 +- include/asm-blackfin/mach-common/bits/otp.h | 21 +- include/configs/bf533-ezkit.h | 2 +- include/configs/bf533-stamp.h | 2 +- include/configs/bf537-stamp.h | 43 +-- include/devices.h | 3 + include/status_led.h | 3 + lib_blackfin/Makefile | 2 +- lib_blackfin/board.c | 37 +- lib_blackfin/boot.c | 63 ++++ lib_blackfin/bootm.c | 56 --- lib_blackfin/string.c | 45 ++- 52 files changed, 1326 insertions(+), 883 deletions(-) create mode 100644 board/bf533-stamp/video.c create mode 100644 board/bf533-stamp/video.h delete mode 100644 cpu/blackfin/i2c.c create mode 100644 cpu/blackfin/jtag-console.c create mode 100644 drivers/i2c/bfin-twi_i2c.c create mode 100644 lib_blackfin/boot.c delete mode 100644 lib_blackfin/bootm.c

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[U-Boot] [PATCH 00/42] Updates cookin for Blackfin for post 2009.03
by Mike Frysinger 12 Feb '09

12 Feb '09

i might snip a simple fix or two for 2009.03, but this is stuff largely cookin for the release after 2009.03. we've got setting unification, cache fix ups, some core cleanups, and crap ton of new board ports. i'm posting this stuff now so it can get sorted out sooner rather than later. Hoan Hoang (1): Blackfin: ibf-dsp561: new board port Mike Frysinger (41): Blackfin: update lockbox api according to latest documentation Blackfin: safely flush data caches when in writeback mode Blackfin: add cache_dump commands Blackfin: print out Flash: before checking it Blackfin: drop now-unused CONFIG_SYS_BFIN_CMD_XXX Blackfin: unify duplicate CPU port definitions Blackfin: drop SPORT_TX read helper macros Blackfin: fix SIC_RVECT definition: it is 16bits, not 32bits Blackfin: simplify symbol_lookup() a bit Blackfin: kill off LDR jump block Blackfin: handle reboot anomaly 432 Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers Blackfin: do not program voltage regulator on parts that do not have one Blackfin: put memory into self-refresh before/after programming clocks Blackfin: unify common ADI board settings Blackfin: bf533-stamp: rewrite startup LED notifications Blackfin: bf533-stamp: bump up default clocks Blackfin: make sure autoconf.mk is generated early enough Blackfin: new spibootldr command Blackfin: add clkin_hz= to default kernel command line for ADI boards Blackfin: bf537-stamp: bump default SCLK up to 125MHz Blackfin: bf537-stamp: increase monitor size Blackfin: add hack for crappy m25p80 Blackfin: add support for SST SPI flashes Blackfin: overhaul SPI flash handling to speed things up Blackfin: add support for S25FL128 parts Blackfin: bf548-ezkit: new board port Blackfin: bf527-ezkit: new board port Blackfin: bf538f-ezkit: new board port Blackfin: bf526-ezbrd: new board port Blackfin: bf518f-ezbrd: new board port Blackfin: cm-bf533: new board port Blackfin: cm-bf537e: new board port Blackfin: cm-bf561: new board port Blackfin: tcm-bf537: new board port Blackfin: cm-bf548: new board port Blackfin: cm-bf527: new board port Blackfin: bf537-pnav: new board port Blackfin: bf537-minotaur: new board port Blackfin: bf537-srv1: new board port Blackfin: blackstamp: new board port MAINTAINERS | 32 ++ MAKEALL | 16 + Makefile | 18 +- blackfin_config.mk | 1 + board/bf518f-ezbrd/.gitignore | 1 + board/bf518f-ezbrd/Makefile | 58 ++ board/bf518f-ezbrd/bf518f-ezbrd.c | 76 +++ board/bf518f-ezbrd/config.mk | 32 ++ board/bf518f-ezbrd/spi_flash.c | 2 + board/bf518f-ezbrd/u-boot.lds.S | 124 ++++ board/bf526-ezbrd/.gitignore | 1 + board/bf526-ezbrd/Makefile | 58 ++ board/bf526-ezbrd/bf526-ezbrd.c | 109 ++++ board/bf526-ezbrd/config.mk | 32 ++ board/bf526-ezbrd/spi_flash.c | 2 + board/bf526-ezbrd/u-boot.lds.S | 124 ++++ board/bf527-ezkit/.gitignore | 1 + board/bf527-ezkit/Makefile | 59 ++ board/bf527-ezkit/bf527-ezkit.c | 60 ++ board/bf527-ezkit/config.mk | 32 ++ board/bf527-ezkit/spi_flash.c | 2 + board/bf527-ezkit/u-boot.lds.S | 124 ++++ board/bf527-ezkit/video.c | 317 +++++++++++ board/bf533-ezkit/u-boot.lds.S | 5 +- board/bf533-stamp/bf533-stamp.c | 62 ++- board/bf533-stamp/u-boot.lds.S | 5 +- board/bf537-minotaur/.gitignore | 1 + board/bf537-minotaur/Makefile | 58 ++ board/bf537-minotaur/bf537-minotaur.c | 43 ++ board/bf537-minotaur/config.mk | 33 ++ board/bf537-minotaur/spi_flash.c | 2 + board/bf537-minotaur/u-boot.lds.S | 143 +++++ board/bf537-pnav/.gitignore | 1 + board/bf537-pnav/Makefile | 59 ++ board/bf537-pnav/bf537-pnav.c | 43 ++ board/bf537-pnav/config.mk | 32 ++ board/bf537-pnav/nand.c | 100 ++++ board/bf537-pnav/spi_flash.c | 2 + board/bf537-pnav/u-boot.lds.S | 143 +++++ board/bf537-srv1/.gitignore | 1 + board/bf537-srv1/Makefile | 58 ++ board/bf537-srv1/bf537-srv1.c | 43 ++ board/bf537-srv1/config.mk | 33 ++ board/bf537-srv1/spi_flash.c | 2 + board/bf537-srv1/u-boot.lds.S | 143 +++++ board/bf537-stamp/spi_flash.c | 297 ++++++++-- board/bf537-stamp/u-boot.lds.S | 5 +- board/bf538f-ezkit/.gitignore | 1 + board/bf538f-ezkit/Makefile | 57 ++ board/bf538f-ezkit/bf538f-ezkit.c | 27 + board/bf538f-ezkit/config.mk | 33 ++ board/bf538f-ezkit/u-boot.lds.S | 143 +++++ board/bf548-ezkit/.gitignore | 1 + board/bf548-ezkit/Makefile | 59 ++ board/bf548-ezkit/bf548-ezkit.c | 79 +++ board/bf548-ezkit/config.mk | 37 ++ board/bf548-ezkit/spi_flash.c | 2 + board/bf548-ezkit/u-boot.lds.S | 124 ++++ board/bf548-ezkit/video.c | 327 +++++++++++ board/bf561-ezkit/u-boot.lds.S | 5 +- board/blackstamp/.gitignore | 1 + board/blackstamp/Makefile | 58 ++ board/blackstamp/blackstamp.c | 53 ++ board/blackstamp/config.mk | 32 ++ board/blackstamp/spi_flash.c | 2 + board/blackstamp/u-boot.lds.S | 143 +++++ board/cm-bf527/.gitignore | 1 + board/cm-bf527/Makefile | 59 ++ board/cm-bf527/cm-bf527.c | 59 ++ board/cm-bf527/config.mk | 32 ++ board/cm-bf527/flash-defines.h | 51 ++ board/cm-bf527/flash.c | 589 ++++++++++++++++++++ board/cm-bf527/gpio.c | 74 +++ board/cm-bf527/nand.c | 2 + board/cm-bf527/spi_flash.c | 2 + board/cm-bf527/u-boot.lds.S | 124 ++++ board/cm-bf533/.gitignore | 1 + board/cm-bf533/Makefile | 57 ++ board/cm-bf533/cm-bf533.c | 25 + board/cm-bf533/config.mk | 33 ++ board/cm-bf533/flash-defines.h | 49 ++ board/cm-bf533/flash.c | 283 ++++++++++ board/cm-bf533/u-boot.lds.S | 143 +++++ board/cm-bf537e/.gitignore | 1 + board/cm-bf537e/Makefile | 58 ++ board/cm-bf537e/cm-bf537e.c | 44 ++ board/cm-bf537e/config.mk | 33 ++ board/cm-bf537e/flash-defines.h | 50 ++ board/cm-bf537e/flash.c | 449 +++++++++++++++ board/cm-bf537e/spi_flash.c | 2 + board/cm-bf537e/u-boot.lds.S | 143 +++++ board/cm-bf548/.gitignore | 1 + board/cm-bf548/Makefile | 60 ++ board/cm-bf548/cm-bf548.c | 79 +++ board/cm-bf548/config.mk | 36 ++ board/cm-bf548/nand.c | 2 + board/cm-bf548/spi_flash.c | 2 + board/cm-bf548/u-boot.lds.S | 124 ++++ board/cm-bf548/video.c | 339 +++++++++++ board/cm-bf561/.gitignore | 1 + board/cm-bf561/Makefile | 57 ++ board/cm-bf561/cm-bf561.c | 25 + board/cm-bf561/config.mk | 33 ++ board/cm-bf561/u-boot.lds.S | 143 +++++ board/ibf-dsp561/.gitignore | 1 + board/ibf-dsp561/Makefile | 57 ++ board/ibf-dsp561/config.mk | 33 ++ board/ibf-dsp561/ibf-dsp561.c | 25 + board/ibf-dsp561/u-boot.lds.S | 145 +++++ board/tcm-bf537/.gitignore | 1 + board/tcm-bf537/Makefile | 58 ++ board/tcm-bf537/config.mk | 33 ++ board/tcm-bf537/flash-defines.h | 52 ++ board/tcm-bf537/flash.c | 583 +++++++++++++++++++ board/tcm-bf537/spi_flash.c | 2 + board/tcm-bf537/tcm-bf537.c | 44 ++ board/tcm-bf537/u-boot.lds.S | 143 +++++ common/Makefile | 1 + common/cmd_spibootldr.c | 36 ++ cpu/blackfin/cpu.c | 8 +- cpu/blackfin/initcode.c | 254 +++++++-- cpu/blackfin/start.S | 83 ++-- cpu/blackfin/traps.c | 2 +- include/asm-blackfin/blackfin-config-pre.h | 6 - .../mach-bf527/ADSP-EDN-BF52x-extended_cdef.h | 8 +- include/asm-blackfin/mach-bf527/ports.h | 75 +--- include/asm-blackfin/mach-bf533/ports.h | 18 +- .../mach-bf537/ADSP-EDN-BF534-extended_cdef.h | 8 +- include/asm-blackfin/mach-bf537/ports.h | 56 +-- .../mach-bf548/ADSP-EDN-BF542-extended_cdef.h | 3 - .../mach-bf548/ADSP-EDN-BF544-extended_cdef.h | 3 - .../mach-bf548/ADSP-EDN-BF547-extended_cdef.h | 4 - .../mach-bf548/ADSP-EDN-BF548-extended_cdef.h | 4 - .../mach-bf548/ADSP-EDN-BF549-extended_cdef.h | 4 - include/asm-blackfin/mach-bf548/ports.h | 189 +------ include/asm-blackfin/mach-bf561/def_local.h | 2 + include/asm-blackfin/mach-bf561/ports.h | 44 ++ .../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h | 2 - .../mach-common/ADSP-EDN-extended_cdef.h | 2 - include/asm-blackfin/mach-common/bits/bootrom.h | 27 + include/asm-blackfin/mach-common/bits/lockbox.h | 70 ++-- include/asm-blackfin/mach-common/bits/ports-a.h | 25 + include/asm-blackfin/mach-common/bits/ports-b.h | 25 + include/asm-blackfin/mach-common/bits/ports-c.h | 25 + include/asm-blackfin/mach-common/bits/ports-d.h | 25 + include/asm-blackfin/mach-common/bits/ports-e.h | 25 + include/asm-blackfin/mach-common/bits/ports-f.h | 25 + include/asm-blackfin/mach-common/bits/ports-g.h | 25 + include/asm-blackfin/mach-common/bits/ports-h.h | 25 + include/asm-blackfin/mach-common/bits/ports-i.h | 25 + include/asm-blackfin/mach-common/bits/ports-j.h | 25 + include/configs/bf518f-ezbrd.h | 137 +++++ include/configs/bf526-ezbrd.h | 166 ++++++ include/configs/bf527-ezkit.h | 158 ++++++ include/configs/bf533-ezkit.h | 286 ++++------ include/configs/bf533-stamp.h | 450 ++++++---------- include/configs/bf537-minotaur.h | 214 +++++++ include/configs/bf537-pnav.h | 271 +++++++++ include/configs/bf537-srv1.h | 214 +++++++ include/configs/bf537-stamp.h | 423 +++++---------- include/configs/bf538f-ezkit.h | 125 +++++ include/configs/bf548-ezkit.h | 201 +++++++ include/configs/bf561-ezkit.h | 295 ++++------ include/configs/bfin_adi_common.h | 199 +++++++ include/configs/blackstamp.h | 266 +++++++++ include/configs/cm-bf527.h | 144 +++++ include/configs/cm-bf533.h | 100 ++++ include/configs/cm-bf537e.h | 133 +++++ include/configs/cm-bf548.h | 150 +++++ include/configs/cm-bf561.h | 100 ++++ include/configs/ibf-dsp561.h | 130 +++++ include/configs/tcm-bf537.h | 135 +++++ lib_blackfin/Makefile | 1 + lib_blackfin/board.c | 2 +- lib_blackfin/cache.c | 42 ++ lib_blackfin/cmd_cache_dump.c | 145 +++++ 176 files changed, 12360 insertions(+), 1508 deletions(-) create mode 100644 board/bf518f-ezbrd/.gitignore create mode 100644 board/bf518f-ezbrd/Makefile create mode 100644 board/bf518f-ezbrd/bf518f-ezbrd.c create mode 100644 board/bf518f-ezbrd/config.mk create mode 100644 board/bf518f-ezbrd/spi_flash.c create mode 100644 board/bf518f-ezbrd/u-boot.lds.S create mode 100644 board/bf526-ezbrd/.gitignore create mode 100644 board/bf526-ezbrd/Makefile create mode 100644 board/bf526-ezbrd/bf526-ezbrd.c create mode 100644 board/bf526-ezbrd/config.mk create mode 100644 board/bf526-ezbrd/spi_flash.c create mode 100644 board/bf526-ezbrd/u-boot.lds.S create mode 100644 board/bf527-ezkit/.gitignore create mode 100644 board/bf527-ezkit/Makefile create mode 100644 board/bf527-ezkit/bf527-ezkit.c create mode 100644 board/bf527-ezkit/config.mk create mode 100644 board/bf527-ezkit/spi_flash.c create mode 100644 board/bf527-ezkit/u-boot.lds.S create mode 100644 board/bf527-ezkit/video.c create mode 100644 board/bf537-minotaur/.gitignore create mode 100644 board/bf537-minotaur/Makefile create mode 100644 board/bf537-minotaur/bf537-minotaur.c create mode 100644 board/bf537-minotaur/config.mk create mode 100644 board/bf537-minotaur/spi_flash.c create mode 100644 board/bf537-minotaur/u-boot.lds.S create mode 100644 board/bf537-pnav/.gitignore create mode 100644 board/bf537-pnav/Makefile create mode 100644 board/bf537-pnav/bf537-pnav.c create mode 100644 board/bf537-pnav/config.mk create mode 100644 board/bf537-pnav/nand.c create mode 100644 board/bf537-pnav/spi_flash.c create mode 100644 board/bf537-pnav/u-boot.lds.S create mode 100644 board/bf537-srv1/.gitignore create mode 100644 board/bf537-srv1/Makefile create mode 100644 board/bf537-srv1/bf537-srv1.c create mode 100644 board/bf537-srv1/config.mk create mode 100644 board/bf537-srv1/spi_flash.c create mode 100644 board/bf537-srv1/u-boot.lds.S create mode 100644 board/bf538f-ezkit/.gitignore create mode 100644 board/bf538f-ezkit/Makefile create mode 100644 board/bf538f-ezkit/bf538f-ezkit.c create mode 100644 board/bf538f-ezkit/config.mk create mode 100644 board/bf538f-ezkit/u-boot.lds.S create mode 100644 board/bf548-ezkit/.gitignore create mode 100644 board/bf548-ezkit/Makefile create mode 100644 board/bf548-ezkit/bf548-ezkit.c create mode 100644 board/bf548-ezkit/config.mk create mode 100644 board/bf548-ezkit/spi_flash.c create mode 100644 board/bf548-ezkit/u-boot.lds.S create mode 100644 board/bf548-ezkit/video.c create mode 100644 board/blackstamp/.gitignore create mode 100644 board/blackstamp/Makefile create mode 100644 board/blackstamp/blackstamp.c create mode 100644 board/blackstamp/config.mk create mode 100644 board/blackstamp/spi_flash.c create mode 100644 board/blackstamp/u-boot.lds.S create mode 100644 board/cm-bf527/.gitignore create mode 100644 board/cm-bf527/Makefile create mode 100644 board/cm-bf527/cm-bf527.c create mode 100644 board/cm-bf527/config.mk create mode 100644 board/cm-bf527/flash-defines.h create mode 100644 board/cm-bf527/flash.c create mode 100644 board/cm-bf527/gpio.c create mode 100644 board/cm-bf527/nand.c create mode 100644 board/cm-bf527/spi_flash.c create mode 100644 board/cm-bf527/u-boot.lds.S create mode 100644 board/cm-bf533/.gitignore create mode 100644 board/cm-bf533/Makefile create mode 100644 board/cm-bf533/cm-bf533.c create mode 100644 board/cm-bf533/config.mk create mode 100644 board/cm-bf533/flash-defines.h create mode 100644 board/cm-bf533/flash.c create mode 100644 board/cm-bf533/u-boot.lds.S create mode 100644 board/cm-bf537e/.gitignore create mode 100644 board/cm-bf537e/Makefile create mode 100644 board/cm-bf537e/cm-bf537e.c create mode 100644 board/cm-bf537e/config.mk create mode 100644 board/cm-bf537e/flash-defines.h create mode 100644 board/cm-bf537e/flash.c create mode 100644 board/cm-bf537e/spi_flash.c create mode 100644 board/cm-bf537e/u-boot.lds.S create mode 100644 board/cm-bf548/.gitignore create mode 100644 board/cm-bf548/Makefile create mode 100644 board/cm-bf548/cm-bf548.c create mode 100644 board/cm-bf548/config.mk create mode 100644 board/cm-bf548/nand.c create mode 100644 board/cm-bf548/spi_flash.c create mode 100644 board/cm-bf548/u-boot.lds.S create mode 100644 board/cm-bf548/video.c create mode 100644 board/cm-bf561/.gitignore create mode 100644 board/cm-bf561/Makefile create mode 100644 board/cm-bf561/cm-bf561.c create mode 100644 board/cm-bf561/config.mk create mode 100644 board/cm-bf561/u-boot.lds.S create mode 100644 board/ibf-dsp561/.gitignore create mode 100644 board/ibf-dsp561/Makefile create mode 100644 board/ibf-dsp561/config.mk create mode 100644 board/ibf-dsp561/ibf-dsp561.c create mode 100644 board/ibf-dsp561/u-boot.lds.S create mode 100644 board/tcm-bf537/.gitignore create mode 100644 board/tcm-bf537/Makefile create mode 100644 board/tcm-bf537/config.mk create mode 100644 board/tcm-bf537/flash-defines.h create mode 100644 board/tcm-bf537/flash.c create mode 100644 board/tcm-bf537/spi_flash.c create mode 100644 board/tcm-bf537/tcm-bf537.c create mode 100644 board/tcm-bf537/u-boot.lds.S create mode 100644 common/cmd_spibootldr.c create mode 100644 include/asm-blackfin/mach-bf561/ports.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-a.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-b.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-c.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-d.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-e.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-f.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-g.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-h.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-i.h create mode 100644 include/asm-blackfin/mach-common/bits/ports-j.h create mode 100644 include/configs/bf518f-ezbrd.h create mode 100644 include/configs/bf526-ezbrd.h create mode 100644 include/configs/bf527-ezkit.h create mode 100644 include/configs/bf537-minotaur.h create mode 100644 include/configs/bf537-pnav.h create mode 100644 include/configs/bf537-srv1.h create mode 100644 include/configs/bf538f-ezkit.h create mode 100644 include/configs/bf548-ezkit.h create mode 100644 include/configs/bfin_adi_common.h create mode 100644 include/configs/blackstamp.h create mode 100644 include/configs/cm-bf527.h create mode 100644 include/configs/cm-bf533.h create mode 100644 include/configs/cm-bf537e.h create mode 100644 include/configs/cm-bf548.h create mode 100644 include/configs/cm-bf561.h create mode 100644 include/configs/ibf-dsp561.h create mode 100644 include/configs/tcm-bf537.h create mode 100644 lib_blackfin/cmd_cache_dump.c

4 57

[U-Boot] [PATCH] drivers/serial/ns16550: move ifdef into Makefile COBJS-$(...)
by Mike Frysinger 12 Feb '09

12 Feb '09

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/serial/Makefile | 4 ++-- drivers/serial/ns16550.c | 5 ----- drivers/serial/serial.c | 4 ---- 3 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 17235ff..abe2c02 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,10 +28,10 @@ LIB := $(obj)libserial.a COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o -COBJS-y += ns16550.o +COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o -COBJS-y += serial.o +COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 93c2243..a9391c7 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -5,9 +5,6 @@ */ #include <config.h> - -#ifdef CONFIG_SYS_NS16550 - #include <ns16550.h> #define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ @@ -75,5 +72,3 @@ int NS16550_tstc (NS16550_t com_port) { return ((com_port->lsr & LSR_DR) != 0); } - -#endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index bce7548..966df9a 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -23,8 +23,6 @@ #include <common.h> -#ifdef CONFIG_SYS_NS16550_SERIAL - #include <ns16550.h> #ifdef CONFIG_NS87308 #include <ns87308.h> @@ -328,5 +326,3 @@ DECLARE_ESERIAL_FUNCTIONS(4); struct serial_device eserial4_device = INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4"); #endif /* CONFIG_SERIAL_MULTI */ - -#endif -- 1.6.1.2

2 3

[U-Boot] [PATCH 1/3] Add support for W90P710 ARM7 SoC
by Vovk Konstantin 12 Feb '09

12 Feb '09

Add support for CPU and serial communication. Interrupt not used for work with Timer0. Serial communication configured for UART0. --- cpu/arm720t/cpu.c | 48 ++++++- cpu/arm720t/interrupts.c | 82 +++++++++++- cpu/arm720t/serial.c | 115 ++++++++++++++- cpu/arm720t/start.S | 30 ++++- include/asm-arm/arch-arm720t/W90P710.h | 240 +++++++++++++++++++++++++++++++ include/asm-arm/arch-arm720t/hardware.h | 2 + include/asm-arm/io.h | 4 + 7 files changed, 512 insertions(+), 9 deletions(-) create mode 100644 include/asm-arm/arch-arm720t/W90P710.h diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 5ac8f59..1cee570 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -73,7 +73,7 @@ int cleanup_before_linux (void) /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) || defined(CONFIG_W90P710) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) @@ -253,6 +253,52 @@ int dcache_status (void) { } #elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ + +#elif defined(CONFIG_W90P710) +void icache_enable (void) +{ + PUT_REG (REG_CAHCON, 0x05); /* Flush I-cache */ + while (GET_REG (REG_CAHCON)); /* Wait for operation progress */ + + PUT_REG (REG_CAHCNF, 0x01); /* Enable I-CACHE */ +} + +void icache_disable (void) +{ + PUT_REG (REG_CAHCON, 0x05); /* Flush I-cache */ + while (GET_REG (REG_CAHCON)); /* Wait for operation progress */ + /* Disable I-cache */ + PUT_REG (REG_CAHCNF, GET_REG (REG_CAHCNF) & (~0x01)); +} + +int icache_status (void) +{ + /* Check if I-Cache enable */ + return (GET_REG (REG_CAHCNF) & 0x01) != 0; +} + +void dcache_enable (void) +{ + PUT_REG (REG_CAHCON, 0x06); /* Flush D-cache */ + while (GET_REG (REG_CAHCON)); /* Wait for operation progress */ + + PUT_REG (REG_CAHCNF, GET_REG (REG_CAHCNF) | 0x02); /* Enable D-CACHE */ +} + +void dcache_disable (void) +{ + PUT_REG (REG_CAHCON, 0x06); /* Flush D-cache */ + while (GET_REG (REG_CAHCON)); /* Wait for operation progress */ + /* Disable D-cache */ + PUT_REG (REG_CAHCNF, GET_REG (REG_CAHCNF) & (~0x02)); +} + +int dcache_status (void) +{ + /* Check if D-Cache enable */ + return (GET_REG (REG_CAHCNF) & 0x02) != 0; +} + #else #error No icache/dcache enable/disable functions defined for this CPU type #endif diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..050610a 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -50,6 +50,14 @@ #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) #endif +#ifdef CONFIG_W90P710 +#undef TIMER_LOAD_VAL +/* We have the 24-bit timer - set maximum value*/ +#define TIMER_LOAD_VAL (0x00FFFFFF) +#undef READ_TIMER +#define READ_TIMER (GET_REG(REG_TDR0) & 0xFFFFFF) +#endif + #ifdef CONFIG_S3C4510B /* require interrupts for the S3C4510B */ # ifndef CONFIG_USE_IRQ @@ -80,6 +88,8 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr; (*pfnct)(); +#elif defined(CONFIG_W90P710) +/* No do_irq() for W90P710 as yet */ #else #error do_irq() not defined for this CPU type #endif @@ -185,7 +195,18 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ - +#elif defined(CONFIG_W90P710) + /* Stop Timer0 */ + PUT_REG(REG_TCR0, 0x00000000); + /* Enable Timer clock */ + PUT_REG(REG_CLKSEL, GET_REG(REG_CLKSEL) | 0x40); + /* Set Timer0 reload value*/ + PUT_REG(REG_TICR0, (TIMER_LOAD_VAL)); + /* Save to lastdec value that we load to the timer*/ + lastdec = TIMER_LOAD_VAL; + /* CEN=1 - Timer0 Start counting, MODE = 01 - Timer0 is operat in pereodic mode */ + /* IE = 0 - Disable Timer0 interrupt Prescaler=0x0E Timer clock is 15000000/(14+1)=1Mhz*/ + PUT_REG(REG_TCR0, 0x4800000E); #else #error No interrupt_init() defined for this CPU type #endif @@ -305,6 +326,65 @@ void udelay (unsigned long usec) #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ + +#elif defined(CONFIG_W90P710) +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + ulong timestamp_in_us; + /* Get timestamp in uS */ + timestamp_in_us = get_timer_masked (); + /* Convert timestamp in mS and subtract base*/ + return timestamp_in_us/1000 - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; + + if (lastdec >= now){ /* normal mode */ + timestamp += (lastdec - now); + } + else{ /* we have an overflow ... */ + timestamp += (lastdec + TIMER_LOAD_VAL - now); + } + lastdec = now; + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + ulong endtime; + signed long diff; + + endtime = get_timer_masked () + usec; + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +void udelay (unsigned long usec) +{ + udelay_masked (usec); +} + #else #error Timer routines not defined for this CPU type #endif diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 54a9b31..e9bc652 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -169,13 +169,13 @@ int serial_init (void) void serial_putc (const char c) { - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ + if (c == '\n') { + /* Wait for empty U0THR */ + while((GET8(U0LSR) & (1<<5)) == 0); PUT8(U0THR, '\r'); } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ + /* Wait for empty U0THR */ + while((GET8(U0LSR) & (1<<5)) == 0); PUT8(U0THR, c); } @@ -199,4 +199,109 @@ int serial_tstc (void) return (GET8(U0LSR) & 1); } +#elif defined(CONFIG_W90P710) + +DECLARE_GLOBAL_DATA_PTR; + +#include <asm/arch/hardware.h> + +void serial_setbrg (void) +{ + unsigned int divider = 0; + + /* use values for 15Mhz quarts */ + switch (gd->baudrate) { + case 1200: divider = 779; break; + case 2400: divider = 389; break; + case 4800: divider = 193; break; + case 9600: divider = 96; break; + case 14400: divider = 65; break; + case 19200: divider = 47; break; + case 38400: divider = 22; break; + case 57600: divider = 14; break; + case 115200: divider = 6; break; + default: hang (); break; + } + + /* Reset LCR register and disable Uart interrupt*/ + PUT_REG (REG_UART0_LCR, 0x0); + PUT_REG (REG_UART0_IER, 0x0); + + /* Set baud rate to mentioned in divider */ + /* Set DLAB to '1' to access Divisor */ + PUT_REG (REG_UART0_LCR, GET_REG (REG_UART0_LCR) | (1 << 7)); + PUT_REG (REG_UART0_LSB, (divider & 0xFF)); + PUT_REG (REG_UART0_MSB, ((divider >> 8) & 0xFF)); + /* Reset DLAB to '0' to access RBR, THR, IER */ + PUT_REG (REG_UART0_LCR, GET_REG (REG_UART0_LCR) & (~(1 << 7))); + + /* Set port parameters 8 bit, 1 stop, no parity */ + PUT_REG (REG_UART0_LCR, GET_REG (REG_UART0_LCR) | + ((1 << 0) | (1 << 1))); + + /* + * Set the RX FIFO trigger level to 8 bytes, + * reset RX, TX FIFO, Enable FIFO + */ + PUT_REG (REG_UART0_FCR, ((0x2 << 6) | (1 << 2) | (1 << 1) | (1 << 0))); + + /* Reset timeout comparator */ + PUT_REG (REG_UART0_TOR, 0x0); +} + +/* Initialise the serial port with the given baudrate. Settings are 8N1 */ +int serial_init (void) +{ + unsigned int Temp; + + serial_setbrg (); + + /* Set GPIO_CFG to use pins PORT5_0 as TXD0 and PORT5_1 as RXD0 */ + Temp = GET_REG (REG_GPIO_CFG5); + Temp |= 0X00000005; + Temp &= 0XFFFFFFF5; + PUT_REG (REG_GPIO_CFG5, Temp); + return (0); +} + +/* Check for Transmitter holding register is empty */ +void CheckForUART0TXReady (void) +{ + unsigned int Status; + + do { + Status = GET_REG (REG_UART0_LSR); + } + while (!(Status & (1 << 6))); /* Check for TE=1*/ +} + +/*Put one character to Uart0 TX FIFO. Add 'LF' after 'CR'*/ +void serial_putc (const char c) +{ + if (c == '\n') { + /* Wait for empty THR */ + CheckForUART0TXReady (); + PUT_REG (REG_UART0_TX, '\r'); + } + CheckForUART0TXReady (); + PUT_REG (REG_UART0_TX, c); +} + +int serial_getc (void) +{ + while ((GET_REG (REG_UART0_LSR) & 1) == 0); + return GET_REG(REG_UART0_RX); +} + +int serial_tstc (void) +{ + return (GET_REG (REG_UART0_LSR) & 1); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} #endif diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 022b873..055515a 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -1,8 +1,8 @@ /* * armboot - Startup Code for ARM720 CPU-core * - * Copyright (c) 2001 Marius Gr?ger <mag(a)sysgo.de> - * Copyright (c) 2002 Alex Z?pke <azu(a)sysgo.de> + * Copyright (c) 2001 Marius Gr???ger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Z???pke <azu(a)sysgo.de> * * See file CREDITS for list of people who contributed to this * project. @@ -224,6 +224,14 @@ PLLSTAT_ADR: .word PLLSTAT VPBDIV_ADR: .word VPBDIV MEMMAP_ADR: .word MEMMAP +#elif defined(CONFIG_W90P710) + +#define CAHCON 0xFFF02004 /* Cache control register */ +#define AIC_MDCR 0xFFF82124 /* AIC Mask Disable Control Register */ +#define CAHCNF 0xFFF02000 /* Cache configuration register */ +#define IDREG 0xFFF00000 /* W90P710 CHIP ID */ +#define CKSKEW 0xFFF01F00 /* Clock Skew Control register */ + #endif cpu_init_crit: @@ -368,6 +376,21 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] + +#elif defined(CONFIG_W90P710) + /* Disable Interrupt */ + LDR r0, =AIC_MDCR + LDR r1, =0x7FFFE + STR r1, [r0] + /* Disable FIQ and IRQ */ + MRS r0, CPSR + ORR r0, r0, #0xC0 + MSR CPSR_c, r0 + /* Disable I-Cache and D-cache entirely */ + LDR r1,=CAHCNF + MOV r0, #0x0 + STR r0, [r1] + #else #error No cpu_init_crit() defined for current CPU type #endif @@ -606,6 +629,9 @@ reset_cpu: .globl reset_cpu reset_cpu: mov pc, r0 +#elif defined(CONFIG_W90P710) +/* Nothing done here as reseting the CPU is board specific, depending on external peripherals see lowlevel_init.c*/ + #else #error No reset_cpu() defined for current CPU type #endif diff --git a/include/asm-arm/arch-arm720t/W90P710.h b/include/asm-arm/arch-arm720t/W90P710.h new file mode 100644 index 0000000..c6be724 --- /dev/null +++ b/include/asm-arm/arch-arm720t/W90P710.h @@ -0,0 +1,240 @@ +/* + * (C) Copyright 2008 + * KSL Embedded Development Team <www.kslemb.com> + * Konstantin Vovk <ksl(a)kslemb.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: Nuvoton W90P710 register layout definition + */ +#ifndef _W90P710_H +#define _W90P710_H + +/* L1 8KB on chip SRAM base address */ +#define SRAM_BASE 0xFFE00000 + +#define GET_REG(reg) (*((volatile unsigned int *)(reg))) +#define PUT_REG(reg, val) (*((volatile unsigned int *)(reg))) = (unsigned int)(val) + +/* System Address Map - Defines the register base address */ +#define GCR_BA 0xFFF00000 /* Global Control */ +#define EBI_BA 0xFFF01000 /* EBI Control */ +#define CACHE_BA 0xFFF02000 /* Cache Control */ +#define EMC_BA 0xFFF03000 /* Ethernet MAC */ +#define GDMA_BA 0xFFF04000 /* GDMA control */ +#define USBH_BA 0xFFF05000 /* USB Host Control */ +#define USBD_BA 0xFFF06000 /* USB Device Control */ +#define FMI_BA 0xFFF07000 /* Flash Memory Card Interface */ +#define LCD_BA 0xFFF08000 /* Display, LCM Interface & Bypass */ +#define ADO_BA 0xFFF09000 /* Audio Control */ + +#define UART0_BA 0xFFF80000 /* UART0 Control (console) */ +#define UART1_BA 0xFFF80100 /* UART1 Control (Bluetooth) */ +#define UART2_BA 0xFFF80200 /* UART2 Control (IrDA) */ +#define UART3_BA 0xFFF80300 /* UART3 Control (micro-printer) */ +#define TMR_BA 0xFFF81000 /* Timer */ +#define AIC_BA 0xFFF82000 /* Interrupt Controller */ +#define GPIO_BA 0xFFF83000 /* GPIO Control */ +#define RTC_BA 0xFFF84000 /* Real Time Clock Control */ +#define SCHI0_BA 0xFFF85000 /* Smart Card Host Interface 0 Control */ +#define SCHI1_BA 0xFFF85800 /* Smart Card Host Interface 1 Control */ +#define I2C0_BA 0xFFF86000 /* I2C 0 Control */ +#define I2C1_BA 0xFFF86100 /* I2C 1 Control */ +#define SSP_BA 0xFFF86200 /* Synchronous Serial Port */ +#define PWM_BA 0xFFF87000 /* Pulse Width Modulation Control */ +#define KPI_BA 0xFFF88000 /* Keypad Interface Control */ +#define PS2_BA 0xFFF89000 /* PS2 Interface Control */ + +/* System Manager Control Registers */ +#define REG_PDID (GCR_BA+0x0000) /* Product Identifier */ +#define REG_ARBCON (GCR_BA+0x0004) /* Arbitration Control */ +#define REG_PLLCON (GCR_BA+0x0008) /* PLL Control */ +#define REG_CLKSEL (GCR_BA+0x000C) /* Clock Select */ +#define REG_PLLCON2 (GCR_BA+0x0010) /* PLL Control2 */ +#define REG_I2SCKCON (GCR_BA+0x0014) /* Audio IIS Clock Control */ +#define REG_IRQWAKECON (GCR_BA+0x0020) /* IRQ Wakeup Control */ +#define REG_IRQWAKEFLAG (GCR_BA+0x0024) /* IRQ Wakeup Flag */ +#define REG_PMCON (GCR_BA+0x0028) /* Power Manager */ +#define REG_USBTXRCON (GCR_BA+0x0030) /* USB transceiver */ + +/* Memory Control Registers */ +#define REG_EBICON (EBI_BA+0x000) /* EBI control */ +#define REG_ROMCON (EBI_BA+0x004) /* ROM/FLASH control */ +#define REG_SDCONF0 (EBI_BA+0x008) /* SDRAM bank 0 configuration */ +#define REG_SDCONF1 (EBI_BA+0x00C) /* SDRAM bank 1 configuration */ +#define REG_SDTIME0 (EBI_BA+0x010) /* SDRAM bank 0 timing control */ +#define REG_SDTIME1 (EBI_BA+0x014) /* SDRAM bank 1 timing control */ +#define REG_EXT0CON (EBI_BA+0x018) /* External I/O 0 control */ +#define REG_EXT1CON (EBI_BA+0x01C) /* External I/O 1 control */ +#define REG_EXT2CON (EBI_BA+0x020) /* External I/O 2 control */ +#define REG_EXT3CON (EBI_BA+0x024) /* External I/O 3 control */ + +/* Cache Control Registers */ +#define REG_CAHCNF (CACHE_BA+0x000)/* Cache configuration */ +#define REG_CAHCON (CACHE_BA+0x004)/* Cache control */ +#define REG_CAHADR (CACHE_BA+0x008)/* Cache address */ + +/* MAC Control registers*/ +#define REG_CAMCMR (EMC_BA+0x000) /* CAM Command */ +#define REG_CAMEN (EMC_BA+0x004) /* CAM Enable */ +#define REG_CAM0M_Base (EMC_BA+0x008) +#define REG_CAM0L_Base (EMC_BA+0x00c) + +#define REG_TXDLSA (EMC_BA+0x088) /* Transmit Descriptor Link List Start Address Register */ +#define REG_RXDLSA (EMC_BA+0x08C) /* Receive Descriptor Link List Start Address Register */ +#define REG_MCMDR (EMC_BA+0x090) /* MAC Command */ +#define REG_MIID (EMC_BA+0x094) /* MII Management Data */ +#define REG_MIIDA (EMC_BA+0x098) /* MII Management Control and Address */ +#define REG_FFTCR (EMC_BA+0x09C) /* FIFO Threshold Control */ +#define REG_TSDR (EMC_BA+0x0a0) /* Transmit Start Demand */ +#define REG_RSDR (EMC_BA+0x0a4) /* Receive Start Demand */ +#define REG_DMARFC (EMC_BA+0x0a8) /* Maximum Receive Frame Control */ +#define REG_MIEN (EMC_BA+0x0ac) /* MAC Interrupt Enable */ + +/* MAC Status Registers */ +#define REG_MISTA (EMC_BA+0x0b0) /* MAC Interrupt Status */ +#define REG_MGSTA (EMC_BA+0x0b4) /* MAC General Status */ +#define REG_MPCNT (EMC_BA+0x0b8) /* Missed Packet Count */ +#define REG_MRPC (EMC_BA+0x0bc) /* MAC Receive Pause Count */ +#define REG_MRPCC (EMC_BA+0x0c0) /* MAC Receive Pause Current Count */ +#define REG_MREPC (EMC_BA+0x0c4) /* MAC Remote Pause Count */ +#define REG_DMARFS (EMC_BA+0x0c8) /* DMA Receive Frame Status */ +#define REG_CTXDSA (EMC_BA+0x0cc) /* Transmit Descriptor Start Address */ +#define REG_CTXBSA (EMC_BA+0x0d0) /* Transmit Buffer Start Address */ +#define REG_CRXDSA (EMC_BA+0x0d4) /* Receive Descriptor Start Address */ +#define REG_CRXBSA (EMC_BA+0x0d8) /* Receive Buffer Start Address */ + +/* MAC Diagnostic Registers */ +#define REG_RXFSM (EMC_BA+0x200) /* Receive Finite State Machine */ +#define REG_TXFSM (EMC_BA+0x204) /* Transmit Finite State Machine */ +#define REG_FSM0 (EMC_BA+0x208) /* Finite State Machine0 */ +#define REG_FSM1 (EMC_BA+0x20c) /* Finite State Machine1 */ +#define REG_DCR (EMC_BA+0x210) /* Debug Configuration */ +#define REG_DMMIR (EMC_BA+0x214) /* Debug Mode MAC Information */ +#define REG_BISTR (EMC_BA+0x300) /* BIST Mode */ + +/* USB Host Controller Registers */ +#define REG_HcRevision (USBH_BA+0x000) /* Revision */ +#define REG_HcControl (USBH_BA+0x004) /* Control */ +#define REG_HcCommandStatus (USBH_BA+0x008) /* Command Status */ +#define REG_HcInterruptStatus (USBH_BA+0x00C) /* Interrupt Status */ +#define REG_HcInterruptEnable (USBH_BA+0x010) /* Interrupt Enable */ +#define REG_HcInterruptDisable (USBH_BA+0x014) /* Interrupt Disable */ +#define REG_HcHCCA (USBH_BA+0x018) /* Communication Area */ +#define REG_HcPeriodCurrentED (USBH_BA+0x01C) /* Period Current ED */ +#define REG_HcControlHeadED (USBH_BA+0x020) /* Control Head ED */ +#define REG_HcControlCurrentED (USBH_BA+0x024) /* Control Current ED */ +#define REG_HcBulkHeadED (USBH_BA+0x028) /* Bulk Head ED */ +#define REG_HcBulkCurrentED (USBH_BA+0x02C) /* Bulk Current ED */ +#define REG_HcDoneHead (USBH_BA+0x030) /* Done Head */ +#define REG_HcFmInterval (USBH_BA+0x034) /* Frame Interval */ +#define REG_HcFrameRemaining (USBH_BA+0x038) /* Frame Remaining */ +#define REG_HcFmNumber (USBH_BA+0x03C) /* Frame Number */ +#define REG_HcPeriodicStart (USBH_BA+0x040) /* Periodic Start */ +#define REG_HcLSThreshold (USBH_BA+0x044) /* Low Speed Threshold */ +#define REG_HcRhDescriptorA (USBH_BA+0x048) /* Root Hub Descriptor A */ +#define REG_HcRhDescriptorB (USBH_BA+0x04C) /* Root Hub Descriptor B */ +#define REG_HcRhStatus (USBH_BA+0x050) /* Root Hub Status */ +#define REG_HcRhPortStatus1 (USBH_BA+0x054) /* Root Hub Port Status1 */ +#define REG_HcRhPortStatus2 (USBH_BA+0x058) /* Root Hub Port Status2 */ + +/* USB Configuration Registers */ +#define TestModeEnable (USBH_BA+0x200) /* USB Test Mode Enable */ +#define OperationalModeEnable (USBH_BA+0x204) /* USB Operational Mode Enable*/ + +/* UART0 Control Registers */ +#define REG_UART0_TX (UART0_BA+0x0) /* TX buffer */ +#define REG_UART0_RX (UART0_BA+0x0) /* RX buffer */ +#define REG_UART0_LSB (UART0_BA+0x0) /* Divisor latch LSB */ +#define REG_UART0_MSB (UART0_BA+0x04) /* Divisor latch MSB */ +#define REG_UART0_IER (UART0_BA+0x04) /* Interrupt enable */ +#define REG_UART0_IIR (UART0_BA+0x08) /* Interrupt ident */ +#define REG_UART0_FCR (UART0_BA+0x08) /* FIFO control */ +#define REG_UART0_LCR (UART0_BA+0x0C) /* Line control */ +#define REG_UART0_LSR (UART0_BA+0x14) /* Line status */ +#define REG_UART0_TOR (UART0_BA+0x1C) /* Time out */ + +/* Timer Control Registers */ +#define REG_TCR0 (TMR_BA+0x0) /* Control Register 0 */ +#define REG_TCR1 (TMR_BA+0x04) /* Control Register 1 */ +#define REG_TICR0 (TMR_BA+0x08) /* Initial Control Register 0 */ +#define REG_TICR1 (TMR_BA+0x0C) /* Initial Control Register 1 */ +#define REG_TDR0 (TMR_BA+0x10) /* Data Register 0 */ +#define REG_TDR1 (TMR_BA+0x14) /* Data Register 1 */ +#define REG_TISR (TMR_BA+0x18) /* Interrupt Status */ +#define REG_WTCR (TMR_BA+0x1C) /* Watchdog Timer Control */ + +/* Advanced Interrupt Controller Registers */ +#define REG_AIC_IRSR (AIC_BA+0x100) /* Raw status */ +#define REG_AIC_IASR (AIC_BA+0x104) /* Active status */ +#define REG_AIC_ISR (AIC_BA+0x108) /* Status register */ +#define REG_AIC_IPER (AIC_BA+0x10C) /* Priority encoding */ +#define REG_AIC_ISNR (AIC_BA+0x110) /* Source number */ +#define REG_AIC_IMR (AIC_BA+0x114) /* Mask register */ +#define REG_AIC_OISR (AIC_BA+0x118) /* Interrupt status */ +#define REG_AIC_MECR (AIC_BA+0x120) /* Mask enable command */ +#define REG_AIC_MDCR (AIC_BA+0x124) /* Mask disable command */ +#define REG_AIC_SSCR (AIC_BA+0x128) /* Source set command */ +#define REG_AIC_SCCR (AIC_BA+0x12C) /* Source clear command */ +#define REG_AIC_EOSCR (AIC_BA+0x130) /* End of service command */ +#define REG_AIC_TEST (AIC_BA+0x200) /* ICE/Debug mode */ + +/* General-Purpose Input/Output Controller Registers */ + #define GPIO_OFFSET 0x10 +/* Port 0 */ +#define REG_GPIO_CFG0 (GPIO_BA+0x0000) /* Configuration */ +#define REG_GPIO_DIR0 (GPIO_BA+0x0004) /* Direction control */ +#define REG_GPIO_DATAOUT0 (GPIO_BA+0x0008) /* Data out */ +#define REG_GPIO_DATAIN0 (GPIO_BA+0x000c) /* Data input */ +/* Port 1 */ +#define REG_GPIO_CFG1 (GPIO_BA+0x0010) /* Configuration */ +#define REG_GPIO_DIR1 (GPIO_BA+0x0014) /* Direction control */ +#define REG_GPIO_DATAOUT1 (GPIO_BA+0x0018) /* Data out */ +#define REG_GPIO_DATAIN1 (GPIO_BA+0x001c) /* Data input */ +/* Port 2 */ +#define REG_GPIO_CFG2 (GPIO_BA+0x0020) /* Configuration */ +#define REG_GPIO_DIR2 (GPIO_BA+0x0024) /* Direction control */ +#define REG_GPIO_DATAOUT2 (GPIO_BA+0x0028) /* Data out */ +#define REG_GPIO_DATAIN2 (GPIO_BA+0x002c) /* Data input */ +/* Port 3 */ +#define REG_GPIO_CFG3 (GPIO_BA+0x0030) /* Configuration */ +#define REG_GPIO_DIR3 (GPIO_BA+0x0034) /* Direction control */ +#define REG_GPIO_DATAOUT3 (GPIO_BA+0x0038) /* Data out */ +#define REG_GPIO_DATAIN3 (GPIO_BA+0x003c) /* Data input */ +/* Port 4 */ +#define REG_GPIO_CFG4 (GPIO_BA+0x0040) /* Configuration */ +#define REG_GPIO_DIR4 (GPIO_BA+0x0044) /* Direction control */ +#define REG_GPIO_DATAOUT4 (GPIO_BA+0x0048) /* Data out */ +#define REG_GPIO_DATAIN4 (GPIO_BA+0x004c) /* Data input */ +/* Port 5 */ +#define REG_GPIO_CFG5 (GPIO_BA+0x0050) /* Configuration */ +#define REG_GPIO_DIR5 (GPIO_BA+0x0054) /* Direction control */ +#define REG_GPIO_DATAOUT5 (GPIO_BA+0x0058) /* Data out */ +#define REG_GPIO_DATAIN5 (GPIO_BA+0x005c) /* Data input */ +/* Port 6 */ +#define REG_GPIO_CFG6 (GPIO_BA+0x0060) /* Configuration */ +#define REG_GPIO_DIR6 (GPIO_BA+0x0064) /* Direction control */ +#define REG_GPIO_DATAOUT6 (GPIO_BA+0x0068) /* Data out */ +#define REG_GPIO_DATAIN6 (GPIO_BA+0x006c) /* Data input */ + +#define REG_GPIO_DBNCECON (GPIO_BA+0x0070) /* Input debounce */ +#define REG_GPIO_XICFG (GPIO_BA+0x0074) /* Interrupt Configure*/ +#define REG_GPIO_XISTATUS (GPIO_BA+0x0078) /* Interrupt Status */ + +#endif /* _W90P710_H */ diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index 3056ca7..7f31b6c 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -36,6 +36,8 @@ /* include armadillo specific hardware file if there was one */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* include IntegratorCP/CM720T specific hardware file if there was one */ +#elif defined(CONFIG_W90P710) +#include <asm-arm/arch-arm720t/W90P710.h> #else #error No hardware file defined for this configuration #endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index fec3a7e..4e17d22 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -46,6 +46,10 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { + #ifdef CONFIG_W90P710 + if (flags == MAP_NOCACHE) + paddr |= 0x80000000; + #endif return (void *)paddr; } -- 1.5.4.3

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Re: [U-Boot] Loading Linux Image on AT91SAM9263-EK
by Derek Ou 11 Feb '09

11 Feb '09

You can use U-boot to write the file to NAND as well. The address does not matter as long as your bootcmd is reading the kernel from the same address. Please check your U-boot environment settings and your nand dump of the NAND location (0x200000). If you want to get help, post those information. Derek > Date: Wed, 11 Feb 2009 15:33:19 -0400 > From: Amandeep Bhullar <abhullar(a)techlinkentertainment.com> > Subject: [U-Boot] Loading Linux Image on AT91SAM9263-EK > To: dasfoo(a)yahoo.com > > I have questions about loading the Linux Image. Do I just use SAM-BA > v2.7 tool and send file uImage to address 0x200000? I tied that and I > got Error: Cant get kernel image. > > Any help will be appreciated !! > > Aman. >

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