February 2009 - U-Boot

[U-Boot] SDRAM error for RD_EN and 2T_EN
by hendrik 16 Feb '09

16 Feb '09

hi all I am going through the SPD DRAM setup for my mpc8548 board (using DDR2) - when I run uboot I get an error saying: Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] should not be set at the same time. As far as I could tell, neither of these two settings are within my control: RD_EN is set by "populate_memctl_options" according to "spd->dimm_type" (In my case it is a Mini-RDIMM ) 2T_EN is set in ddr/options.c and is hard coded as popts->twoT_en = 1; In U-boot1.2 i found 2T timing is dependant on the CPU version, Should this still be the case? in spd)sdram.c: if (pvr != PVR_85xx_REV1) { #if defined(CONFIG_DDR_2T_TIMING) /* * Enable 2T timing by setting sdram_cfg[16]. */ sdram_cfg |= 0x8000; /* 2T_EN */ #endif } What should i do to get rid of this error? My initial efforts show by hacking RD_en = 0 is the only way to get my board to boot. but this roes not feel like the way to go. I would appreciate any help. thanks Hendrik

1 0

[U-Boot] registered SORDIMM MT9HTF6472RHY-667F1
by arun sharma 16 Feb '09

16 Feb '09

i am using mpc8360 emds board. it is working fine with socdimm. but with sordimm not working. there is minor change i have done it for sordimm as follows for testing only. /* sdram_cfg[3] = RD_EN - registered DIMM enable */ // if (spd.mod_attr & 0x02) vivek // { printf("sdramcfg[3] registered DIMM\n"); sdram_cfg |= SDRAM_CFG_RD_EN; // } //#if defined(CONFIG_DDR_2T_TIMING) vivek /* * Enable 2T timing by setting sdram_cfg[16]. */ // sdram_cfg |= SDRAM_CFG_2T_EN; //#endif i have enabled spd_debug and check the configuration. CPU: e300c1, MPC8358_TBGA_EA, Rev: 2.1 at 396 MHz, CSB: 198 MHz Board: Freescale MPC8360EMDS I2C: ready DRAM: DIMM type: 9HTF6472RHY-667F1 SPD size: 128 EEPROM size: 256 Memory type: 8 Row addr: 14 Column addr: 10 # of rows: 96 Row density: 128 # of banks: 4 Data width: 72 Chip width: 8 Refresh rate: 82 CAS latencies: 38 Write latencies: 04 tRP: 60 tRCD: 60 cs0_bnds = 0x0000001f cs0_config = 0x80010202 DDR:bar=0x00000000 DDR:ar=0x8000001c DDR: caslat SPD bit is 5 DDR:Module maximum data rate is: 666 MHz DDR:Effective data rate is: 200MHz DDR:The MSB 1 of CAS Latency is: 5 DDR: effective data rate is 200 MHz DDR: caslat SPD bit is 5, controller field is 0x9 DDR: timing_cfg_0 = 0x00260802 DDR:timing_cfg_1=0x25293211 DDR:timing_cfg_2=0x0fa028c4 DDR DIMM: data bus width is 64 bit with ECC DDR:sdram_mode=0x04400252 DDR: sdram_mode2 = 0x00000000 DDR:sdram_interval=0x03050100 DDR: sdram_cfg2 = 0x00401000 DDR:sdram_clk_cntl=0x02000000 sdramcfg[3] registered DIMM DDR:err_disable=0x0000000d DDR:err_sbe=0x00ff0000 DDRC ECC mode: ON DDR:sdram_cfg=0xf3000000 ddr init: CPU FP write method READY!! ddr init duration: 2090 ms 512 MB (DDR2, 64-bit, ECC on, 198 MHz) Testing DRAM from 0x00000000 to 0x00200000 DRAM test phase 1: write done DRAM test phase 2: DRAM test passed. regards

1 1

[U-Boot] Pull request: u-boot-usb
by Remy Bohmer 15 Feb '09

15 Feb '09

The following changes since commit 6b67962fd69ac0bcdf1a982669a029c2f0a7bcc1: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx are available in the git repository at: git://git.denx.de/u-boot-usb.git master Abraham, Thomas (1): USB: Remove LUN number from CDB Atin Malaviya (1): Added usbtty_configured() check. Fixed attribute(packed) warnings. common/usb_storage.c | 5 ----- drivers/serial/usbtty.c | 18 +++++++++++------- 2 files changed, 11 insertions(+), 12 deletions(-)

2 1

[U-Boot] [i2c] Please pull git://git.denx.de/u-boot-i2c.git
by Heiko Schocher 15 Feb '09

15 Feb '09

The following changes since commit f15c6515fc23f83c51f3de272ca23d86b80e81b1: Wolfgang Denk (1): Coding style cleanup; update CHANGELOG are available in the git repository at: git://git.denx.de/u-boot-i2c.git master Guennadi Liakhovetski (1): i.MX31: Start the I2C clock on driver initialisation Mike Frysinger (1): i2c.h: drop i2c_reg_{read, write} hack for Blackfin parts drivers/i2c/mxc_i2c.c | 6 ++++++ include/i2c.h | 14 -------------- 2 files changed, 6 insertions(+), 14 deletions(-) [hs@pollux u-boot-i2c]$ -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [i2c] Please pull git://git.denx.de/u-boot-i2c.git
by Heiko Schocher 15 Feb '09

15 Feb '09

The following changes since commit f15c6515fc23f83c51f3de272ca23d86b80e81b1: Wolfgang Denk (1): Coding style cleanup; update CHANGELOG are available in the git repository at: git://git.denx.de/u-boot-i2c.git master Mike Frysinger (1): i2c.h: drop i2c_reg_{read, write} hack for Blackfin parts include/i2c.h | 14 -------------- 1 files changed, 0 insertions(+), 14 deletions(-) -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [U-BOOT][PATCH 3/3] Fix miscalculated total sectors
by unsik Kim 14 Feb '09

14 Feb '09

When using CONFIG_MG_DISK_RES, total sectors should be recalculated. Signed-off-by: unsik Kim <donari75(a)gmail.com> --- drivers/block/mg_disk.c | 18 ++++++++++++++---- 1 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/block/mg_disk.c b/drivers/block/mg_disk.c index e1b1a68..193a441 100644 --- a/drivers/block/mg_disk.c +++ b/drivers/block/mg_disk.c @@ -174,7 +174,7 @@ static int mg_get_disk_id (void) { u32 iobuf[(MG_SECTOR_SIZE / sizeof(u32))]; hd_driveid_t *iop = (hd_driveid_t *)iobuf; - u32 i, err; + u32 i, err, res; u16 *buff = (u16 *)iobuf; writeb(MG_CMD_ID, MG_BASE + MG_REG_COMMAND); @@ -214,11 +214,21 @@ static int mg_get_disk_id (void) #endif /* __LITTLE_ENDIAN */ #ifdef __BIG_ENDIAN - mg_disk_dev.lba = (iop->lba_capacity << 16) | (iop->lba_capacity >> 16); -#else /* ! __BIG_ENDIAN */ - mg_disk_dev.lba = iop->lba_capacity; + iop->lba_capacity = (iop->lba_capacity << 16) | + (iop->lba_capacity >> 16); #endif /* __BIG_ENDIAN */ + if (MG_RES_SEC) { + MG_DBG("MG_RES_SEC=%d\n", MG_RES_SEC); + iop->cyls = (iop->lba_capacity - MG_RES_SEC) / + iop->sectors / iop->heads; + res = iop->lba_capacity - + iop->cyls * iop->heads * iop->sectors; + iop->lba_capacity -= res; + printf("mg_disk: %d sectors reserved\n", res); + } + + mg_disk_dev.lba = iop->lba_capacity; return MG_ERR_NONE; } -- 1.5.6.6

2 1

[U-Boot] [PATCH v2] i.MX31: Start the I2C clock on driver initialisation
by Guennadi Liakhovetski 14 Feb '09

14 Feb '09

i.MX31 powers on with most clocks running, so, after a power on this explicit clock start up is not required. However, as Linux boots it disables most clocks to save power. This includes the I2C clock. If we then soft reboot from Linux the I2C clock stays off. This breaks the phycore, which has its environment in I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver initialisation routine. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: Clock is initialised in the I2C driver now, not in board code. Thanks to Jean-Christophe for suggesting. drivers/i2c/mxc_i2c.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index eedad06..8e10fbb 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -49,10 +49,13 @@ #ifdef CONFIG_SYS_I2C_MX31_PORT1 #define I2C_BASE 0x43f80000 +#define I2C_CLK_OFFSET 26 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) #define I2C_BASE 0x43f98000 +#define I2C_CLK_OFFSET 28 #elif defined (CONFIG_SYS_I2C_MX31_PORT3) #define I2C_BASE 0x43f84000 +#define I2C_CLK_OFFSET 30 #else #error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver" #endif @@ -72,6 +75,9 @@ void i2c_init(int speed, int unused) int freq = mx31_get_ipg_clk(); int i; + /* start the required I2C clock */ + __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET); + for (i = 0; i < 0x1f; i++) if (freq / div[i] <= speed) break; -- 1.5.4

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[U-Boot] [PATCH] Multiadapter/multibus I2C, at91rm9200 and friends
by ksi＠koi8.net 14 Feb '09

14 Feb '09

Initial multiadapter/multibus I2C support. Atmel AT91RM9200 based boards. This goes on top of previous patches. Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.ORIG/board/cmc_pu2/load_sernum_ethaddr.c u-boot-i2c/board/cmc_pu2/load_sernum_ethaddr.c --- u-boot-i2c.ORIG/board/cmc_pu2/load_sernum_ethaddr.c 2009-02-12 10:43:40.000000000 -0800 +++ u-boot-i2c/board/cmc_pu2/load_sernum_ethaddr.c 2009-02-13 16:29:00.000000000 -0800 @@ -75,7 +75,7 @@ void load_sernum_ethaddr (void) unsigned char *p; unsigned short i, is, id; -#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C) +#if !defined(CONFIG_HAS_I2C) #error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C) #endif if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data, diff -purN u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/i2c.c u-boot-i2c/cpu/arm920t/at91rm9200/i2c.c --- u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/i2c.c 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/cpu/arm920t/at91rm9200/i2c.c 1969-12-31 16:00:00.000000000 -0800 @@ -1,202 +0,0 @@ -/* - * i2c Support for Atmel's AT91RM9200 Two-Wire Interface - * - * (c) Rick Bronson - * - * Borrowed heavily from original work by: - * Copyright (c) 2000 Philip Edelbrock <phil(a)stimpy.netroedge.com> - * - * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj(a)denx.de - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * -*/ -#include <common.h> - -#ifdef CONFIG_HARD_I2C - -#include <i2c.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -#include <at91rm9200_i2c.h> - -/* define DEBUG */ - -/* - * Poll the i2c status register until the specified bit is set. - * Returns 0 if timed out (100 msec) - */ -static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { - int loop_cntr = 10000; - do { - udelay(10); - } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); - - return (loop_cntr > 0); -} - -/* - * Generic i2c master transfer entrypoint - * - * rw == 1 means that this is a read - */ -static int -at91_xfer(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len, int rw) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - int length; - unsigned char *buf; - /* Set the TWI Master Mode Register */ - twi->TWI_MMR = (chip << 16) | (alen << 8) - | ((rw == 1) ? AT91C_TWI_MREAD : 0); - - /* Set TWI Internal Address Register with first messages data field */ - if (alen > 0) - twi->TWI_IADR = addr; - - length = len; - buf = buffer; - if (length && buf) { /* sanity check */ - if (rw) { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { - debug ("at91_i2c: timeout 1\n"); - return 1; - } - *buf++ = twi->TWI_RHR; - } - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 2\n"); - return 1; - } - } else { - twi->TWI_CR = AT91C_TWI_START; - while (length--) { - twi->TWI_THR = *buf++; - if (!length) - twi->TWI_CR = AT91C_TWI_STOP; - if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { - debug ("at91_i2c: timeout 3\n"); - return 1; - } - } - /* Wait until transfer is finished */ - if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { - debug ("at91_i2c: timeout 4\n"); - return 1; - } - } - } - return 0; -} - -int -i2c_probe(unsigned char chip) -{ - unsigned char buffer[1]; - - return at91_xfer(chip, 0, 0, buffer, 1, 1); -} - -int -i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 1); -} - -int -i2c_write(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - int i; - unsigned char *buf; - - /* we only allow one address byte */ - if (alen > 1) - return 1; - /* XXX assume an ATMEL AT24C16 */ - if (alen == 1) { - buf = buffer; - /* do single byte writes */ - for (i = 0; i < len; i++) { -#if 0 /* EEPROM code already sets this correctly */ - chip |= (addr >> 8) & 0xff; -#endif - addr = addr & 0xff; - if (at91_xfer(chip, addr, alen, buf++, 1, 0)) - return 1; - addr++; - } - return 0; - } -#endif - return at91_xfer(chip, addr, alen, buffer, len, 0); -} - -/* - * Main initialization routine - */ -void -i2c_init(int speed, int slaveaddr) -{ - AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; - - *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; - *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ - - twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ - twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ - twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ - - /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ - twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); - - debug ("Found AT91 i2c\n"); - return; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - return -1; -} - -unsigned int i2c_get_bus_speed(void) -{ - return CONFIG_SYS_I2C_SPEED; -} - -#endif /* CONFIG_HARD_I2C */ diff -purN u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/Makefile u-boot-i2c/cpu/arm920t/at91rm9200/Makefile --- u-boot-i2c.ORIG/cpu/arm920t/at91rm9200/Makefile 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/cpu/arm920t/at91rm9200/Makefile 2009-02-13 15:36:53.000000000 -0800 @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ +COBJS = bcm5221.o dm9161.o ether.o interrupts.o \ lxt972.o serial.o usb.o spi.o SOBJS = lowlevel_init.o diff -purN u-boot-i2c.ORIG/drivers/i2c/at91_i2c.c u-boot-i2c/drivers/i2c/at91_i2c.c --- u-boot-i2c.ORIG/drivers/i2c/at91_i2c.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-i2c/drivers/i2c/at91_i2c.c 2009-02-13 15:52:08.000000000 -0800 @@ -0,0 +1,216 @@ +/* + * i2c Support for Atmel's AT91RM9200 Two-Wire Interface + * + * Copyright (c) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Changes for multibus/multiadapter I2C support. + * + * (c) Rick Bronson + * + * Borrowed heavily from original work by: + * Copyright (c) 2000 Philip Edelbrock <phil(a)stimpy.netroedge.com> + * + * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj(a)denx.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * +*/ +#include <common.h> + +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#include <at91rm9200_i2c.h> + +/* define DEBUG */ + +i2c_adap_t at91_i2c_adap; + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Poll the i2c status register until the specified bit is set. + * Returns 0 if timed out (100 msec) + */ +static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { + int loop_cntr = 10000; + do { + udelay(10); + } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); + + return (loop_cntr > 0); +} + +/* + * Generic i2c master transfer entrypoint + * + * rw == 1 means that this is a read + */ +static int +at91_xfer(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len, int rw) +{ + AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; + int length; + unsigned char *buf; + /* Set the TWI Master Mode Register */ + twi->TWI_MMR = (chip << 16) | (alen << 8) + | ((rw == 1) ? AT91C_TWI_MREAD : 0); + + /* Set TWI Internal Address Register with first messages data field */ + if (alen > 0) + twi->TWI_IADR = addr; + + length = len; + buf = buffer; + if (length && buf) { /* sanity check */ + if (rw) { + twi->TWI_CR = AT91C_TWI_START; + while (length--) { + if (!length) + twi->TWI_CR = AT91C_TWI_STOP; + /* Wait until transfer is finished */ + if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { + debug ("at91_i2c: timeout 1\n"); + return 1; + } + *buf++ = twi->TWI_RHR; + } + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + debug ("at91_i2c: timeout 2\n"); + return 1; + } + } else { + twi->TWI_CR = AT91C_TWI_START; + while (length--) { + twi->TWI_THR = *buf++; + if (!length) + twi->TWI_CR = AT91C_TWI_STOP; + if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { + debug ("at91_i2c: timeout 3\n"); + return 1; + } + } + /* Wait until transfer is finished */ + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + debug ("at91_i2c: timeout 4\n"); + return 1; + } + } + } + return 0; +} + +static int at91_i2c_probe(unsigned char chip) +{ + unsigned char buffer[1]; + + return at91_xfer(chip, 0, 0, buffer, 1, 1); +} + +static int at91_i2c_read (unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* we only allow one address byte */ + if (alen > 1) + return 1; + /* XXX assume an ATMEL AT24C16 */ + if (alen == 1) { +#if 0 /* EEPROM code already sets this correctly */ + chip |= (addr >> 8) & 0xff; +#endif + addr = addr & 0xff; + } +#endif + return at91_xfer(chip, addr, alen, buffer, len, 1); +} + +static int at91_i2c_write(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len) +{ +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + int i; + unsigned char *buf; + + /* we only allow one address byte */ + if (alen > 1) + return 1; + /* XXX assume an ATMEL AT24C16 */ + if (alen == 1) { + buf = buffer; + /* do single byte writes */ + for (i = 0; i < len; i++) { +#if 0 /* EEPROM code already sets this correctly */ + chip |= (addr >> 8) & 0xff; +#endif + addr = addr & 0xff; + if (at91_xfer(chip, addr, alen, buf++, 1, 0)) + return 1; + addr++; + } + return 0; + } +#endif + return at91_xfer(chip, addr, alen, buffer, len, 0); +} + +/* + * Main initialization routine + */ +static void at91_i2c_init(int speed, int slaveaddr) +{ + AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE; + + *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; + *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ + + twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ + twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ + twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */ + + /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */ + twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8); + + debug ("Found AT91 i2c\n"); + return; +} + +static unsigned int at91_i2c_set_bus_speed(unsigned int speed) +{ + return CONFIG_SYS_AT91_I2C_SPEED; +} + +static unsigned int at91_i2c_get_bus_speed(void) +{ + return CONFIG_SYS_AT91_I2C_SPEED; +} + + +i2c_adap_t at91_i2c_adap = { + .init = at91_i2c_init, + .probe = at91_i2c_probe, + .read = at91_i2c_read, + .write = at91_i2c_write, + .set_bus_speed = at91_i2c_set_bus_speed, + .get_bus_speed = at91_i2c_get_bus_speed, + .speed = CONFIG_SYS_AT91_I2C_SPEED, + .slaveaddr = CONFIG_SYS_AT91_I2C_SLAVE, + .init_done = 0, + .name = "at91_i2c" +}; diff -purN u-boot-i2c.ORIG/drivers/i2c/i2c_core.c u-boot-i2c/drivers/i2c/i2c_core.c --- u-boot-i2c.ORIG/drivers/i2c/i2c_core.c 2009-02-13 16:34:36.000000000 -0800 +++ u-boot-i2c/drivers/i2c/i2c_core.c 2009-02-13 15:52:58.000000000 -0800 @@ -6,6 +6,10 @@ #include <common.h> #include <i2c.h> +#ifdef CONFIG_AT91_I2C +extern i2c_adap_t at91_i2c_adap; +#endif + #ifdef CONFIG_BFIN_TWI_I2C extern i2c_adap_t bfin_twi_i2c_adap; #endif diff -purN u-boot-i2c.ORIG/drivers/i2c/Makefile u-boot-i2c/drivers/i2c/Makefile --- u-boot-i2c.ORIG/drivers/i2c/Makefile 2009-02-13 16:34:36.000000000 -0800 +++ u-boot-i2c/drivers/i2c/Makefile 2009-02-13 16:26:58.000000000 -0800 @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libi2c.a +COBJS-$(CONFIG_AT91_I2C) += at91_i2c.o COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_MXC_I2C) += mxc_i2c.o Binary files u-boot-i2c.ORIG/.git/index and u-boot-i2c/.git/index differ diff -purN u-boot-i2c.ORIG/include/configs/cmc_pu2.h u-boot-i2c/include/configs/cmc_pu2.h --- u-boot-i2c.ORIG/include/configs/cmc_pu2.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/cmc_pu2.h 2009-02-13 16:18:53.000000000 -0800 @@ -96,11 +96,14 @@ #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -#define CONFIG_HARD_I2C +#define CONFIG_HAS_I2C -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ +#ifdef CONFIG_HAS_I2C +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ #define CONFIG_SYS_I2C_RTC_ADDR 0x32 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 @@ -136,7 +139,7 @@ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MISC -#if defined(CONFIG_HARD_I2C) +#if defined(CONFIG_HAS_I2C) #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C diff -purN u-boot-i2c.ORIG/include/configs/kb9202.h u-boot-i2c/include/configs/kb9202.h --- u-boot-i2c.ORIG/include/configs/kb9202.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/kb9202.h 2009-02-13 16:10:08.000000000 -0800 @@ -128,7 +128,11 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_HARD_I2C +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_ENV_IS_IN_EEPROM @@ -142,8 +146,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ diff -purN u-boot-i2c.ORIG/include/configs/m501sk.h u-boot-i2c/include/configs/m501sk.h --- u-boot-i2c.ORIG/include/configs/m501sk.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/m501sk.h 2009-02-13 16:11:36.000000000 -0800 @@ -94,9 +94,11 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100 -#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_ENV_IS_IN_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 diff -purN u-boot-i2c.ORIG/include/configs/mp2usb.h u-boot-i2c/include/configs/mp2usb.h --- u-boot-i2c.ORIG/include/configs/mp2usb.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/mp2usb.h 2009-02-13 16:14:57.000000000 -0800 @@ -115,11 +115,14 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#undef CONFIG_HARD_I2C +#undef CONFIG_HAS_I2C -#ifdef CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ +#ifdef CONFIG_HAS_I2C +#define CONFIG_NEW_I2C +#define CONFIG_AT91_I2C +#define CONFIG_SYS_AT91_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_AT91_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_ADAPTERS {&at91_i2c_adap} #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ #define CONFIG_SYS_I2C_RTC_ADDR 0x32 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 @@ -131,7 +134,7 @@ #define CONFIG_BOOTDELAY 3 -#if !defined(CONFIG_HARD_I2C) +#if !defined(CONFIG_HAS_I2C) #define CONFIG_TIMESTAMP #endif @@ -154,7 +157,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP -#if defined(CONFIG_HARD_I2C) +#if defined(CONFIG_HAS_I2C) #define CONFIG_CMD_DATE #define CONFIG_CMD_EEPROM

2 1

[U-Boot] [PATCH] 9/12 Multiadapter/multibus I2C, configs part 2, fixed
by ksi＠koi8.net 13 Feb '09

13 Feb '09

Initial multiadapter/multibus I2C support. Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/include/configs/MHPC.h u-boot-i2c/include/configs/MHPC.h --- u-boot-i2c.orig/include/configs/MHPC.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MHPC.h 2009-02-12 10:46:00.000000000 -0800 @@ -72,7 +72,12 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_NEW_I2C +#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS +#define CONFIG_SYS_SOFT_I2C_SPEED 50000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_ADAPTERS {&soft_i2c_adap[0]} /* * Software (bit-bang) I2C driver configuration */ @@ -89,8 +94,6 @@ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ diff -purN u-boot-i2c.orig/include/configs/MPC8313ERDB.h u-boot-i2c/include/configs/MPC8313ERDB.h --- u-boot-i2c.orig/include/configs/MPC8313ERDB.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8313ERDB.h 2009-02-12 10:46:00.000000000 -0800 @@ -318,15 +318,17 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 #define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ /* * General PCI diff -purN u-boot-i2c.orig/include/configs/MPC8315ERDB.h u-boot-i2c/include/configs/MPC8315ERDB.h --- u-boot-i2c.orig/include/configs/MPC8315ERDB.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8315ERDB.h 2009-02-12 10:46:00.000000000 -0800 @@ -272,13 +272,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ /* * Board info - revision and where boot from diff -purN u-boot-i2c.orig/include/configs/MPC8323ERDB.h u-boot-i2c/include/configs/MPC8323ERDB.h --- u-boot-i2c.orig/include/configs/MPC8323ERDB.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8323ERDB.h 2009-02-12 10:46:00.000000000 -0800 @@ -313,13 +313,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ /* * Config on-board EEPROM diff -purN u-boot-i2c.orig/include/configs/MPC832XEMDS.h u-boot-i2c/include/configs/MPC832XEMDS.h --- u-boot-i2c.orig/include/configs/MPC832XEMDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC832XEMDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -323,13 +323,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ /* * Config on-board RTC diff -purN u-boot-i2c.orig/include/configs/MPC8349EMDS.h u-boot-i2c/include/configs/MPC8349EMDS.h --- u-boot-i2c.orig/include/configs/MPC8349EMDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8349EMDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -347,16 +347,17 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 #define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ /* SPI */ #define CONFIG_MPC8XXX_SPI diff -purN u-boot-i2c.orig/include/configs/MPC8349ITX.h u-boot-i2c/include/configs/MPC8349ITX.h --- u-boot-i2c.orig/include/configs/MPC8349ITX.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8349ITX.h 2009-02-12 10:46:00.000000000 -0800 @@ -90,31 +90,29 @@ */ /* I2C */ -#ifdef CONFIG_HARD_I2C - +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 #define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +/* Don't probe these addresses: */ +#define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ + {1, CONFIG_SYS_I2C_8574_ADDR2}, \ + {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ + {1, CONFIG_SYS_I2C_8574A_ADDR2}} #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ - #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ - -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* Don't probe these addresses: */ -#define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574_ADDR2}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR2}} +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ +#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ /* Bit definitions for the 8574[A] I2C expander */ #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ @@ -122,10 +120,6 @@ #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ -#undef CONFIG_SOFT_I2C - -#endif - /* Compact Flash */ #ifdef CONFIG_COMPACT_FLASH diff -purN u-boot-i2c.orig/include/configs/MPC8360EMDS.h u-boot-i2c/include/configs/MPC8360EMDS.h --- u-boot-i2c.orig/include/configs/MPC8360EMDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8360EMDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -348,14 +348,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */ /* * Config on-board RTC diff -purN u-boot-i2c.orig/include/configs/MPC8360ERDK.h u-boot-i2c/include/configs/MPC8360ERDK.h --- u-boot-i2c.orig/include/configs/MPC8360ERDK.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8360ERDK.h 2009-02-12 10:46:00.000000000 -0800 @@ -261,16 +261,17 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 #define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x52}} /* Don't probe these addrs */ /* * General PCI diff -purN u-boot-i2c.orig/include/configs/MPC837XEMDS.h u-boot-i2c/include/configs/MPC837XEMDS.h --- u-boot-i2c.orig/include/configs/MPC837XEMDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC837XEMDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -320,14 +320,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ /* * Config on-board RTC diff -purN u-boot-i2c.orig/include/configs/MPC837XERDB.h u-boot-i2c/include/configs/MPC837XERDB.h --- u-boot-i2c.orig/include/configs/MPC837XERDB.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC837XERDB.h 2009-02-12 10:46:00.000000000 -0800 @@ -342,14 +342,13 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_NEW_I2C #define CONFIG_FSL_I2C -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ /* * Config on-board RTC diff -purN u-boot-i2c.orig/include/configs/MPC8536DS.h u-boot-i2c/include/configs/MPC8536DS.h --- u-boot-i2c.orig/include/configs/MPC8536DS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8536DS.h 2009-02-12 10:46:00.000000000 -0800 @@ -331,16 +331,17 @@ extern unsigned long get_board_ddr_clk(u /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_NEW_I2C +#define CONFIG_SYS_NUM_I2C_ADAPTERS 2 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1]} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ /* * I2C2 EEPROM diff -purN u-boot-i2c.orig/include/configs/MPC8540ADS.h u-boot-i2c/include/configs/MPC8540ADS.h --- u-boot-i2c.orig/include/configs/MPC8540ADS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8540ADS.h 2009-02-12 10:46:00.000000000 -0800 @@ -299,13 +299,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* RapidIO MMU */ #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ diff -purN u-boot-i2c.orig/include/configs/MPC8540EVAL.h u-boot-i2c/include/configs/MPC8540EVAL.h --- u-boot-i2c.orig/include/configs/MPC8540EVAL.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8540EVAL.h 2009-02-12 10:46:00.000000000 -0800 @@ -195,13 +195,13 @@ /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* General PCI */ #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 diff -purN u-boot-i2c.orig/include/configs/MPC8541CDS.h u-boot-i2c/include/configs/MPC8541CDS.h --- u-boot-i2c.orig/include/configs/MPC8541CDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8541CDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -322,13 +322,13 @@ extern unsigned long get_clock_freq(void /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* EEPROM */ #define CONFIG_ID_EEPROM diff -purN u-boot-i2c.orig/include/configs/MPC8544DS.h u-boot-i2c/include/configs/MPC8544DS.h --- u-boot-i2c.orig/include/configs/MPC8544DS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8544DS.h 2009-02-12 10:46:00.000000000 -0800 @@ -250,14 +250,14 @@ extern unsigned long get_board_sys_clk(u #define CONFIG_SYS_64BIT_VSPRINTF 1 /* I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_NEW_I2C +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3100 /* * General PCI diff -purN u-boot-i2c.orig/include/configs/MPC8548CDS.h u-boot-i2c/include/configs/MPC8548CDS.h --- u-boot-i2c.orig/include/configs/MPC8548CDS.h 2009-02-12 10:43:41.000000000 -0800 +++ u-boot-i2c/include/configs/MPC8548CDS.h 2009-02-12 10:46:00.000000000 -0800 @@ -343,16 +343,88 @@ extern unsigned long get_clock_freq(void #define CONFIG_SYS_64BIT_VSPRINTF 1 #define CONFIG_SYS_64BIT_STRTOUL 1 + +#define CONFIG_NEW_I2C +#if 1 +#define CONFIG_FSL_I2C +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0]} +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#else /* - * I2C + * Illustrative example with 5 I2C adapters and 7 I2C busses. + * + * Adapters: 2x FSL_I2C (0 and 1,) SM502 adapter (2,) 2x SOFT_I2C (3 and 4) + * + * Busses: + * + * 0: Direct off of FSL_I2C[0] + * 1: FSL_I2C[1]->PCA9542(0)->PCA9542(0) + * 2: FSL_I2C[1]->PCA9542(0)->PCA9542(1) + * 3: FSL_I2C[1]->PCA9542(1) + * 4: Direct off of SM502_I2C + * 5: Direct off of SOFT_I2C[0] + * 6: Direct off of SOFT_I2C[1] + * + * This might not have sense (it is much more logical to use a single + * PCA9544 for 3 busses off of FSL_I2C[1]) but it is just an illustrative + * example. SOFT_I2C declarations are totally bogus. */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_NUM_I2C_ADAPTERS 5 +#define CONFIG_SYS_NUM_I2C_BUSSES 7 +#define CONFIG_SYS_I2C_MAX_HOPS 2 + +#define CONFIG_SOFT_I2C +#define I2C_SOFT_DECLARATIONS I2C_SOFT_DEFS + +#define I2C_INIT (printf("init")) +#define I2C_ACTIVE (printf("active")) +#define I2C_TRISTATE (printf("tristate")) +#define I2C_READ (1) +#define I2C_SDA(bit) (printf("sda: %d", bit)) +#define I2C_SCL(bit) (printf("scl: %d", bit)) +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_SOFT_I2C_SPEED 100000 +#define CONFIG_SYS_SOFT_I2C_SLAVE 0x7f + +#define I2C_SOFT_DECLARATIONS2 I2C_SOFT_DEFS + +#define I2C_INIT2 (printf("init1")) +#define I2C_ACTIVE2 (printf("active1")) +#define I2C_TRISTATE2 (printf("tristate1")) +#define I2C_READ2 (1) +#define I2C_SDA2(bit) (printf("sda1: %d", bit)) +#define I2C_SCL2(bit) (printf("scl1: %d", bit)) +#define I2C_DELAY2 udelay(2) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_SOFT_I2C2_SPEED 100000 +#define CONFIG_SYS_SOFT_I2C2_SLAVE 0x7f + +#define CONFIG_SM502_I2C /* Use SM502 I2C driver */ +#define CONFIG_SYS_SM501_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_SM501_I2C_SLAVE 0x7F /* Adapter #1 */ +#define CONFIG_SYS_SM501_BASEADDR 0x80000000 /* Bogus */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F /* Adapter #1 */ +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F /* Adapter #2 */ +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_ADAPTERS {&fsl_i2c_adap[0], &fsl_i2c_adap[1], &sm501_i2c_adap, &soft_i2c_adap[0], &soft_i2c_adap[1]} +#define CONFIG_SYS_I2C_BUSSES { {0, {I2C_NULL_HOP, I2C_NULL_HOP}}, \ + {1, {{I2C_MUX_PCA9542, 0x70, 0}, {I2C_MUX_PCA9542, 0x71, 0}}}, \ + {1, {{I2C_MUX_PCA9542, 0x70, 0}, {I2C_MUX_PCA9542, 0x71, 1}}}, \ + {1, {{I2C_MUX_PCA9542, 0x70, 1}, I2C_NULL_HOP}}, \ + {2, {I2C_NULL_HOP, I2C_NULL_HOP}}, \ + {3, {I2C_NULL_HOP, I2C_NULL_HOP}}, \ + {4, {I2C_NULL_HOP, I2C_NULL_HOP}}} +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69},{1,0x69}} /* Don't probe these addrs */ +#endif /* EEPROM */ #define CONFIG_ID_EEPROM @@ -369,23 +441,23 @@ extern unsigned long get_clock_freq(void #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif #ifdef CONFIG_PCIE1 @@ -394,7 +466,7 @@ extern unsigned long get_clock_freq(void #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif @@ -403,9 +475,9 @@ extern unsigned long get_clock_freq(void /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif #ifdef CONFIG_LEGACY @@ -490,8 +562,11 @@ extern unsigned long get_clock_freq(void */ #include <config_cmd_default.h> +#define CONFIG_I2C_CMD_TREE + #define CONFIG_CMD_PING #define CONFIG_CMD_I2C +#define CONFIG_CMD_SDRAM #define CONFIG_CMD_MII #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ

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[U-Boot] [PATCH] 6/12 Multiadapter/multibus I2C, drivers part 3, fixed
by ksi＠koi8.net 13 Feb '09

13 Feb '09

Initial multiadapter/multibus I2C support. Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot-i2c.orig/drivers/i2c/sm502_i2c.c u-boot-i2c/drivers/i2c/sm502_i2c.c --- u-boot-i2c.orig/drivers/i2c/sm502_i2c.c 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-i2c/drivers/i2c/sm502_i2c.c 2009-02-12 10:46:00.000000000 -0800 @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2009 Sergey Kubushyn <ksi(a)koi8.net> + * + * Driver for Silicon Motion SM501/SM502 I2C interface. + */ + +#include <common.h> + +#ifdef CONFIG_SM502_I2C + +#include <command.h> +#include <i2c.h> + +#include <sm501-regs.h> +#include <asm/io.h> + +/* I2C registers field definitions */ +/* --------------------------------*/ +/* I2C_CONTROL (R/W) */ +#define SM501_I2C_ENABLE (1<<0) +#define SM501_I2C_SPEED (1<<1) +#define SM501_I2C_START (1<<2) +#define SM501_I2C_IRQ_ENA (1<<4) +#define SM501_I2C_IRQ_ACK (1<<5) +#define SM501_I2C_RPT_START_ENA (1<<6) +/* I2C_STATUS (R/O) */ +#define SM501_I2C_BUS_BUSY (1<<0) +#define SM501_I2C_NACK (1<<1) +#define SM501_I2C_BUS_ERROR (1<<2) +#define SM501_I2C_XFER_DONE (1<<3) +/* I2C_RESET (W/O) */ +#define SM501_I2C_CLEAR (1<<2) + +#define SM501_I2C_MAX_COUNT 16 + +#define SM501_I2C_READ 1 +#define SM501_I2C_WRITE 0 + +#define SM501_I2C_TIMEOUT (1<<7) + +#define SM501_CHECK_NACK() \ + do {\ + if (tmp & (SM501_I2C_NACK | SM501_I2C_BUS_ERROR)) {\ + tmp = read_i2c_reg(SM501_I2C_CONTROL) & SM501_I2C_SPEED;\ + write_i2c_reg(SM501_I2C_CONTROL, tmp);\ + return(1);\ + }\ + } while (0) + + +i2c_adap_t sm501_i2c_adap; + +DECLARE_GLOBAL_DATA_PTR; + + +static __inline__ u_int8_t read_i2c_reg(unsigned long offset) +{ + return(readb(sm501_iomem_base + SM501_I2C + offset)); +} + +static __inline__ void write_i2c_reg(unsigned long offset, u_int8_t data) +{ + writeb(data, sm501_iomem_base + SM501_I2C + offset); + __asm__("sync;isync;msync"); +#ifndef CONFIG_SYS_SM501_BASEADDR + /* Dummy read to push it through PCI */ + readb(sm501_iomem_base + SM501_I2C + offset); +#endif +} + +static int poll_i2c_status(u_int8_t mask, int timeout) +{ + u_int8_t stat; + int i; + + i = 0; + + do { + stat = read_i2c_reg(SM501_I2C_STATUS); + if (stat & mask) { + return(stat); + } + udelay(1000); + + } while (i++ < timeout); + + return(stat | SM501_I2C_TIMEOUT); +} + +static int wait_for_bus(void) +{ + int timeout = 10; + + while ((read_i2c_reg(SM501_I2C_STATUS) & SM501_I2C_BUS_BUSY) && timeout--) { + udelay (1000); + } + + if (timeout <= 0) { + printf ("SM501_I2C timed out in wait_for_bb: I2C_STAT=%x\n", + read_i2c_reg(SM501_I2C_STATUS)); + return(1); + } + + return(0); +} + +static void sm501_i2c_init(int speed, int slaveadd) +{ + unsigned long tmpl; + + /* Set GPIO pins for hardware I2C */ + tmpl = readl(sm501_iomem_base + SM501_GPIO + SM501_GPIO_DATA_HIGH); + tmpl |= 0x0000c000; + writel(tmpl, sm501_iomem_base + SM501_GPIO + SM501_GPIO_DATA_HIGH); + __asm__("sync;isync;msync"); +#ifndef CONFIG_SYS_SM501_BASEADDR + /* Dummy read to push is through PCI */ + readl(sm501_iomem_base + SM501_GPIO + SM501_GPIO_DATA_HIGH); +#endif + + /* SM501/502 only allows 100 or 400 KHz speed (standard or fast) */ + if (speed <= 100000) + write_i2c_reg(SM501_I2C_CONTROL, SM501_I2C_ENABLE); + else + write_i2c_reg(SM501_I2C_CONTROL, SM501_I2C_ENABLE | SM501_I2C_SPEED); + + if (gd->flags & GD_FLG_RELOC) { + sm501_i2c_adap.speed = speed <= 100000 ? 100000 : 400000; + sm501_i2c_adap.init_done = 1; + } +} + + +static int sm501_i2c_probe(u_int8_t chip) +{ + u_int8_t tmp; + + /* Fail if I2C address is invalid */ + if (chip > 0x7f) {return(1);} + + tmp = read_i2c_reg(SM501_I2C_CONTROL); + write_i2c_reg(SM501_I2C_CONTROL, tmp & ~(SM501_I2C_START | SM501_I2C_ENABLE)); + if (wait_for_bus()) {return(1);} + + /* try to read one byte from current (or only) address */ + write_i2c_reg(SM501_I2C_CONTROL, tmp | SM501_I2C_ENABLE); + write_i2c_reg(SM501_I2C_BYTE_COUNT, 0); + write_i2c_reg(SM501_I2C_SLAVE_ADDRESS, (chip << 1) | SM501_I2C_READ); + tmp = read_i2c_reg(SM501_I2C_CONTROL); + write_i2c_reg(SM501_I2C_CONTROL, tmp | SM501_I2C_START); + udelay (1000); + + if (!(read_i2c_reg(SM501_I2C_STATUS) & (SM501_I2C_NACK | SM501_I2C_BUS_ERROR))) { + tmp = read_i2c_reg(SM501_I2C_CONTROL); + write_i2c_reg(SM501_I2C_CONTROL, tmp & ~(SM501_I2C_START | SM501_I2C_ENABLE)); + if (wait_for_bus()) {return(1);} + return(0); + } + + return(1); +} + + +static int sm501_i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int8_t tmp; + u_int8_t *ptr = buf; + int i, bytes_read = 0; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + + if (len < 0) { + printf("%s(): bogus length %x\n", __FUNCTION__, len); + return(1); + } + + if (wait_for_bus()) {return(1);} + + if (alen != 0) { + /* Start address phase */ + if (alen == 2) { + /* MSB goes first... */ + write_i2c_reg(SM501_I2C_DATA, (addr >> 8) & 0xff); + write_i2c_reg(SM501_I2C_DATA + 1, addr & 0xff); + } else { + write_i2c_reg(SM501_I2C_DATA, addr & 0xff); + } + + /* Now write it out without STOP condition */ + tmp = read_i2c_reg(SM501_I2C_CONTROL); + tmp |= SM501_I2C_ENABLE | SM501_I2C_START | SM501_I2C_RPT_START_ENA; + write_i2c_reg(SM501_I2C_SLAVE_ADDRESS, (chip << 1) | SM501_I2C_WRITE); + write_i2c_reg(SM501_I2C_BYTE_COUNT, (u_int8_t)(alen - 1)); + write_i2c_reg(SM501_I2C_CONTROL, tmp); + + tmp = poll_i2c_status(SM501_I2C_NACK | SM501_I2C_BUS_ERROR | SM501_I2C_XFER_DONE, 2); + + SM501_CHECK_NACK(); + } + + /* + * Address phase is over, now read 'len' bytes. + * SM502 can read up to 16 bytes per transaction so + * we will be reading in 16-bytes batches if len > 16. + */ + do { + i = (len - bytes_read) > 16 ? 16 : len - bytes_read; + tmp = read_i2c_reg(SM501_I2C_CONTROL); + tmp |= SM501_I2C_ENABLE | SM501_I2C_START; + write_i2c_reg(SM501_I2C_SLAVE_ADDRESS, (chip << 1) | SM501_I2C_READ); + write_i2c_reg(SM501_I2C_BYTE_COUNT, (u_int8_t)(i - 1)); + write_i2c_reg(SM501_I2C_CONTROL, tmp); + + tmp = poll_i2c_status(SM501_I2C_NACK | SM501_I2C_BUS_ERROR | SM501_I2C_XFER_DONE, 100); + + SM501_CHECK_NACK(); + + bytes_read += i; + + for (; i > 0; i--) { + *ptr++ = read_i2c_reg(SM501_I2C_DATA + 16 - i); + } + + } while (len > bytes_read); + + tmp = read_i2c_reg(SM501_I2C_CONTROL); + write_i2c_reg(SM501_I2C_CONTROL, tmp & ~(SM501_I2C_START | SM501_I2C_ENABLE)); + + return(0); +} + + +static int sm501_i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +{ + u_int8_t tmp; + u_int8_t *ptr = buf; + int i, bytes_written = 0; + + if ((alen < 0) || (alen > 2)) { + printf("%s(): bogus address length %x\n", __FUNCTION__, alen); + return(1); + } + + if (len < 0) { + printf("%s(): bogus length %x\n", __FUNCTION__, len); + return(1); + } + + if (wait_for_bus()) {return(1);} + + /* + * SM502 can write up to 16 bytes per transaction so we will be + * writing in 16-bytes batches if len > (16 - alen). Address is + * sent first, then data hence (16 - alen)... + */ + do { + i = (len - bytes_written) > (16 - alen) ? 16 - alen : len - bytes_written; + + /* Prepend address */ + if (alen == 2) { + /* MSB goes first... */ + write_i2c_reg(SM501_I2C_DATA, ((addr + bytes_written) >> 8) & 0xff); + write_i2c_reg(SM501_I2C_DATA + 1, (addr + bytes_written) & 0xff); + } + + if (alen == 1) { + write_i2c_reg(SM501_I2C_DATA, (addr + bytes_written) & 0xff); + } + + + for (; i > 0; i--) { + write_i2c_reg(SM501_I2C_DATA + 16 + alen - i, *ptr++); + } + + /* Push it down the bus */ + tmp = read_i2c_reg(SM501_I2C_CONTROL); + tmp |= SM501_I2C_ENABLE | SM501_I2C_START; + write_i2c_reg(SM501_I2C_SLAVE_ADDRESS, (chip << 1) | SM501_I2C_WRITE); + write_i2c_reg(SM501_I2C_BYTE_COUNT, (u_int8_t)(i + alen - 1)); + write_i2c_reg(SM501_I2C_CONTROL, tmp); + + tmp = poll_i2c_status(SM501_I2C_NACK | SM501_I2C_BUS_ERROR | SM501_I2C_XFER_DONE, 100); + + SM501_CHECK_NACK(); + + bytes_written += i; + + } while (len > bytes_written); + + tmp = read_i2c_reg(SM501_I2C_CONTROL); + write_i2c_reg(SM501_I2C_CONTROL, tmp & ~(SM501_I2C_START | SM501_I2C_ENABLE)); + + return(0); +} + + +static unsigned int sm501_i2c_set_bus_speed(unsigned int speed) +{ + u_int8_t tmp; + + tmp = read_i2c_reg(SM501_I2C_CONTROL); + + /* SM501/502 only allows 100 or 400 KHz speed (standard or fast) */ + if (speed <= 100000) + tmp &= ~SM501_I2C_SPEED; + else + tmp |= SM501_I2C_SPEED; + + write_i2c_reg(SM501_I2C_CONTROL, tmp); + + if (gd->flags & GD_FLG_RELOC) { + sm501_i2c_adap.speed = speed <= 100000 ? 100000 : 400000; + } + + return(speed <= 100000 ? 100000 : 400000); +} + + +static unsigned int sm501_i2c_get_bus_speed(void) +{ + return(sm501_i2c_adap.speed); +} + + +i2c_adap_t sm501_i2c_adap = { + .init = sm501_i2c_init, + .probe = sm501_i2c_probe, + .read = sm501_i2c_read, + .write = sm501_i2c_write, + .set_bus_speed = sm501_i2c_set_bus_speed, + .get_bus_speed = sm501_i2c_get_bus_speed, + .speed = CONFIG_SYS_SM501_I2C_SPEED, + .slaveaddr = CONFIG_SYS_SM501_I2C_SLAVE, + .init_done = 0, + .name = "sm501_i2c" +}; +#endif /* CONFIG_SM502_I2C */ diff -purN u-boot-i2c.orig/include/sm501-regs.h u-boot-i2c/include/sm501-regs.h --- u-boot-i2c.orig/include/sm501-regs.h 1969-12-31 16:00:00.000000000 -0800 +++ u-boot-i2c/include/sm501-regs.h 2009-02-12 10:46:00.000000000 -0800 @@ -0,0 +1,394 @@ +/* sm501-regs.h + * + * Copyright 2006 Simtec Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Silicon Motion SM501 register definitions +*/ + +#ifndef CONFIG_SYS_SM501_BASEADDR +/* SM501/502 on PCI bus, resides and initialized in $(BOARD).c */ +extern unsigned long sm501_iomem_base; +#else +/* SM501/502 on processor bus, preassigned address */ +#define sm501_iomem_base CONFIG_SYS_SM501_BASEADDR +#endif + +/* System Configuration area */ +/* System config base */ +#define SM501_SYS_CONFIG (0x000000) + +/* config 1 */ +#define SM501_SYSTEM_CONTROL (0x000000) + +#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0) +#define SM501_SYSCTRL_MEM_TRISTATE (1<<1) +#define SM501_SYSCTRL_CRT_TRISTATE (1<<2) + +#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4) +#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4) + +#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6) +#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7) +#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11) +#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15) + +/* miscellaneous control */ + +#define SM501_MISC_CONTROL (0x000004) + +#define SM501_MISC_BUS_SH (0x0) +#define SM501_MISC_BUS_PCI (0x1) +#define SM501_MISC_BUS_XSCALE (0x2) +#define SM501_MISC_BUS_NEC (0x6) +#define SM501_MISC_BUS_MASK (0x7) + +#define SM501_MISC_VR_62MB (1<<3) +#define SM501_MISC_CDR_RESET (1<<7) +#define SM501_MISC_USB_LB (1<<8) +#define SM501_MISC_USB_SLAVE (1<<9) +#define SM501_MISC_BL_1 (1<<10) +#define SM501_MISC_MC (1<<11) +#define SM501_MISC_DAC_POWER (1<<12) +#define SM501_MISC_IRQ_INVERT (1<<16) +#define SM501_MISC_SH (1<<17) + +#define SM501_MISC_HOLD_EMPTY (0<<18) +#define SM501_MISC_HOLD_8 (1<<18) +#define SM501_MISC_HOLD_16 (2<<18) +#define SM501_MISC_HOLD_24 (3<<18) +#define SM501_MISC_HOLD_32 (4<<18) +#define SM501_MISC_HOLD_MASK (7<<18) + +#define SM501_MISC_FREQ_12 (1<<24) +#define SM501_MISC_PNL_24BIT (1<<25) +#define SM501_MISC_8051_LE (1<<26) + + + +#define SM501_GPIO31_0_CONTROL (0x000008) +#define SM501_GPIO63_32_CONTROL (0x00000C) +#define SM501_DRAM_CONTROL (0x000010) + +/* command list */ +#define SM501_ARBTRTN_CONTROL (0x000014) + +/* command list */ +#define SM501_COMMAND_LIST_STATUS (0x000024) + +/* interrupt debug */ +#define SM501_RAW_IRQ_STATUS (0x000028) +#define SM501_RAW_IRQ_CLEAR (0x000028) +#define SM501_IRQ_STATUS (0x00002C) +#define SM501_IRQ_MASK (0x000030) +#define SM501_DEBUG_CONTROL (0x000034) + +/* power management */ +#define SM501_POWERMODE_P2X_SRC (1<<29) +#define SM501_POWERMODE_V2X_SRC (1<<20) +#define SM501_POWERMODE_M_SRC (1<<12) +#define SM501_POWERMODE_M1_SRC (1<<4) + +#define SM501_CURRENT_GATE (0x000038) +#define SM501_CURRENT_CLOCK (0x00003C) +#define SM501_POWER_MODE_0_GATE (0x000040) +#define SM501_POWER_MODE_0_CLOCK (0x000044) +#define SM501_POWER_MODE_1_GATE (0x000048) +#define SM501_POWER_MODE_1_CLOCK (0x00004C) +#define SM501_SLEEP_MODE_GATE (0x000050) +#define SM501_POWER_MODE_CONTROL (0x000054) + +/* power gates for units within the 501 */ +#define SM501_GATE_HOST (0) +#define SM501_GATE_MEMORY (1) +#define SM501_GATE_DISPLAY (2) +#define SM501_GATE_2D_ENGINE (3) +#define SM501_GATE_CSC (4) +#define SM501_GATE_ZVPORT (5) +#define SM501_GATE_GPIO (6) +#define SM501_GATE_UART0 (7) +#define SM501_GATE_UART1 (8) +#define SM501_GATE_SSP (10) +#define SM501_GATE_USB_HOST (11) +#define SM501_GATE_USB_GADGET (12) +#define SM501_GATE_UCONTROLLER (17) +#define SM501_GATE_AC97 (18) + +/* panel clock */ +#define SM501_CLOCK_P2XCLK (24) +/* crt clock */ +#define SM501_CLOCK_V2XCLK (16) +/* main clock */ +#define SM501_CLOCK_MCLK (8) +/* SDRAM controller clock */ +#define SM501_CLOCK_M1XCLK (0) + +/* config 2 */ +#define SM501_PCI_MASTER_BASE (0x000058) +#define SM501_ENDIAN_CONTROL (0x00005C) +#define SM501_DEVICEID (0x000060) +/* 0x050100A0 */ + +#define SM501_DEVICEID_SM501 (0x05010000) +#define SM501_DEVICEID_IDMASK (0xffff0000) +#define SM501_DEVICEID_REVMASK (0x000000ff) + +#define SM501_PLLCLOCK_COUNT (0x000064) +#define SM501_MISC_TIMING (0x000068) +#define SM501_CURRENT_SDRAM_CLOCK (0x00006C) + +#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074) + +/* GPIO base */ +#define SM501_GPIO (0x010000) +#define SM501_GPIO_DATA_LOW (0x00) +#define SM501_GPIO_DATA_HIGH (0x04) +#define SM501_GPIO_DDR_LOW (0x08) +#define SM501_GPIO_DDR_HIGH (0x0C) +#define SM501_GPIO_IRQ_SETUP (0x10) +#define SM501_GPIO_IRQ_STATUS (0x14) +#define SM501_GPIO_IRQ_RESET (0x14) + +/* I2C controller base */ +#define SM501_I2C (0x010040) +#define SM501_I2C_BYTE_COUNT (0x00) +#define SM501_I2C_CONTROL (0x01) +#define SM501_I2C_STATUS (0x02) +#define SM501_I2C_RESET (0x02) +#define SM501_I2C_SLAVE_ADDRESS (0x03) +#define SM501_I2C_DATA (0x04) + +/* SSP base */ +#define SM501_SSP (0x020000) + +/* Uart 0 base */ +#define SM501_UART0 (0x030000) + +/* Uart 1 base */ +#define SM501_UART1 (0x030020) + +/* USB host port base */ +#define SM501_USB_HOST (0x040000) + +/* USB slave/gadget base */ +#define SM501_USB_GADGET (0x060000) + +/* USB slave/gadget data port base */ +#define SM501_USB_GADGET_DATA (0x070000) + +/* Display controller/video engine base */ +#define SM501_DC (0x080000) + +/* common defines for the SM501 address registers */ +#define SM501_ADDR_FLIP (1<<31) +#define SM501_ADDR_EXT (1<<27) +#define SM501_ADDR_CS1 (1<<26) +#define SM501_ADDR_MASK (0x3f << 26) + +#define SM501_FIFO_MASK (0x3 << 16) +#define SM501_FIFO_1 (0x0 << 16) +#define SM501_FIFO_3 (0x1 << 16) +#define SM501_FIFO_7 (0x2 << 16) +#define SM501_FIFO_11 (0x3 << 16) + +/* common registers for panel and the crt */ +#define SM501_OFF_DC_H_TOT (0x000) +#define SM501_OFF_DC_V_TOT (0x008) +#define SM501_OFF_DC_H_SYNC (0x004) +#define SM501_OFF_DC_V_SYNC (0x00C) + +#define SM501_DC_PANEL_CONTROL (0x000) + +#define SM501_DC_PANEL_CONTROL_FPEN (1<<27) +#define SM501_DC_PANEL_CONTROL_BIAS (1<<26) +#define SM501_DC_PANEL_CONTROL_DATA (1<<25) +#define SM501_DC_PANEL_CONTROL_VDD (1<<24) +#define SM501_DC_PANEL_CONTROL_DP (1<<23) + +#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) +#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) +#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) + +#define SM501_DC_PANEL_CONTROL_DE (1<<20) + +#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) +#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) +#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) + +#define SM501_DC_PANEL_CONTROL_CP (1<<14) +#define SM501_DC_PANEL_CONTROL_VSP (1<<13) +#define SM501_DC_PANEL_CONTROL_HSP (1<<12) +#define SM501_DC_PANEL_CONTROL_CK (1<<9) +#define SM501_DC_PANEL_CONTROL_TE (1<<8) +#define SM501_DC_PANEL_CONTROL_VPD (1<<7) +#define SM501_DC_PANEL_CONTROL_VP (1<<6) +#define SM501_DC_PANEL_CONTROL_HPD (1<<5) +#define SM501_DC_PANEL_CONTROL_HP (1<<4) +#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) +#define SM501_DC_PANEL_CONTROL_EN (1<<2) + +#define SM501_DC_PANEL_CONTROL_8BPP (0<<0) +#define SM501_DC_PANEL_CONTROL_16BPP (1<<0) +#define SM501_DC_PANEL_CONTROL_32BPP (2<<0) + + +#define SM501_DC_PANEL_PANNING_CONTROL (0x004) +#define SM501_DC_PANEL_COLOR_KEY (0x008) +#define SM501_DC_PANEL_FB_ADDR (0x00C) +#define SM501_DC_PANEL_FB_OFFSET (0x010) +#define SM501_DC_PANEL_FB_WIDTH (0x014) +#define SM501_DC_PANEL_FB_HEIGHT (0x018) +#define SM501_DC_PANEL_TL_LOC (0x01C) +#define SM501_DC_PANEL_BR_LOC (0x020) +#define SM501_DC_PANEL_H_TOT (0x024) +#define SM501_DC_PANEL_H_SYNC (0x028) +#define SM501_DC_PANEL_V_TOT (0x02C) +#define SM501_DC_PANEL_V_SYNC (0x030) +#define SM501_DC_PANEL_CUR_LINE (0x034) + +#define SM501_DC_VIDEO_CONTROL (0x040) +#define SM501_DC_VIDEO_FB0_ADDR (0x044) +#define SM501_DC_VIDEO_FB_WIDTH (0x048) +#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) +#define SM501_DC_VIDEO_TL_LOC (0x050) +#define SM501_DC_VIDEO_BR_LOC (0x054) +#define SM501_DC_VIDEO_SCALE (0x058) +#define SM501_DC_VIDEO_INIT_SCALE (0x05C) +#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) +#define SM501_DC_VIDEO_FB1_ADDR (0x064) +#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) + +#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) +#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) +#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) +#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) +#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) +#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) +#define SM501_DC_VIDEO_ALPHA_SCALE (0x098) +#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) +#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) +#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) + +#define SM501_DC_PANEL_HWC_BASE (0x0F0) +#define SM501_DC_PANEL_HWC_ADDR (0x0F0) +#define SM501_DC_PANEL_HWC_LOC (0x0F4) +#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) +#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) + +#define SM501_HWC_EN (1<<31) + +#define SM501_OFF_HWC_ADDR (0x00) +#define SM501_OFF_HWC_LOC (0x04) +#define SM501_OFF_HWC_COLOR_1_2 (0x08) +#define SM501_OFF_HWC_COLOR_3 (0x0C) + +#define SM501_DC_ALPHA_CONTROL (0x100) +#define SM501_DC_ALPHA_FB_ADDR (0x104) +#define SM501_DC_ALPHA_FB_OFFSET (0x108) +#define SM501_DC_ALPHA_TL_LOC (0x10C) +#define SM501_DC_ALPHA_BR_LOC (0x110) +#define SM501_DC_ALPHA_CHROMA_KEY (0x114) +#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) + +#define SM501_DC_CRT_CONTROL (0x200) + +#define SM501_DC_CRT_CONTROL_TVP (1<<15) +#define SM501_DC_CRT_CONTROL_CP (1<<14) +#define SM501_DC_CRT_CONTROL_VSP (1<<13) +#define SM501_DC_CRT_CONTROL_HSP (1<<12) +#define SM501_DC_CRT_CONTROL_VS (1<<11) +#define SM501_DC_CRT_CONTROL_BLANK (1<<10) +#define SM501_DC_CRT_CONTROL_SEL (1<<9) +#define SM501_DC_CRT_CONTROL_TE (1<<8) +#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) +#define SM501_DC_CRT_CONTROL_GAMMA (1<<3) +#define SM501_DC_CRT_CONTROL_ENABLE (1<<2) + +#define SM501_DC_CRT_CONTROL_8BPP (0<<0) +#define SM501_DC_CRT_CONTROL_16BPP (1<<0) +#define SM501_DC_CRT_CONTROL_32BPP (2<<0) + +#define SM501_DC_CRT_FB_ADDR (0x204) +#define SM501_DC_CRT_FB_OFFSET (0x208) +#define SM501_DC_CRT_H_TOT (0x20C) +#define SM501_DC_CRT_H_SYNC (0x210) +#define SM501_DC_CRT_V_TOT (0x214) +#define SM501_DC_CRT_V_SYNC (0x218) +#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) +#define SM501_DC_CRT_CUR_LINE (0x220) +#define SM501_DC_CRT_MONITOR_DETECT (0x224) + +#define SM501_DC_CRT_HWC_BASE (0x230) +#define SM501_DC_CRT_HWC_ADDR (0x230) +#define SM501_DC_CRT_HWC_LOC (0x234) +#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) +#define SM501_DC_CRT_HWC_COLOR_3 (0x23C) + +#define SM501_DC_PANEL_PALETTE (0x400) + +#define SM501_DC_VIDEO_PALETTE (0x800) + +#define SM501_DC_CRT_PALETTE (0xC00) + +/* Zoom Video port base */ +#define SM501_ZVPORT (0x090000) + +/* AC97/I2S base */ +#define SM501_AC97 (0x0A0000) + +/* 8051 micro controller base */ +#define SM501_UCONTROLLER (0x0B0000) + +/* 8051 micro controller SRAM base */ +#define SM501_UCONTROLLER_SRAM (0x0C0000) + +/* DMA base */ +#define SM501_DMA (0x0D0000) + +/* 2d engine base */ +#define SM501_2D_ENGINE (0x100000) +#define SM501_2D_SOURCE (0x00) +#define SM501_2D_DESTINATION (0x04) +#define SM501_2D_DIMENSION (0x08) +#define SM501_2D_CONTROL (0x0C) +#define SM501_2D_PITCH (0x10) +#define SM501_2D_FOREGROUND (0x14) +#define SM501_2D_BACKGROUND (0x18) +#define SM501_2D_STRETCH (0x1C) +#define SM501_2D_COLOR_COMPARE (0x20) +#define SM501_2D_COLOR_COMPARE_MASK (0x24) +#define SM501_2D_MASK (0x28) +#define SM501_2D_CLIP_TL (0x2C) +#define SM501_2D_CLIP_BR (0x30) +#define SM501_2D_MONO_PATTERN_LOW (0x34) +#define SM501_2D_MONO_PATTERN_HIGH (0x38) +#define SM501_2D_WINDOW_WIDTH (0x3C) +#define SM501_2D_SOURCE_BASE (0x40) +#define SM501_2D_DESTINATION_BASE (0x44) +#define SM501_2D_ALPHA (0x48) +#define SM501_2D_WRAP (0x4C) +#define SM501_2D_STATUS (0x50) + +#define SM501_CSC_Y_SOURCE_BASE (0xC8) +#define SM501_CSC_CONSTANTS (0xCC) +#define SM501_CSC_Y_SOURCE_X (0xD0) +#define SM501_CSC_Y_SOURCE_Y (0xD4) +#define SM501_CSC_U_SOURCE_BASE (0xD8) +#define SM501_CSC_V_SOURCE_BASE (0xDC) +#define SM501_CSC_SOURCE_DIMENSION (0xE0) +#define SM501_CSC_SOURCE_PITCH (0xE4) +#define SM501_CSC_DESTINATION (0xE8) +#define SM501_CSC_DESTINATION_DIMENSION (0xEC) +#define SM501_CSC_DESTINATION_PITCH (0xF0) +#define SM501_CSC_SCALE_FACTOR (0xF4) +#define SM501_CSC_DESTINATION_BASE (0xF8) +#define SM501_CSC_CONTROL (0xFC) + +/* 2d engine data port base */ +#define SM501_2D_ENGINE_DATA (0x110000)

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