October 2009 - U-Boot

[U-Boot] [Patch v2] vxworks: Add CONFIG_VXWORKS_PREBOOT
by Niklaus Giger 18 Oct '09

18 Oct '09

The option CONFIG_VXWORKS_PREBOOT allows a board specific vxworks_preboot to be run just before jumping into the vxWorks images. This can be used to alter a register which is used differently by U-boot and vxWorks. The patch defines a weak function which may be overridden by a board specific version. vxworks_preboot should return 0 to indicated that everything worked fine. The error code is checked and the vxWorks image will not be loaded in case of errors. Signed-off-by: Niklaus Giger <niklaus.giger(a)netstal.com> --- board/netstal/mcu25/mcu25.c | 8 ++++++++ common/cmd_elf.c | 11 +++++++++++ include/vxworks.h | 2 ++ 3 files changed, 21 insertions(+), 0 deletions(-) diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 9054282..d64194d 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -53,6 +53,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define CPC0_CR0_VALUE 0x0007F03C #define CPC0_CR1_VALUE 0x00004051 +#define CPCO_CR1_USE_EXTERNAL 0x00804051 int board_early_init_f (void) { @@ -161,6 +162,13 @@ int misc_init_r(void) return 0; } +int vxworks_preboot(void) { + if (sys_install_requested()) { + mtdcr(CPC0_CR1, CPCO_CR1_USE_EXTERNAL); + } + return 0; +} + phys_size_t initdram(int board_type) { unsigned int dram_size = 64*1024*1024; diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 63f6fe7..c8eb88a 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -53,6 +53,11 @@ unsigned long do_bootelf_exec (ulong (*entry)(int, char *[]), int argc, char *ar return ret; } +__attribute__((weak)) int vxworks_preboot(void) +{ + return 0; +} + /* ====================================================================== * Interpreter command to boot an arbitrary ELF image from memory. * ====================================================================== */ @@ -100,6 +105,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *bootline; /* Text of the bootline */ char *tmp; /* Temporary char pointer */ char build_buf[128]; /* Buffer for building the bootline */ + int rc; /* Checking vxworks_preboot */ /* --------------------------------------------------- * @@ -211,6 +217,11 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("## Using bootline (@ 0x%lx): %s\n", bootaddr, (char *) bootaddr); + rc = vxworks_preboot(); + if (rc != 0) { + printf ("## vxworks_preboot failed with %d\n", rc); + return 1; + } printf ("## Starting vxWorks at 0x%08lx ...\n", addr); ((void (*)(void)) addr) (); diff --git a/include/vxworks.h b/include/vxworks.h index 1633904..2edbf8e 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -50,4 +50,6 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #define CONFIG_SYS_VXWORKS_SERVERNAME "srv" #endif +int vxworks_preboot(void); + #endif -- 1.6.3.3

2 1

[U-Boot] arm/master merged
by Tom Rix 18 Oct '09

18 Oct '09

I have merged arm/next into arm/master. There are new warnings in CPU9260 , CONFIG_SYS_64BIT_VSPRINTF CPU9G20 , CONFIG_SYS_64BIT_VSPRINTF GPUAT91 , CONFIG_NET_MULTI, davinci_dm355evm , CONFIG_SYS_64BIT_VSPRINTF, generic_set_bit I have ack-ed patches for these.. openrd_base , kwgbe_init breaking strict aliasing rules Fixes for these devkit8000 omap3_beagle omap3_evm omap3_overo omap3_pandora omap3_zoom1 omap3_zoom2 Thanks for all the good submissions Tom For the curious, here is the output from the merge git merge t-next Updating 1d96cfe..617da90 Fast forward MAINTAINERS | 10 + MAKEALL | 6 +- Makefile | 17 + board/Marvell/mv88f6281gtw_ge/config.mk | 3 + board/Marvell/mv88f6281gtw_ge/kwbimage.cfg | 165 +++++++ board/Marvell/openrd_base/Makefile | 56 +++ board/Marvell/openrd_base/config.mk | 33 ++ board/Marvell/openrd_base/kwbimage.cfg | 168 +++++++ board/Marvell/openrd_base/openrd_base.c | 160 +++++++ board/Marvell/openrd_base/openrd_base.h | 46 ++ board/Marvell/rd6281a/config.mk | 3 + board/Marvell/rd6281a/kwbimage.cfg | 167 +++++++ board/davinci/dm365evm/dm365evm.c | 44 ++- board/esd/meesc/meesc.c | 65 +++- board/eukrea/cpu9260/Makefile | 59 +++ board/eukrea/cpu9260/config.mk | 1 + board/eukrea/cpu9260/cpu9260.c | 220 +++++++++ board/eukrea/cpu9260/led.c | 153 +++++++ board/eukrea/cpuat91/Makefile | 50 +++ board/eukrea/cpuat91/config.mk | 1 + board/eukrea/cpuat91/cpuat91.c | 81 ++++ board/logicpd/zoom1/zoom1.h | 164 ++++---- board/logicpd/zoom2/zoom2.h | 188 ++++---- board/overo/overo.c | 59 +++ board/overo/overo.h | 645 ++++++++++++++-------------- board/pandora/pandora.h | 662 ++++++++++++++-------------- board/ti/beagle/beagle.h | 640 ++++++++++++++-------------- board/ti/evm/evm.h | 662 ++++++++++++++-------------- board/timll/devkit8000/devkit8000.h | 628 +++++++++++++------------- cpu/arm920t/at91rm9200/Makefile | 5 +- cpu/arm920t/at91rm9200/ks8721.c | 249 +++++++++++ cpu/arm926ejs/at91/lowlevel_init.S | 3 +- cpu/arm926ejs/davinci/Makefile | 1 + cpu/arm926ejs/davinci/dm646x.c | 41 ++ cpu/arm926ejs/kirkwood/cpu.c | 1 + cpu/arm_cortexa8/cpu.c | 2 +- cpu/arm_cortexa8/omap3/Makefile | 2 +- cpu/arm_cortexa8/omap3/board.c | 2 +- cpu/arm_cortexa8/omap3/cache.S | 191 ++++++++ cpu/arm_cortexa8/omap3/cache.c | 95 ---- cpu/arm_cortexa8/start.S | 85 ---- drivers/mmc/omap3_mmc.c | 48 +-- drivers/net/smc911x.c | 14 +- drivers/net/smc911x.h | 7 +- include/asm-arm/arch-davinci/emac_defs.h | 4 +- include/asm-arm/arch-davinci/gpio_defs.h | 53 +++ include/asm-arm/arch-davinci/hardware.h | 11 + include/asm-arm/arch-davinci/nand_defs.h | 2 +- include/asm-arm/arch-omap3/mmc.h | 7 + include/asm-arm/arch-omap3/omap3.h | 2 + include/asm-arm/arch-omap3/sys_proto.h | 2 +- include/configs/cpu9260.h | 453 +++++++++++++++++++ include/configs/cpuat91.h | 228 ++++++++++ include/configs/davinci_dm355evm.h | 26 +- include/configs/davinci_dm365evm.h | 11 +- include/configs/davinci_dvevm.h | 6 +- include/configs/davinci_schmoogie.h | 3 +- include/configs/davinci_sffsdr.h | 3 +- include/configs/davinci_sonata.h | 3 +- include/configs/devkit8000.h | 1 + include/configs/meesc.h | 25 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm.h | 1 + include/configs/omap3_overo.h | 18 +- include/configs/omap3_pandora.h | 1 + include/configs/omap3_zoom1.h | 1 + include/configs/omap3_zoom2.h | 1 + include/configs/openrd_base.h | 220 +++++++++ include/ks8721.h | 78 ++++ 69 files changed, 4988 insertions(+), 2075 deletions(-) create mode 100644 board/Marvell/mv88f6281gtw_ge/kwbimage.cfg create mode 100644 board/Marvell/openrd_base/Makefile create mode 100644 board/Marvell/openrd_base/config.mk create mode 100644 board/Marvell/openrd_base/kwbimage.cfg create mode 100644 board/Marvell/openrd_base/openrd_base.c create mode 100644 board/Marvell/openrd_base/openrd_base.h create mode 100644 board/Marvell/rd6281a/kwbimage.cfg create mode 100644 board/eukrea/cpu9260/Makefile create mode 100644 board/eukrea/cpu9260/config.mk create mode 100644 board/eukrea/cpu9260/cpu9260.c create mode 100644 board/eukrea/cpu9260/led.c create mode 100644 board/eukrea/cpuat91/Makefile create mode 100644 board/eukrea/cpuat91/config.mk create mode 100644 board/eukrea/cpuat91/cpuat91.c create mode 100644 cpu/arm920t/at91rm9200/ks8721.c create mode 100644 cpu/arm926ejs/davinci/dm646x.c create mode 100644 cpu/arm_cortexa8/omap3/cache.S delete mode 100644 cpu/arm_cortexa8/omap3/cache.c create mode 100644 include/asm-arm/arch-davinci/gpio_defs.h create mode 100644 include/configs/cpu9260.h create mode 100644 include/configs/cpuat91.h create mode 100644 include/configs/openrd_base.h create mode 100644 include/ks8721.h

4 8

[U-Boot] Arm pull requests v2
by Tom 18 Oct '09

18 Oct '09

The change from v1 of yesterday is to include the s5pc1xx fix < Minkyu Kang (4): --- > Minkyu Kang (5): 18a19 > s5pc1xx: SMDKC100: fix compile warnings Tom The following changes since commit a380279b2abe130c2d3d2c8de36f8ff98bc6b3b0: Daniel Gorsulowski (1): at91: Update MEESC board support are available in the git repository at: git://git.denx.de/u-boot-arm master-sync Eric Benard (3): CPU9260 : fix machine ID when using a CPU9G20. fix CPU9260/CPU9G20 compile warnings main.c: In function 'abortboot': Minkyu Kang (5): s5pc1xx: support Samsung s5pc1xx SoC s5pc1xx: support onenand driver s5pc1xx: support serial driver s5pc1xx: add support SMDKC100 board s5pc1xx: SMDKC100: fix compile warnings Nishanth Menon (4): OMAP3: export enable_gpmc_cs_config to board files OMAP3: fix warnings when NAND/ONENAND is not used OMAP3: Fix SDRC init TI OMAP3: make gpmc_config as const Sandeep Paulraj (13): TI DaVinci DM355: Fix Compilation warning for DM355 EVM TI DaVinci DM365: Fix Compilation warning for DM365 EVM TI DaVinci DM646x: Adding initial support for DM6467 EVM TI: DaVinci: DM355 Leopard board support TI DaVinci: Maintainer for DM355 and DM365 EVM TI: OMAP3: Remove SZ_xx references TI DaVinci DM355: Add Config option for 64 bit Support TI DaVinci DM365: Add Config option for 64 bit Support TI DaVinci DVEVM: Add Config option for 64 bit Support TI DaVinci Sonata: Add Config option for 64 bit Support TI DaVinci: DM355 Leopard: Fix compilation warning TI DaVinci: Fix DM6467 EVM Compilation Warning TI DaVinci: Adding Copyright for DM365 EVM Simon Kagstrom (1): arm926ejs: 8-byte align stack to avoid LDRD/STRD problems Steve Sakoman (2): TI: OMAP3: Refactors the SM911x driver OMAP3: Update Overo and Beagle environment Tom Rix (2): Zoom2 Fix serial gpmc setup TI OMAP3 SDP3430: Initial Support kevin.morfitt(a)fearnside-systems.co.uk (5): CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code Clean-up of s3c24x0 header files Clean-up of s3c24x0 drivers excluding nand driver Clean-up of s3c24x0 nand driver MAINTAINERS | 12 + MAKEALL | 4 + Makefile | 12 + board/davinci/dm355evm/dm355evm.c | 4 +- board/davinci/dm355leopard/Makefile | 52 ++ board/davinci/dm355leopard/config.mk | 6 + board/davinci/dm355leopard/dm355leopard.c | 98 +++ board/davinci/dm365evm/dm365evm.c | 5 +- board/davinci/dm6467evm/Makefile | 52 ++ board/davinci/dm6467evm/config.mk | 2 + board/davinci/dm6467evm/dm6467evm.c | 31 + board/eukrea/cpu9260/cpu9260.c | 2 +- board/logicpd/zoom2/zoom2.c | 5 +- board/mpl/vcma9/vcma9.c | 13 +- board/mpl/vcma9/vcma9.h | 20 +- board/samsung/smdk2400/smdk2400.c | 5 +- board/samsung/smdk2410/smdk2410.c | 5 +- board/samsung/smdkc100/Makefile | 55 ++ board/samsung/smdkc100/config.mk | 16 + board/samsung/smdkc100/lowlevel_init.S | 215 +++++ board/samsung/smdkc100/mem_setup.S | 197 +++++ board/samsung/smdkc100/onenand.c | 83 ++ board/samsung/smdkc100/smdkc100.c | 51 ++ board/sbc2410x/sbc2410x.c | 7 +- board/ti/sdp3430/Makefile | 49 ++ board/ti/sdp3430/config.mk | 33 + board/ti/sdp3430/sdp.c | 204 +++++ board/ti/sdp3430/sdp.h | 417 +++++++++ board/trab/cmd_trab.c | 12 +- board/trab/rs485.c | 12 +- board/trab/trab.c | 17 +- board/trab/trab_fkt.c | 26 +- board/trab/tsc2000.c | 17 +- board/trab/tsc2000.h | 4 +- board/trab/vfd.c | 12 +- common/serial.c | 18 + cpu/arm920t/s3c24x0/interrupts.c | 4 +- cpu/arm920t/s3c24x0/speed.c | 42 +- cpu/arm920t/s3c24x0/timer.c | 110 ++-- cpu/arm920t/s3c24x0/usb.c | 30 +- cpu/arm920t/s3c24x0/usb_ohci.c | 1323 +++++++++++++++-------------- cpu/arm920t/s3c24x0/usb_ohci.h | 209 +++--- cpu/arm920t/start.S | 63 +- cpu/arm926ejs/start.S | 1 + cpu/arm_cortexa8/omap3/mem.c | 21 +- cpu/arm_cortexa8/omap3/sys_info.c | 2 +- cpu/arm_cortexa8/s5pc1xx/Makefile | 53 ++ cpu/arm_cortexa8/s5pc1xx/cache.c | 43 + cpu/arm_cortexa8/s5pc1xx/clock.c | 308 +++++++ cpu/arm_cortexa8/s5pc1xx/cpu_info.c | 57 ++ cpu/arm_cortexa8/s5pc1xx/reset.S | 47 + cpu/arm_cortexa8/s5pc1xx/timer.c | 195 +++++ doc/README.s5pc1xx | 56 ++ drivers/i2c/s3c24x0_i2c.c | 273 +++--- drivers/mtd/nand/s3c2410_nand.c | 62 +- drivers/mtd/onenand/Makefile | 1 + drivers/mtd/onenand/samsung.c | 636 ++++++++++++++ drivers/net/smc911x.c | 12 +- drivers/rtc/s3c24x0_rtc.c | 130 ++-- drivers/serial/Makefile | 1 + drivers/serial/serial_s3c24x0.c | 160 ++-- drivers/serial/serial_s5pc1xx.c | 195 +++++ include/asm-arm/arch-davinci/hardware.h | 2 + include/asm-arm/arch-omap3/cpu.h | 1 + include/asm-arm/arch-omap3/mem.h | 8 +- include/asm-arm/arch-omap3/sys_proto.h | 2 + include/asm-arm/arch-s5pc1xx/clk.h | 32 + include/asm-arm/arch-s5pc1xx/clock.h | 94 ++ include/asm-arm/arch-s5pc1xx/cpu.h | 72 ++ include/asm-arm/arch-s5pc1xx/gpio.h | 129 +++ include/asm-arm/arch-s5pc1xx/power.h | 42 + include/asm-arm/arch-s5pc1xx/pwm.h | 59 ++ include/asm-arm/arch-s5pc1xx/uart.h | 47 + include/configs/cpu9260.h | 1 + include/configs/cpuat91.h | 4 +- include/configs/davinci_dm355evm.h | 1 + include/configs/davinci_dm355leopard.h | 162 ++++ include/configs/davinci_dm365evm.h | 2 + include/configs/davinci_dm6467evm.h | 132 +++ include/configs/davinci_dvevm.h | 1 + include/configs/davinci_sonata.h | 1 + include/configs/devkit8000.h | 15 +- include/configs/omap3_beagle.h | 42 +- include/configs/omap3_evm.h | 15 +- include/configs/omap3_overo.h | 42 +- include/configs/omap3_pandora.h | 15 +- include/configs/omap3_sdp3430.h | 369 ++++++++ include/configs/omap3_zoom1.h | 15 +- include/configs/omap3_zoom2.h | 15 +- include/configs/sbc2410x.h | 4 +- include/configs/smdk2400.h | 4 +- include/configs/smdk2410.h | 4 +- include/configs/smdkc100.h | 242 ++++++ include/configs/trab.h | 12 +- include/linux/mtd/onenand.h | 1 + include/linux/mtd/onenand_regs.h | 4 + include/linux/mtd/samsung_onenand.h | 131 +++ include/s3c2400.h | 494 +---------- include/s3c2410.h | 159 +--- include/s3c24x0.h | 605 ++------------ include/serial.h | 7 + 101 files changed, 6329 insertions(+), 2465 deletions(-) create mode 100644 board/davinci/dm355leopard/Makefile create mode 100644 board/davinci/dm355leopard/config.mk create mode 100644 board/davinci/dm355leopard/dm355leopard.c create mode 100644 board/davinci/dm6467evm/Makefile create mode 100644 board/davinci/dm6467evm/config.mk create mode 100644 board/davinci/dm6467evm/dm6467evm.c create mode 100644 board/samsung/smdkc100/Makefile create mode 100644 board/samsung/smdkc100/config.mk create mode 100644 board/samsung/smdkc100/lowlevel_init.S create mode 100644 board/samsung/smdkc100/mem_setup.S create mode 100644 board/samsung/smdkc100/onenand.c create mode 100644 board/samsung/smdkc100/smdkc100.c create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 cpu/arm_cortexa8/s5pc1xx/Makefile create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/clock.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/cpu_info.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/reset.S create mode 100644 cpu/arm_cortexa8/s5pc1xx/timer.c create mode 100644 doc/README.s5pc1xx create mode 100644 drivers/mtd/onenand/samsung.c create mode 100644 drivers/serial/serial_s5pc1xx.c create mode 100644 include/asm-arm/arch-s5pc1xx/clk.h create mode 100644 include/asm-arm/arch-s5pc1xx/clock.h create mode 100644 include/asm-arm/arch-s5pc1xx/cpu.h create mode 100644 include/asm-arm/arch-s5pc1xx/gpio.h create mode 100644 include/asm-arm/arch-s5pc1xx/power.h create mode 100644 include/asm-arm/arch-s5pc1xx/pwm.h create mode 100644 include/asm-arm/arch-s5pc1xx/uart.h create mode 100644 include/configs/davinci_dm355leopard.h create mode 100644 include/configs/davinci_dm6467evm.h create mode 100644 include/configs/omap3_sdp3430.h create mode 100644 include/configs/smdkc100.h create mode 100644 include/linux/mtd/samsung_onenand.h

1 0

[U-Boot] [PATCH 5/5] add TI da8xx support: integration into build system
by Thompson, Nick (GE EntSol, Intelligent Platforms) 18 Oct '09

18 Oct '09

Add config, Makefile and common header changes to integrate DA8xx Support. Creates a new config target: make ... da8xx_omapl1_evm_config Tested build with Sourcery G++ Lite 2009q1-203 tool chain on an OMAP-L137 EVM board RevE with Rev1.1 DA830 silicon. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- Applies to u-boot-ti Makefile | 4 + include/common.h | 3 + include/configs/da8xx_evm.h | 241 +++++++++++++++++++++++++++++++++++++++++++ diff --git a/Makefile b/Makefile index 449099a..26170db 100644 --- a/Makefile +++ b/Makefile @@ -2936,6 +2936,10 @@ davinci_dm365evm_config : unconfig davinci_dm6467evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci +xtract_da8xx = $(subst da8xx_omapl1,da8xx,$(subst _config,,$1)) +da8xx_omapl1_evm_config : unconfig + @$(MKCONFIG) $(call xtract_da8xx,$@) arm arm926ejs da8xx-evm da8xx da8xx + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 diff --git a/include/common.h b/include/common.h index f7c93bf..5c8d609 100644 --- a/include/common.h +++ b/include/common.h @@ -107,6 +107,9 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_BLACKFIN #include <asm/blackfin.h> #endif +#ifdef CONFIG_DA8XX +#include <asm/arch/hardware.h> +#endif #include <part.h> #include <flash.h> diff --git a/include/configs/da8xx_evm.h b/include/configs/da8xx_evm.h new file mode 100644 index 0000000..8bdbb71 --- /dev/null +++ b/include/configs/da8xx_evm.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> + * + * Based on davinci_dvevm.h. Original Copyrights follow: + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> +#include <asm/arch/clock.h> + +/*=======*/ +/* Board */ +/*=======*/ +/* #define CONFIG_USE_SPIFLASH */ +/* #define CONFIG_USE_NAND */ + +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) /* Arm Clock */ +#define CONFIG_SYS_OSCIN_FREQ 24000000 +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* Timer Input clock freq */ +#define CONFIG_SYS_HZ 1000 +#undef CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is _always_ loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ + +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* SDRAM size 64MB */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start address */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define SDRAM_4BANKS_10COLS /* TODO: Update this! */ + +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ + +/*====================================================*/ +/* I2C EEPROM definitions for catalyst 24W256 EEPROM chip */ +/*====================================================*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_DA8XX_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI + +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CONFIG_USE_NAND +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_CS 3 +#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CONFIG_SYS_CLE_MASK 0x10 +#define CONFIG_SYS_ALE_MASK 0x8 +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define DEF_BOOTM "" +#endif + +#ifdef CONFIG_USE_NOR +#define CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3) +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */ +#define CONFIG_SYS_FLASH_SPL_ACCESS +#endif + +#ifdef CONFIG_USE_SPIFLASH +#undef CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_OFFSET SZ_256K +#define CONFIG_ENV_SECT_SIZE SZ_4K +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000) /* default Linux kernel load address */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/* #define CONFIG_USB_DA8XX */ +/* #define CONFIG_MUSB_HCD */ +#define CONFIG_USE_PINMUX + +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTDELAY 3 + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#define CONFIG_CMD_EEPROM + +#ifdef CONFIG_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#endif + +#ifdef CONFIG_USE_SPIFLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SAVEENV +#endif + +#if !defined(CONFIG_USE_NAND) && !defined(CONFIG_USE_NOR) && !defined(CONFIG_USE_SPIFLASH) +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE SZ_16K +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_ENV +#endif + +#ifdef CONFIG_USB_DA8XX +#define CONFIG_CMD_USB /* inclue support for usb */ +#define CONFIG_CMD_STORAGE /* inclue support for usb */ +#define CONFIG_CMD_FAT /* inclue support for FAT/storage*/ +#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage*/ +#endif + +#endif /* __CONFIG_H */

2 1

[U-Boot] [PATCH 3/5] add TI da8xx support: new board directory for spectrum digital EVM
by Thompson, Nick (GE EntSol, Intelligent Platforms) 18 Oct '09

18 Oct '09

Create initial contents of the board/da8xx/da8xx-evm directory: Low level board initialisation. Board level initilisation. Linker control. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- Applies to u-boot-ti board/da8xx/da8xx-evm/Makefile | 52 ++++++ board/da8xx/da8xx-evm/board_init.S | 29 +++ board/da8xx/da8xx-evm/config.mk | 30 ++++ board/da8xx/da8xx-evm/dv_board.c | 330 ++++++++++++++++++++++++++++++++++++ board/da8xx/da8xx-evm/u-boot.lds | 52 ++++++ 5 files changed, 493 insertions(+), 0 deletions(-) diff --git a/board/da8xx/da8xx-evm/Makefile b/board/da8xx/da8xx-evm/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/da8xx/da8xx-evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/da8xx/da8xx-evm/board_init.S b/board/da8xx/da8xx-evm/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/da8xx/da8xx-evm/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/da8xx/da8xx-evm/config.mk b/board/da8xx/da8xx-evm/config.mk new file mode 100644 index 0000000..56de37a --- /dev/null +++ b/board/da8xx/da8xx-evm/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# (C) Copyright 2003 +# Texas Instruments, <www.ti.com> +# Swaminathan <swami.iyer(a)ti.com> +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# (C) Copyright 2008 +# Sekhar Nori, Texas Instruments, Inc. <nsekhar(a)ti.com> +# +# Texas Instruments DA8xx EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# DA8xx EVM has 1 bank of 64 MB SDRAM (2 16Meg x16 chips). +# Physical Address: +# C000'0000 to C400'0000 +# +# Linux-Kernel is expected to be at C000'8000, entry C000'8000 +# (mem base + reserved) +# +# we load ourself to C108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0xC1080000 diff --git a/board/da8xx/da8xx-evm/dv_board.c b/board/da8xx/da8xx-evm/dv_board.c new file mode 100644 index 0000000..b551bc5 --- /dev/null +++ b/board/da8xx/da8xx-evm/dv_board.c @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson(a)gefanuc.com> + * + * Use the board_eth_init hook to initialise the ethernet in the + * correct order. (Has to wait until after call to miiphy_init().) + * + * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar(a)ti.com> + * + * Modified for DA8xx EVM. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <i2c.h> +#include <net.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> +#include <asm/io.h> + +#define MACH_TYPE_DA8XX_EVM 1781 + +DECLARE_GLOBAL_DATA_PTR; + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + + if (id >= 64) + return; + + if(id < 32) { + mdstat = REG_P(PSC0_MDSTAT + (id * 4)); + mdctl = REG_P(PSC0_MDCTL + (id * 4)); + ptstat = REG_P(PSC0_PTSTAT); + ptcmd = REG_P(PSC0_PTCMD); + } else { + id -= 32; + mdstat = REG_P(PSC1_MDSTAT + (id * 4)); + mdctl = REG_P(PSC1_MDCTL + (id * 4)); + ptstat = REG_P(PSC1_PTSTAT); + ptcmd = REG_P(PSC1_PTCMD); + } + + while (*ptstat & 0x01) {;} + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + /* TBD: Confirm if such cases exist for Primus */ + if (0) + *mdctl |= 0x200; + + *ptcmd = 0x01; + + while (*ptstat & 0x01) {;} + while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ +} + +int board_init(void) +{ + + dv_reg_p intc; + + /*-------------------------------------------------------* + * Mask all IRQs by clearing the global enable and setting + * the enable clear for all the 90 interrupts. This code is + * also included in low level init. Including it here in case + * low level init is skipped. Not removing it from low level + * init in case some of the low level init code generates + * interrupts... Not expected... but you never know... + *-------------------------------------------------------*/ + +#ifndef CONFIG_USE_IRQ + intc = REG_P(INTC_GLB_EN); + intc[0] = 0; + + intc = REG_P(INTC_HINT_EN); + intc[0] = 0; + intc[1] = 0; + intc[2] = 0; + + intc = REG_P(INTC_EN_CLR0); + intc[0] = 0xFFFFFFFF; + intc[1] = 0xFFFFFFFF; + intc[2] = 0xFFFFFFFF; +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DA8XX_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Power on required peripherals + * ARM does not have acess by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + lpsc_on(DAVINCI_LPSC_AEMIF); /* NAND, NOR */ + lpsc_on(DAVINCI_LPSC_SPI0); /* Serial Flash */ + lpsc_on(DAVINCI_LPSC_EMAC); /* image download */ + lpsc_on(DAVINCI_LPSC_UART2); /* console */ + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Pin Muxing support */ + + /* setup the SUSPSRC for ARM to control emulation suspend */ + REG(SUSPSRC) &= ~( (1 << 27) /* Timer0 */ + | (1 << 21) /* SPI0 */ + | (1 << 20) /* UART2 */ + | (1 << 5) /* EMAC */ + | (1 << 16) /* I2C0 */ + ); + +#ifdef CONFIG_USE_PINMUX + +#ifdef CONFIG_SPI_FLASH + /* SPI0 */ + REG(PINMUX7) &= 0x00000FFF; + REG(PINMUX7) |= 0x11111000; +#endif + +#ifdef CONFIG_DRIVER_DA8XX_EMAC + /* RMII clock is sourced externally */ + REG(PINMUX9) &= 0xFF0FFFFF; + REG(PINMUX10) &= 0x0000000F; + REG(PINMUX10) |= 0x22222220; + REG(PINMUX11) &= 0xFFFFFF00; + REG(PINMUX11) |= 0x00000022; +#endif + + /* Async EMIF */ +#if defined(CONFIG_USE_NAND) || defined(CONFIG_USE_NOR) + REG(PINMUX13) &= 0x00FFFFFF; + REG(PINMUX13) |= 0x11000000; + REG(PINMUX14) = 0x11111111; + REG(PINMUX15) = 0x11111111; + REG(PINMUX16) = 0x11111111; + REG(PINMUX17) = 0x11111111; + REG(PINMUX18) = 0x11111111; + REG(PINMUX19) &= 0xFFFFFFF0; + REG(PINMUX19) |= 0x1; +#endif + + /* UART Muxing and enabling */ + REG(PINMUX8) &= 0x0FFFFFFF; + REG(PINMUX8) |= 0x20000000; + + REG(PINMUX9) &= 0xFFFFFFF0; + REG(PINMUX9) |= 0x00000002; + + /* I2C muxing */ + REG(PINMUX8) &= 0xFFF00FFF; + REG(PINMUX8) |= 0x00022000; + +#endif + + REG(DAVINCI_UART2_BASE + 0x30) = 0xE001; + + + return(0); +} + +int misc_init_r (void) +{ + printf ("ARM Clock : %d Hz\n", clk_get(DAVINCI_ARM_CLKID)); + + return(0); +} + +/* TODO: find a header file to put these in */ +extern void da8xx_eth_set_mac_addr (const u_int8_t *addr); +extern int da8xx_eth_hw_init(void); +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_DA8XX_EMAC + u_int8_t tmp[20], buf[10]; + int i; + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7f00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CONFIG_SYS_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + tmp[0] = 0x01; + tmp[1] = 0x23; + if(i2c_write(0x5f, 0, 0, tmp, 2)) { + printf("Ethernet switch start failed!\n"); + } + + if (getenv ("ethaddr")) { + uchar enetaddr[6]; + eth_getenv_enetaddr("ethaddr", enetaddr); + da8xx_eth_set_mac_addr(enetaddr); + } + + if (!da8xx_eth_hw_init()) { + printf("Error: Ethernet init failed!\n"); + } +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} + +#if defined(CONFIG_USE_NOR) +static u8 nor_read8(void *addr) +{ + u32 temp = (u32) addr; + + temp &= 0x00FFFFFF; + temp >>= 13; + temp |= 0x62000000; + *(unsigned char*) temp = 0; + + return __raw_readb(addr); +} + +static u16 nor_read16(void *addr) +{ + u32 temp = (u32) addr; + + temp &= 0x00FFFFFF; + temp >>= 13; + temp |= 0x62000000; + *(unsigned char*) temp = 0; + + return __raw_readw(addr); +} + +static u32 nor_read32(void *addr) +{ + u32 temp = (u32) addr; + + temp &= 0x00FFFFFF; + temp >>= 13; + temp |= 0x62000000; + *(unsigned char*) temp = 0; + + return __raw_readl(addr); +} + +static void nor_write8(u8 value, void *addr) +{ + u32 temp = (u32) addr; + temp &= 0x00FFFFFF; + temp >>= 13; + temp |= 0x62000000; + *(unsigned char*) temp = 0; + __raw_writeb(value, addr); +} + +static void nor_write16(u8 value, void *addr) +{ + u32 temp = (u32) addr; + temp &= 0x00FFFFFF; + temp >>= 13; + temp |= 0x62000000; + *(unsigned char*) temp = 0; + __raw_writew(value, addr); +} + +static void nor_write32(u8 value, void *addr) +{ + u32 temp = (u32) addr; + temp &= 0x00FFFFFF; + temp >>= 13; + temp |= 0x62000000; + *(unsigned char*) temp = 0; + __raw_writel(value, addr); +} + +void board_flash_set_access(ulong bank_base, int banknum, flash_info_t* info) +{ + info->read8 = nor_read8; + info->read16 = nor_read16; + info->read32 = nor_read32; + + info->write8 = nor_write8; + info->write16 = nor_write16; + info->write32 = nor_write32; +} +#endif diff --git a/board/da8xx/da8xx-evm/u-boot.lds b/board/da8xx/da8xx-evm/u-boot.lds new file mode 100644 index 0000000..a4fcd1a --- /dev/null +++ b/board/da8xx/da8xx-evm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +}

2 1

[U-Boot] [PATCH 2/5] add TI da8xx support: new arch directory
by Thompson, Nick (GE EntSol, Intelligent Platforms) 18 Oct '09

18 Oct '09

Create initial contents of the include/asm-arm/arch-da8xx directory: General hardware definitions. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- Applies to u-boot-ti include/asm-arm/arch-da8xx/clock.h | 24 +++ include/asm-arm/arch-da8xx/emac_defs.h | 328 ++++++++++++++++++++++++++++++++ include/asm-arm/arch-da8xx/emif_defs.h | 71 +++++++ include/asm-arm/arch-da8xx/hardware.h | 206 ++++++++++++++++++++ include/asm-arm/arch-da8xx/i2c_defs.h | 95 +++++++++ 5 files changed, 724 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/arch-da8xx/clock.h b/include/asm-arm/arch-da8xx/clock.h new file mode 100644 index 0000000..a9b74f4 --- /dev/null +++ b/include/asm-arm/arch-da8xx/clock.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson(a)gefanuc.com> + * + * DA8xx clock include header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ------------------------------------------------------------------------ ---- + */ + +#ifndef __ASSEMBLER__ +int clk_get(unsigned int id); +#endif diff --git a/include/asm-arm/arch-da8xx/emac_defs.h b/include/asm-arm/arch-da8xx/emac_defs.h new file mode 100644 index 0000000..2da0c41 --- /dev/null +++ b/include/asm-arm/arch-da8xx/emac_defs.h @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Based on: + * + * ------------------------------------------------------------------------ ---- + * + * dm644x_emac.h + * + * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ------------------------------------------------------------------------ ---- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ------------------------------------------------------------------------ ---- + + * Modifications: + * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. + * + */ + +#ifndef _DA8XX_EMAC_H_ +#define _DA8XX_EMAC_H_ + +#include <asm/arch/hardware.h> + +#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE +#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE +#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE +#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) + +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ + +/* Ethernet Min/Max packet size */ +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 +#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 +#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ + +/* Number of RX packet buffers + * NOTE: Only 1 buffer supported as of now + */ +#define EMAC_MAX_RX_BUFFERS 10 + + +/*********************************************** + ******** Internally used macros *************** + ***********************************************/ + +#define EMAC_CH_TX 1 +#define EMAC_CH_RX 0 + +/* Each descriptor occupies 4 words, lets start RX desc's at 0 and + * reserve space for 64 descriptors max + */ +#define EMAC_RX_DESC_BASE 0x0 +#define EMAC_TX_DESC_BASE 0x1000 + +/* EMAC Teardown value */ +#define EMAC_TEARDOWN_VALUE 0xfffffffc + +/* MII Status Register */ +#define MII_STATUS_REG 1 + +/* Number of statistics registers */ +#define EMAC_NUM_STATS 36 + + +/* EMAC Descriptor */ +typedef volatile struct _emac_desc +{ + u_int32_t next; /* Pointer to next descriptor in chain */ + u_int8_t *buffer; /* Pointer to data buffer */ + u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ + u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ +} emac_desc; + +/* CPPI bit positions */ +#define EMAC_CPPI_SOP_BIT (0x80000000) +#define EMAC_CPPI_EOP_BIT (0x40000000) +#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) +#define EMAC_CPPI_EOQ_BIT (0x10000000) +#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) +#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) + +#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) + +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) + +#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) +#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) + + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +/* Ethernet MAC Registers Structure */ +typedef struct { + dv_reg TXIDVER; + dv_reg TXCONTROL; + dv_reg TXTEARDOWN; + u_int8_t RSVD0[4]; + dv_reg RXIDVER; + dv_reg RXCONTROL; + dv_reg RXTEARDOWN; + u_int8_t RSVD1[100]; + dv_reg TXINTSTATRAW; + dv_reg TXINTSTATMASKED; + dv_reg TXINTMASKSET; + dv_reg TXINTMASKCLEAR; + dv_reg MACINVECTOR; + u_int8_t RSVD2[12]; + dv_reg RXINTSTATRAW; + dv_reg RXINTSTATMASKED; + dv_reg RXINTMASKSET; + dv_reg RXINTMASKCLEAR; + dv_reg MACINTSTATRAW; + dv_reg MACINTSTATMASKED; + dv_reg MACINTMASKSET; + dv_reg MACINTMASKCLEAR; + u_int8_t RSVD3[64]; + dv_reg RXMBPENABLE; + dv_reg RXUNICASTSET; + dv_reg RXUNICASTCLEAR; + dv_reg RXMAXLEN; + dv_reg RXBUFFEROFFSET; + dv_reg RXFILTERLOWTHRESH; + u_int8_t RSVD4[8]; + dv_reg RX0FLOWTHRESH; + dv_reg RX1FLOWTHRESH; + dv_reg RX2FLOWTHRESH; + dv_reg RX3FLOWTHRESH; + dv_reg RX4FLOWTHRESH; + dv_reg RX5FLOWTHRESH; + dv_reg RX6FLOWTHRESH; + dv_reg RX7FLOWTHRESH; + dv_reg RX0FREEBUFFER; + dv_reg RX1FREEBUFFER; + dv_reg RX2FREEBUFFER; + dv_reg RX3FREEBUFFER; + dv_reg RX4FREEBUFFER; + dv_reg RX5FREEBUFFER; + dv_reg RX6FREEBUFFER; + dv_reg RX7FREEBUFFER; + dv_reg MACCONTROL; + dv_reg MACSTATUS; + dv_reg EMCONTROL; + dv_reg FIFOCONTROL; + dv_reg MACCONFIG; + dv_reg SOFTRESET; + u_int8_t RSVD5[88]; + dv_reg MACSRCADDRLO; + dv_reg MACSRCADDRHI; + dv_reg MACHASH1; + dv_reg MACHASH2; + dv_reg BOFFTEST; + dv_reg TPACETEST; + dv_reg RXPAUSE; + dv_reg TXPAUSE; + u_int8_t RSVD6[16]; + dv_reg RXGOODFRAMES; + dv_reg RXBCASTFRAMES; + dv_reg RXMCASTFRAMES; + dv_reg RXPAUSEFRAMES; + dv_reg RXCRCERRORS; + dv_reg RXALIGNCODEERRORS; + dv_reg RXOVERSIZED; + dv_reg RXJABBER; + dv_reg RXUNDERSIZED; + dv_reg RXFRAGMENTS; + dv_reg RXFILTERED; + dv_reg RXQOSFILTERED; + dv_reg RXOCTETS; + dv_reg TXGOODFRAMES; + dv_reg TXBCASTFRAMES; + dv_reg TXMCASTFRAMES; + dv_reg TXPAUSEFRAMES; + dv_reg TXDEFERRED; + dv_reg TXCOLLISION; + dv_reg TXSINGLECOLL; + dv_reg TXMULTICOLL; + dv_reg TXEXCESSIVECOLL; + dv_reg TXLATECOLL; + dv_reg TXUNDERRUN; + dv_reg TXCARRIERSENSE; + dv_reg TXOCTETS; + dv_reg FRAME64; + dv_reg FRAME65T127; + dv_reg FRAME128T255; + dv_reg FRAME256T511; + dv_reg FRAME512T1023; + dv_reg FRAME1024TUP; + dv_reg NETOCTETS; + dv_reg RXSOFOVERRUNS; + dv_reg RXMOFOVERRUNS; + dv_reg RXDMAOVERRUNS; + u_int8_t RSVD7[624]; + dv_reg MACADDRLO; + dv_reg MACADDRHI; + dv_reg MACINDEX; + u_int8_t RSVD8[244]; + dv_reg TX0HDP; + dv_reg TX1HDP; + dv_reg TX2HDP; + dv_reg TX3HDP; + dv_reg TX4HDP; + dv_reg TX5HDP; + dv_reg TX6HDP; + dv_reg TX7HDP; + dv_reg RX0HDP; + dv_reg RX1HDP; + dv_reg RX2HDP; + dv_reg RX3HDP; + dv_reg RX4HDP; + dv_reg RX5HDP; + dv_reg RX6HDP; + dv_reg RX7HDP; + dv_reg TX0CP; + dv_reg TX1CP; + dv_reg TX2CP; + dv_reg TX3CP; + dv_reg TX4CP; + dv_reg TX5CP; + dv_reg TX6CP; + dv_reg TX7CP; + dv_reg RX0CP; + dv_reg RX1CP; + dv_reg RX2CP; + dv_reg RX3CP; + dv_reg RX4CP; + dv_reg RX5CP; + dv_reg RX6CP; + dv_reg RX7CP; +} emac_regs; + +/* EMAC Wrapper Registers Structure */ +typedef struct { + dv_reg REV; + dv_reg SOFTRESET; + dv_reg INTCONTROL; + dv_reg C0RXTHRESHEN; + dv_reg C0RXEN; + dv_reg C0TXEN; + dv_reg C0MISCEN; + dv_reg C1RXTHRESHEN; + dv_reg C1RXEN; + dv_reg C1TXEN; + dv_reg C1MISCEN; + dv_reg C2RXTHRESHEN; + dv_reg C2RXEN; + dv_reg C2TXEN; + dv_reg C2MISCEN; + dv_reg C0RXTHRESHSTAT; + dv_reg C0RXSTAT; + dv_reg C0TXSTAT; + dv_reg C0MISCSTAT; + dv_reg C1RXTHRESHSTAT; + dv_reg C1RXSTAT; + dv_reg C1TXSTAT; + dv_reg C1MISCSTAT; + dv_reg C2RXTHRESHSTAT; + dv_reg C2RXSTAT; + dv_reg C2TXSTAT; + dv_reg C2MISCSTAT; + dv_reg C0RXIMAX; + dv_reg C0TXIMAX; + dv_reg C1RXIMAX; + dv_reg C1TXIMAX; + dv_reg C2RXIMAX; + dv_reg C2TXIMAX; +} ewrap_regs; + + +/* EMAC MDIO Registers Structure */ +typedef struct { + dv_reg VERSION; + dv_reg CONTROL; + dv_reg ALIVE; + dv_reg LINK; + dv_reg LINKINTRAW; + dv_reg LINKINTMASKED; + u_int8_t RSVD0[8]; + dv_reg USERINTRAW; + dv_reg USERINTMASKED; + dv_reg USERINTMASKSET; + dv_reg USERINTMASKCLEAR; + u_int8_t RSVD1[80]; + dv_reg USERACCESS0; + dv_reg USERPHYSEL0; + dv_reg USERACCESS1; + dv_reg USERPHYSEL1; +} mdio_regs; + +typedef struct +{ + char name[64]; + int (*init)(int phy_addr); + int (*is_phy_connected)(int phy_addr); + int (*get_link_speed)(int phy_addr); + int (*auto_negotiate)(int phy_addr); +} phy_t; + +#endif /* _DA8XX_EMAC_H_ */ diff --git a/include/asm-arm/arch-da8xx/emif_defs.h b/include/asm-arm/arch-da8xx/emif_defs.h new file mode 100644 index 0000000..c91e30c --- /dev/null +++ b/include/asm-arm/arch-da8xx/emif_defs.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include <asm/arch/hardware.h> + +typedef struct { + dv_reg ERCSR; + dv_reg AWCCR; + dv_reg SDBCR; + dv_reg SDRCR; + dv_reg AB1CR; + dv_reg AB2CR; + dv_reg AB3CR; + dv_reg AB4CR; + dv_reg SDTIMR; + dv_reg DDRSR; + dv_reg DDRPHYCR; + dv_reg DDRPHYSR; + dv_reg TOTAR; + dv_reg TOTACTR; + dv_reg DDRPHYID_REV; + dv_reg SDSRETR; + dv_reg EIRR; + dv_reg EIMR; + dv_reg EIMSR; + dv_reg EIMCR; + dv_reg IOCTRLR; + dv_reg IOSTATR; + u_int8_t RSVD0[8]; + dv_reg NANDFCR; + dv_reg NANDFSR; + u_int8_t RSVD1[8]; + dv_reg NANDF1ECC; + dv_reg NANDF2ECC; + dv_reg NANDF3ECC; + dv_reg NANDF4ECC; + u_int8_t RSVD2[60]; + dv_reg NAND4BITECCLOAD; + dv_reg NAND4BITECC1; + dv_reg NAND4BITECC2; + dv_reg NAND4BITECC3; + dv_reg NAND4BITECC4; + dv_reg NANDERRADD1; + dv_reg NANDERRADD2; + dv_reg NANDERRVAL1; + dv_reg NANDERRVAL2; +} emif_registers; + +typedef emif_registers *emifregs; +#endif diff --git a/include/asm-arm/arch-da8xx/hardware.h b/include/asm-arm/arch-da8xx/hardware.h new file mode 100644 index 0000000..ec2176d --- /dev/null +++ b/include/asm-arm/arch-da8xx/hardware.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc + * + * Based on hardware.h for DaVinci. Original Copyrights follow. + * + * Sergey Kubushyn <ksi(a)koi8.net> + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Based on: + * + * ------------------------------------------------------------------------ - + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <config.h> + +#ifndef __ASSEMBLY__ + +#include <asm/sizes.h> + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int * dv_reg_p; + +#endif + +/* + * Base register addresses + */ +#define DAVINCI_UART0_BASE (0x01c42000) +#define DAVINCI_UART1_BASE (0x01d0c000) +#define DAVINCI_UART2_BASE (0x01d0d000) +#define DAVINCI_I2C0_BASE (0x01c22000) +#define DAVINCI_I2C1_BASE (0x01e28000) +#define DAVINCI_TIMER0_BASE (0x01c20000) +#define DAVINCI_TIMER1_BASE (0x01c21000) +#define DAVINCI_WDOG_BASE (0x01c21000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01c11000) +#define DAVINCI_PSC0_BASE (0x01c10000) +#define DAVINCI_PSC1_BASE (0x01e27000) +#define DAVINCI_SPI0_BASE (0x01c41000) +#define DAVINCI_USB_OTG_BASE (0x01e00000) +#define DAVINCI_SPI1_BASE (0x01e12000) +#define DAVINCI_GPIO_BASE (0x01e26000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01e23000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01e22000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01e20000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01e24000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x68000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x40000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x60000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x62000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE (0x64000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE (0x66000000) +#define DAVINCI_DDR_EMIF_CTRL_BASE (0xb0000000) +#define DAVINCI_DDR_EMIF_DATA_BASE (0xc0000000) +#define DAVINCI_INTC_BASE (0xfffee000) +#define DAVINCI_BOOTCFG_BASE (0x01c14000) + +/* Clock IDs */ +#define DAVINCI_PLLM_CLKID (0xFF + 0) +#define DAVINCI_PLLC_CLKID (0xFF + 1) +#define DAVINCI_AUXCLK_CLKID (0xFF + 2) +#define DAVINCI_MDIO_CLKID 4 +#define DAVINCI_SPI0_CLKID 2 +#define DAVINCI_UART2_CLKID 2 +#define DAVINCI_ARM_CLKID 6 + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +/* LPSCs in PSC0 */ +#define DAVINCI_LPSC_TPCC 0 +#define DAVINCI_LPSC_TPTC0 1 +#define DAVINCI_LPSC_TPTC1 2 +#define DAVINCI_LPSC_AEMIF 3 +#define DAVINCI_LPSC_SPI0 4 +#define DAVINCI_LPSC_MMC_SD 5 +#define DAVINCI_LPSC_AINTC 6 +#define DAVINCI_LPSC_ARM_RAM_ROM 7 +#define DAVINCI_LPSC_SECCTL_KEYMGR 8 +#define DAVINCI_LPSC_UART0 9 +#define DAVINCI_LPSC_SCR0 10 +#define DAVINCI_LPSC_SCR1 11 +#define DAVINCI_LPSC_SCR2 12 +#define DAVINCI_LPSC_DMAX 13 +#define DAVINCI_LPSC_ARM 14 +#define DAVINCI_LPSC_GEM 15 + +/* for LPSCs in PSC1, 32 + actual id is being used for differentiation */ +#define DAVINCI_LPSC_USB11 (32 + 1) +#define DAVINCI_LPSC_USB20 (32 + 2) +#define DAVINCI_LPSC_GPIO (32 + 3) +#define DAVINCI_LPSC_UHPI (32 + 4) +#define DAVINCI_LPSC_EMAC (32 + 5) +#define DAVINCI_LPSC_DDR_EMIF (32 + 6) +#define DAVINCI_LPSC_McASP0 (32 + 7) +#define DAVINCI_LPSC_McASP1 (32 + 8) +#define DAVINCI_LPSC_McASP2 (32 + 9) +#define DAVINCI_LPSC_SPI1 (32 + 10) +#define DAVINCI_LPSC_I2C1 (32 + 11) +#define DAVINCI_LPSC_UART1 (32 + 12) +#define DAVINCI_LPSC_UART2 (32 + 13) +#define DAVINCI_LPSC_LCDC (32 + 16) +#define DAVINCI_LPSC_ePWM (32 + 17) +#define DAVINCI_LPSC_eCAP (32 + 20) +#define DAVINCI_LPSC_eQEP (32 + 21) +#define DAVINCI_LPSC_SCR_P0 (32 + 22) +#define DAVINCI_LPSC_SCR_P1 (32 + 23) +#define DAVINCI_LPSC_CR_P3 (32 + 26) +#define DAVINCI_LPSC_L3_CBA_RAM (32 + 31) + +/* Some PSC defines */ + +#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define PSC0_MDSTAT (DAVINCI_PSC0_BASE + 0x800) +#define PSC0_PTCMD (DAVINCI_PSC0_BASE + 0x120) +#define PSC0_PTSTAT (DAVINCI_PSC0_BASE + 0x128) + +#define PSC1_MDCTL (DAVINCI_PSC1_BASE + 0xa00) +#define PSC1_MDSTAT (DAVINCI_PSC1_BASE + 0x800) +#define PSC1_PTCMD (DAVINCI_PSC1_BASE + 0x120) +#define PSC1_PTSTAT (DAVINCI_PSC1_BASE + 0x128) + +/* Some PLL defines */ +#define PLL0_PLLCTL (DAVINCI_PLL_CNTRL0_BASE + 0x100) +#define PLL0_PLLM (DAVINCI_PLL_CNTRL0_BASE + 0x110) +#define PLL0_PREDIV (DAVINCI_PLL_CNTRL0_BASE + 0x114) +#define PLL0_POSTDIV (DAVINCI_PLL_CNTRL0_BASE + 0x128) +#define PLL0_DIV1 (DAVINCI_PLL_CNTRL0_BASE + 0x118) +#define PLL0_DIV2 (DAVINCI_PLL_CNTRL0_BASE + 0x11c) +#define PLL0_DIV3 (DAVINCI_PLL_CNTRL0_BASE + 0x120) +#define PLL0_DIV4 (DAVINCI_PLL_CNTRL0_BASE + 0x160) +#define PLL0_DIV5 (DAVINCI_PLL_CNTRL0_BASE + 0x164) +#define PLL0_DIV6 (DAVINCI_PLL_CNTRL0_BASE + 0x168) +#define PLL0_DIV7 (DAVINCI_PLL_CNTRL0_BASE + 0x16c) +#define PLL0_DIV8 (DAVINCI_PLL_CNTRL0_BASE + 0x170) +#define PLL0_DIV9 (DAVINCI_PLL_CNTRL0_BASE + 0x114) + +/* Boot config */ +#define PINMUX0 (DAVINCI_BOOTCFG_BASE + 0x120) +#define PINMUX1 (DAVINCI_BOOTCFG_BASE + 0x124) +#define PINMUX2 (DAVINCI_BOOTCFG_BASE + 0x128) +#define PINMUX3 (DAVINCI_BOOTCFG_BASE + 0x12c) +#define PINMUX4 (DAVINCI_BOOTCFG_BASE + 0x130) +#define PINMUX5 (DAVINCI_BOOTCFG_BASE + 0x134) +#define PINMUX6 (DAVINCI_BOOTCFG_BASE + 0x138) +#define PINMUX7 (DAVINCI_BOOTCFG_BASE + 0x13c) +#define PINMUX8 (DAVINCI_BOOTCFG_BASE + 0x140) +#define PINMUX9 (DAVINCI_BOOTCFG_BASE + 0x144) +#define PINMUX10 (DAVINCI_BOOTCFG_BASE + 0x148) +#define PINMUX11 (DAVINCI_BOOTCFG_BASE + 0x14c) +#define PINMUX12 (DAVINCI_BOOTCFG_BASE + 0x150) +#define PINMUX13 (DAVINCI_BOOTCFG_BASE + 0x154) +#define PINMUX14 (DAVINCI_BOOTCFG_BASE + 0x158) +#define PINMUX15 (DAVINCI_BOOTCFG_BASE + 0x15C) +#define PINMUX16 (DAVINCI_BOOTCFG_BASE + 0x160) +#define PINMUX17 (DAVINCI_BOOTCFG_BASE + 0x164) +#define PINMUX18 (DAVINCI_BOOTCFG_BASE + 0x168) +#define PINMUX19 (DAVINCI_BOOTCFG_BASE + 0x16c) +#define SUSPSRC (DAVINCI_BOOTCFG_BASE + 0x170) +#define CFGCHIP0 (DAVINCI_BOOTCFG_BASE + 0x17c) +#define CFGCHIP2 (DAVINCI_BOOTCFG_BASE + 0x184) + +/* Interrupt controller */ +#define INTC_GLB_EN (DAVINCI_INTC_BASE + 0x10) +#define INTC_HINT_EN (DAVINCI_INTC_BASE + 0x1500) +#define INTC_EN_CLR0 (DAVINCI_INTC_BASE + 0x380) + +/* GPIO */ +#define GPIO_BANK4_ADDR 0x01E26000 +#define GPIO_BANK4_REG_DIR_ADDR ( GPIO_BANK4_ADDR + 0x60 ) +#define GPIO_BANK4_REG_OPDATA_ADDR ( GPIO_BANK4_ADDR + 0x64 ) +#define GPIO_BANK4_REG_SET_ADDR ( GPIO_BANK4_ADDR + 0x68 ) +#define GPIO_BANK4_REG_CLR_ADDR ( GPIO_BANK4_ADDR + 0x6C ) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-da8xx/i2c_defs.h b/include/asm-arm/arch-da8xx/i2c_defs.h new file mode 100644 index 0000000..714211f --- /dev/null +++ b/include/asm-arm/arch-da8xx/i2c_defs.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * + * Some changes copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DAVINCI_I2C_H_ +#define _DAVINCI_I2C_H_ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_BASE 0x01c22000 + +#define I2C_OA (I2C_BASE + 0x00) +#define I2C_IE (I2C_BASE + 0x04) +#define I2C_STAT (I2C_BASE + 0x08) +#define I2C_SCLL (I2C_BASE + 0x0c) +#define I2C_SCLH (I2C_BASE + 0x10) +#define I2C_CNT (I2C_BASE + 0x14) +#define I2C_DRR (I2C_BASE + 0x18) +#define I2C_SA (I2C_BASE + 0x1c) +#define I2C_DXR (I2C_BASE + 0x20) +#define I2C_CON (I2C_BASE + 0x24) +#define I2C_IV (I2C_BASE + 0x28) +#define I2C_PSC (I2C_BASE + 0x30) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */ +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ + + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 5) /* I2C module enable */ +#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */ +#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ + +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ + +#endif

2 2

[U-Boot] [PATCH 1/5] add TI da8xx support: new cpu directory
by Thompson, Nick (GE EntSol, Intelligent Platforms) 18 Oct '09

18 Oct '09

Create initial contents of the cpu/arm926ejs/da8xx directory: Low level initilisation. Support for SoC clock, timer and reset functions. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- Applies to u-boot-ti cpu/arm926ejs/da8xx/Makefile | 53 +++++++++++++ cpu/arm926ejs/da8xx/clock.c | 58 ++++++++++++++ cpu/arm926ejs/da8xx/lowlevel_init.S | 73 +++++++++++++++++ cpu/arm926ejs/da8xx/reset.S | 77 ++++++++++++++++++ cpu/arm926ejs/da8xx/timer.c | 148 +++++++++++++++++++++++++++++++++++ 5 files changed, 409 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/da8xx/Makefile b/cpu/arm926ejs/da8xx/Makefile new file mode 100644 index 0000000..76fb7b8 --- /dev/null +++ b/cpu/arm926ejs/da8xx/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o clock.o +SOBJS = reset.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS += lowlevel_init.o +endif + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +####################################################################### ## + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +####################################################################### ## diff --git a/cpu/arm926ejs/da8xx/clock.c b/cpu/arm926ejs/da8xx/clock.c new file mode 100644 index 0000000..25cf4df --- /dev/null +++ b/cpu/arm926ejs/da8xx/clock.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar(a)ti.com> + * + * DA8xx clock module + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ------------------------------------------------------------------------ ---- + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +dv_reg_p sysdiv[9] = { + REG_P(PLL0_DIV1), REG_P(PLL0_DIV2), REG_P(PLL0_DIV3), REG_P(PLL0_DIV4), + REG_P(PLL0_DIV5), REG_P(PLL0_DIV6), REG_P(PLL0_DIV7), REG_P(PLL0_DIV8), + REG_P(PLL0_DIV9) }; + +int clk_get(unsigned int id) +{ + int pre_div = (REG(PLL0_PREDIV) & 0xff) + 1; + int pllm = REG(PLL0_PLLM) + 1; + int post_div = (REG(PLL0_POSTDIV) & 0xff) + 1; + int pll_out = CONFIG_SYS_OSCIN_FREQ; + + if(id == DAVINCI_AUXCLK_CLKID) + goto out; + + /* Lets keep this simple. Combining operations can result in + * unexpected approximations + */ + pll_out /= pre_div; + pll_out *= pllm; + + if(id == DAVINCI_PLLM_CLKID) + goto out; + + pll_out /= post_div; + + if(id == DAVINCI_PLLC_CLKID) + goto out; + + pll_out /= (REG(sysdiv[id - 1]) & 0xff) + 1; + +out: + return pll_out; +} diff --git a/cpu/arm926ejs/da8xx/lowlevel_init.S b/cpu/arm926ejs/da8xx/lowlevel_init.S new file mode 100644 index 0000000..53f801a --- /dev/null +++ b/cpu/arm926ejs/da8xx/lowlevel_init.S @@ -0,0 +1,73 @@ +/* + * Low-level board setup code for TI DA8xx SoC based boards. + * + * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> + * Sekhar Nori <nsekhar(a)ti.com> + * + * Based on TI DaVinci low level init code. Original copyrights follow. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Partially based on TI sources, original copyrights follow: + */ + +/* + * Board specific setup info + * + * (C) Copyright 2003 + * Texas Instruments, <www.ti.com> + * Kshitij Gupta <Kshitij(a)ti.com> + * + * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 + * + * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * Modified for DV-EVM board by Swaminathan S, Nov 2005 + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/hardware.h> + +.globl lowlevel_init +lowlevel_init: + + /* + * Call board-specific lowlevel init. + * That MUST be present and THAT returns + * back to arch calling code with "mov pc, lr." + */ + b dv_board_init + nop + +.ltorg + +INTC_GLB_EN_ADDR: + .word INTC_GLB_EN +INTC_EN_CLR0_ADDR: + .word INTC_EN_CLR0 +INTC_HINT_EN_ADDR: + .word INTC_HINT_EN + diff --git a/cpu/arm926ejs/da8xx/reset.S b/cpu/arm926ejs/da8xx/reset.S new file mode 100644 index 0000000..a687d44 --- /dev/null +++ b/cpu/arm926ejs/da8xx/reset.S @@ -0,0 +1,77 @@ +/* + * Processor reset using WDT for TI TMS320DM644x SoC. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, WDT_TGCR + mov r1, $0x08 + str r1, [r0] + ldr r1, [r0] + orr r1, r1, $0x03 + str r1, [r0] + mov r1, $0 + ldr r0, WDT_TIM12 + str r1, [r0] + ldr r0, WDT_TIM34 + str r1, [r0] + ldr r0, WDT_PRD12 + str r1, [r0] + ldr r0, WDT_PRD34 + str r1, [r0] + ldr r0, WDT_TCR + ldr r1, [r0] + orr r1, r1, $0x40 + str r1, [r0] + ldr r0, WDT_WDTCR + ldr r1, [r0] + orr r1, r1, $0x4000 + str r1, [r0] + ldr r1, WDTCR_VAL1 + str r1, [r0] + ldr r1, WDTCR_VAL2 + str r1, [r0] + nop + nop + nop + nop +reset_cpu_loop: + b reset_cpu_loop + +WDT_TGCR: + .word 0x01c21c24 +WDT_TIM12: + .word 0x01c21c10 +WDT_TIM34: + .word 0x01c21c14 +WDT_PRD12: + .word 0x01c21c18 +WDT_PRD34: + .word 0x01c21c1c +WDT_TCR: + .word 0x01c21c20 +WDT_WDTCR: + .word 0x01c21c28 +WDTCR_VAL1: + .word 0xa5c64000 +WDTCR_VAL2: + .word 0xda7e4000 diff --git a/cpu/arm926ejs/da8xx/timer.c b/cpu/arm926ejs/da8xx/timer.c new file mode 100644 index 0000000..728167a --- /dev/null +++ b/cpu/arm926ejs/da8xx/timer.c @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +/* #include <arm926ejs.h> */ + +typedef volatile struct { + u_int32_t pid12; + u_int32_t emumgt; + u_int32_t na1; + u_int32_t na2; + u_int32_t tim12; + u_int32_t tim34; + u_int32_t prd12; + u_int32_t prd34; + u_int32_t tcr; + u_int32_t tgcr; + u_int32_t wdtcr; +} davinci_timer; + +davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE; + +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) +#define TIM_CLK_DIV 16 + +static ulong timestamp; +static ulong lastinc; + +int timer_init(void) +{ + /* We are using timer34 in unchained 32-bit mode, full speed */ + timer->tcr = 0x0; + timer->tgcr = 0x0; + timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8); + timer->tim34 = 0x0; + timer->prd34 = TIMER_LOAD_VAL; + lastinc = 0; + timestamp = 0; + timer->tcr = 2 << 22; + + return(0); +} + +void reset_timer(void) +{ + timer->tcr = 0x0; + timer->tim34 = 0; + lastinc = 0; + timestamp = 0; + timer->tcr = 2 << 22; +} + +static ulong get_timer_raw(void) +{ + ulong now = timer->tim34; + + if (now >= lastinc) { + /* normal mode */ + timestamp += now - lastinc; + } else { + /* overflow ... */ + timestamp += now + TIMER_LOAD_VAL - lastinc; + } + lastinc = now; + return timestamp; +} + +ulong get_timer(ulong base) +{ + return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= (1000 * TIM_CLK_DIV); + + endtime = get_timer_raw() + tmo; + + do { + ulong now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return(get_timer(0)); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +}

2 1

[U-Boot] [PATCH 0/5] add TI da8xx support:
by Thompson, Nick (GE EntSol, Intelligent Platforms) 18 Oct '09

18 Oct '09

Patches 1/5 and 2/5 both *still* contain small amounts of wrapping - why does outlook even consider that it's okay to mangle my e-mails??? - Please excuse the mess. I can fix them, but I'm not going to send them again until people have had chance to comment on other aspects of the patch set. Thanks, Nick.

4 3

[U-Boot] [PATCH] s5pc1xx: SMDKC100: fix compile warnings
by Minkyu Kang 18 Oct '09

18 Oct '09

fix the following compile warnings warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- drivers/serial/serial_s5pc1xx.c | 2 +- include/asm-arm/arch-s5pc1xx/clock.h | 88 +++++++++++++++++----------------- include/asm-arm/arch-s5pc1xx/gpio.h | 12 ++-- include/asm-arm/arch-s5pc1xx/pwm.h | 36 +++++++------- include/asm-arm/arch-s5pc1xx/uart.h | 18 ++++---- include/linux/mtd/samsung_onenand.h | 70 +++++++++++++------------- 6 files changed, 113 insertions(+), 113 deletions(-) diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c index 64c1dcc..68c06a9 100644 --- a/drivers/serial/serial_s5pc1xx.c +++ b/drivers/serial/serial_s5pc1xx.c @@ -74,7 +74,7 @@ void serial_setbrg_dev(const int dev_index) val = pclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); - writel(udivslot[val % 16], &uart->udivslot); + writew(udivslot[val % 16], &uart->udivslot); } /* diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h index 0cad922..7b4eb89 100644 --- a/include/asm-arm/arch-s5pc1xx/clock.h +++ b/include/asm-arm/arch-s5pc1xx/clock.h @@ -25,69 +25,69 @@ #ifndef __ASSEMBLY__ struct s5pc100_clock { - unsigned long apll_lock; - unsigned long mpll_lock; - unsigned long epll_lock; - unsigned long hpll_lock; + unsigned int apll_lock; + unsigned int mpll_lock; + unsigned int epll_lock; + unsigned int hpll_lock; unsigned char res1[0xf0]; - unsigned long apll_con; - unsigned long mpll_con; - unsigned long epll_con; - unsigned long hpll_con; + unsigned int apll_con; + unsigned int mpll_con; + unsigned int epll_con; + unsigned int hpll_con; unsigned char res2[0xf0]; - unsigned long src0; - unsigned long src1; - unsigned long src2; - unsigned long src3; + unsigned int src0; + unsigned int src1; + unsigned int src2; + unsigned int src3; unsigned char res3[0xf0]; - unsigned long div0; - unsigned long div1; - unsigned long div2; - unsigned long div3; - unsigned long div4; + unsigned int div0; + unsigned int div1; + unsigned int div2; + unsigned int div3; + unsigned int div4; unsigned char res4[0x1ec]; - unsigned long gate_d00; - unsigned long gate_d01; - unsigned long gate_d02; + unsigned int gate_d00; + unsigned int gate_d01; + unsigned int gate_d02; unsigned char res5[0x54]; - unsigned long gate_sclk0; - unsigned long gate_sclk1; + unsigned int gate_sclk0; + unsigned int gate_sclk1; }; struct s5pc110_clock { - unsigned long apll_lock; + unsigned int apll_lock; unsigned char res1[0x4]; - unsigned long mpll_lock; + unsigned int mpll_lock; unsigned char res2[0x4]; - unsigned long epll_lock; + unsigned int epll_lock; unsigned char res3[0xc]; - unsigned long vpll_lock; + unsigned int vpll_lock; unsigned char res4[0xdc]; - unsigned long apll_con; + unsigned int apll_con; unsigned char res5[0x4]; - unsigned long mpll_con; + unsigned int mpll_con; unsigned char res6[0x4]; - unsigned long epll_con; + unsigned int epll_con; unsigned char res7[0xc]; - unsigned long vpll_con; + unsigned int vpll_con; unsigned char res8[0xdc]; - unsigned long src0; - unsigned long src1; - unsigned long src2; - unsigned long src3; + unsigned int src0; + unsigned int src1; + unsigned int src2; + unsigned int src3; unsigned char res9[0xf0]; - unsigned long div0; - unsigned long div1; - unsigned long div2; - unsigned long div3; - unsigned long div4; + unsigned int div0; + unsigned int div1; + unsigned int div2; + unsigned int div3; + unsigned int div4; unsigned char res10[0x1ec]; - unsigned long gate_d00; - unsigned long gate_d01; - unsigned long gate_d02; + unsigned int gate_d00; + unsigned int gate_d01; + unsigned int gate_d02; unsigned char res11[0x54]; - unsigned long gate_sclk0; - unsigned long gate_sclk1; + unsigned int gate_sclk0; + unsigned int gate_sclk1; }; #endif diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index 0010405..afbc7ea 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -23,12 +23,12 @@ #ifndef __ASSEMBLY__ struct s5pc1xx_gpio_bank { - unsigned long con; - unsigned long dat; - unsigned long pull; - unsigned long drv; - unsigned long pdn_con; - unsigned long pdn_pull; + unsigned int con; + unsigned int dat; + unsigned int pull; + unsigned int drv; + unsigned int pdn_con; + unsigned int pdn_pull; unsigned char res1[8]; }; diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h index 53c23cd..e02a8d8 100644 --- a/include/asm-arm/arch-s5pc1xx/pwm.h +++ b/include/asm-arm/arch-s5pc1xx/pwm.h @@ -35,24 +35,24 @@ #ifndef __ASSEMBLY__ struct s5pc1xx_timer { - unsigned long tcfg0; - unsigned long tcfg1; - unsigned long tcon; - unsigned long tcntb0; - unsigned long tcmpb0; - unsigned long tcnto0; - unsigned long tcntb1; - unsigned long tcmpb1; - unsigned long tcnto1; - unsigned long tcntb2; - unsigned long tcmpb2; - unsigned long tcnto2; - unsigned long tcntb3; - unsigned long res1; - unsigned long tcnto3; - unsigned long tcntb4; - unsigned long tcnto4; - unsigned long tintcstat; + unsigned int tcfg0; + unsigned int tcfg1; + unsigned int tcon; + unsigned int tcntb0; + unsigned int tcmpb0; + unsigned int tcnto0; + unsigned int tcntb1; + unsigned int tcmpb1; + unsigned int tcnto1; + unsigned int tcntb2; + unsigned int tcmpb2; + unsigned int tcnto2; + unsigned int tcntb3; + unsigned int res1; + unsigned int tcnto3; + unsigned int tcntb4; + unsigned int tcnto4; + unsigned int tintcstat; }; #endif /* __ASSEMBLY__ */ diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h index bd7d6b2..140dbdc 100644 --- a/include/asm-arm/arch-s5pc1xx/uart.h +++ b/include/asm-arm/arch-s5pc1xx/uart.h @@ -25,19 +25,19 @@ #ifndef __ASSEMBLY__ struct s5pc1xx_uart { - unsigned long ulcon; - unsigned long ucon; - unsigned long ufcon; - unsigned long umcon; - unsigned long utrstat; - unsigned long uerstat; - unsigned long ufstat; - unsigned long umstat; + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; unsigned char utxh; unsigned char res1[3]; unsigned char urxh; unsigned char res2[3]; - unsigned long ubrdiv; + unsigned int ubrdiv; unsigned short udivslot; unsigned char res3[2]; unsigned char res4[0x3d0]; diff --git a/include/linux/mtd/samsung_onenand.h b/include/linux/mtd/samsung_onenand.h index 9865780..021fa27 100644 --- a/include/linux/mtd/samsung_onenand.h +++ b/include/linux/mtd/samsung_onenand.h @@ -31,75 +31,75 @@ #ifndef __ASSEMBLY__ struct samsung_onenand { - unsigned long mem_cfg; /* 0x0000 */ + unsigned int mem_cfg; /* 0x0000 */ unsigned char res1[0xc]; - unsigned long burst_len; /* 0x0010 */ + unsigned int burst_len; /* 0x0010 */ unsigned char res2[0xc]; - unsigned long mem_reset; /* 0x0020 */ + unsigned int mem_reset; /* 0x0020 */ unsigned char res3[0xc]; - unsigned long int_err_stat; /* 0x0030 */ + unsigned int int_err_stat; /* 0x0030 */ unsigned char res4[0xc]; - unsigned long int_err_mask; /* 0x0040 */ + unsigned int int_err_mask; /* 0x0040 */ unsigned char res5[0xc]; - unsigned long int_err_ack; /* 0x0050 */ + unsigned int int_err_ack; /* 0x0050 */ unsigned char res6[0xc]; - unsigned long ecc_err_stat; /* 0x0060 */ + unsigned int ecc_err_stat; /* 0x0060 */ unsigned char res7[0xc]; - unsigned long manufact_id; /* 0x0070 */ + unsigned int manufact_id; /* 0x0070 */ unsigned char res8[0xc]; - unsigned long device_id; /* 0x0080 */ + unsigned int device_id; /* 0x0080 */ unsigned char res9[0xc]; - unsigned long data_buf_size; /* 0x0090 */ + unsigned int data_buf_size; /* 0x0090 */ unsigned char res10[0xc]; - unsigned long boot_buf_size; /* 0x00A0 */ + unsigned int boot_buf_size; /* 0x00A0 */ unsigned char res11[0xc]; - unsigned long buf_amount; /* 0x00B0 */ + unsigned int buf_amount; /* 0x00B0 */ unsigned char res12[0xc]; - unsigned long tech; /* 0x00C0 */ + unsigned int tech; /* 0x00C0 */ unsigned char res13[0xc]; - unsigned long fba; /* 0x00D0 */ + unsigned int fba; /* 0x00D0 */ unsigned char res14[0xc]; - unsigned long fpa; /* 0x00E0 */ + unsigned int fpa; /* 0x00E0 */ unsigned char res15[0xc]; - unsigned long fsa; /* 0x00F0 */ + unsigned int fsa; /* 0x00F0 */ unsigned char res16[0x3c]; - unsigned long sync_mode; /* 0x0130 */ + unsigned int sync_mode; /* 0x0130 */ unsigned char res17[0xc]; - unsigned long trans_spare; /* 0x0140 */ + unsigned int trans_spare; /* 0x0140 */ unsigned char res18[0x3c]; - unsigned long err_page_addr; /* 0x0180 */ + unsigned int err_page_addr; /* 0x0180 */ unsigned char res19[0x1c]; - unsigned long int_pin_en; /* 0x01A0 */ + unsigned int int_pin_en; /* 0x01A0 */ unsigned char res20[0x1c]; - unsigned long acc_clock; /* 0x01C0 */ + unsigned int acc_clock; /* 0x01C0 */ unsigned char res21[0x1c]; - unsigned long err_blk_addr; /* 0x01E0 */ + unsigned int err_blk_addr; /* 0x01E0 */ unsigned char res22[0xc]; - unsigned long flash_ver_id; /* 0x01F0 */ + unsigned int flash_ver_id; /* 0x01F0 */ unsigned char res23[0x6c]; - unsigned long watchdog_cnt_low; /* 0x0260 */ + unsigned int watchdog_cnt_low; /* 0x0260 */ unsigned char res24[0xc]; - unsigned long watchdog_cnt_hi; /* 0x0270 */ + unsigned int watchdog_cnt_hi; /* 0x0270 */ unsigned char res25[0xc]; - unsigned long sync_write; /* 0x0280 */ + unsigned int sync_write; /* 0x0280 */ unsigned char res26[0x1c]; - unsigned long cold_reset; /* 0x02A0 */ + unsigned int cold_reset; /* 0x02A0 */ unsigned char res27[0xc]; - unsigned long ddp_device; /* 0x02B0 */ + unsigned int ddp_device; /* 0x02B0 */ unsigned char res28[0xc]; - unsigned long multi_plane; /* 0x02C0 */ + unsigned int multi_plane; /* 0x02C0 */ unsigned char res29[0x1c]; - unsigned long trans_mode; /* 0x02E0 */ + unsigned int trans_mode; /* 0x02E0 */ unsigned char res30[0x1c]; - unsigned long ecc_err_stat2; /* 0x0300 */ + unsigned int ecc_err_stat2; /* 0x0300 */ unsigned char res31[0xc]; - unsigned long ecc_err_stat3; /* 0x0310 */ + unsigned int ecc_err_stat3; /* 0x0310 */ unsigned char res32[0xc]; - unsigned long ecc_err_stat4; /* 0x0320 */ + unsigned int ecc_err_stat4; /* 0x0320 */ unsigned char res33[0x1c]; - unsigned long dev_page_size; /* 0x0340 */ + unsigned int dev_page_size; /* 0x0340 */ unsigned char res34[0x4c]; - unsigned long int_mon_status; /* 0x0390 */ + unsigned int int_mon_status; /* 0x0390 */ }; #endif -- 1.5.4.3

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[U-Boot] uboot MPC5200B DDR memsize hangs
by Chris Alfred (Internode) 18 Oct '09

18 Oct '09

> Hm... U-Boot 1.2.0 is very old. Please consider it obsolelte and > unsupported. Is there any special reason for not using current code? No reason, UBoot 1.2.0 is in ELDK4.1. Will seek and download latest uboot >> UBoot starts and we see serial output; but UBoot hangs on the very >> first read from DDR which is done in memsize.c:get_ram_size(). >> >> The serial output is: >> CPU: MPC5200 v2.2, Core v1.4 at 462 MHz >> Bus 132 MHz, IPB 66 MHz, PCI 33 MHz >> Board: JKC5200N7 >> I2C: 85 kHz, ready >> DRAM: >> >> We are pretty sure the DDR configuration is correct, but we would >> have thought this would not cause get_ram_size() to hang - merely >> return 0 or incorrect memory size. > > You are almost certainly wron - either your hardware or your DDR > initialization is broken. Can bad DDR configuration really hang the processor? I thought there was no acknowledgement system for DDR. > See also the FAQ at > http://www.denx.de/wiki/view/DULG/UBootCrashAfterRelocation Does the relocation occur before checking the DDR size? Chris

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