October 2009 - U-Boot

[U-Boot] [PATCH v1 1/2] NET: Move MDIO regs out of TSEC Space
by Sandeep Gopalpet 19 Oct '09

19 Oct '09

Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different. Signed-off-by: Sandeep Gopalpet <sandeep.kumar(a)freescale.com> --- drivers/net/tsec.c | 20 ++++++++-------- include/asm-ppc/immap_85xx.h | 10 ++++++++ include/tsec.h | 48 +++++++++++++++++++++++++++++++---------- 3 files changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5c3d261..2ad033e 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -83,7 +83,7 @@ static struct tsec_info_struct tsec_info[] = { #ifdef CONFIG_MPC85XX_FEC { .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), - .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS @@ -136,6 +136,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs = tsec_info->miiregs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; @@ -222,7 +223,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) } /* Writes the given phy's reg with value, using the specified MDIO regs */ -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, uint reg, uint value) { int timeout = 1000000; @@ -245,7 +246,7 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) +uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum) { uint value; @@ -290,11 +291,11 @@ static void tsec_configure_serdes(struct tsec_private *priv) { /* Access TBI PHY registers at given TSEC register offset as opposed to the * register offset used for external PHY accesses */ - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } @@ -306,12 +307,11 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ regs->tbipa = CONFIG_SYS_TBIPA_VALUE; - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -739,7 +739,7 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; - volatile tsec_t *regbase = priv->phyregs; + volatile tsec_mdio_t *regbase = priv->phyregs; int timeout = 1000000; for (phyid = 0; phyid < 4; phyid++) { @@ -1772,7 +1772,7 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; phyregs->miimcfg = MIIMCFG_RESET; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 4194295..6c9baac 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1932,4 +1932,14 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +/* TSEC and MDIO OFFSETS */ +#define CONFIG_SYS_TSEC1_OFFSET (0x24000) +#define TSEC_SIZE (0x01000) + +#define CONFIG_SYS_MDIO1_OFFSET (0x24520) +#define MDIO_OFFSET (0x01000) + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_85xx__*/ diff --git a/include/tsec.h b/include/tsec.h index 0ac3034..342c07e 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao(a)motorola.com) * author Andy Fleming @@ -24,18 +24,34 @@ #define CONFIG_SYS_TSEC1_OFFSET (0x24000) #endif -#define TSEC_SIZE 0x01000 +#ifndef TSEC_SIZE + #define TSEC_SIZE 0x01000 +#endif + +#ifndef CONFIG_SYS_MDIO1_OFFSET + #define CONFIG_SYS_MDIO1_OFFSET (0x24520) +#endif + +#ifndef MDIO_OFFSET + #define MDIO_OFFSET 0x01000 +#endif /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ || defined(CONFIG_MPC83xx) +#ifndef TSEC_BASE_ADDR #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #endif +#ifndef MDIO_BASE_ADDR + #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#endif +#endif #define STD_TSEC_INFO(num) \ { \ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ + .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR + (num -1)*MDIO_OFFSET ), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS \ @@ -44,7 +60,8 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ + x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ + x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR + (num -1)*MDIO_OFFSET); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -461,6 +478,16 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; +typedef struct tsec_mdio +{ + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ +} tsec_mdio_t; + typedef struct tsec { /* General Control and Status Registers (0x2_n000) */ @@ -526,12 +553,7 @@ typedef struct tsec uint res51c; - uint miimcfg; /* MII Management: Configuration */ - uint miimcom; /* MII Management: Command */ - uint miimadd; /* MII Management: Address */ - uint miimcon; /* MII Management: Control */ - uint miimstat; /* MII Management: Status */ - uint miimind; /* MII Management: Indicators */ + uint resmdio[6]; uint res538; @@ -571,7 +593,8 @@ typedef struct tsec struct tsec_private { volatile tsec_t *regs; - volatile tsec_t *phyregs; + volatile tsec_mdio_t *phyregs; + volatile tsec_mdio_t *phyregs_sgmii; struct phy_info *phyinfo; uint phyaddr; u32 flags; @@ -630,7 +653,8 @@ struct phy_info { struct tsec_info_struct { tsec_t *regs; - tsec_t *miiregs; + tsec_mdio_t *miiregs; + tsec_mdio_t *miiregs_sgmii; char *devname; unsigned int phyaddr; u32 flags; -- 1.5.2.2

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[U-Boot] [PATCH 4/4] ppc4xx: Yosemite/Yellowstone: Check and reconfigure the PCI sync clock
by Stefan Roese 19 Oct '09

19 Oct '09

This patch now uses the 440EP(x)/GR(x) function to check and dynamically reconfigure the PCI sync clock. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/yosemite/yosemite.c | 26 +++++++++++++++++++++++--- 1 files changed, 23 insertions(+), 3 deletions(-) diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 7ceccfa..ccbeb0e 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -33,6 +33,15 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static inline u32 get_async_pci_freq(void) +{ + if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & + CONFIG_SYS_BCSR5_PCI66EN) + return 66666666; + else + return 33333333; +} + int board_early_init_f(void) { register uint reg; @@ -106,6 +115,9 @@ int board_early_init_f(void) mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ + /* Check and reconfigure the PCI sync clock if necessary */ + ppc4xx_pci_sync_clock_config(get_async_pci_freq()); + /*clear tmrclk divisor */ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; @@ -178,7 +190,7 @@ int checkboard(void) { char *s = getenv("serial#"); u8 rev; - u8 val; + u32 clock = get_async_pci_freq(); #ifdef CONFIG_440EP printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); @@ -187,8 +199,7 @@ int checkboard(void) #endif rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN; - printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); if (s != NULL) { puts(", serial# "); @@ -196,6 +207,15 @@ int checkboard(void) } putc('\n'); + /* + * Reconfiguration of the PCI sync clock is already done, + * now check again if everything is in range: + */ + if (ppc4xx_pci_sync_clock_config(clock)) { + printf("ERROR: PCI clocking incorrect (async=%d " + "sync=%ld)!\n", clock, get_PCI_freq()); + } + return (0); } -- 1.6.5.1

1 0

[U-Boot] [PATCH 3/4] ppc4xx: Sequoia/Rainer: Check and reconfigure the PCI sync clock
by Stefan Roese 19 Oct '09

19 Oct '09

This patch now uses the 440EP(x)/GR(x) function to check and dynamically reconfigure the PCI sync clock. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/sequoia/sequoia.c | 26 +++++++++++++++++++++++--- 1 files changed, 23 insertions(+), 3 deletions(-) diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index d42c802..00f6408 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -40,6 +40,15 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); +static inline u32 get_async_pci_freq(void) +{ + if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & + CONFIG_SYS_BCSR5_PCI66EN) + return 66666666; + else + return 33333333; +} + int board_early_init_f(void) { u32 sdr0_cust0; @@ -76,6 +85,9 @@ int board_early_init_f(void) mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(UIC2SR, 0xffffffff); /* clear all */ + /* Check and reconfigure the PCI sync clock if necessary */ + ppc4xx_pci_sync_clock_config(get_async_pci_freq()); + /* 50MHz tmrclk */ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); @@ -319,7 +331,7 @@ int checkboard(void) { char *s = getenv("serial#"); u8 rev; - u8 val; + u32 clock = get_async_pci_freq(); #ifdef CONFIG_440EPX printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); @@ -328,8 +340,7 @@ int checkboard(void) #endif rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN; - printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); if (s != NULL) { puts(", serial# "); @@ -337,6 +348,15 @@ int checkboard(void) } putc('\n'); + /* + * Reconfiguration of the PCI sync clock is already done, + * now check again if everything is in range: + */ + if (ppc4xx_pci_sync_clock_config(clock)) { + printf("ERROR: PCI clocking incorrect (async=%d " + "sync=%ld)!\n", clock, get_PCI_freq()); + } + return (0); } -- 1.6.5.1

1 0

[U-Boot] [PATCH 2/4] ppc4xx: Print PCI synchronous clock frequency upon bootup
by Stefan Roese 19 Oct '09

19 Oct '09

Some 4xx variants (e.g. 440EP(x)/GR(x)) have an internal synchronous PCI clock. Knowledge about the currently configured value might be helpful. So let's print it out upon bootup. Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/cpu.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index a9a0ac3..e1b00a7 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -608,10 +608,17 @@ int checkcpu (void) break; } - printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), + printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu", + strmhz(buf, clock), sys_info.freqPLB / 1000000, get_OPB_freq() / 1000000, sys_info.freqEBC / 1000000); +#if defined(CONFIG_PCI) && \ + (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX)) + printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000); +#endif + printf(")\n"); if (addstr[0] != 0) printf(" %s\n", addstr); -- 1.6.5.1

1 0

[U-Boot] [PATCH 0/3] mpc52xx: IPEK01 board support
by Wolfgang Grandegger 19 Oct '09

19 Oct '09

Hello, this patch add support for the IPEK01 MPC5200 based board. It requires two patchs for the Fujitsu MB862xx driver: [PATCH 1/3] video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for X888RGB mode [PATCH 2/3] video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01 [PATCH 3/3] mpc52xx: add support for the IPEK01 board Wolfgang.

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[U-Boot] CONFIG_GENERIC_MMC Usage
by Shane Volpe 19 Oct '09

19 Oct '09

I have a PXA270 system with U-boot v2009.08 installed, currently this system is successfully using the U-boot mmc interface (legacy) . However, after looking through the u-boot source code, I see there is a new mmc interface (CONFIG_GENERIC_MMC), should I be using the generic mmc interface? I have tried it but it does not seem to work, I'm assuming that it probably requires initialization of the MMC hardware in the board files whereas in the legacy mmc system that was done by the (legacy_mmc_init) board specific mmc (pxa_mmc.c) code. Questions regarding the new GENERIC_MMC interface: 1.) Is there any documentation in place (or can someone send me off a quick reply) on how to set up the generic mmc driver with a board? 2.) Is it ready (recommended) to use or is it still under heavy development? 3.) Does it support SDHC or just SD? Regards, Shane

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[U-Boot] [u-boot] [PATCH] [2/2] mxc_fec: put freed pointers to NULL to avoid problems with further free() calls.
by javier Martin 19 Oct '09

19 Oct '09

If a free() call is used on an already freed pointer we run into stability problems. Put all pointers to NULL after freeing to avoid this problem. Tested on i.MX27 Litekit board with eldk-2.0 toolchain. Signed-off-by: Javier Martin <javier.martin(a)vista-silicon.com> -- diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bd83a24..7e86bc6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -444,6 +444,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) */ if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { free(fec->base_ptr); + fec->base_ptr = NULL; return -ENOMEM; } fec_tbd_init(fec); @@ -492,7 +493,9 @@ static void fec_halt(struct eth_device *dev) fec->rbd_index = 0; fec->tbd_index = 0; free(fec->rdb_ptr); + fec->rdb_ptr = NULL; free(fec->base_ptr); + fec->base_ptr = NULL; debug("eth_halt: done\n"); } -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com

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[U-Boot] [PATCH 4/5] add TI da8xx support: new ethenet driver for da830 EMAC
by Thompson, Nick (GE EntSol, Intelligent Platforms) 19 Oct '09

19 Oct '09

Add a driver for the DA830 EMAC. This is very similar to the davinci_emac driver. It has been restructured to make it as similar as possible. Potentially the two could be merged, but I don't have access to other davinci type platforms to test for breakage after the inevitable mangling required. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- Applies to u-boot-ti drivers/net/Makefile | 1 + drivers/net/da8xx_emac.c | 654 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 655 insertions(+), 0 deletions(-) diff --git a/drivers/net/Makefile b/drivers/net/Makefile index be5c484..9cbe736 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -68,6 +68,7 @@ COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o COBJS-$(CONFIG_SMC911X) += smc911x.o COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o +COBJS-$(CONFIG_DRIVER_DA8XX_EMAC) += da8xx_emac.o COBJS-$(CONFIG_TSEC_ENET) += tsec.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o diff --git a/drivers/net/da8xx_emac.c b/drivers/net/da8xx_emac.c new file mode 100644 index 0000000..e1d232f --- /dev/null +++ b/drivers/net/da8xx_emac.c @@ -0,0 +1,654 @@ +/* + * Ethernet driver for TI OMAP-L1x/DA8xx chips. + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson(a)gefanuc.com> + * + * Much of this is very similar to the davinci_emac driver. Possibly they + * could be merged, but I have no access to non DA8xx platforms + * and can't test for breakage after the inevitable mangling. + * + * Code base is not new. Original copyright follows: + * + * ---------------------------------------------------------------------------- + * + * Ethernet driver for TI TMS320DM644x (DaVinci) chips. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright + * follows: + * + * ---------------------------------------------------------------------------- + * + * dm644x_emac.c + * + * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM + * + * Copyright (C) 2005 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ +#include <common.h> +#include <command.h> +#include <net.h> +#include <miiphy.h> +#include <malloc.h> +#include <asm/arch/emac_defs.h> + +#ifdef CONFIG_DRIVER_DA8XX_EMAC + +#ifdef CONFIG_CMD_NET + +unsigned int emac_dbg = 0; +#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) + +/* Internal static functions */ +static int da8xx_eth_open (struct eth_device *dev, bd_t *bis); +static void da8xx_eth_close (struct eth_device *dev); +static int da8xx_eth_send_packet (struct eth_device *dev, volatile void *packet, int length); +static int da8xx_eth_rcv_packet (struct eth_device *dev); +static void da8xx_eth_mdio_enable(void); + +static int gen_init_phy(int phy_addr); +static int gen_is_phy_connected(int phy_addr); +static int gen_get_link_speed(int phy_addr); +static int gen_auto_negotiate(int phy_addr); + +/* mac address for EMAC registers only (not packet data) */ +static u_int8_t da8xx_eth_mac_addr[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00 }; + +/* + * This function must be called before emac_open() if you want to override + * the default mac address. + */ +void da8xx_eth_set_mac_addr(const u_int8_t *addr) +{ + int i; + + for (i = 0; i < sizeof (da8xx_eth_mac_addr); i++) { + da8xx_eth_mac_addr[i] = addr[i]; + } +} + +/* EMAC Addresses */ +static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; +static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; +static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; + +/* EMAC descriptors */ +static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); +static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); +static volatile emac_desc *emac_rx_active_head = 0; +static volatile emac_desc *emac_rx_active_tail = 0; +static int emac_rx_queue_active = 0; + +/* Receive packet buffers */ +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + +/* PHY address for a discovered PHY (0xff - not found) */ +static volatile u_int8_t active_phy_addr = 0xff; + +static int no_phy_init (int phy_addr) { return(1); } +static int no_phy_is_connected (int phy_addr) { return(1); } +static int no_phy_get_link_speed (int phy_addr) { return(1); } +static int no_phy_auto_negotiate (int phy_addr) { return(1); } +phy_t phy = { + .name = "da8xx_evm", + .init = no_phy_init, + .is_phy_connected = no_phy_is_connected, + .get_link_speed = no_phy_get_link_speed, + .auto_negotiate = no_phy_auto_negotiate +}; + +static void da8xx_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + adap_mdio->CONTROL = (clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE; + + while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} +} + +/* + * Tries to find an active connected PHY. Returns 1 if address if found. + * If no active PHY found returns 0. If more than one active PHY (switch) + * returns 2 + * Sets active_phy_addr variable when returns 1. + */ +static int da8xx_eth_phy_detect(void) +{ + u_int32_t phy_act_state; + int i; + + active_phy_addr = 0xff; + + if ((phy_act_state = adap_mdio->ALIVE) == 0) + return(0); /* No active PHYs */ + + debug_emac("da8xx_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); + + for (i = 0; i < 32; i++) { + if (phy_act_state & (1 << i)) { + if (phy_act_state & ~(1 << i)) + return(2); /* More than one PHY */ + else { + active_phy_addr = i; + return(1); + } + } + } + + return(0); /* Just to make GCC happy */ +} + + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int da8xx_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16); + + /* Wait for command to complete */ + while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return(1); + } + + *data = -1; + return(0); +} + +/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ +int da8xx_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff); + + /* Wait for command to complete */ + while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + + return(1); +} + +/* PHY functions for a generic PHY */ +static int gen_init_phy(int phy_addr) +{ + int ret = 1; + + if (gen_get_link_speed(phy_addr)) { + /* Try another time */ + ret = gen_get_link_speed(phy_addr); + } + + return(ret); +} + +static int gen_is_phy_connected(int phy_addr) +{ + u_int16_t dummy; + + return(da8xx_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); +} + +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if (da8xx_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04)) + return(1); + + return(0); +} + +static int gen_auto_negotiate(int phy_addr) +{ + u_int16_t tmp; + + if (!da8xx_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + return(0); + + /* Restart Auto_negotiation */ + tmp |= PHY_BMCR_AUTON; + da8xx_eth_phy_write(phy_addr, PHY_BMCR, tmp); + + /*check AutoNegotiate complete */ + udelay (10000); + if (!da8xx_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + return(0); + + if (!(tmp & PHY_BMSR_AUTN_COMP)) + return(0); + + return(gen_get_link_speed(phy_addr)); +} +/* End of generic PHY functions */ + + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static int da8xx_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +{ + return(da8xx_eth_phy_read(addr, reg, value) ? 0 : 1); +} + +static int da8xx_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value) +{ + return(da8xx_eth_phy_write(addr, reg, value) ? 0 : 1); +} + +#endif + +/* + * This function initializes the emac hardware. It does NOT initialize + * EMAC modules power or pin multiplexors, that is done by board_init() + * much earlier in bootup process. Returns 1 on success, 0 otherwise. + */ +int da8xx_eth_hw_init(void) +{ + u_int32_t phy_id; + u_int16_t tmp; + int i, ret; + struct eth_device *dev; + + /* register the ethernet driver functions */ + dev = malloc(sizeof *dev); + + if (dev == NULL) { + return -1; + } + + dev->iobase = 0; + dev->init = da8xx_eth_open; + dev->halt = da8xx_eth_close; + dev->send = da8xx_eth_send_packet; + dev->recv = da8xx_eth_rcv_packet; + + eth_register(dev); + + /* The RMII clock can be sources internally through the SYSCLK7 + * or can come externally through a dedicated pin. This selection is + * controlled by PinMux9[21]. PinMux registers are off-limits for ARM. + * In short, we just assume there is a 50MHz RMII clock available. + */ + + da8xx_eth_mdio_enable(); + + for (i = 0; i < 256; i++) { + if (adap_mdio->ALIVE) + break; + udelay(1000); + } + + if (i >= 256) { + printf("No ETH PHY detected!!!\n"); + return(0); + } + + /* Find if a PHY is connected and get it's address */ + ret = da8xx_eth_phy_detect(); + + if (ret == 0) + return 0; + + if (ret == 2) { + printf("More than one PHY detected.\n"); + } else { + /* Get PHY ID and initialize phy_ops for a detected PHY */ + if (!da8xx_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id = (tmp << 16) & 0xffff0000; + + if (!da8xx_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + active_phy_addr = 0xff; + return(0); + } + + phy_id |= tmp & 0x0000ffff; + + switch (phy_id) { + default: + sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); + phy.init = gen_init_phy; + phy.is_phy_connected = gen_is_phy_connected; + phy.get_link_speed = gen_get_link_speed; + phy.auto_negotiate = gen_auto_negotiate; + } + } + + miiphy_register(phy.name, da8xx_mii_phy_read, da8xx_mii_phy_write); + + return(1); +} + + +/* Eth device open */ +static int da8xx_eth_open(struct eth_device *dev, bd_t *bis) +{ + dv_reg_p addr; + u_int32_t clkdiv, cnt; + volatile emac_desc *rx_desc; + int i; + + debug_emac("+ emac_open\n"); + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + while (adap_emac->SOFTRESET != 0) {;} + adap_ewrap->SOFTRESET = 1; + while (adap_ewrap->SOFTRESET != 0) {;} + + adap_ewrap->C0RXEN = adap_ewrap->C1RXEN = adap_ewrap->C2RXEN = 0; + adap_ewrap->C0TXEN = adap_ewrap->C1TXEN = adap_ewrap->C2TXEN = 0; + adap_ewrap->C0MISCEN = adap_ewrap->C1MISCEN = adap_ewrap->C2MISCEN = 0; + + rx_desc = emac_rx_desc; + + adap_emac->TXCONTROL = 0x01; + adap_emac->RXCONTROL = 0x01; + + /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ + /* Using channel 0 only - other channels are disabled */ + for (i = 0; i < 8; i++) { + adap_emac->MACINDEX = i; + adap_emac->MACADDRHI = + (da8xx_eth_mac_addr[3] << 24) | /* bits 23-16 */ + (da8xx_eth_mac_addr[2] << 16) | /* bits 31-24 */ + (da8xx_eth_mac_addr[1] << 8) | /* bits 39-32 */ + (da8xx_eth_mac_addr[0]); /* bits 47-40 */ + adap_emac->MACADDRLO = + (da8xx_eth_mac_addr[5] << 8) | /* bits 8-0*/ + (da8xx_eth_mac_addr[4]) | (1 << 19) | (1 << 20); /* bits 8-0 */ + } + + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Set source MAC address - REQUIRED for pause frames */ + adap_emac->MACSRCADDRHI = + (da8xx_eth_mac_addr[3] << 24) | /* bits 23-16 */ + (da8xx_eth_mac_addr[2] << 16) | /* bits 31-24 */ + (da8xx_eth_mac_addr[1] << 8) | /* bits 39-32 */ + (da8xx_eth_mac_addr[0]); /* bits 47-40 */ + adap_emac->MACSRCADDRLO = + (da8xx_eth_mac_addr[5] << 8) | /* bits 8-0 */ + (da8xx_eth_mac_addr[4]); /* bits 15-8 */ + + /* Set DMA 8 TX / 8 RX Head pointers to 0 */ + addr = &adap_emac->TX0HDP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + addr = &adap_emac->TX0CP; + for(cnt = 0; cnt < 16; cnt++) + *addr++ = 0; + + /* Clear Statistics (do this before setting MacControl register) */ + addr = &adap_emac->RXGOODFRAMES; + for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) + *addr++ = 0; + + /* No multicast addressing */ + adap_emac->MACHASH1 = 0; + adap_emac->MACHASH2 = 0; + + /* Create RX queue and set receive process in place */ + emac_rx_active_head = emac_rx_desc; + for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { + rx_desc->next = (u_int32_t)(rx_desc + 1); + rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; + rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_desc++; + } + + /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + rx_desc--; + rx_desc->next = 0; + emac_rx_active_tail = rx_desc; + emac_rx_queue_active = 1; + + /* Enable TX/RX */ + adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; + adap_emac->RXBUFFEROFFSET = 0; + + /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ + adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + + /* Enable ch 0 only */ + adap_emac->RXUNICASTSET = 0x01; + + /* Enable MII interface and Full duplex mode */ + adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE) | EMAC_MACCONTROL_RMIISPEED_100; + + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + + if (!phy.get_link_speed(active_phy_addr)) + return(0); + + /* Start receive process */ + adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + + debug_emac("- emac_open\n"); + + return(1); +} + +/* EMAC Channel Teardown */ +static void da8xx_eth_ch_teardown(int ch) +{ + dv_reg dly = 0xff; + dv_reg cnt; + + debug_emac("+ emac_ch_teardown\n"); + + if (ch == EMAC_CH_TX) { + /* Init TX channel teardown */ + adap_emac->TXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { + /* Wait here for Tx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->TX0CP = cnt; + adap_emac->TX0HDP = 0; + } else { + /* Init RX channel teardown */ + adap_emac->RXTEARDOWN = 1; + for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { + /* Wait here for Rx teardown completion interrupt to occur + * Note: A task delay can be called here to pend rather than + * occupying CPU cycles - anyway it has been found that teardown + * takes very few cpu cycles and does not affect functionality */ + dly--; + udelay(1); + if (dly == 0) + break; + } + adap_emac->RX0CP = cnt; + adap_emac->RX0HDP = 0; + } + + debug_emac("- emac_ch_teardown\n"); +} + +/* Eth device close */ +static void da8xx_eth_close(struct eth_device *dev) +{ + debug_emac("+ emac_close\n"); + + da8xx_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ + da8xx_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ + + /* Reset EMAC module and disable interrupts in wrapper */ + adap_emac->SOFTRESET = 1; + adap_ewrap->SOFTRESET = 1; + + adap_ewrap->C0RXEN = adap_ewrap->C1RXEN = adap_ewrap->C2RXEN = 0; + adap_ewrap->C0TXEN = adap_ewrap->C1TXEN = adap_ewrap->C2TXEN = 0; + adap_ewrap->C0MISCEN = adap_ewrap->C1MISCEN = adap_ewrap->C2MISCEN = 0; + + debug_emac("- emac_close\n"); +} + +static int tx_send_loop = 0; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int da8xx_eth_send_packet(struct eth_device *dev, volatile void *packet, int length) +{ + int ret_status = -1; + tx_send_loop = 0; + + /* Return error if no link */ + if (!phy.get_link_speed(active_phy_addr)) + { + printf("WARN: emac_send_packet: No link\n"); + return (ret_status); + } + + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + { + length = EMAC_MIN_ETHERNET_PKT_SIZE; + } + + /* Populate the TX descriptor */ + emac_tx_desc->next = 0; + emac_tx_desc->buffer = (u_int8_t *)packet; + emac_tx_desc->buff_off_len = (length & 0xffff); + emac_tx_desc->pkt_flag_len = ((length & 0xffff) | + EMAC_CPPI_SOP_BIT | + EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT); + /* Send the packet */ + adap_emac->TX0HDP = (unsigned int)emac_tx_desc; + + /* Wait for packet to complete or link down */ + while (1) { + if (!phy.get_link_speed(active_phy_addr)) { + da8xx_eth_ch_teardown(EMAC_CH_TX); + return (ret_status); + } + if (adap_emac->TXINTSTATRAW & 0x01) { + ret_status = length; + break; + } + tx_send_loop++; + } + + return(ret_status); +} + +/* + * This function handles receipt of a packet from the network + */ +static int da8xx_eth_rcv_packet(struct eth_device *dev) +{ + volatile emac_desc *rx_curr_desc; + volatile emac_desc *curr_desc; + volatile emac_desc *tail_desc; + int status, ret = -1; + + rx_curr_desc = emac_rx_active_head; + status = rx_curr_desc->pkt_flag_len; + if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if (status & EMAC_CPPI_RX_ERROR_FRAME) { + /* Error in packet - discard it and requeue desc */ + printf("WARN: emac_rcv_pkt: Error in packet\n"); + } else { + NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xffff)); + ret = rx_curr_desc->buff_off_len & 0xffff; + } + + /* Ack received packet descriptor */ + adap_emac->RX0CP = (unsigned int)rx_curr_desc; + curr_desc = rx_curr_desc; + emac_rx_active_head = (volatile emac_desc *)rx_curr_desc->next; + + if (status & EMAC_CPPI_EOQ_BIT) { + if (emac_rx_active_head) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + } else { + emac_rx_queue_active = 0; + printf("INFO:emac_rcv_packet: RX Queue not active\n"); + } + } + + /* Recycle RX descriptor */ + rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; + rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; + rx_curr_desc->next = 0; + + if (emac_rx_active_head == 0) { + printf("INFO: emac_rcv_pkt: active queue head = 0\n"); + emac_rx_active_head = curr_desc; + emac_rx_active_tail = curr_desc; + if (emac_rx_queue_active != 0) { + adap_emac->RX0HDP = (unsigned int)emac_rx_active_head; + printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); + emac_rx_queue_active = 1; + } + } else { + tail_desc = emac_rx_active_tail; + emac_rx_active_tail = curr_desc; + tail_desc->next = (unsigned int)curr_desc; + status = tail_desc->pkt_flag_len; + if (status & EMAC_CPPI_EOQ_BIT) { + adap_emac->RX0HDP = (unsigned int)curr_desc; + status &= ~EMAC_CPPI_EOQ_BIT; + tail_desc->pkt_flag_len = status; + } + } + return(ret); + } + return(0); +} + +#endif /* CONFIG_CMD_NET */ + +#endif /* CONFIG_DRIVER_DA8XX_EMAC */

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[U-Boot] [PATCH] avr32 portmux : fix incorrect port mask
by Mark Jackson 19 Oct '09

19 Oct '09

The portmux peripheral pin selection code used when setting up the MACB1 ethernet port has a small (but critical !!) typo. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- cpu/at32ap/at32ap700x/portmux.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/at32ap/at32ap700x/portmux.c b/cpu/at32ap/at32ap700x/portmux.c index b1f2c6f..a60288f 100644 --- a/cpu/at32ap/at32ap700x/portmux.c +++ b/cpu/at32ap/at32ap700x/portmux.c @@ -122,7 +122,7 @@ void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength) portd_mask |= (1 << 15);/* SPD */ /* REVISIT: Some pins are probably pure outputs */ - portmux_select_peripheral(PORTMUX_PORT_D, portc_mask, + portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);

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[U-Boot] Platform Flash XL
by moschos.kogimtzis＠stfc.ac.uk 19 Oct '09

19 Oct '09

Can U-boot support platform Flash XL memories? When we tried it, u-boot crashed just before reading the size of the memory. Platform Flash XL by default supports synchronous reads. The memory controller that drives it however supports asynchronous read (there is no clock output). So the platform flash XL need to be explicitly set to asynchronous reads. Can U-boot cope with that (perhaps by changing some parameters in a header file?) Best Regards Mos Kogimtzis -- Scanned by iCritical.

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