October 2009 - U-Boot

[U-Boot] My SPI driver not working in u-boot.
by sunr2007 22 Oct '09

22 Oct '09

Dear All Im tryin to write a SPI Driver in u-boot-1.3.4 with SPI BUS 1 support for my processor AT91SAM9261 . I have defined the base macro for SPI bus 1 AT91SAM9261_BASE_SPI1 in /asm/arch/hardware.h and i av passed the bus id and chip select id . but im not getting any data or clock value on the pins . can any body let me what stupid mistake im committing? below is my source if this is not correct way to post plz let me know right way! #include <common.h> #include <spi.h> #include <malloc.h> #include <asm/io.h> #include <asm/arch/hardware.h #include <asm/arch/at91_spi.h> #include "atmel_spi.h" void spi_init() { /* do some initialization of SPI bus pins*/ at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_NPCS01 */ at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI0_MISO */ at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI0_MOSI */ at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1); /* Reset the SPI */ //spi_writel(ATMEL_SPI_SWRST, ATMEL_SPI_CR,1); } struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct atmel_spi_slave *as; unsigned int scbr; u32 csrx; void *regs; max_hz=15000000;/* modified for AMOLED*/ mode=ATMEL_SPI_MR_MSTR; mode =0;/* falling edge of clock spi XFER*/ bus=AT91SAM9261_ID_SPI1; cs=AT91_PIN_PA25;/* chip select of the slave connected to . */ if (cs > 3 || !spi_cs_is_valid(bus, cs)) return NULL; regs = (void *)AT91SAM9261_BASE_SPI1; /* spi bus 1 ID of the */ /* Reset the SPI */ spi_writel(as,ATMEL_SPI_CR,ATMEL_SPI_SWRST); scbr = (AT91_MASTER_CLOCK/max_hz)<<8; /* configure serial clock baud rate*/ if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) /* Too low max SCK rate */ return NULL; if (scbr < 1) scbr = 1; csrx = ATMEL_SPI_CSRx_SCBR(scbr); csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); if (!(mode & SPI_CPHA)) csrx |= ATMEL_SPI_CSRx_NCPHA; if (mode & SPI_CPOL) csrx |= ATMEL_SPI_CSRx_CPOL; as = malloc(sizeof(struct atmel_spi_slave)); if (!as) return NULL; as->slave.bus = bus; as->slave.cs = cs; as->regs = regs; as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); as->mr = ATMEL_SPI_CSRx_NCPHA | ATMEL_SPI_CSR(2) | ATMEL_SPI_MR_MSTR ;/* configure chipselect*/ spi_writel(as, CSR(cs), csrx); return &as->slave; } void spi_free_slave(struct spi_slave *slave) { struct atmel_spi_slave *as = to_atmel_spi(slave); free(as); } int spi_claim_bus(struct spi_slave *slave) { struct atmel_spi_slave *as = to_atmel_spi(slave); /* Enable the SPI hardware */ spi_writel(as, CR, ATMEL_SPI_CR_SPIEN); /* * Select the slave. This should set SCK to the correct * initial state, etc. */ spi_writel(as, MR, as->mr); return 0; } void spi_release_bus(struct spi_slave *slave) { struct atmel_spi_slave *as = to_atmel_spi(slave); /* Disable the SPI hardware */ spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS); } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct atmel_spi_slave *as = to_atmel_spi(slave); unsigned int len_tx; unsigned int len_rx; unsigned int len; int ret; u32 status; unsigned short mask ; const u8 *txp = dout; u8 *rxp = din; u8 value; unsigned int pol; bitlen=8; ret = 0; if (bitlen == 0) /* Finish any previously submitted transfers */ goto out; /* * TODO: The controller can do non-multiple-of-8 bit * transfers, but this driver currently doesn't support it. * * It's also not clear how such transfers are supposed to be * represented as a stream of bytes...this is a limitation of * the current SPI interface. */ if (bitlen % 8) { /* Errors always terminate an ongoing transfer */ flags |= SPI_XFER_END; goto out; } len = bitlen / 8; /* * The controller can do automatic CS control, but it is * somewhat quirky, and it doesn't really buy us much anyway * in the context of U-Boot. */ if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); for (len_tx = 0, len_rx = 0; len_rx < len; ) { status = spi_readl(as, SR); if (status & ATMEL_SPI_SR_OVRES) return -1; if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) { if (txp) value = *txp++; else value = 0; udelay(500000); pol=spi_claim_bus(slave); spi_writel(as, TDR, value); /*write data into device */ spi_release_bus(slave) len_tx++; if (status & ATMEL_SPI_SR_RDRF) { value = spi_readl(as, RDR); if (rxp) *rxp++ = value; len_rx++; } } out: if (flags & SPI_XFER_END) { /* * Wait until the transfer is completely done before * we deactivate CS. */ do { status = spi_readl(as, SR); } while (!(status & ATMEL_SPI_SR_TXEMPTY)); //spi_writel(as,ATMEL_SPI_CSRx_CSAAT, value); spi_cs_deactivate(slave); } return 0; } -- View this message in context: http://www.nabble.com/My-SPI-driver-not-working-in-u-boot.-tp25998508p25998… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] Regarding NAND flash support in IMX31 and bootm in ubootv2
by R Arun Kumar 22 Oct '09

22 Oct '09

Hai, I have populated ST 64MB chip and found that the nand flash commands work for ST 64MB chip.But the same NAND flash drivers does not work for SAMSUNG flash , Any Help? Also one more issue is that the linux kernel boot is not seen after the "booting the kernel." , even though the kernel image works fine in old u-boot version 2009-08 Any help Please? Arun The log is ============================== ============================== U-Boot 2.0.0-rc9 (Oct 21 2009 - 09:35:47) Board: Phytec phyCORE-i.MX31 NAND device: Manufacturer ID: 0x20, Chip ID: 0x76 (ST Micro NAND 64MiB 3,3V 8-bi t) Scanning device for bad blocks got MAC address from EEPROM: 00:08:EE:01:7B:56 mx31 cpu clock: 513MHz ipg clock : 64133247Hz Malloc space: 0x80000000 -> 0x80400000 (size 4 MB) Stack space : 0x86000000 -> 0x86020000 (size 128 kB) Open /dev/env0 No such file or directory no valid environment found on /dev/env0. Using default environment running /env/bin/init... Hit any key to stop autoboot: 2 type update_kernel nand|nor [<imagename>] to update kernel into flash type update_root nand|nor [<imagename>] to update rootfs into flash uboot:/ devinfo devices: |----cs0 |----mem |----nor0 |----nand0 | |----nand0.kernel | | `----nand0.kernel.bb | `----nand0.root | | `----nand0.root.bb |----eth0 |----phy0 |----ram0 |----defaultenv |----filesystem: / |----filesystem: /dev drivers: imx_serial partition smc911x miiphy nand_device imx_nand cfi_flash mem ram rom nand_bb ramfs devfs uboot:/ update_kernel nand phy0: Link is up - 100/Full host 192.168.50.247 is alive protect: Function not implemented erasing partition /dev/nand0.kernel.bb flashing uImage to /dev/nand0.kernel.bb phy0: Link is up - 100/Full TFTP from server 192.168.50.247; our IP address is 192.168.50.182 Filename 'uImage'. Loading: ####################################T ############################# ################################################################# ################################################################# ################################################################# ################################################################# ############################### done Bytes transferred = 1822068 (1bcd74 hex) uboot:/bootm /dev/nand0.kernel.bb Verifying Checksum ... OK Image Name: Linux-2.6.24 Created: 2009-10-20 11:06:36 UTC Data Size: 1822004 Bytes = 1.7 MB Load Address: 80008000 Entry Point: 80008000 OK commandline: console=ttymxc0 arch_number: 1673 Starting kernel ... ## Transferring control to Linux (at address 80008000) ... Uncompressing Linux............................................................. ............................................................... done, booting the kernel. ==============================================================

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[U-Boot] [PATCH] Fix DM9000 MAC address handling
by Ben Warren 22 Oct '09

22 Oct '09

Proper behavior is to pull MAC address from NVRAM in the initialization() and stuff it in dev->address, then program the device from dev->address in the init() function. Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- drivers/net/dm9000x.c | 27 +++++++++++++++------------ 1 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index efe9135..d89488e 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -284,7 +284,6 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) int i, oft, lnk; u8 io_mode; struct board_info *db = &dm9000_info; - uchar enetaddr[6]; DM9000_DBG("%s\n", __func__); @@ -342,20 +341,11 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) /* Clear interrupt status */ DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); - /* Set Node address */ - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { -#if !defined(CONFIG_DM9000_NO_SROM) - for (i = 0; i < 3; i++) - dm9000_read_srom_word(i, enetaddr + 2 * i); - eth_setenv_enetaddr("ethaddr", enetaddr); -#endif - } - - printf("MAC: %pM\n", enetaddr); + printf("MAC: %pM\n", dev->enetaddr); /* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) - DM9000_iow(oft, enetaddr[i]); + DM9000_iow(oft, dev->enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); @@ -558,6 +548,16 @@ void dm9000_write_srom_word(int offset, u16 val) } #endif +void dm9000_get_enetaddr(struct eth_device *dev) +{ +#if !defined(CONFIG_DM9000_NO_SROM) + int i; + for (i = 0; i < 3; i++) { + dm9000_read_srom_word(i, dev->enetaddr + (2 * i)); + } +#endif +} + /* Read a byte from I/O port */ @@ -621,6 +621,9 @@ int dm9000_initialize(bd_t *bis) { struct eth_device *dev = &(dm9000_info.netdev); + /* Load MAC address from EEPROM */ + dm9000_get_enetaddr(dev); + dev->init = dm9000_init; dev->halt = dm9000_halt; dev->send = dm9000_send; -- 1.6.0.4

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[U-Boot] DM9000 issue in DM355
by Paulraj, Sandeep 22 Oct '09

22 Oct '09

Ben, I was taking a closer look at the DM9000 driver by trying it on the DM355 EVM. And it behaving a little different from before, i.e before we moved to the NET_MULTI stuff. When the board comes after I reflash with a new U-boot image, I no longer see the ethaddr being set. But when I do a tftp I can see the ethaddr being read. tftp complains and says no ethaddr set. So then I goto the U-Boot prompt and can clearly see that after giving the tftp command I have the ethaddr in my environment. I do a saveenv and set a static ip and then can boot the kernel. Even dhcp command does not work and times out. Is there any CONFIG flag I am missing? Just a couple months ago the DM9000 worked fine without any such issues. Thanks, Sandeep

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[U-Boot] Warning - delayed mail
by postmaster＠acn2.net 21 Oct '09

21 Oct '09

*************************************** ** This is a warning only ** ** No action is required by you ** *************************************** Re: Message to thaikl(a)pop.jaring.my Your message has not been delivered after 24 hours. Attempts to deliver your message will continue for a further 48 hours. If it has still not been delivered, it will be returned to you. The first few lines of your message are repeated below. The message headers follow: -

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[U-Boot] SD-Card boot from SPI SD-Card
by news.gmane.org 21 Oct '09

21 Oct '09

I have a Coldfire MCF5235 Board and I want to boot the uclinux direct from the sd-card connected to the spi-bus. Is that possible ? What do I have to configure ? Any driver to write ? Regards Wilfried

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[U-Boot] [PATCH] OneNAND partial read/write support
by Kyungmin Park 21 Oct '09

21 Oct '09

Now OneNAND handles block operation only. With this patch OneNAND handles all read/write size. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 9090940..2b8f01b 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -36,7 +36,7 @@ static inline int str2long(char *p, ulong *num) return (*p != '\0' && *endptr == '\0') ? 1 : 0; } -static int arg_off_size(int argc, char *argv[], ulong *off, size_t *size) +static int arg_off_size(int argc, char *argv[], ulong *off, ssize_t *size) { if (argc >= 1) { if (!(str2long(argv[0], off))) { @@ -69,61 +69,65 @@ static int arg_off_size(int argc, char *argv[], ulong *off, size_t *size) return 0; } -static int onenand_block_read(loff_t from, size_t len, - size_t *retlen, u_char *buf, int oob) +static int onenand_block_read(loff_t from, ssize_t len, + ssize_t *retlen, u_char *buf, int oob) { struct onenand_chip *this = mtd->priv; - int blocks = (int) len >> this->erase_shift; int blocksize = (1 << this->erase_shift); loff_t ofs = from; struct mtd_oob_ops ops = { .retlen = 0, }; + ssize_t thislen; int ret; - if (oob) - ops.ooblen = blocksize; - else - ops.len = blocksize; + while (len > 0) { + thislen = min_t(ssize_t, len, blocksize); + thislen = ALIGN(thislen, mtd->writesize); - while (blocks) { ret = mtd->block_isbad(mtd, ofs); if (ret) { printk("Bad blocks %d at 0x%x\n", (u32)(ofs >> this->erase_shift), (u32)ofs); - ofs += blocksize; + ofs += thislen; continue; } - if (oob) + if (oob) { ops.oobbuf = buf; - else + ops.ooblen = thislen; + } else { ops.datbuf = buf; + ops.len = thislen; + } ops.retlen = 0; ret = mtd->read_oob(mtd, ofs, &ops); if (ret) { printk("Read failed 0x%x, %d\n", (u32)ofs, ret); - ofs += blocksize; + ofs += thislen; continue; } - ofs += blocksize; - buf += blocksize; - blocks--; + ofs += thislen; + buf += thislen; + len -= thislen; *retlen += ops.retlen; } return 0; } -static int onenand_block_write(loff_t to, size_t len, - size_t *retlen, const u_char * buf) +static int onenand_block_write(loff_t to, ssize_t len, + ssize_t *retlen, const u_char * buf) { struct onenand_chip *this = mtd->priv; - int blocks = len >> this->erase_shift; int blocksize = (1 << this->erase_shift); + struct mtd_oob_ops ops = { + .retlen = 0, + .oobbuf = NULL, + }; loff_t ofs; - size_t _retlen = 0; + ssize_t thislen; int ret; if (to == next_ofs) { @@ -135,27 +139,34 @@ static int onenand_block_write(loff_t to, size_t len, } ofs = to; - while (blocks) { + while (len > 0) { + thislen = min_t(ssize_t, len, blocksize); + thislen = ALIGN(thislen, mtd->writesize); + ret = mtd->block_isbad(mtd, ofs); if (ret) { printk("Bad blocks %d at 0x%x\n", (u32)(ofs >> this->erase_shift), (u32)ofs); - skip_ofs += blocksize; + skip_ofs += thislen; goto next; } - ret = mtd->write(mtd, ofs, blocksize, &_retlen, buf); + + ops.datbuf = (u_char *) buf; + ops.len = thislen; + ops.retlen = 0; + ret = mtd->write_oob(mtd, ofs, &ops); if (ret) { printk("Write failed 0x%x, %d", (u32)ofs, ret); - skip_ofs += blocksize; + skip_ofs += thislen; goto next; } - buf += blocksize; - blocks--; - *retlen += _retlen; + buf += thislen; + len -= thislen; + *retlen += ops.retlen; next: - ofs += blocksize; + ofs += thislen; } return 0; @@ -234,7 +245,7 @@ static int onenand_block_test(u32 start, u32 size) end_block = mtd->size >> this->erase_shift; blocks = start_block; - ofs = start; + ofs = start_block << this->erase_shift; while (blocks < end_block) { printf("\rTesting block %d at 0x%x", (u32)(ofs >> this->erase_shift), (u32)ofs); @@ -265,9 +276,10 @@ static int onenand_block_test(u32 start, u32 size) goto next; } - if (memcmp(buf, verify_buf, blocksize)) + if (memcmp(buf, verify_buf, blocksize)) { printk("\nRead/Write test failed at 0x%x\n", (u32)ofs); - + break; + } next: ofs += blocksize; blocks++; @@ -322,6 +334,7 @@ static int onenand_dump(struct mtd_info *mtd, ulong off, int only_oob) p += 16; } puts("OOB:\n"); + p = oobbuf; i = mtd->oobsize >> 3; while (i--) { printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n", @@ -339,7 +352,7 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) struct onenand_chip *this; int blocksize; ulong addr, ofs; - size_t len, retlen = 0; + ssize_t len, retlen = 0; int ret = 0; char *cmd, *s; @@ -385,7 +398,8 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int erase; erase = strcmp(cmd, "erase") == 0; /* 1 = erase, 0 = test */ - printf("\nOneNAND %s: ", erase ? "erase" : "test"); + printf("\nOneNAND %s %s: ", erase ? "erase" : "test", + force ? "force" : ""); /* skip first two or three arguments, look for offset and size */ if (arg_off_size(argc - o, argv + o, &ofs, &len) != 0)

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Re: [U-Boot] [PATCH] Add mpc5125ads board and processor to the mpc512x family
by m stan 21 Oct '09

21 Oct '09

Hi Wolfgang, I had to chuckle when I read your opening paragraph – let me say that I have never thought of myself as a victim – even at the hands of these FSL silicon guys!!! But I did get a pretty raw deal – yes. Now I am going to respond a little before I go and resubmit. Very Best Regards, Martha >> diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h >> index 4b14778..b79c656 100644 >> --- a/cpu/mpc512x/asm-offsets.h >> +++ b/cpu/mpc512x/asm-offsets.h >> @@ -11,5 +11,11 @@ >> #define CS_CTRL 0x00020 >> #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ >> >> +/* needed for pin muxing in MPC5125 */ >> +#define IOCTRL_OFFSET 0xA000 >> +#define IOCTRL_LPC_AX03 0x09 >> +#define IOCTRL_I2C1_SCL 0x4f >> +#define IOCTRL_I2C1_SDA 0x50 >We should avoid adding stuff to asm-offsets.h; instead, we should >finally auto-generate this file from the respective C structs as it's >done in Linux. Do you dare to tackle this? > I can't do this any time soon Wolfgang … I work part-time now (post wedding issues to take care of). > > diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c >> index 673d61e..09985e7 100644 >> --- a/cpu/mpc512x/fixed_sdram.c >> +++ b/cpu/mpc512x/fixed_sdram.c >> @@ -36,6 +36,7 @@ u32 default_mddrc_config[4] = { >> }; >> >> u32 default_init_seq[] = { >> +#ifndef CONFIG_SYS_DDR_OVRIDE_DEF /* makes it unnecessary to declare these */ >> CONFIG_SYS_DDRCMD_NOP, >> CONFIG_SYS_DDRCMD_NOP, >> CONFIG_SYS_DDRCMD_NOP, >> @@ -67,6 +68,7 @@ u32 default_init_seq[] = { >> CONFIG_SYS_DDRCMD_OCD_DEFAULT, >> CONFIG_SYS_DDRCMD_PCHG_ALL, >> CONFIG_SYS_DDRCMD_NOP >> +#endif >> }; > NAK. Please don't add #ifdef's here. This is the default init > sequence, and if it does not fit your purposes, then please use a > private one. > Yes but the default has constants like CONFIG_SYS_MICRON_INIT_DEV_OP … must I then declare this if I am using CONFIG_SYS_ELPIDA_INIT_DEV_OP ? The default constants are a large mem array that just plain doesn't need to be there if you must override it anyway. I don't understand the impetus to save on printf strings, for example, and not wanting to save here ??? >>> /* Initialize IO Control */ >> +#ifdef CONFIG_MPC5125 >> + out_8(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); >> +#else >> out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); >> +#endif > This is something which happens a lot in the remaining code - so often > that it is plain unacceptable. As mentioned above, I know that you are > just a victim here, but we need a less ugly implementation. Actually – since I redid the entire iopin_initialize function to a separate one for the mpc5125 this is the only place where an ugly #ifdef'ed iopin init occurs now. > If I understand correctly, all MPC512x actually use 8 bit only here, > even though the register declarations on MPC5121/5123 are 32 bit > wide. Eventually we should do what Grant Likely already did in the > Linux kernel and change all thjis code to use 8 bit accesses only, > which means to add the needed padding to the respective data stricts > - similar to what was done to make the 16550 serial driver really > generic. > However, this is a pretty invasive operation, that will have to wait > for the next release in any case. And actually I would like to delay > this until at least an official Reference Manual for the MPC5125 has > been publicly released by Freescale. > As I said – since I redid the iopin_initialize (there are now 2 different functions) I don't think this is necessary … it's not just a size difference … there is also a bit configuration difference. I redid the #define for this too. Also .. the elements within the struct are all different. > > diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c >> index 4fc4693..89fa139 100644 >> --- a/cpu/mpc512x/serial.c >> +++ b/cpu/mpc512x/serial.c >> @@ -80,7 +80,7 @@ int serial_init(void) >> volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; >> >> fifo_init (psc); >> - >> +#ifndef CONFIG_MPC5125 >> /* set MR register to point to MR1 */ >> out_8(&psc->command, PSC_SEL_MODE_REG_1); >> >> @@ -93,12 +93,25 @@ int serial_init(void) >> /* switch to UART mode */ >> out_be32(&psc->sicr, 0); >> >> - /* mode register points to mr1 */ >> /* configure parity, bit length and so on in mode register 1*/ >> + /* mode register points to mr1 */ >> out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); >> /* now, mode register points to mr2 */ >> out_8(&psc->mode, PSC_MODE_1_STOPBIT); >> +#else >> + /* disable Tx/Rx */ >> + out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE); >> + >> + /* choose the prescaler the Tx/Rx clock generation */ >> + out_8(&psc->psc_clock_select, 0xdd); >> + >> + /* switch to UART mode */ >> + out_be32(&psc->sicr, 0); >> >> + /* configure parity, bit length and so on in mode registers */ >> + out_8(&psc->mr1, PSC_MODE_8_BITS | PSC_MODE_PARNONE); >> + out_8(&psc->mr2, PSC_MODE_1_STOPBIT); >> +#endif >> /* set baudrate */ >> serial_setbrg(); > I think we should move the differing code into separate functions. Fine – but I'll have to check the processor type to see which one to call at some point if I take out the ifdefs ??? > > diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c >> index fb2c19a..9f839a1 100644 >> --- a/drivers/net/mpc512x_fec.c >> +++ b/drivers/net/mpc512x_fec.c >> @@ -41,7 +41,12 @@ static int rx_buff_idx = 0; >> static void mpc512x_fec_phydump (char *devname) >> { >> u16 phyStatus, i; >> - u8 phyAddr = CONFIG_PHY_ADDR; >> +#ifdef CONFIG_MPC5125 >> + uint8 phyAddr = ((devname[3] == '2') ? CONFIG_PHY2_ADDR : >> + CONFIG_PHY_ADDR); >> +#else >> + uint8 phyAddr = CONFIG_PHY_ADDR; >> +#endif > Can we not do without this #ifdef here? I'm open to suggestions … there are possibly two active FECS and this seemed to be the best solution … The MPC5125 code will work for the MPC5121e so I suppose I could take out the ifdefs in lieu of doing this check each time. Are you against this extra check for non-5125 boards ? > > u8 reg_mask[] = { >> /* regs to print: 0...8, 21,27,31 */ >> 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, >> @@ -242,9 +247,17 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) >> /* Set Opcode/Pause Duration Register */ >> out_be32(&fec->eth->op_pause, 0x00010020); >> >> +#ifdef CONFIG_MPC5125 >> + /* RMII Mode */ >> + if (dev->name[3] == '2') >> + out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x124); >> + else >> + /* Frame length=1522; MII mode */ >> + out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24); >> +#else >> /* Frame length=1522; MII mode */ >> out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24); > > Ditto. There is a lot of code duplication here. How about something > similar to this: OK – will do > /* Frame length=1522; MII mode */ > val = (FEC_MAX_FRAME_LEN << 16) | 0x24; > if (dev->name[3] == '2') > val |= 0x100; /* RMII Mode */ > out_be32(&fec->eth->r_cntrl, val); > etc. > More simplifications like this should be applied elsewhere. Please > rework globally. > > - sprintf (dev->name, "FEC ETHERNET"); >> + if (cur_fec == &(im->fec)) >> + sprintf (dev->name, "FEC ETHERNET"); >> + else >> + sprintf (dev->name, "FEC2 ETHERNET"); >> + >Maybe > sprintf (dev->name, "FEC%s ETHERNET", > (cur_fec == &(im->fec)) ? "" : "2"); >or similar? > > +#ifdef CONFIG_MPC5125 >> + /* 2nd fec may not be in use */ >> + if (cur_fec == &(im->fec) && >> + (in_be32(&im->clk.sccr[0]) & CLOCK_SCCR1_FEC2_EN)) { >> + cur_fec = &(im->fec2); >> + goto fec_init_start; >> + } >> +#endif > > What do you mean by "2nd fec may not be in use"? > I will consolidate my printf strings .. yes. As far as the Clock on the 2nd FEC – I check it to see if it's ON – Only the 1st FEC is necessary in u-boot while the 2nd is optional. The board code – in my board's case – either has the DIU or a 2nd FEC and a 2nd USB .. I assume other boards may or may not use the 2nd fec. I am planning a README for the board to explain these things … Speaking of README … do you think one should be done for the CPU family now that this processor has changed things a little ? > > diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h >> index 79cdd80..1c1d235 100644 >> --- a/include/asm-ppc/immap_512x.h >> +++ b/include/asm-ppc/immap_512x.h >... >> +#ifndef CONFIG_MPC5125 >> /* >> - * PSC >> + * MPC5121 PSC >> + * note: MPC5121e register overloading is handled by unions with #defines to >> + * reference the reg seemlessly these #defines must not exist for MPC5125 code >> + * since it does not have this overloading. Since the register naming is the >> + * same as the MPC5125 Reference Manual and this naming is exactly the reg names >> + * used in the init code (which is nearly identical) it causes compile errors to >> + * leave in and must be #ifdef'ed out. It also helps to share code to have the >> + * same structure for both MPC5121 and MPC5125 >> */ > I disagree. To me the code becomes pretty much unreadable. I think we > need to find a better implementation for this. Look Wolfgang … It's very readable – with a 5121 type processor it's one struct and with a 5125 it's the other definition … I took out all the register by register #ifdefs and now there is only one... and it's very appropriate that it's like this considering the silicon differences. All the regs are the same names but in different places – the beauty of a struct hides this nicely. The same code works for both because all the Freescale guys did was to give the registers more room – Everything is functionally the same. > > @@ -1200,23 +1445,39 @@ typedef struct immap { >> fec512x_t fec; /* Fast Ethernet Controller */ >> ulpi512x_t ulpi; /* USB ULPI */ >> u8 res4[0xa00]; >> +#ifdef CONFIG_MPC5125 >> + ulpi512x_t ulpi2; /* USB ULPI */ >> + u8 res5[0x200]; >> + fec512x_t fec2; /* 2nd Fast Eth Controller */ >> + gpt512x_t gpt2; /* 2nd General Purpose Timer */ >> + sdhc512x_t sdhc2; /* 2nd SDHC */ >> + u8 res6[0x3e00]; >> + ddr512x_t mddrc; /* DDR Memory Controller */ >> + ioctrl5125_t io_ctrl; /* IO Control */ >> +#else >> utmi512x_t utmi; /* USB UTMI */ >> u8 res5[0x1000]; >> pcidma512x_t pci_dma; /* PCI DMA */ >> pciconf512x_t pci_conf; /* PCI Configuration */ >> u8 res6[0x80]; >> ios512x_t ios; /* PCI Sequencer */ >> - pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ >> + pcictrl512x_t pci_ctrl; /* PCI Controller Control */ >> u8 res7[0xa00]; >> ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ >> ioctrl512x_t io_ctrl; /* IO Control */ >> +#endif > Is there any reason for having identical entries (mddrc, io_ctrl) in > both branches? Whyno factor these out, too? They differ from the utmi/ulpi thru ioctrl .. I put the ioctrl in a different struct like you asked ,i.e. ioctrl5125_t > > +#ifdef CONFIG_MPC5125 >> + psc512x_t psc[10]; /* PSCs */ >> + u8 res10[0x500]; >> +#else >> psc512x_t psc[12]; /* PSCs */ >> u8 res10[0x300]; >> +#endif > This should be handled by #defining constants and without an #ifdef > here. > I disagree … I think I'd rather see these most basic Memory map differences … it's almost as good as reading the manual sometimes … And I think it would just obfuscate things esp when there are 2 constants -- the PSC array size and the reserve array size -- also -- none of the other reserve arrays in the memory map have constants. ... >> +#include <config_cmd_default.h> >> + >> +#define CONFIG_CMD_ASKENV >> +#define CONFIG_CMD_DHCP >> +#define CONFIG_CMD_MII >> +#define CONFIG_CMD_NFS >> +#define CONFIG_CMD_PING >> +#define CONFIG_CMD_REGINFO >> +#define CONFIG_CMD_FUSE >> + >> +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) >> +#define CONFIG_CMD_EEPROM >> +#define CONFIG_CMD_DATE >> +#define CONFIG_CMD_I2C >> +#endif > You may want to keep such lists sorted. > Will do

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[U-Boot] Got trap No.23 when booting mips32
by wilbur.chan 21 Oct '09

21 Oct '09

Hi all, I've got some problem when booting mips32 in kernel. I know this is uboot maillist , but I think people here may be more famililar with booting,so I post here for your help :D I got a No.23 trap when calling start_kernel ---> local_irq_enable : irq 23, desc: 802a98a0, depth: 1, count: 0, unhandled: 0 ->handle_irq(): 80148c6c, handle_bad_irq+0x0/0x2b4 ->chip(): 8029f738, 0x8029f738 ->action(): 00000000 IRQ_DISABLED set unexpected IRQ # 23 No.23 trap is a Watch trap, which means that, when "Physical address of load/store matched enabled value in WatchLo/ WatahHi registers."---<see mips sun> happened, a No.23 trap was triggered by cpu. So I used macro __u32 watch_regh0= read_c0_watchhi0(); __u32 watch_regl0= read_c0_watchlo0(); to retrieve value from WatchHi and WatchLo register, found them 0x1 and 0x0 respectively,which mean that ,'r' together with 'w' bits were set to zero and no trap should be triggered. But now , I got a 23 trap, why ? At last , I used to set WatchHi to 0x0, but failed , and found it still 0x1 after calling write_c0_watchhi0(0) Any suggestion would be grateful. regards

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[U-Boot] Micrel KS8995MA 5 port managed switch initialise
by Chris Alfred (Internode) 21 Oct '09

21 Oct '09

We have the MPC5200 MAC connected to the Micrel KS8995MA MII-SW port. The configuration pins of the 8995 are set to: SPI slave PS0=0 PS1=1 PHY mode MII SCONF0=1 SCONF1=0 SCONF2=0 The MII and SPI ports are working, checked with the uboot mii and sspi commands. However, ethernet transmit and receive do not appear to work. Looks like the switch is not configured correctly and does not pass any data. The manual initialisation sequence we are using is: sspi 0 24 020100 sspi 0 24 02024c sspi 0 24 020305 sspi 0 24 0204F1 sspi 0 24 020620 sspi 0 24 021061 sspi 0 24 022061 sspi 0 24 023061 sspi 0 24 024061 sspi 0 24 025061 sspi 0 24 025B18 sspi 0 24 0260FF sspi 0 24 0261FF sspi 0 24 0262FF sspi 0 24 0263FF sspi 0 24 0264FF sspi 0 24 0265FF sspi 0 24 0266FF sspi 0 24 0267FE sspi 0 24 020101 This was taken from the example: https://dev.openwrt.org/browser/trunk/package/spi-ks8995/src/spi_ks8995.c Does anyone have an example that works? Regards to all uboot-ers, Chris

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