October 2008 - U-Boot

[U-Boot-Users] [PATCH][resubmit] AX88180: new gigabit network driver
by Louis 20 Oct '08

20 Oct '08

Resubmit the driver for the ASIX AX88180 gigabit ethernet chip. Signed-off-by: Louis Su louis(a)asix.com.tw --- drivers/net/Makefile | 1 + drivers/net/ax88180.c | 842 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ax88180.h | 415 ++++++++++++++++++++++++ 3 files changed, 1258 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ax88180.c create mode 100644 drivers/net/ax88180.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 84be288..3a574e0 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o +COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c new file mode 100644 index 0000000..5579ef0 --- /dev/null +++ b/drivers/net/ax88180.c @@ -0,0 +1,842 @@ +/* ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ +/* + This program is free software; you can distribute it and/or modify + it under the terms of the GNU General Public License (Version 2) as + published by the Free Software Foundation. + This program is distributed in the hope it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, + USA. +*/ + +/* + ======================================================================== + ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver + + The AX88180 Ethernet controller is a high performance and highly + integrated local CPU bus Ethernet controller with embedded 40K bytes + SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any + embedded systems. + The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet + controller that supports both MII and RGMII interfaces and is + compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards. + + Please visit ASIX's web site (http://www.asix.com.tw) for more + details. + + Module Name : ax88180.c + Date : 2008-07-01 + History + 09/06/2006 : New release for AX88180 US2 chip. + 07/01/2008 : Fix up the coding style and using functions + instead of most macros + ======================================================================== +*/ +#include <common.h> +#include <command.h> +#include <net.h> + +#include "ax88180.h" + +#ifdef CONFIG_DRIVER_AX88180 + +/* +=========================================================================== +<<<<<< Local SubProgram Declaration >>>>>> +=========================================================================== +*/ +static void ax88180_rx_handler (void); +static int ax88180_PHY_initial (void); +static void ax88180_meida_config (void); +static unsigned long get_CicadaPHY_meida_mode (void); +static unsigned long get_MarvellPHY_meida_mode (void); +static unsigned short ax88180_mdio_read (unsigned long phyaddr, + unsigned long regaddr); +static void ax88180_mdio_write (unsigned long phyaddr, + unsigned long regaddr, + unsigned short regdata); + +/* +=========================================================================== +<<<<<< Declare Macro/Structure Definition >>>>>> +=========================================================================== +*/ +typedef enum _AX88180_LINK_STATE { + INS_LINK_DOWN, + INS_LINK_UP, + INS_LINK_UNKNOWN +} AX88180_LINK_STATE; + +typedef struct _AX88180_PRIVATE { + unsigned long PhyAddr; + unsigned long PhyID0; + unsigned long FirstTxDesc; + unsigned long NextTxDesc; + unsigned long rxbuf_overflow_count; + AX88180_LINK_STATE LinkState; +} AX88180_PRIVATE; + +AX88180_PRIVATE axlocal; + +#if (DEBUG_FLAGS & DEBUG_MSG) +static inline void ax88180_disp_all_reg (void) +{ + unsigned long tmpval; + int i; + PRINTK (DEBUG_MSG, "ax88180: AX88180 MAC Registers:\n"); + for (i = 0xFC00; i <= 0xFCFF; i += 4) { + READ_MACREG (i, tmpval); + PRINTK (DEBUG_MSG, "0x%04x=0x%08lx ", i, tmpval); + if ((i & 0xF) == 0xC) + PRINTK (DEBUG_MSG, "\n"); + } + PRINTK (DEBUG_MSG, "\n"); +} + +static inline void ax88180_disp_phy_reg (void) +{ + unsigned long tmpval; + tmpval = ax88180_mdio_read (axlocal.PhyAddr, BMCR); + PRINTK (DEBUG_MSG, "BMCR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + PRINTK (DEBUG_MSG, "BMSR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR0); + PRINTK (DEBUG_MSG, "PHYIDR0=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR1); + PRINTK (DEBUG_MSG, "PHYIDR1=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, ANAR); + PRINTK (DEBUG_MSG, "ANAR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, ANLPAR); + PRINTK (DEBUG_MSG, "ANLPAR=0x%04x \n", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, ANER); + PRINTK (DEBUG_MSG, "ANER=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, AUX_1000_CTRL); + PRINTK (DEBUG_MSG, "1G_CTRL=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, AUX_1000_STATUS); + PRINTK (DEBUG_MSG, "1G_STATUS=0x%04x \n", (unsigned int)tmpval); + if (axlocal.PhyID0 == MARVELL_88E1111_PHYIDR0) { + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_SSR); + PRINTK (DEBUG_MSG, "M88_SSR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_IER); + PRINTK (DEBUG_MSG, "M88_IER=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_ISR); + PRINTK (DEBUG_MSG, "M88_ISR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_EXT_SCR); + PRINTK (DEBUG_MSG, "M88_EXT_SCR=0x%04x ", + (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_EXT_SSR); + PRINTK (DEBUG_MSG, "M88_EXT_SSR=0x%04x \n", + (unsigned int)tmpval); + } else if (axlocal.PhyID0 == CICADA_CIS8201_PHYIDR0) { + tmpval = ax88180_mdio_read (axlocal.PhyAddr, CIS_IMR); + PRINTK (DEBUG_MSG, "CIS_IMR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, CIS_ISR); + PRINTK (DEBUG_MSG, "CIS_ISR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS); + PRINTK (DEBUG_MSG, "CIS_AUX=0x%04x \n", + (unsigned int)tmpval); + } + READ_MACREG (RXCFG, tmpval); + PRINTK (DEBUG_MSG, "RXCFG=0x%08lx ", tmpval); + READ_MACREG (MACCFG0, tmpval); + PRINTK (DEBUG_MSG, "MACCFG0=0x%08lx ", tmpval); + READ_MACREG (MACCFG1, tmpval); + PRINTK (DEBUG_MSG, "MACCFG1=0x%08lx ", tmpval); + READ_MACREG (MACCFG2, tmpval); + PRINTK (DEBUG_MSG, "MACCFG2=0x%08lx \n\n", tmpval); +} +#else +static inline void ax88180_disp_all_reg (void) {} +static inline void ax88180_disp_phy_reg (void) {} +#endif + +/* +=========================================================================== +<<<<<< Local SubProgram Bodies >>>>>> +=========================================================================== +*/ +static int +ax88180_mdio_check_complete (void) +{ + int us_cnt = 10000; + unsigned long tmpval; + + /* MDIO read/write should not take more than 10 ms */ + while (--us_cnt) { + READ_MACREG (MDIOCTRL, tmpval); + if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0)) + break; + } + + return us_cnt; +} + +static unsigned short +ax88180_mdio_read (unsigned long phyaddr, unsigned long regaddr) +{ + unsigned long tmpval = 0; + + WRITE_MACREG (MDIOCTRL, READ_PHY | (regaddr << 8) | phyaddr); + + if (ax88180_mdio_check_complete ()) + READ_MACREG (MDIODP, tmpval); + else + printf("Failed to read PHY register!\n"); + return (unsigned short)(tmpval & 0xFFFF); +} + +static void +ax88180_mdio_write (unsigned long phyaddr, unsigned long regaddr, + unsigned short regdata) +{ + WRITE_MACREG (MDIODP, regdata); + WRITE_MACREG (MDIOCTRL, WRITE_PHY | (regaddr << 8) | phyaddr); + + if(!ax88180_mdio_check_complete ()) + printf("Failed to write PHY register!\n"); +} + +static int ax88180_phy_reset (void) +{ + unsigned short delay_cnt = 500; + + ax88180_mdio_write (axlocal.PhyAddr, BMCR, PHY_RESET | AUTONEG_EN); + + /* Wait for the reset to complete, or time out (500 ms) */ + while (ax88180_mdio_read (axlocal.PhyAddr, BMCR) & PHY_RESET) { + udelay (1000); + if (--delay_cnt == 0) { + printf("Failed to reset PHY!\n"); + return -1; + } + } + + return 0; +} + +static void ax88180_mac_reset (void) +{ + unsigned long tmpval; + + WRITE_MACREG (MISC, MISC_RESET_MAC); + READ_MACREG (MISC, tmpval); + WRITE_MACREG (MISC, MISC_NORMAL); + WRITE_MACREG (RXINDICATOR, DEFAULT_RXINDICATOR); + WRITE_MACREG (TXCMD, DEFAULT_TXCMD); + WRITE_MACREG (TXBS, DEFAULT_TXBS); + WRITE_MACREG (TXDES0, DEFAULT_TXDES0); + WRITE_MACREG (TXDES1, DEFAULT_TXDES1); + WRITE_MACREG (TXDES2, DEFAULT_TXDES2); + WRITE_MACREG (TXDES3, DEFAULT_TXDES3); + WRITE_MACREG (TXCFG, DEFAULT_TXCFG); + WRITE_MACREG (MACCFG2, DEFAULT_MACCFG2); + WRITE_MACREG (MACCFG3, DEFAULT_MACCFG3); + WRITE_MACREG (TXLEN, DEFAULT_TXLEN); + WRITE_MACREG (RXBTHD0, DEFAULT_RXBTHD0); + WRITE_MACREG (RXBTHD1, DEFAULT_RXBTHD1); + WRITE_MACREG (RXFULTHD, DEFAULT_RXFULTHD); + WRITE_MACREG (DOGTHD0, DEFAULT_DOGTHD0); + WRITE_MACREG (DOGTHD1, DEFAULT_DOGTHD1); +} + +static int ax88180_poll_tx_complete (void) +{ + unsigned long tmp_data, txbs_txdp; + int TimeOutCnt = 10000; + + txbs_txdp = 1 << axlocal.NextTxDesc; + + while (TimeOutCnt--) { + + READ_MACREG (TXBS, tmp_data); + if ((tmp_data & txbs_txdp) == 0) + break; + + udelay (100); + } + + if (TimeOutCnt) + return 0; + else + return -TimeOutCnt; +} + +static void ax88180_rx_handler (void) +{ + unsigned char *rxdata; + unsigned long tmp_data; + unsigned long rx_packet_len; + unsigned int data_size; + unsigned int dword_count, byte_count; + unsigned long rxcurt_ptr, rxbound_ptr, next_ptr; + int i; + int j; + + READ_MACREG (RXCURT, rxcurt_ptr); + READ_MACREG (RXBOUND, rxbound_ptr); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + PRINTK (RX_MSG, "ax88180: RX original RXBOUND=0x%08lx," + " RXCURT=0x%08lx\n", rxbound_ptr, rxcurt_ptr); + + while (next_ptr != rxcurt_ptr) { + WRITE_MACREG (RXINDICATOR, RX_START_READ); + READ_RXBUF (rx_packet_len); + if ((rx_packet_len == 0) || (rx_packet_len > MAX_RX_SIZE)) { + WRITE_MACREG (RXINDICATOR, RX_STOP_READ); + ax88180_mac_reset (); + printf ("ax88180: Invalid Rx packet length!" + " (len=0x%08lx)\n", rx_packet_len); + + printf ("ax88180: RX RXBOUND=0x%08lx," + "RXCURT=0x%08lx\n", rxbound_ptr, rxcurt_ptr); + return; + } + data_size = (unsigned int)rx_packet_len; + rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1; + rxbound_ptr &= RX_PAGE_NUM_MASK; + + rxdata = (unsigned char *)NetRxPackets[0]; + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + dword_count = data_size >> 1; + byte_count = data_size & 0x1; +#else + dword_count = data_size >> 2; + byte_count = data_size & 0x3; +#endif + for (i = 0; i < dword_count; i++) { + READ_RXBUF (tmp_data); +#if defined (CONFIG_DRIVER_AX88180_16BIT) + *((unsigned short *)rxdata + i) = tmp_data; +#else + *((unsigned long *)rxdata + i) = tmp_data; +#endif + } + if (byte_count != 0) { + READ_RXBUF (tmp_data); + for (j = 0; j < byte_count; j++) { + *(rxdata + (dword_count * 4) + j) = + (unsigned char)(tmp_data >> (j * 8)); + } + } + + WRITE_MACREG (RXINDICATOR, RX_STOP_READ); + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], data_size); + + WRITE_MACREG (RXBOUND, rxbound_ptr); + + READ_MACREG (RXCURT, rxcurt_ptr); + READ_MACREG (RXBOUND, rxbound_ptr); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + PRINTK (RX_MSG, "ax88180: RX updated RXBOUND=0x%08lx," + "RXCURT=0x%08lx\n", rxbound_ptr, rxcurt_ptr); + } + + if (axlocal.rxbuf_overflow_count > 0) + axlocal.rxbuf_overflow_count--; + + return; +} + +static int ax88180_PHY_initial (void) +{ + unsigned long tmp_regval; + int i; + int ret; + + /* Check avaliable PHY chipset */ + axlocal.PhyAddr = MARVELL_88E1111_PHYADDR; + axlocal.PhyID0 = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR0); + + if (axlocal.PhyID0 == MARVELL_88E1111_PHYIDR0) { + PRINTK (DEBUG_MSG, "ax88180: Found Marvell 88E1111 PHY." + " (PHY Addr=0x%lx)\n", axlocal.PhyAddr); + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, M88_EXT_SSR); + if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) { + ax88180_mdio_write (axlocal.PhyAddr, M88_EXT_SCR, + DEFAULT_EXT_SCR); + if ((ret = ax88180_phy_reset ()) < 0) + return ret; + ax88180_mdio_write (axlocal.PhyAddr, M88_IER, + LINK_CHANGE_INT); + } + } else { + axlocal.PhyAddr = CICADA_CIS8201_PHYADDR; + axlocal.PhyID0 = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR0); + if (axlocal.PhyID0 == CICADA_CIS8201_PHYIDR0) { + PRINTK (DEBUG_MSG, "ax88180: Found CICADA CIS8201 PHY" + " chipset. (PHY Addr=0x%lx)\n", + axlocal.PhyAddr); + ax88180_mdio_write (axlocal.PhyAddr, CIS_IMR, + (CIS_INT_ENABLE | LINK_CHANGE_INT)); + + /* + Set CIS_SMI_PRIORITY bit before force the media mode + */ + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS); + tmp_regval &= ~CIS_SMI_PRIORITY; + ax88180_mdio_write (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS, tmp_regval); + } else { + printf ("ax88180: Unknown PHY chipset!!\n"); + return -1; + } + } + + /* Waiting for auto-negotiation complete. */ + /* This may take up to 5 seconds */ + PRINTK (DEBUG_MSG, + "ax88180: Waiting for auto-negotiation completion......\n"); + for (i = 0; i < 5000; i++) { + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + if (tmp_regval & AUTONEG_COMPLETE) { + break; + } + udelay (1000); + } + + return 0; +} + +static void ax88180_meida_config (void) +{ + unsigned long bmcr_val, bmsr_val; + unsigned long rxcfg_val, maccfg0_val, maccfg1_val; + unsigned long RealMediaMode; + int i; + + /* Waiting 200 msecs for PHY link stable */ + for (i = 0; i < 200; i++) { + bmsr_val = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + if (bmsr_val & LINKOK) { + break; + } + udelay (1000); + } + + bmsr_val = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + PRINTK (DEBUG_MSG, "ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val); + + if (bmsr_val & LINKOK) { + bmcr_val = ax88180_mdio_read (axlocal.PhyAddr, BMCR); + if (bmcr_val & AUTONEG_EN) { + /* Waiting for Auto-negotiation completion */ + /* This may take up to 5 seconds */ + PRINTK (DEBUG_MSG, "ax88180: Auto-negotiation is " + "enabled. Waiting for NWay completion..\n"); + for (i = 0; i < 5000; i++) { + bmsr_val = ax88180_mdio_read (axlocal.PhyAddr, + BMSR); + if (bmsr_val & AUTONEG_COMPLETE) { + break; + } + udelay (1000); + } + } else + PRINTK (DEBUG_MSG, + "ax88180: Auto-negotiation is disabled.\n"); + + PRINTK (DEBUG_MSG, "ax88180: BMCR=0x%04x, BMSR=0x%04x\n", + (unsigned int)bmcr_val, (unsigned int)bmsr_val); + + /* Get real media mode here */ + if (axlocal.PhyID0 == MARVELL_88E1111_PHYIDR0) { + RealMediaMode = get_MarvellPHY_meida_mode (); + } else if (axlocal.PhyID0 == CICADA_CIS8201_PHYIDR0) { + RealMediaMode = get_CicadaPHY_meida_mode (); + } else { + RealMediaMode = MEDIA_1000FULL; + } + + switch (RealMediaMode) { + default: + case MEDIA_1000FULL: + PRINTK (DEBUG_MSG, + "ax88180: 1000Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | RXFLOW_EN | + FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_1000HALF: + PRINTK (DEBUG_MSG, + "ax88180: 1000Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1; + break; + + case MEDIA_100FULL: + PRINTK (DEBUG_MSG, + "ax88180: 100Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = SPEED100 | TXFLOW_ENABLE + | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX + | DEFAULT_MACCFG1; + break; + + case MEDIA_100HALF: + PRINTK (DEBUG_MSG, + "ax88180: 100Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = SPEED100 | DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + + case MEDIA_10FULL: + PRINTK (DEBUG_MSG, + "ax88180: 10Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX + | DEFAULT_MACCFG1; + break; + + case MEDIA_10HALF: + PRINTK (DEBUG_MSG, + "ax88180: 10Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + } + + axlocal.LinkState = INS_LINK_UP; + } else { + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + + axlocal.LinkState = INS_LINK_DOWN; + } + + WRITE_MACREG (RXCFG, rxcfg_val); + WRITE_MACREG (MACCFG0, maccfg0_val); + WRITE_MACREG (MACCFG1, maccfg1_val); + + return; +} + +static unsigned long +get_MarvellPHY_meida_mode (void) +{ + unsigned long m88_ssr; + unsigned long MediaMode; + + m88_ssr = ax88180_mdio_read (axlocal.PhyAddr, M88_SSR); + switch (m88_ssr & SSR_MEDIA_MASK) { + default: + case SSR_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case SSR_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case SSR_100FULL: + MediaMode = MEDIA_100FULL; + break; + case SSR_100HALF: + MediaMode = MEDIA_100HALF; + break; + case SSR_10FULL: + MediaMode = MEDIA_10FULL; + break; + case SSR_10HALF: + MediaMode = MEDIA_10HALF; + break; + } + + return MediaMode; +} + +static unsigned long +get_CicadaPHY_meida_mode (void) +{ + unsigned long tmp_regval; + unsigned long MediaMode; + + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS); + switch (tmp_regval & CIS_MEDIA_MASK) { + default: + case CIS_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case CIS_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case CIS_100FULL: + MediaMode = MEDIA_100FULL; + break; + case CIS_100HALF: + MediaMode = MEDIA_100HALF; + break; + case CIS_10FULL: + MediaMode = MEDIA_10FULL; + break; + case CIS_10HALF: + MediaMode = MEDIA_10HALF; + break; + } + + return MediaMode; +} + +/* +=========================================================================== +<<<<<< Exported SubProgram Bodies >>>>>> +=========================================================================== +*/ +void eth_halt (void) +{ + /* Disable AX88180 TX/RX functions */ + WRITE_MACREG (CMD, WAKEMOD); +} + +int eth_init (bd_t *bd) +{ + unsigned long tmp_regval; + unsigned long macid0_val, macid1_val, macid2_val; + int ret, i; + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + *((volatile unsigned short *)(AX88180_BASE + 6)) = (START_BASE >> 8); + *((volatile unsigned short *)AX88180_BASE ) = 1; +#endif + memset (&axlocal, 0, sizeof (AX88180_PRIVATE)); + + ax88180_mac_reset (); + + /* Disable AX88180 interrupt */ + WRITE_MACREG (IMR, CLEAR_IMR); + + /* Disable AX88180 TX/RX functions */ + WRITE_MACREG (CMD, WAKEMOD); + + axlocal.LinkState = INS_LINK_UNKNOWN; + + /* Initial PHY registers */ + if ((ret = ax88180_PHY_initial ()) < 0) + return ret; + ax88180_meida_config (); + + /* Reload MAC address from EEPROM */ + WRITE_MACREG (PROMCTRL, RELOAD_EEPROM); + + /* Waiting for reload eeprom completion */ + for (i = 0; i < 500; i++) { + READ_MACREG (PROMCTRL, tmp_regval); + if ((tmp_regval & RELOAD_EEPROM) == 0) + break; + udelay (1000); + } + + /* Get MAC addresses */ + READ_MACREG (MACID0, macid0_val); + READ_MACREG (MACID1, macid1_val); + READ_MACREG (MACID2, macid2_val); + + bd->bi_enetaddr[0] = (unsigned char)macid0_val; + bd->bi_enetaddr[1] = (unsigned char)(macid0_val >> 8); + bd->bi_enetaddr[2] = (unsigned char)macid1_val; + bd->bi_enetaddr[3] = (unsigned char)(macid1_val >> 8); + bd->bi_enetaddr[4] = (unsigned char)macid2_val; + bd->bi_enetaddr[5] = (unsigned char)(macid2_val >> 8); + + if (((macid0_val | macid1_val | macid2_val) == 0) || + (bd->bi_enetaddr[0] & 0x01)) { + /* try to get MAC address from environment */ + u8 i; + char *s, *e; + unsigned short tmp16; + + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? + simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + tmp16 = bd->bi_enetaddr[1]; + macid0_val = (tmp16 << 8) | bd->bi_enetaddr[0]; + tmp16 = bd->bi_enetaddr[3]; + macid1_val = (tmp16 << 8) | bd->bi_enetaddr[2]; + tmp16 = bd->bi_enetaddr[5]; + macid2_val = (tmp16 << 8) | bd->bi_enetaddr[4]; + + WRITE_MACREG (MACID0, macid0_val); + WRITE_MACREG (MACID1, macid1_val); + WRITE_MACREG (MACID2, macid2_val); + } + + WRITE_MACREG (RXFILTER, DEFAULT_RXFILTER); + + /* Initial variables here */ + axlocal.FirstTxDesc = TXDP0; + axlocal.NextTxDesc = TXDP0; + axlocal.rxbuf_overflow_count = 0; + + ax88180_disp_all_reg (); + + /* Check if there is any invalid interrupt status. If yes, clear it. */ + READ_MACREG (ISR, tmp_regval); + PRINTK (DEBUG_MSG, "ax88180: The interrupt status = 0x%08lx\n", + tmp_regval); + if (tmp_regval) + WRITE_MACREG (ISR, tmp_regval); + + /* Start AX88180 TX/RX functions */ + WRITE_MACREG (CMD, RXEN | TXEN | WAKEMOD); + + return 0; +} + +/* Get a data block via Ethernet */ +int eth_rx (void) +{ + unsigned long ISR_Status; + unsigned long rxcurt_ptr, rxbound_ptr; + unsigned long tmp_regval; + + /* Read and check interrupt status here...... */ + READ_MACREG (ISR, ISR_Status); + + while (ISR_Status) { + /* Clear the interrupt status */ + WRITE_MACREG (ISR, ISR_Status); + + PRINTK (INT_MSG, + "\nax88180: The interrupt status = 0x%08lx\n", + ISR_Status); + + if (ISR_Status & ISR_PHY) { + /* Read ISR register once to clear PHY interrupt bit */ + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, + M88_ISR); + ax88180_meida_config (); + ax88180_disp_phy_reg (); + } + + if (ISR_Status & ISR_RXBUFFOVR) { + axlocal.rxbuf_overflow_count++; + READ_MACREG (RXCURT, rxcurt_ptr); + READ_MACREG (RXBOUND, rxbound_ptr); + PRINTK (INT_MSG, "ax88180: RX Buffer overflow! " + "count=%d, RXBOUND=0x%08lx, RXCURT=0x%08lx\n", + (int)axlocal.rxbuf_overflow_count, rxbound_ptr, + rxcurt_ptr); + + if (axlocal.rxbuf_overflow_count > 10) { + ax88180_mac_reset (); + axlocal.FirstTxDesc = TXDP0; + axlocal.NextTxDesc = TXDP0; + axlocal.rxbuf_overflow_count = 0; + } + } + + if (ISR_Status & ISR_RX) { + ax88180_rx_handler (); + } + + /* Read and check interrupt status here...... */ + READ_MACREG (ISR, ISR_Status); + } + + return 0; +} + +/* Send a data block via Ethernet. */ +int eth_send (volatile void *packet, int length) +{ + volatile unsigned char *txdata; + unsigned long TXDES_addr; + unsigned long txcmd_txdp, txbs_txdp; + unsigned long tmp_data; + int i; + + if (axlocal.LinkState != INS_LINK_UP) { + return 0; + } + + txdata = (volatile unsigned char *)packet; + + axlocal.FirstTxDesc = axlocal.NextTxDesc; + txbs_txdp = 1 << axlocal.FirstTxDesc; + + READ_MACREG (TXBS, tmp_data); + READ_MACREG (TXBS, tmp_data); + PRINTK (TX_MSG, "ax88180: Checking available TXDP (TXBS=0x%08lx)\n", + tmp_data); + + /* check the available transmit descriptor */ + if (tmp_data & txbs_txdp) { + /* we should never get here. */ + /* we are running out of resource */ + return 0; + } + + PRINTK (TX_MSG, "ax88180: TXDP%d is available, i=%d\n", + (int)axlocal.FirstTxDesc, i); + + txcmd_txdp = axlocal.FirstTxDesc << 13; + TXDES_addr = TXDES0 + (axlocal.FirstTxDesc << 2); + + WRITE_MACREG (TXCMD, txcmd_txdp | length | TX_START_WRITE); + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + for (i = 0; i < length; i += 2) { + tmp_data = + (unsigned short)*(txdata + i) + + (unsigned short)(*(txdata + i + 1) << 8); + WRITE_TXBUF (tmp_data); + } +#else + for (i = 0; i < length; i += 4) { + tmp_data = + (unsigned long)*(txdata + i) + + (unsigned long)(*(txdata + i + 1) << 8) + + (unsigned long)(*(txdata + i + 2) << 16) + + (unsigned long)(*(txdata + i + 3) << 24); + WRITE_TXBUF (tmp_data); + } +#endif + + WRITE_MACREG (TXCMD, txcmd_txdp | length); + WRITE_MACREG (TXBS, txbs_txdp); + WRITE_MACREG (TXDES_addr, TXDPx_ENABLE | length); + + axlocal.NextTxDesc = (axlocal.NextTxDesc + 1) & TXDP_MASK; + + /* + Check the available transmit descriptor, if we had exhausted all + transmit descriptor ,then we have to wait for at least one free + descriptor + */ + txbs_txdp = 1 << axlocal.NextTxDesc; + READ_MACREG (TXBS, tmp_data); + if (tmp_data & txbs_txdp) { + if (ax88180_poll_tx_complete () < 0) { + ax88180_mac_reset (); + axlocal.FirstTxDesc = TXDP0; + axlocal.NextTxDesc = TXDP0; + printf ("ax88180: Transmit time out occurred!\n"); + } + } + + return 0; +} +#endif /* CONFIG_DRIVER_AX88180 */ + diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h new file mode 100644 index 0000000..ae4b1b3 --- /dev/null +++ b/drivers/net/ax88180.h @@ -0,0 +1,415 @@ +/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ +/* + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include <asm/types.h> +#include <config.h> + +#ifdef CONFIG_DRIVER_AX88180 + +#define ENABLE_JUMBO 1 +#define DISABLE_JUMBO 0 + +#define ENABLE_BURST 1 +#define DISABLE_BURST 0 + +#define NORMAL_RX_MODE 0 +#define RX_LOOPBACK_MODE 1 +#define RX_INIFINIT_LOOP_MODE 2 +#define TX_INIFINIT_LOOP_MODE 3 + +#define DEFAULT_ETH_MTU 1500 + +/* Jumbo packet size 4086 bytes included 4 bytes CRC*/ +#define MAX_JUMBO_MTU 4072 + +/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */ +#define MAX_TX_JUMBO_SIZE 4086 + +/* Max Rx Jumbo size is 15K Bytes */ +#define MAX_RX_SIZE 0x3C00 + +#define MARVELL_88E1111_PHYADDR 0x18 +#define MARVELL_88E1111_PHYIDR0 0x0141 + +#define CICADA_CIS8201_PHYADDR 0x01 +#define CICADA_CIS8201_PHYIDR0 0x000F + +#define MEDIA_AUTO 0 +#define MEDIA_1000FULL 1 +#define MEDIA_1000HALF 2 +#define MEDIA_100FULL 3 +#define MEDIA_100HALF 4 +#define MEDIA_10FULL 5 +#define MEDIA_10HALF 6 + +#define AUTO_MEDIA 0 +#define FORCE_MEDIA 1 + +#define TXDP_MASK 3 +#define TXDP0 0 +#define TXDP1 1 +#define TXDP2 2 +#define TXDP3 3 + +#define CMD_MAP_SIZE 0x100 + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + #define AX88180_MEMORY_SIZE 0x00004000 + #define START_BASE 0x1000 + + #define RX_BUF_SIZE 0x1000 + #define TX_BUF_SIZE 0x0F00 + + #define TX_BASE START_BASE + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) + #define RX_BASE (CMD_BASE + CMD_MAP_SIZE) +#else + #define AX88180_MEMORY_SIZE 0x00010000 + + #define RX_BUF_SIZE 0x8000 + #define TX_BUF_SIZE 0x7C00 + + #define RX_BASE 0x0000 + #define TX_BASE (RX_BASE + RX_BUF_SIZE) + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) +#endif + +/* AX88180 Memory Mapping Definition */ +#define RXBUFFER_START RX_BASE + #define RX_PACKET_LEN_OFFSET 0 + #define RX_PAGE_NUM_MASK 0x7FF //RX pages 0~7FFh +#define TXBUFFER_START TX_BASE + +/* AX88180 MAC Register Definition */ +#define CMD (CMD_BASE + 0x0000) + #define WAKEMOD 0x00000001 + #define TXEN 0x00000100 + #define RXEN 0x00000200 + #define DEFAULT_CMD WAKEMOD +#define IMR (CMD_BASE + 0x0004) + #define IMR_RXBUFFOVR 0x00000001 + #define IMR_WATCHDOG 0x00000002 + #define IMR_TX 0x00000008 + #define IMR_RX 0x00000010 + #define IMR_PHY 0x00000020 + #define CLEAR_IMR 0x00000000 + #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\ + IMR_RXBUFFOVR | IMR_WATCHDOG) +#define ISR (CMD_BASE + 0x0008) + #define ISR_RXBUFFOVR 0x00000001 + #define ISR_WATCHDOG 0x00000002 + #define ISR_TX 0x00000008 + #define ISR_RX 0x00000010 + #define ISR_PHY 0x00000020 +#define TXCFG (CMD_BASE + 0x0010) + #define AUTOPAD_CRC 0x00000050 + #define DEFAULT_TXCFG AUTOPAD_CRC +#define TXCMD (CMD_BASE + 0x0014) + #define TXCMD_TXDP_MASK 0x00006000 + #define TXCMD_TXDP0 0x00000000 + #define TXCMD_TXDP1 0x00002000 + #define TXCMD_TXDP2 0x00004000 + #define TXCMD_TXDP3 0x00006000 + #define TX_START_WRITE 0x00008000 + #define TX_STOP_WRITE 0x00000000 + #define DEFAULT_TXCMD 0x00000000 +#define TXBS (CMD_BASE + 0x0018) + #define TXDP0_USED 0x00000001 + #define TXDP1_USED 0x00000002 + #define TXDP2_USED 0x00000004 + #define TXDP3_USED 0x00000008 + #define DEFAULT_TXBS 0x00000000 +#define TXDES0 (CMD_BASE + 0x0020) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES0 0x00000000 +#define TXDES1 (CMD_BASE + 0x0024) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES1 0x00000000 +#define TXDES2 (CMD_BASE + 0x0028) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES2 0x00000000 +#define TXDES3 (CMD_BASE + 0x002C) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES3 0x00000000 +#define RXCFG (CMD_BASE + 0x0030) + #define RXBUFF_PROTECT 0x00000001 + #define RXTCPCRC_CHECK 0x00000010 + #define RXFLOW_ENABLE 0x00000100 + #define DEFAULT_RXCFG RXBUFF_PROTECT +#define RXCURT (CMD_BASE + 0x0034) + #define DEFAULT_RXCURT 0x00000000 +#define RXBOUND (CMD_BASE + 0x0038) + #define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh +#define MACCFG0 (CMD_BASE + 0x0040) + #define MACCFG0_BIT3_0 0x00000007 + #define IPGT_VAL 0x00000150 + #define TXFLOW_ENABLE 0x00001000 + #define SPEED100 0x00008000 + #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0) +#define MACCFG1 (CMD_BASE + 0x0044) + #define RGMII_EN 0x00000002 + #define RXFLOW_EN 0x00000020 + #define FULLDUPLEX 0x00000040 + #define MAX_JUMBO_LEN_MASK 0x00000780 + #define RXJUMBO_EN 0x00000800 + #define GIGA_MODE_EN 0x00001000 + #define RXCRC_CHECK 0x00002000 + #define RXPAUSE_DA_CHECK 0x00004000 + + #define JUMBO_LEN_4K 0x00000200 + #define JUMBO_LEN_15K 0x00000780 + #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK |\ + RGMII_EN) + #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK) +#define MACCFG2 (CMD_BASE + 0x0048) + #define MACCFG2_BIT15_8 0x00000100 + #define JAM_LIMIT_MASK 0x000000FC + #define DEFAULT_JAM_LIMIT 0x00000064 + #define DEFAULT_MACCFG2 MACCFG2_BIT15_8 +#define MACCFG3 (CMD_BASE + 0x004C) + #define IPGR2_VAL 0x0000000E + #define IPGR1_VAL 0x00000600 + #define NOABORT 0x00008000 + #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL) +#define TXPAUT (CMD_BASE + 0x0054) + #define DEFAULT_TXPAUT 0x001FE000 +#define RXBTHD0 (CMD_BASE + 0x0058) + #define DEFAULT_RXBTHD0 0x00000300 +#define RXBTHD1 (CMD_BASE + 0x005C) + #define DEFAULT_RXBTHD1 0x00000600 +#define RXFULTHD (CMD_BASE + 0x0060) + #define DEFAULT_RXFULTHD 0x00000100 +#define MISC (CMD_BASE + 0x0068) + /* Normal operation mode */ + #define MISC_NORMAL 0x00000003 + /* Clear bit 0 to reset MAC */ + #define MISC_RESET_MAC 0x00000002 + /* Clear bit 1 to reset PHY */ + #define MISC_RESET_PHY 0x00000001 + /* Clear bit 0 and 1 to reset MAC and PHY */ + #define MISC_RESET_MAC_PHY 0x00000000 + #define DEFAULT_MISC MISC_NORMAL +#define MACID0 (CMD_BASE + 0x0070) +#define MACID1 (CMD_BASE + 0x0074) +#define MACID2 (CMD_BASE + 0x0078) +#define TXLEN (CMD_BASE + 0x007C) + #define DEFAULT_TXLEN 0x000005FC +#define RXFILTER (CMD_BASE + 0x0080) + #define RX_RXANY 0x00000001 + #define RX_MULTICAST 0x00000002 + #define RX_UNICAST 0x00000004 + #define RX_BROADCAST 0x00000008 + #define RX_MULTI_HASH 0x00000010 + #define DISABLE_RXFILTER 0x00000000 + #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST) +#define MDIOCTRL (CMD_BASE + 0x0084) + #define PHY_ADDR_MASK 0x0000001F + #define REG_ADDR_MASK 0x00001F00 + #define READ_PHY 0x00004000 + #define WRITE_PHY 0x00008000 +#define MDIODP (CMD_BASE + 0x0088) +#define GPIOCTRL (CMD_BASE + 0x008C) +#define RXINDICATOR (CMD_BASE + 0x0090) + #define RX_START_READ 0x00000001 + #define RX_STOP_READ 0x00000000 + #define DEFAULT_RXINDICATOR RX_STOP_READ +#define TXST (CMD_BASE + 0x0094) +#define MDCCLKPAT (CMD_BASE + 0x00A0) +#define RXIPCRCCNT (CMD_BASE + 0x00A4) +#define RXCRCCNT (CMD_BASE + 0x00A8) +#define TXFAILCNT (CMD_BASE + 0x00AC) +#define PROMDP (CMD_BASE + 0x00B0) +#define PROMCTRL (CMD_BASE + 0x00B4) + #define RELOAD_EEPROM 0x00000200 +#define MAXRXLEN (CMD_BASE + 0x00B8) +#define HASHTAB0 (CMD_BASE + 0x00C0) +#define HASHTAB1 (CMD_BASE + 0x00C4) +#define HASHTAB2 (CMD_BASE + 0x00C8) +#define HASHTAB3 (CMD_BASE + 0x00CC) +#define DOGTHD0 (CMD_BASE + 0x00E0) + #define DEFAULT_DOGTHD0 0x0000FFFF +#define DOGTHD1 (CMD_BASE + 0x00E4) + #define START_WATCHDOG_TIMER 0x00008000 + #define DEFAULT_DOGTHD1 0x00000FFF +#define SOFTRST (CMD_BASE + 0x00EC) + #define SOFTRST_NORMAL 0x00000003 + #define SOFTRST_RESET_MAC 0x00000002 + +/* External PHY Register Definition */ +#define BMCR 0x0000 + #define LINE_SPEED_MSB 0x0040 + #define DUPLEX_MODE 0x0100 + #define RESTART_AUTONEG 0x0200 + #define POWER_DOWN 0x0800 + #define AUTONEG_EN 0x1000 + #define LINE_SPEED_LSB 0x2000 + #define PHY_RESET 0x8000 + + #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\ + DUPLEX_MODE) + #define BMCR_SPEED_1000 LINE_SPEED_MSB + #define BMCR_SPEED_100 LINE_SPEED_LSB + #define BMCR_SPEED_10 0x0000 + + #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE) + #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE) + #define BMCR_100HALF BMCR_SPEED_100 + #define BMCR_10FULL DUPLEX_MODE + #define BMCR_10HALF 0x0000 +#define BMSR 0x0001 + #define LINKOK 0x0004 + #define AUTONEG_ENABLE_STS 0x0008 + #define AUTONEG_COMPLETE 0x0020 +#define PHYIDR0 0x0002 +#define PHYIDR1 0x0003 +#define ANAR 0x0004 + #define ANAR_PAUSE 0x0400 + #define ANAR_100FULL 0x0100 + #define ANAR_100HALF 0x0080 + #define ANAR_10FULL 0x0040 + #define ANAR_10HALF 0x0020 + #define ANAR_8023BIT 0x0001 +#define ANLPAR 0x0005 +#define ANER 0x0006 +#define AUX_1000_CTRL 0x0009 + #define ENABLE_1000HALF 0x0100 + #define ENABLE_1000FULL 0x0200 + #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL) +#define AUX_1000_STATUS 0x000A + #define LP_1000HALF 0x0400 + #define LP_1000FULL 0x0800 + +/* Marvell 88E1111 Gigabit PHY Register Definition */ +#define M88_SSR 0x0011 + #define SSR_SPEED_MASK 0xC000 + #define SSR_SPEED_1000 0x8000 + #define SSR_SPEED_100 0x4000 + #define SSR_SPEED_10 0x0000 + #define SSR_DUPLEX 0x2000 + #define SSR_MEDIA_RESOLVED_OK 0x0800 + + #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX) + #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX) + #define SSR_1000HALF SSR_SPEED_1000 + #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX) + #define SSR_100HALF SSR_SPEED_100 + #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX) + #define SSR_10HALF SSR_SPEED_10 +#define M88_IER 0x0012 + #define LINK_CHANGE_INT 0x0400 +#define M88_ISR 0x0013 + #define LINK_CHANGE_STATUS 0x0400 +#define M88_EXT_SCR 0x0014 + #define RGMII_RXCLK_DELAY 0x0080 + #define RGMII_TXCLK_DELAY 0x0002 + #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) +#define M88_EXT_SSR 0x001B + #define HWCFG_MODE_MASK 0x000F + #define RGMII_COPPER_MODE 0x000B + +/* CICADA CIS8201 Gigabit PHY Register Definition */ +#define CIS_IMR 0x0019 + #define CIS_INT_ENABLE 0x8000 + #define CIS_LINK_CHANGE_INT 0x2000 +#define CIS_ISR 0x001A + #define CIS_INT_PENDING 0x8000 + #define CIS_LINK_CHANGE_STATUS 0x2000 +#define CIS_AUX_CTRL_STATUS 0x001C + #define CIS_AUTONEG_COMPLETE 0x8000 + #define CIS_SPEED_MASK 0x0018 + #define CIS_SPEED_1000 0x0010 + #define CIS_SPEED_100 0x0008 + #define CIS_SPEED_10 0x0000 + #define CIS_DUPLEX 0x0020 + + #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX) + #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX) + #define CIS_1000HALF CIS_SPEED_1000 + #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX) + #define CIS_100HALF CIS_SPEED_100 + #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX) + #define CIS_10HALF CIS_SPEED_10 + #define CIS_SMI_PRIORITY 0x0004 + +/* Debug Message Display Level Definition */ +#define TX_MSG 0x0001 +#define RX_MSG 0x0002 +#define INT_MSG 0x0004 +#define DEBUG_MSG 0x0008 +#define NO_MSG 0x0000 +#define DEBUG_FLAGS (NO_MSG) + +#define PRINTK(flag, args...) if (flag & DEBUG_FLAGS) printf (args) + +/* + Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer +*/ +#if defined (CONFIG_DRIVER_AX88180_16BIT) +#define READ_RXBUF(data) \ + do { \ + data = *(volatile unsigned short *) \ + (AX88180_BASE + RXBUFFER_START); \ + } while (0) + +#define WRITE_TXBUF(data) \ + do { \ + *(volatile unsigned short *)(AX88180_BASE + TXBUFFER_START) \ + = data; \ + } while (0) + +#define READ_MACREG(regaddr, regdata) \ + do { \ + regdata = *(volatile unsigned short *) \ + (AX88180_BASE + regaddr); \ + } while (0) + +#define WRITE_MACREG(regaddr, regdata) \ + do { \ + *(volatile unsigned short*)(AX88180_BASE + regaddr) \ + = regdata; \ + } while (0) +#else +#define READ_RXBUF(data) \ + do { \ + data = *(volatile unsigned long *) \ + (AX88180_BASE + RXBUFFER_START); \ + } while (0) + +#define WRITE_TXBUF(data) \ + do { \ + *(volatile unsigned long *)(AX88180_BASE + TXBUFFER_START) \ + = data; \ + } while (0) + +#define READ_MACREG(regaddr, regdata) \ + do { \ + regdata = *(volatile unsigned long*)(AX88180_BASE + regaddr); \ + } while (0) + +#define WRITE_MACREG(regaddr, regdata) \ + do { \ + *(volatile unsigned long*)(AX88180_BASE + regaddr) \ + = regdata; \ + } while (0) +#endif /* end of CONFIG_DRIVER_AX88180_16BIT */ + +#endif /*end of CONFIG_DRIVER_AX88180 */ -- 1.5.4.5

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[U-Boot] [PATCH 01/13 v4] ARM: OMAP3: Add pin mux, clock and cpu headers
by dirk.behme＠googlemail.com 19 Oct '08

19 Oct '08

Subject: [PATCH 01/13 v4] ARM: OMAP3: Add pin mux, clock and cpu headers From: Dirk Behme <dirk.behme(a)gmail.com> Add pin mux, clock and cpu header files for OMAP3. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v3: - Replace space by tabs in headers as proposed by Jean-Christophe PLAGNIOL-VILLARD include/asm-arm/arch-omap3/bits.h | 48 +++ include/asm-arm/arch-omap3/clocks.h | 62 ++++ include/asm-arm/arch-omap3/clocks_omap3.h | 101 +++++++ include/asm-arm/arch-omap3/cpu.h | 249 ++++++++++++++++++ include/asm-arm/arch-omap3/mux.h | 407 ++++++++++++++++++++++++++++++ 5 files changed, 867 insertions(+) Index: u-boot-arm/include/asm-arm/arch-omap3/mux.h =================================================================== --- /dev/null +++ u-boot-arm/include/asm-arm/arch-omap3/mux.h @@ -0,0 +1,407 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_H_ +#define _MUX_H_ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ + +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +/* + * To get the actual address the offset has to added + * with OMAP34XX_CTRL_BASE to get the actual address + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_nCS0 0x00AE +#define CONTROL_PADCONF_GPMC_nCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_nCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_nCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_nCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_nCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_nCS6 0x00BA +#define CONTROL_PADCONF_GPMC_nCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_nOE 0x00C2 +#define CONTROL_PADCONF_GPMC_nWE 0x00C4 +#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_nBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_nWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_McBSP2_FSX 0x013C +#define CONTROL_PADCONF_McBSP2_CLKX 0x013E +#define CONTROL_PADCONF_McBSP2_DR 0x0140 +#define CONTROL_PADCONF_McBSP2_DX 0x0142 +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_McBSP3_DX 0x016C +#define CONTROL_PADCONF_McBSP3_DR 0x016E +#define CONTROL_PADCONF_McBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_McBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_McBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_McBSP4_DR 0x0186 +#define CONTROL_PADCONF_McBSP4_DX 0x0188 +#define CONTROL_PADCONF_McBSP4_FSX 0x018A +#define CONTROL_PADCONF_McBSP1_CLKR 0x018C +#define CONTROL_PADCONF_McBSP1_FSR 0x018E +#define CONTROL_PADCONF_McBSP1_DX 0x0190 +#define CONTROL_PADCONF_McBSP1_DR 0x0192 +#define CONTROL_PADCONF_McBSP_CLKS 0x0194 +#define CONTROL_PADCONF_McBSP1_FSX 0x0196 +#define CONTROL_PADCONF_McBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_McSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_McSPI1_CS0 0x01CE +#define CONTROL_PADCONF_McSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_McSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_McSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_McSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_McSPI2_CS0 0x01DC +#define CONTROL_PADCONF_McSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_nIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +/*Die to Die */ +#define CONTROL_PADCONF_d2d_mcad0 0x01E4 +#define CONTROL_PADCONF_d2d_mcad1 0x01E6 +#define CONTROL_PADCONF_d2d_mcad2 0x01E8 +#define CONTROL_PADCONF_d2d_mcad3 0x01EA +#define CONTROL_PADCONF_d2d_mcad4 0x01EC +#define CONTROL_PADCONF_d2d_mcad5 0x01EE +#define CONTROL_PADCONF_d2d_mcad6 0x01F0 +#define CONTROL_PADCONF_d2d_mcad7 0x01F2 +#define CONTROL_PADCONF_d2d_mcad8 0x01F4 +#define CONTROL_PADCONF_d2d_mcad9 0x01F6 +#define CONTROL_PADCONF_d2d_mcad10 0x01F8 +#define CONTROL_PADCONF_d2d_mcad11 0x01FA +#define CONTROL_PADCONF_d2d_mcad12 0x01FC +#define CONTROL_PADCONF_d2d_mcad13 0x01FE +#define CONTROL_PADCONF_d2d_mcad14 0x0200 +#define CONTROL_PADCONF_d2d_mcad15 0x0202 +#define CONTROL_PADCONF_d2d_mcad16 0x0204 +#define CONTROL_PADCONF_d2d_mcad17 0x0206 +#define CONTROL_PADCONF_d2d_mcad18 0x0208 +#define CONTROL_PADCONF_d2d_mcad19 0x020A +#define CONTROL_PADCONF_d2d_mcad20 0x020C +#define CONTROL_PADCONF_d2d_mcad21 0x020E +#define CONTROL_PADCONF_d2d_mcad22 0x0210 +#define CONTROL_PADCONF_d2d_mcad23 0x0212 +#define CONTROL_PADCONF_d2d_mcad24 0x0214 +#define CONTROL_PADCONF_d2d_mcad25 0x0216 +#define CONTROL_PADCONF_d2d_mcad26 0x0218 +#define CONTROL_PADCONF_d2d_mcad27 0x021A +#define CONTROL_PADCONF_d2d_mcad28 0x021C +#define CONTROL_PADCONF_d2d_mcad29 0x021E +#define CONTROL_PADCONF_d2d_mcad30 0x0220 +#define CONTROL_PADCONF_d2d_mcad31 0x0222 +#define CONTROL_PADCONF_d2d_mcad32 0x0224 +#define CONTROL_PADCONF_d2d_mcad33 0x0226 +#define CONTROL_PADCONF_d2d_mcad34 0x0228 +#define CONTROL_PADCONF_d2d_mcad35 0x022A +#define CONTROL_PADCONF_d2d_mcad36 0x022C +#define CONTROL_PADCONF_d2d_clk26mi 0x022E +#define CONTROL_PADCONF_d2d_nrespwron 0x0230 +#define CONTROL_PADCONF_d2d_nreswarm 0x0232 +#define CONTROL_PADCONF_d2d_arm9nirq 0x0234 +#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236 +#define CONTROL_PADCONF_d2d_spint 0x0238 +#define CONTROL_PADCONF_d2d_frint 0x023A +#define CONTROL_PADCONF_d2d_dmareq0 0x023C +#define CONTROL_PADCONF_d2d_dmareq1 0x023E +#define CONTROL_PADCONF_d2d_dmareq2 0x0240 +#define CONTROL_PADCONF_d2d_dmareq3 0x0242 +#define CONTROL_PADCONF_d2d_n3gtrst 0x0244 +#define CONTROL_PADCONF_d2d_n3gtdi 0x0246 +#define CONTROL_PADCONF_d2d_n3gtdo 0x0248 +#define CONTROL_PADCONF_d2d_n3gtms 0x024A +#define CONTROL_PADCONF_d2d_n3gtck 0x024C +#define CONTROL_PADCONF_d2d_n3grtck 0x024E +#define CONTROL_PADCONF_d2d_mstdby 0x0250 +#define CONTROL_PADCONF_d2d_swakeup 0x0A4C +#define CONTROL_PADCONF_d2d_idlereq 0x0252 +#define CONTROL_PADCONF_d2d_idleack 0x0254 +#define CONTROL_PADCONF_d2d_mwrite 0x0256 +#define CONTROL_PADCONF_d2d_swrite 0x0258 +#define CONTROL_PADCONF_d2d_mread 0x025A +#define CONTROL_PADCONF_d2d_sread 0x025C +#define CONTROL_PADCONF_d2d_mbusflag 0x025E +#define CONTROL_PADCONF_d2d_sbusflag 0x0260 +#define CONTROL_PADCONF_sdrc_cke0 0x0262 +#define CONTROL_PADCONF_sdrc_cke1 0x0264 + +#endif Index: u-boot-arm/include/asm-arm/arch-omap3/bits.h =================================================================== --- /dev/null +++ u-boot-arm/include/asm-arm/arch-omap3/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif Index: u-boot-arm/include/asm-arm/arch-omap3/clocks.h =================================================================== --- /dev/null +++ u-boot-arm/include/asm-arm/arch-omap3/clocks.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 +#define FCK_PER_ON 0x0003ffff +#define ICK_PER_ON 0x0003ffff + +/* Used to index into DPLL parameter tables */ +typedef struct { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +} dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(void); +extern dpll_param *get_iva_dpll_param(void); +extern dpll_param *get_core_dpll_param(void); +extern dpll_param *get_per_dpll_param(void); + +extern void *_end_vect, *_start; + +#endif Index: u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h =================================================================== --- /dev/null +++ u-boot-arm/include/asm-arm/arch-omap3/clocks_omap3.h @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP3_H_ +#define _CLOCKS_OMAP3_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +#define CORE_FUSB_DIV 2 /* 41.5MHz: */ +#define CORE_L4_DIV 2 /* 83MHz : L4 */ +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#define M_12 0xA6 +#define N_12 0x05 +#define FSEL_12 0x07 +#define M2_12 0x01 /* M3 of 2 */ + +#define M_12_ES1 0x19F +#define N_12_ES1 0x0E +#define FSL_12_ES1 0x03 +#define M2_12_ES1 0x1 /* M3 of 2 */ + +#define M_13 0x14C +#define N_13 0x0C +#define FSEL_13 0x03 +#define M2_13 0x01 /* M3 of 2 */ + +#define M_13_ES1 0x1B2 +#define N_13_ES1 0x10 +#define FSL_13_ES1 0x03 +#define M2_13_ES1 0x01 /* M3 of 2 */ + +#define M_19p2 0x19F +#define N_19p2 0x17 +#define FSEL_19p2 0x03 +#define M2_19p2 0x01 /* M3 of 2 */ + +#define M_19p2_ES1 0x19F +#define N_19p2_ES1 0x17 +#define FSL_19p2_ES1 0x03 +#define M2_19p2_ES1 0x01 /* M3 of 2 */ + +#define M_26 0xA6 +#define N_26 0x0C +#define FSEL_26 0x07 +#define M2_26 0x01 /* M3 of 2 */ + +#define M_26_ES1 0x1B2 +#define N_26_ES1 0x21 +#define FSL_26_ES1 0x03 +#define M2_26_ES1 0x01 /* M3 of 2 */ + +#define M_38p4 0x19F +#define N_38p4 0x2F +#define FSEL_38p4 0x03 +#define M2_38p4 0x01 /* M3 of 2 */ + +#define M_38p4_ES1 0x19F +#define N_38p4_ES1 0x2F +#define FSL_38p4_ES1 0x03 +#define M2_38p4_ES1 0x01 /* M3 of 2 */ + +#endif /* endif _CLOCKS_OMAP3_H_ */ Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h =================================================================== --- /dev/null +++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _CPU_H +#define _CPU_H + +/* Register offsets of common modules */ +/* Control */ +#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) +#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) +#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) + +/* Tap Information */ +#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10) +#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18) +#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54) + +#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + +/* GPMC Mapping */ +#define FLASH_BASE 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ + /* aligned to 64 Meg */ +#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define DEBUG_BASE 0x08000000 /* debug board */ +#define NAND_BASE 0x30000000 /* NAND addr */ + /* (actual size small port) */ +#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +#define ONENAND_MAP 0x20000000 /* OneNand addr */ + /* (actual size small port) */ + +/* SMS */ +#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) +#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48) +#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68) +#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + +#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70) +#define WAKEUPPROC BIT26 + +#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP34XX_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8) +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + /* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0<<2)|BIT1|BIT0) + +/* Watchdog */ +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define CM_FCLKEN_IVA2 0x48004000 +#define CM_CLKEN_PLL_IVA2 0x48004004 +#define CM_IDLEST_PLL_IVA2 0x48004024 +#define CM_CLKSEL1_PLL_IVA2 0x48004040 +#define CM_CLKSEL2_PLL_IVA2 0x48004044 +#define CM_CLKEN_PLL_MPU 0x48004904 +#define CM_IDLEST_PLL_MPU 0x48004924 +#define CM_CLKSEL1_PLL_MPU 0x48004940 +#define CM_CLKSEL2_PLL_MPU 0x48004944 +#define CM_FCLKEN1_CORE 0x48004a00 +#define CM_ICLKEN1_CORE 0x48004a10 +#define CM_ICLKEN2_CORE 0x48004a14 +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_FCLKEN_GFX 0x48004b00 +#define CM_ICLKEN_GFX 0x48004b10 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_FCLKEN_WKUP 0x48004c00 +#define CM_ICLKEN_WKUP 0x48004c10 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_IDLEST_WKUP 0x48004c20 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_IDLEST_CKGEN 0x48004d20 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL2_PLL 0x48004d44 +#define CM_CLKSEL3_PLL 0x48004d48 +#define CM_FCLKEN_DSS 0x48004e00 +#define CM_ICLKEN_DSS 0x48004e10 +#define CM_CLKSEL_DSS 0x48004e40 +#define CM_FCLKEN_CAM 0x48004f00 +#define CM_ICLKEN_CAM 0x48004f10 +#define CM_CLKSEL_CAM 0x48004F40 +#define CM_FCLKEN_PER 0x48005000 +#define CM_ICLKEN_PER 0x48005010 +#define CM_CLKSEL_PER 0x48005040 +#define CM_CLKSEL1_EMU 0x48005140 + +#define PRM_CLKSEL 0x48306d40 +#define PRM_RSTCTRL 0x48307250 +#define PRM_CLKSRC_CTRL 0x48307270 + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) +#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) +#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) + +#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) +#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) +#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) + +#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) +#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) +#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +#endif /* _CPU_H */

2 1

[U-Boot] CUSTODIANS: Final boarding call for flight 2008-10
by Wolfgang Denk 19 Oct '08

19 Oct '08

Hi Custodians (and everybody else), can you please check if all urgent patches have been added to the U-Boot master branch? If anything should still be missing, please respond *now*. My intention is to push out the 2008-10 release tomorrow, i. e. in approximately 30 hours from now. Note: after the release is out, I will merge the current "next" branch into "master", so this will be the starting point for the next merge window. Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de A supercomputer is a machine that runs an endless loop in 2 seconds.

3 6

[U-Boot] [PATCH 01/24] FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.
by Kumar Gala 19 Oct '08

19 Oct '08

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc86xx/ddr-8641.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c index 932ef22..f936182 100644 --- a/cpu/mpc86xx/ddr-8641.c +++ b/cpu/mpc86xx/ddr-8641.c @@ -35,7 +35,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); out_be32(&ddr->cs0_config, regs->cs[i].config); } else if (i == 1) { -- 1.5.5.1

3 28

[U-Boot] [PATCH] bootm: Move to using a function pointer table for the boot os function
by Kumar Gala 19 Oct '08

19 Oct '08

This removes a bit of code and makes it easier for the upcoming sub bootm command support to call into the proper OS specific handler. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- common/cmd_bootm.c | 67 +++++++++++++++++++++++---------------------------- 1 files changed, 30 insertions(+), 37 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index b02da3e..5182124 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -119,6 +119,22 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); static boot_os_fn do_bootm_integrity; #endif +boot_os_fn * boot_os[] = { + [IH_OS_LINUX] = do_bootm_linux, + [IH_OS_NETBSD] = do_bootm_netbsd, +#ifdef CONFIG_LYNXKDI + [IH_OS_LYNXOS] = do_bootm_lynxkdi, +#endif + [IH_OS_RTEMS] = do_bootm_rtems, +#if defined(CONFIG_CMD_ELF) + [IH_OS_VXWORKS] = do_bootm_vxworks, + [IH_OS_QNX] = do_bootm_qnxelf, +#endif +#ifdef CONFIG_INTEGRITY + [IH_OS_INTEGRITY] = do_bootm_integrity, +#endif +}; + ulong load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */ static bootm_headers_t images; /* pointers to os/initrd/fdt images */ @@ -386,12 +402,21 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) /*******************************************************************/ /* bootm - boot application image from image in memory */ /*******************************************************************/ +static int relocated = 0; + int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong iflag; ulong load_end = 0; int ret; + boot_os_fn *boot_fn; + + /* relocate boot function table */ + if (0 == relocated) { + int i; + for (i = 0; i < ARRAY_SIZE(boot_os); i++) + boot_os[i] += gd->reloc_off; + } if (bootm_start(cmdtp, flag, argc, argv)) return 1; @@ -454,45 +479,13 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) show_boot_progress (8); - switch (images.os.os) { - default: /* handled by (original) Linux case */ - case IH_OS_LINUX: #ifdef CONFIG_SILENT_CONSOLE - fixup_silent_linux(); + if (images.os.os == IH_OS_LINUX) + fixup_silent_linux(); #endif - do_bootm_linux (0, argc, argv, &images); - break; - - case IH_OS_NETBSD: - do_bootm_netbsd (0, argc, argv, &images); - break; -#ifdef CONFIG_LYNXKDI - case IH_OS_LYNXOS: - do_bootm_lynxkdi (0, argc, argv, &images); - break; -#endif - - case IH_OS_RTEMS: - do_bootm_rtems (0, argc, argv, &images); - break; - -#if defined(CONFIG_CMD_ELF) - case IH_OS_VXWORKS: - do_bootm_vxworks (0, argc, argv, &images); - break; - - case IH_OS_QNX: - do_bootm_qnxelf (0, argc, argv, &images); - break; -#endif - -#ifdef CONFIG_INTEGRITY - case IH_OS_INTEGRITY: - do_bootm_integrity (0, argc, argv, &images); - break; -#endif - } + boot_fn = boot_os[images.os.os]; + boot_fn(0, argc, argv, &images); show_boot_progress (-9); #ifdef DEBUG -- 1.5.5.1

1 0

[U-Boot] lookup tables: how can i manage them?
by Luigi 'Comio' Mantellini 19 Oct '08

19 Oct '08

Hi ML, in my code (for now a stupid SMI interface) I'm using a jump table like this: struct reg:{ callback_1 c1, callback_2 c2, ... }; struct reg mytable[100]={ ......... } c1 and c2 are pointer to functions. My problem is that U-boot relocates itself into ram and these pointers are calculated at linking time. Which is the best practice (into u.boot) to manage these loolup tables/jmps tables? is there a suggest way or a common place to put the needed relocation code (adding the gd->reloc_off to the pointers)? I'm working on mips, but I thinks that this is a general question. thanks in advance. best regards, luigi PS.: I made a stupid driver to manage smi interface, that is a "theme variation" on mii bus, to manage a tantos switch. I can send the code if there is interest. -- Luigi Mantellini R&D - Software Industrie Dial Face S.p.A. Via Canzo, 4 20068 Peschiera Borromeo (MI), Italy Tel.: +39 02 5167 2813 Fax: +39 02 5167 2459 Email: luigi.mantellini(a)idf-hit.com

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[U-Boot] net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_init
by Shinya Kuribayashi 19 Oct '08

19 Oct '08

This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init as a part of ongoing eth_initialize cleanup work. The function ret value is also fixed as it should be negative on fail. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- Hi Ben, build tested. Please review. Shinya cpu/mips/au1x00_eth.c | 2 +- cpu/mips/cpu.c | 7 +++++++ include/netdev.h | 1 + net/eth.c | 4 ---- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index 8ddc06a..6272a3a 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -283,7 +283,7 @@ int au1x00_enet_initialize(bd_t *bis){ if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) { puts ("malloc failed\n"); - return 0; + return -1; } memset(dev, 0, sizeof *dev); diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 38d8697..c70cf0b 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -73,3 +73,10 @@ void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) write_c0_index(index); tlb_write_indexed(); } + +int cpu_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SOC_AU1X00 + return au1x00_enet_initialize(bis); +#endif +} diff --git a/include/netdev.h b/include/netdev.h index 87d578c..b0d5c63 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis); int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ +int au1x00_enet_initialize(bd_t*); int bfin_EMAC_initialize(bd_t *bis); int dc21x4x_initialize(bd_t *bis); int e1000_initialize(bd_t *bis); diff --git a/net/eth.c b/net/eth.c index ccd871a..9f121c2 100644 --- a/net/eth.c +++ b/net/eth.c @@ -39,7 +39,6 @@ static int __def_eth_init(bd_t *bis) int cpu_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init"))); int board_eth_init(bd_t *bis) __attribute((weak, alias("__def_eth_init"))); -extern int au1x00_enet_initialize(bd_t*); extern int fec_initialize(bd_t*); extern int mpc8220_fec_initialize(bd_t*); extern int mv6436x_eth_initialize(bd_t *); @@ -190,9 +189,6 @@ int eth_initialize(bd_t *bis) #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); #endif -#if defined(CONFIG_AU1X00) - au1x00_enet_initialize(bis); -#endif #if defined(CONFIG_IXP4XX_NPE) npe_initialize(bis); #endif

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[U-Boot] U-Boot 2008.10 Release
by Wolfgang Denk 18 Oct '08

18 Oct '08

Hi everybody, U-Boot v2008.10 has been released and is available from the git repository and the FTP server. The Merge Window for the next release is open until Halloween night, i. e. 14 days remaining. The next release is scheduled for December 18. See http://www.denx.de/wiki/U-Boot/ReleaseCycle for details. Note: the "next" branch has been merged into mainline. A little statistics [1] - changes since release v1.3.4: Processed 618 csets from 106 developers 47 employers found A total of 108280 lines added, 56955 removed (delta 51325) Compare v1.3.4: Processed 593 csets from 101 developers 41 employers found A total of 61927 lines added, 41596 removed (delta 20331) Developers with the most changesets Jean-Christophe PLAGNIOL-VILLARD 76 (12.3%) Kumar Gala 54 (8.7%) Stefan Roese 37 (6.0%) Wolfgang Denk 30 (4.9%) Ben Warren 27 (4.4%) TsiChung Liew 25 (4.0%) Matthias Fuchs 22 (3.6%) Nobuhiro Iwamatsu 22 (3.6%) Scott Wood 15 (2.4%) Guennadi Liakhovetski 14 (2.3%) ... Developers with the most changed lines William Juul 32310 (24.6%) Jean-Christophe PLAGNIOL-VILLARD 13340 (10.1%) Kumar Gala 9891 (7.5%) Wolfgang Denk 7380 (5.6%) TsiChung Liew 5810 (4.4%) Stefan Roese 5546 (4.2%) Nobuhiro Iwamatsu 4950 (3.8%) Guennadi Liakhovetski 4753 (3.6%) Ben Warren 3264 (2.5%) Luigi 'Comio' Mantellini 2540 (1.9%) ... Developers with the most lines removed Stefan Roese 2717 (4.8%) Andre Schwarz 1459 (2.6%) Matthias Fuchs 382 (0.7%) Ira W. Snyder 151 (0.3%) Andreas Engel 113 (0.2%) Timur Tabi 90 (0.2%) Andrew Dyer 80 (0.1%) Michal Simek 47 (0.1%) Peter Tyser 45 (0.1%) Haavard Skinnemoen 17 (0.0%) ... Developers with the most signoffs (total 1543) Stefan Roese 188 (12.2%) Jean-Christophe PLAGNIOL-VILLARD 161 (10.4%) Kumar Gala 127 (8.2%) Ben Warren 94 (6.1%) Wolfgang Denk 83 (5.4%) Scott Wood 73 (4.7%) Nobuhiro Iwamatsu 72 (4.7%) TsiChung Liew 49 (3.2%) Matthias Fuchs 44 (2.9%) Kim Phillips 40 (2.6%) ... Top changeset contributors by employer DENX 159 (25.7%) Freescale 134 (21.7%) jcrosoft 76 (12.3%) Ben Warren 27 (4.4%) (Unknown) 27 (4.4%) Renesas Technology 25 (4.0%) ESD Electronics 22 (3.6%) Universidad Autonoma de Madrid 13 (2.1%) AMCC 13 (2.1%) Atmel 11 (1.8%) ... Top lines changed by employer TANDBERG 42788 (32.5%) Freescale 24717 (18.8%) DENX 21579 (16.4%) jcrosoft 14586 (11.1%) Renesas Technology 5149 (3.9%) Ben Warren 3421 (2.6%) AMCC 2939 (2.2%) Industrie Dial Face 2540 (1.9%) Universidad Autonoma de Madrid 2268 (1.7%) Matrix Vision 2156 (1.6%) ... [1] See http://www.denx.de/wiki/UBoot/UbootStat_2008_10 for full statistics, and http://www.denx.de/wiki/UBoot/ReleaseCycle for links to statistics for earlier releases. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de There is is no reason for any individual to have a computer in their home. -- Ken Olsen (President of Digital Equipment Corporation), Convention of the World Future Society, in Boston, 1977

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Re: [U-Boot] [U-Boot-Users] Compilation problem for TI3430 board.
by Jerry Van Baren 18 Oct '08

18 Oct '08

Hi Radha, Please don't top post. Radha Krishna wrote: > Hi GVB, > You are right. Could you tell me the solution. Don't use DOS (aka Windows). Since you already have a problem there, you can use "dos2unix" or equivalent. If you feel you must use Windows, many Windows editors (e.g. UltraEdit) allow you to control/convert line endings. > Best Regards, > Kris. [snip] >>> $ make CROSS_COMPILE=arm-none-linux-gnueabi- >> omap3430sdp_config >>> ./mkconfig: line 2: $'\r': command not >> found >>> make: *** [omap3430sdp_config] Error 127 >> Is that telling you that you have DOS line endings >> (<CR>+<LF> i.e. \r\n) >> as opposed to unix line endings (\n only)? >> >>> $ make CROSS_COMPILE=arm-none-linux-gnueabi- >>> System not configured - see README >>> make: *** [all] Error 1 >>> >>> Could somebody tell me steps to compile U-Boot for >>> TI3430. >>> >>> Best Regards, >>> Krishna. >> My best guess, >> gvb HTH, gvb

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[U-Boot] [PATCH] 85xx: properly document MPC85xx_PORDEVSR2_SEC_CFG
by Timur Tabi 18 Oct '08

18 Oct '08

Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot to add a comment that the correct value disagrees with the 8544 reference manual. Without this comment, a developer looking at the code would get confused. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/asm-ppc/immap_85xx.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 6c81c39..920afd2 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1579,6 +1579,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ +/* The 8544 RM says this is bit 26, but it's really bit 28 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ -- 1.5.5

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