October 2008 - U-Boot

[U-Boot] [PATCH 1/2] rename CFG_ macros to CONFIG_SYS
by Jean-Christophe PLAGNIOL-VILLARD 21 Oct '08

21 Oct '08

3 7

[U-Boot] [PATCH] i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
by Timur Tabi 21 Oct '08

21 Oct '08

All implementations of the functions i2c_reg_read() and i2c_reg_write() are identical. We can save space and simplify the code by converting these functions into inlines and putting them in i2c.h. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- I'm posting this patch because I'm enhancing the I2C routines to support multiple I2C busses more easily, but I need to clean up the existing code first. cpu/arm920t/at91rm9200/i2c.c | 14 -------------- cpu/arm926ejs/davinci/i2c.c | 17 ----------------- cpu/blackfin/i2c.c | 16 ---------------- cpu/mpc512x/i2c.c | 17 ----------------- cpu/mpc5xxx/i2c.c | 16 ---------------- cpu/mpc8220/i2c.c | 16 ---------------- cpu/mpc824x/drivers/i2c/i2c.c | 14 -------------- cpu/mpc8260/i2c.c | 16 ---------------- cpu/mpc8xx/i2c.c | 20 -------------------- cpu/ppc4xx/i2c.c | 20 -------------------- cpu/pxa/i2c.c | 15 --------------- drivers/i2c/fsl_i2c.c | 16 ---------------- drivers/i2c/soft_i2c.c | 19 ------------------- include/i2c.h | 15 +++++++++++++-- 14 files changed, 13 insertions(+), 218 deletions(-) diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c index 90f95df..fb4725d 100644 --- a/cpu/arm920t/at91rm9200/i2c.c +++ b/cpu/arm920t/at91rm9200/i2c.c @@ -189,20 +189,6 @@ i2c_init(int speed, int slaveaddr) return; } -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - unsigned char buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return(buf); -} - -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - int i2c_set_bus_speed(unsigned int speed) { return -1; diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c index af9dc03..1029b03 100644 --- a/cpu/arm926ejs/davinci/i2c.c +++ b/cpu/arm926ejs/davinci/i2c.c @@ -331,21 +331,4 @@ int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) return(0); } - -u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) -{ - u_int8_t tmp; - - i2c_read(chip, reg, 1, &tmp, 1); - return(tmp); -} - - -void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) -{ - u_int8_t tmp; - - i2c_write(chip, reg, 1, &tmp, 1); -} - #endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c index 60f03d4..2a3e223 100644 --- a/cpu/blackfin/i2c.c +++ b/cpu/blackfin/i2c.c @@ -425,20 +425,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) } -uchar i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg); - i2c_read(chip, reg, 0, &buf, 1); - return (buf); -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip, - reg, val); - i2c_write(chip, reg, 0, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 56ba443..95cc942 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -382,23 +382,6 @@ Done: return ret; } -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - i2c_read (chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write (uchar chip, uchar reg, uchar val) -{ - i2c_write (chip, reg, 1, &val, 1); - - return; -} - - int i2c_set_bus_num (unsigned int bus) { if (bus >= I2C_BUS_CNT) { diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c index 0f02e78..015256f 100644 --- a/cpu/mpc5xxx/i2c.c +++ b/cpu/mpc5xxx/i2c.c @@ -380,20 +380,4 @@ Done: return ret; } -uchar i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - i2c_read(chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - i2c_write(chip, reg, 1, &val, 1); - - return; -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c index d67936d..76ecdf1 100644 --- a/cpu/mpc8220/i2c.c +++ b/cpu/mpc8220/i2c.c @@ -387,20 +387,4 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buf, int len) return ret; } -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - i2c_read (chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write (uchar chip, uchar reg, uchar val) -{ - i2c_write (chip, reg, 1, &val, 1); - - return; -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c index 3add687..48d754e 100644 --- a/cpu/mpc824x/drivers/i2c/i2c.c +++ b/cpu/mpc824x/drivers/i2c/i2c.c @@ -267,18 +267,4 @@ int i2c_probe (uchar chip) return i2c_read (chip, 0, 1, (uchar *) &tmp, 1); } -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index c3af7b6..71dac3b 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -749,20 +749,4 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -uchar -i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - i2c_read(chip, reg, 1, &buf, 1); - - return (buf); -} - -void -i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - i2c_write(chip, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index f05b666..0a2fe95 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -717,24 +717,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -uchar -i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return (buf); -} - -void -i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); - - i2c_write(i2c_addr, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index d8be2ce..39c3fef 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -420,26 +420,6 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); } -/*----------------------------------------------------------------------- - * Read a register - */ -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return (buf); -} - -/*----------------------------------------------------------------------- - * Write a register - */ -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - #if defined(CONFIG_I2C_MULTI_BUS) /* * Functions for multiple I2C bus handling diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index df537c4..539ca25 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -455,19 +455,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); - i2c_read(chip, reg, 1, &buf, 1); - return (buf); -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); - i2c_write(chip, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 264553d..a8ab0f0 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -368,22 +368,6 @@ i2c_probe(uchar chip) return i2c_read(chip, 0, 0, NULL, 0); } -uchar -i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read(i2c_addr, reg, 1, buf, 1); - - return buf[0]; -} - -void -i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - int i2c_set_bus_num(unsigned int bus) { #ifdef CFG_I2C2_OFFSET diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 23db2ee..4d7abdd 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -402,22 +402,3 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return(failures); } -/*----------------------------------------------------------------------- - * Read a register - */ -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return(buf); -} - -/*----------------------------------------------------------------------- - * Write a register - */ -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} diff --git a/include/i2c.h b/include/i2c.h index a51c164..169e487 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -100,8 +100,19 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); /* * Utility routines to read/write registers. */ -uchar i2c_reg_read (uchar chip, uchar reg); -void i2c_reg_write(uchar chip, uchar reg, uchar val); +static inline u8 i2c_reg_read(u8 addr, u8 reg) +{ + u8 buf; + + i2c_read(addr, reg, 1, &buf, 1); + + return buf; +} + +static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) +{ + i2c_write(addr, reg, 1, &val, 1); +} /* * Functions for setting the current I2C bus and its speed -- 1.5.5

4 16

[U-Boot] [PATCH][iMX31] Change to use "do_div" macro
by Tomohiro Masubuchi 21 Oct '08

21 Oct '08

I tryed to build u-boot by Sourcery G++ Lite 2008q3-41 for ARM GNU/Linux. But, it was failed with some link error of divide function. Thus, I changed to use the "do_div" macro to calculate the dividing. In my environment, the "next" branch with this patch worked correctly. Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi(a)tripeaks.co.jp> ---- Change to use the "do_div" macro. cpu/arm1136/mx31/interrupts.c | 36 ++++++++++++++++++++++++++++++------ 1 files changed, 30 insertions(+), 6 deletions(-) diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c index b36c58c..807e791 100644 --- a/cpu/arm1136/mx31/interrupts.c +++ b/cpu/arm1136/mx31/interrupts.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/mx31-regs.h> +#include <div64.h> #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ @@ -41,17 +42,40 @@ /* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION /* ~0.4% error - measured with stop-watch on 100s boot-delay */ -#define TICK_TO_TIME(t) ((t) * CONFIG_SYS_HZ / CONFIG_MX31_CLK32) -#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CONFIG_SYS_HZ) -#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \ - 999999) / 1000000) +#define TICK_TO_TIME(t) ({ \ + unsigned long long tmp = (t); \ + t *= CONFIG_SYS_HZ; \ + do_div(tmp, CONFIG_MX31_CLK32); \ + tmp; \ + }) +#define TIME_TO_TICK(t) ({ \ + unsigned long long tmp = (t); \ + tmp *= CONFIG_MX31_CLK32; \ + do_div(tmp, CONFIG_SYS_HZ); \ + tmp; \ + }) +#define US_TO_TICK(t) ({ \ + unsigned long long tmp = (t); \ + tmp = tmp * CONFIG_MX31_CLK32 + 999999; \ + do_div(tmp, 1000000); \ + tmp; \ + }) #else /* ~2% error */ #define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) -#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME) +#define TICK_TO_TIME(t) ({ \ + unsigned long long tmp = (t); \ + do_div(tmp, TICK_PER_TIME); \ + tmp; \ + }) #define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME) -#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK) +#define US_TO_TICK(t) ({ \ + unsigned long long tmp = (t); \ + tmp += US_PER_TICK - 1; \ + do_div(tmp, US_PER_TICK); \ + tmp; \ + }) #endif static ulong timestamp;

2 2

[U-Boot] [PATCH] ARM/Versatile port: Removed unused functions
by Roman Mashak 21 Oct '08

21 Oct '08

Removal of never used functions. Signed-off-by: Roman Mashak <romez777(a)gmail.com> --- board/versatile/versatile.c | 22 ---------------------- 1 files changed, 0 insertions(+), 22 deletions(-) diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c index 3b9b020..0f35caa 100644 --- a/board/versatile/versatile.c +++ b/board/versatile/versatile.c @@ -37,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -void flash__init (void); -void ether__init (void); -void peripheral_power_enable (void); - #if defined(CONFIG_SHOW_BOOT_PROGRESS) void show_boot_progress(int progress) { @@ -82,8 +78,6 @@ int board_init (void) icache_enable (); - flash__init (); - ether__init (); return 0; } @@ -98,22 +92,6 @@ int misc_init_r (void) Routine: Description: ******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ int dram_init (void) { return 0; -- 1.4.4.4

1 0

[U-Boot] [PATCH] AT91SAM9263-pm9263-support
by Ilko Iliev 20 Oct '08

20 Oct '08

This patch adds support for the PM9263 board of Ronetix GmbH (www.ronetix.at) Signed-off-by: Ilko Iliev <iliev(a)ronetix.at> --- MAKEALL | 1 + Makefile | 3 + board/ronetix/pm9263/Makefile | 60 +++++ board/ronetix/pm9263/config.mk | 1 + board/ronetix/pm9263/led.c | 68 ++++++ board/ronetix/pm9263/lowlevel_init.S | 375 ++++++++++++++++++++++++++++++++ board/ronetix/pm9263/partition.c | 47 ++++ board/ronetix/pm9263/pm9263.c | 393 ++++++++++++++++++++++++++++++++++ board/ronetix/pm9263/pm9263_nand.c | 79 +++++++ common/lcd.c | 9 + cpu/arm926ejs/at91/lowlevel_init.S | 6 +- drivers/mtd/dataflash.c | 5 +- include/configs/pm9263.h | 285 ++++++++++++++++++++++++ tools/Makefile | 3 + tools/logos/ronetix.bmp | Bin 0 -> 5638 bytes 15 files changed, 1330 insertions(+), 5 deletions(-) mode change 100755 => 100644 MAKEALL create mode 100644 board/ronetix/pm9263/Makefile create mode 100644 board/ronetix/pm9263/config.mk create mode 100644 board/ronetix/pm9263/led.c create mode 100644 board/ronetix/pm9263/lowlevel_init.S create mode 100644 board/ronetix/pm9263/partition.c create mode 100644 board/ronetix/pm9263/pm9263.c create mode 100644 board/ronetix/pm9263/pm9263_nand.c create mode 100644 include/configs/pm9263.h create mode 100644 tools/logos/ronetix.bmp diff --git a/MAKEALL b/MAKEALL old mode 100755 new mode 100644 index 9ccb9ac..bde7d73 --- a/MAKEALL +++ b/MAKEALL @@ -536,6 +536,7 @@ LIST_at91=" \ at91sam9260ek \ at91sam9261ek \ at91sam9263ek \ + pm9263 \ at91sam9rlek \ cmc_pu2 \ csb637 \ diff --git a/Makefile b/Makefile index 9055747..2772dd5 100644 --- a/Makefile +++ b/Makefile @@ -2493,6 +2493,9 @@ at91sam9261ek_config : unconfig at91sam9263ek_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91 +pm9263_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 + at91sam9rlek_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91 diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile new file mode 100644 index 0000000..df9ed4f --- /dev/null +++ b/board/ronetix/pm9263/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# Ilko Iliev <www.ronetix.at> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += pm9263.o +COBJS-y += led.o +COBJS-y += partition.o +COBJS-$(CONFIG_CMD_NAND) += pm9263_nand.o + +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ronetix/pm9263/config.mk b/board/ronetix/pm9263/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/ronetix/pm9263/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c new file mode 100644 index 0000000..f86c7c3 --- /dev/null +++ b/board/ronetix/pm9263/led.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#define RED_LED AT91_PIN_PB7 /* this is the power led */ +#define GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ + +void red_LED_on(void) +{ + at91_set_gpio_value(RED_LED, 1); +} + +void red_LED_off(void) +{ + at91_set_gpio_value(RED_LED, 0); +} + +void green_LED_on(void) +{ + at91_set_gpio_value(GREEN_LED, 0); +} + +void green_LED_off(void) +{ + at91_set_gpio_value(GREEN_LED, 1); +} + + + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE); + + at91_set_gpio_output(RED_LED, 1); + at91_set_gpio_output(GREEN_LED, 1); + + at91_set_gpio_value(RED_LED, 0); + at91_set_gpio_value(GREEN_LED, 1); +} diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S new file mode 100644 index 0000000..de240b7 --- /dev/null +++ b/board/ronetix/pm9263/lowlevel_init.S @@ -0,0 +1,375 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * + * Modified for the Ronetix PM9263 board by Ilko Iliev (www.ronetix.at) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +#define SDRAM 0x20000000 /* address of the SDRAM */ + +/* clocks */ +#define MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */ +#define PLLAR_VAL (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +/* #define PLLAR_VAL 0x200CBF01 */ /* 239.616000 MHz for PCK */ +#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB) */ + +#define MCKR1_VAL 0x00000100 /* PCK/2 = MCK Master Clock from PLLA*/ +#define MCKR2_VAL 0x00000102 /* PCK/2 = MCK Master Clock from PLLA*/ + +#define AT91_PIOD_PDR (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) +#define AT91_PIOD_PPUDR (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) +#define AT91_PIOD_ASR (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) +#define AT91_CCFG_EBI0CSA (0xFFFFED20) /* (CCFG) EBI0 Chip Select */ +#define AT91_CCFG_EBI1CSA (0xFFFFED24) /* (CCFG) EBI1 Chip Select */ + +#define AT91_SMC0_CTRL0 (0xFFFFE40C) /* (SMC0) Control Register for CS 0 */ +#define AT91_SMC0_CYCLE0 (0xFFFFE408) /* (SMC0) Cycle Register for CS 0 */ +#define AT91_SMC0_SETUP0 (0xFFFFE400) /* (SMC0) Setup Register for CS 0 */ +#define AT91_SMC0_PULSE0 (0xFFFFE404) /* (SMC0) Pulse Register for CS 0 */ + +#define AT91_SMC1_CTRL0 (0xFFFFEA0C) /* (SMC1) Control Register for CS 0 */ +#define AT91_SMC1_CYCLE0 (0xFFFFEA08) /* (SMC1) Cycle Register for CS 0 */ +#define AT91_SMC1_SETUP0 (0xFFFFEA00) /* (SMC1) Setup Register for CS 0 */ +#define AT91_SMC1_PULSE0 (0xFFFFEA04) /* (SMC1) Pulse Register for CS 0 */ + +#define AT91_SDRAMC0_CR (0xFFFFE208) /* (SDRAMC0) SDRAM Configuration Reg.*/ +#define AT91_SDRAMC0_MR (0xFFFFE200) /* (SDRAMC0) SDRAM Mode Register */ +#define AT91_SDRAMC0_MDR (0xFFFFE224) /* (SDRAMC0) SDRAM Memory Device Reg.*/ +#define AT91_SDRAMC0_TR (0xFFFFE204) /* (SDRAMC0) SDRAM Refresh Timer Reg.*/ + +#define AT91_RSTC_RMR (0xFFFFFD08) /* (RSTC) Reset Mode Register */ + +#define PIOD_PDR_VAL1 0xFFFF0000 /* define PDC[31:16] as DATA[31:16] */ +#define PIOD_PPUDR_VAL 0xFFFF0000 /* no pull-up for D[31:16] */ +#define MATRIX_EBI0CSA_VAL 0x0001010A /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define MATRIX_EBI1CSA_VAL 0x00010100 /* EBI1_CSA, 3.3v, no pull-ups*/ + +/* SDRAM */ +#define SDRC_MR_VAL1 0 /* SDRAMC_MR Mode register */ +#define SDRC_TR_VAL1 0x13C /* SDRAMC_TR - Refresh Timer register*/ +/*#define SDRC_CR_VAL 0x85237279*/ /* SDRAMC_CR - Configuration register*/ +/*#define SDRC_CR_VAL 0x85227259 CL2 */ +#define SDRC_CR_VAL 0x85227279 /*CL3*/ +#define SDRC_MDR_VAL 0 /* Memory Device Register -> SDRAM */ +#define SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */ +#define SDRAM_VAL1 0 /* SDRAM_BASE */ +#define SDRC_MR_VAL3 4 /* SDRC_MR */ +#define SDRAM_VAL2 0 /* SDRAM_BASE */ +#define SDRAM_VAL3 0 /* SDRAM_BASE */ +#define SDRAM_VAL4 0 /* SDRAM_BASE */ +#define SDRAM_VAL5 0 /* SDRAM_BASE */ +#define SDRAM_VAL6 0 /* SDRAM_BASE */ +#define SDRAM_VAL7 0 /* SDRAM_BASE */ +#define SDRAM_VAL8 0 /* SDRAM_BASE */ +#define SDRAM_VAL9 0 /* SDRAM_BASE */ +#define SDRC_MR_VAL4 3 /* SDRC_MR */ +#define SDRAM_VAL10 0 /* SDRAM_BASE */ +#define SDRC_MR_VAL5 0 /* SDRC_MR */ +#define SDRAM_VAL11 0 /* SDRAM_BASE */ +#define SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ +#define SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ +#define SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ +#define SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */ + +/* setup SMC1, CS0 (PSRAM) - 16-bit */ +#define SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */ +#define SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */ +#define SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */ +#define SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */ + +#define RSTC_RMR_VAL 0xA5000301 /* user reset enable */ + +#define AT91_WDTC_WDMR (0xFFFFFD44) /* (WDTC) Watchdog Mode Register */ +#define WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + + mov r5, pc /* r5 = POS1 + 4 current */ +POS1: + ldr r0, =POS1 /* r0 = POS1 compile */ + ldr r2, _TEXT_BASE + sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ + sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ + sub r5, r5, #4 /* r1 = text base - current */ + + /* memory control configuration 1 */ + ldr r0, =SMRDATA + ldr r2, =SMRDATA1 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + +/*----------------------------------------------------------------------------- +;PMC Init Step 1. +;------------------------------------------------------------------------------ +;- Check if the PLL is already initialized +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r0, [r1] + and r0, r0, #3 + cmp r0, #0 + bne setup_PLLB + +/*;--------------------------------------------------------------------------- +;- Enable the Main Oscillator +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + ldr r0, =0x0000FF01 + str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */ + + /* Reading the PMC Status to detect when the Main Oscillator is enabled */ + mov r4, #AT91_PMC_MOSCS +MOSCS_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MOSCS + bne MOSCS_Loop + +/*----------------------------------------------------------------------------- +;PMC Init Step 2. +;------------------------------------------------------------------------------ +;- Setup PLLA +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r0, =PLLAR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLA is locked */ + mov r4, #AT91_PMC_LOCKA +MOSCS_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKA + bne MOSCS_Loop1 + +/*----------------------------------------------------------------------------- +;PMC Init Step 3. +;------------------------------------------------------------------------------ +;- Switch on the Main Oscillator 18.432 MHz +;----------------------------------------------------------------------------*/ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + + /* -Master Clock Controller register PMC_MCKR */ + ldr r0, =0x100 + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop + + ldr r0, =0x102 + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop1 + +/*----------------------------------------------------------------------------- +;PMC Init Step 4. +;------------------------------------------------------------------------------ +;- Setup PLLB +;----------------------------------------------------------------------------*/ +setup_PLLB: + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + mov r4, #AT91_PMC_LOCKB + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKB + beq PLL_setup_end + + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLBR) + ldr r0, =PLLBR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLB is locked */ + mov r4, #AT91_PMC_LOCKB +MOSCS_Loop2: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKB + bne MOSCS_Loop2 + +PLL_setup_end: + + /* memory control configuration 2 */ + ldr r0, =AT91_SDRAMC0_TR + ldr r1, [r0] + cmp r1, #0 + bne SDRAM_setup_end + + ldr r0, =SMRDATA1 + ldr r2, =SMRDATA2 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 + +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + +SDRAM_setup_end: + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word AT91_WDTC_WDMR + .word WDTC_WDMR_VAL + + .word AT91_PIOD_PDR + .word PIOD_PDR_VAL1 + .word AT91_PIOD_PPUDR + .word PIOD_PPUDR_VAL + .word AT91_PIOD_ASR + .word PIOD_PPUDR_VAL + + .word AT91_CCFG_EBI0CSA + .word MATRIX_EBI0CSA_VAL + .word AT91_CCFG_EBI1CSA + .word MATRIX_EBI1CSA_VAL + + /* flash */ + .word AT91_SMC0_CTRL0 + .word SMC0_CTRL0_VAL + + .word AT91_SMC0_CYCLE0 + .word SMC0_CYCLE0_VAL + + .word AT91_SMC0_PULSE0 + .word SMC0_PULSE0_VAL + + .word AT91_SMC0_SETUP0 + .word SMC0_SETUP0_VAL + + /* PSRAM */ + .word AT91_SMC1_CTRL0 + .word SMC1_CTRL0_VAL + + .word AT91_SMC1_CYCLE0 + .word SMC1_CYCLE0_VAL + + .word AT91_SMC1_PULSE0 + .word SMC1_PULSE0_VAL + + .word AT91_SMC1_SETUP0 + .word SMC1_SETUP0_VAL + +SMRDATA1: + .word AT91_SDRAMC0_MR + .word SDRC_MR_VAL1 + .word AT91_SDRAMC0_TR + .word SDRC_TR_VAL1 + .word AT91_SDRAMC0_CR + .word SDRC_CR_VAL + .word AT91_SDRAMC0_MDR + .word SDRC_MDR_VAL + .word AT91_SDRAMC0_MR + .word SDRC_MR_VAL2 + .word SDRAM + .word SDRAM_VAL1 + .word AT91_SDRAMC0_MR + .word SDRC_MR_VAL3 + .word SDRAM + .word SDRAM_VAL2 + .word SDRAM + .word SDRAM_VAL3 + .word SDRAM + .word SDRAM_VAL4 + .word SDRAM + .word SDRAM_VAL5 + .word SDRAM + .word SDRAM_VAL6 + .word SDRAM + .word SDRAM_VAL7 + .word SDRAM + .word SDRAM_VAL8 + .word SDRAM + .word SDRAM_VAL9 + .word AT91_SDRAMC0_MR + .word SDRC_MR_VAL4 + .word SDRAM + .word SDRAM_VAL10 + .word AT91_SDRAMC0_MR + .word SDRC_MR_VAL5 + .word SDRAM + .word SDRAM_VAL11 + .word AT91_SDRAMC0_TR + .word SDRC_TR_VAL2 + .word SDRAM + .word SDRAM_VAL12 + /* User reset enable*/ + .word AT91_RSTC_RMR + .word RSTC_RMR_VAL + /* MATRIX_MCFG - REMAP all masters */ +/* .word AT91_MATRIX_MRCR + .word 0x1FF +*/ + +SMRDATA2: + .word 0 + +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + diff --git a/board/ronetix/pm9263/partition.c b/board/ronetix/pm9263/partition.c new file mode 100644 index 0000000..e4e8a6b --- /dev/null +++ b/board/ronetix/pm9263/partition.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson <ulf(a)atmel.com> + * Ilko Iliev <www.ronetix.at> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +#if (CFG_MAX_DATAFLASH_PART == 1) +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""}, +}; + +#else +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; +#endif diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c new file mode 100644 index 0000000..0953110 --- /dev/null +++ b/board/ronetix/pm9263/pm9263.c @@ -0,0 +1,393 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9263_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#include <lcd.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void pm9263_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +#ifdef CONFIG_CMD_NAND +static void pm9263_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CFG_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CFG_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOCDE); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PB30, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PD15, 1); +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +static void pm9263_spi_hw_init(void) +{ + at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */ + + at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); +} +#endif + +#ifdef CONFIG_MACB +static void pm9263_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); + + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUER); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + + at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ + at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ +#endif + +} +#endif + +#ifdef CONFIG_USB_OHCI_NEW +static void pm9263_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_gpio_output(AT91_PIN_PA21, 0); + at91_set_gpio_output(AT91_PIN_PA24, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91SAM9263_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */ +} + +#ifdef LCD_IN_PSRAM + +#define PSRAM_CRE_PIN AT91_PIN_PB29 +#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2) + +/* Initialize the PSRAM memory */ +static int pm9263_lcd_hw_psram_init(void) +{ +volatile uint16_t *p; +volatile uint16_t x; + + /* setup PB29 as output */ + at91_set_gpio_output(PSRAM_CRE_PIN, 1); + + at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ + + p = (volatile uint16_t *) PSRAM_CTRL_REG; + + /* PSRAM: write BCR */ + x = *p; /* mem r16 0x703ffffe 1 */ + x = *p; /* mem r16 0x703ffffe 1 */ + *p = 1; /* mem w16 0x703ffffe 1 ; 0 for RCR, 1 for BCR */ + *p = 0x9d4f; /* write the BCR */ + + /* write RCR of the PSRAM */ + p = (volatile uint16_t *) PSRAM_CTRL_REG; + x = *p; /* mem r16 0x703ffffe 1 */ + x = *p; /* mem r16 0x703ffffe 1 */ + *p = 0; /* mem w16 0x703ffffe 0 ; 0 for RCR, 1 for BCR */ + + *p = 0x90; /* set RCR; 0x10 - async mode, 0x90 - page mode */ + + /* test to see if the PSRAM is MT45W2M16A or MT45W2M16B + MT45W2M16B - CRE must be 0 + MT45W2M16A - CRE must be 1 + */ + p = (volatile uint16_t *) PHYS_PSRAM; + p[0] = 0x1234; + p[1] = 0x5678; + + /* test if the chip is MT45W2M16B */ + if ( (p[0] != 0x1234) || (p[1] != 0x5678) ) + { + /* try with CRE=1 (MT45W2M16A) */ + at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ + + /* write RCR of the PSRAM */ + p = (volatile uint16_t *) PSRAM_CTRL_REG; + x = *p; /* mem r16 0x703ffffe 1 */ + x = *p; /* mem r16 0x703ffffe 1 */ + *p = 0; /* mem w16 0x703ffffe 0 ; 0 for RCR, 1 for BCR */ + + *p = 0x90; /* set RCR; 0x10 - async mode, 0x90 - page mode */ + + p = (volatile uint16_t *) PHYS_PSRAM; + p[0] = 0x1234; + p[1] = 0x5678; + if ( (p[0] != 0x1234) || (p[1] != 0x5678) ) + return 1; + + } + return 0; +} +#endif + + +static void pm9263_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC); + + /* Power Control */ + at91_set_gpio_output(AT91_PIN_PA22, 1); + at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */ + +#ifdef LCD_IN_PSRAM + /* initialize te PSRAM */ + int stat = pm9263_lcd_hw_psram_init(); + + gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE; +#else + gd->fb_base = AT91SAM9263_SRAM0_BASE; +#endif + +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* PB27 enables the 50MHz oscillator for Ethernet PHY + 1 - enable + 0 - disable */ + at91_set_gpio_output(AT91_PIN_PB27, 1); + at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */ + + /* arch number of AT91SAM9263EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PM9263; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + pm9263_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + pm9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + pm9263_spi_hw_init(); +#endif +#ifdef CONFIG_MACB + pm9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + pm9263_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + pm9263_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x01); +#endif + return rc; +} diff --git a/board/ronetix/pm9263/pm9263_nand.c b/board/ronetix/pm9263/pm9263_nand.c new file mode 100644 index 0000000..03f5ac2 --- /dev/null +++ b/board/ronetix/pm9263/pm9263_nand.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +static void pm9263_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int pm9263_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(AT91_PIN_PB30); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; +#ifdef CFG_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->cmd_ctrl = pm9263_nand_hwcontrol; + nand->dev_ready = pm9263_nand_ready; + nand->chip_delay = 20; + + return 0; +} diff --git a/common/lcd.c b/common/lcd.c index 25f8664..9f81031 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -824,14 +824,23 @@ static void *lcd_logo (void) #ifdef CONFIG_ATMEL_LCD # ifdef CONFIG_LCD_INFO + sprintf (info, "%s", U_BOOT_VERSION); lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info)); +#ifdef CONFIG_LCD_LOGO_TEXT1 + sprintf (info, CONFIG_LCD_LOGO_TEXT1); +#else sprintf (info, "(C) 2008 ATMEL Corp"); +#endif lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT, (uchar *)info, strlen(info)); +#ifdef CONFIG_LCD_LOGO_TEXT2 + sprintf (info, CONFIG_LCD_LOGO_TEXT2); +#else sprintf (info, "at91support(a)atmel.com"); +#endif lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2, (uchar *)info, strlen(info)); diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index ec6ad5d..7882e89 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -27,7 +27,7 @@ #include <config.h> #include <version.h> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_USER_LOWLEVEL_INIT) .globl lowlevel_init lowlevel_init: @@ -39,5 +39,5 @@ lowlevel_init: mov pc, lr .ltorg - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_USER_LOWLEVEL_INIT */ diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c index 049da69..e926b38 100644 --- a/drivers/mtd/dataflash.c +++ b/drivers/mtd/dataflash.c @@ -130,8 +130,9 @@ int AT91F_DataflashInit (void) dfcode = 0; break; } + /* set the last area end to the dataflash size*/ - area_list[NB_DATAFLASH_AREA -1].end = + dataflash_info[i].end_address = (dataflash_info[i].Device.pages_number * dataflash_info[i].Device.pages_size)-1; @@ -146,7 +147,7 @@ int AT91F_DataflashInit (void) if(area_list[part].end == 0xffffffff) { dataflash_info[i].Device.area_list[j].end = dataflash_info[i].end_address + - dataflash_info [i].logical_address; + dataflash_info[i].logical_address; last_part = 1; } else { dataflash_info[i].Device.area_list[j].end = diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h new file mode 100644 index 0000000..1646e9f --- /dev/null +++ b/include/configs/pm9263.h @@ -0,0 +1,285 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * Configuation settings for the RONETIX PM9263 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9263" + +#define PM9263_CRYSTAL 18432000 +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 + +#define AT91_MAIN_CLOCK (PM9263_CRYSTAL / MASTER_PLL_DIV * MASTER_PLL_MUL) +#define AT91_MASTER_CLOCK (AT91_MAIN_CLOCK / MAIN_PLL_DIV) + +#define CFG_HZ 1000000 /* 1us resolution */ + +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_USER_LOWLEVEL_INIT 1 + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_LOGO_TEXT1 "(C) 2008 Ronetix GmbH" +#define CONFIG_LCD_LOGO_TEXT2 "support(a)ronetix.at" +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CFG_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define LCD_IN_PSRAM 1 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_IDENT_STRING "\r\n""Ronetix PM9263 Board" + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_HAS_DATAFLASH 1 +#define CFG_SPI_WRITE_TOUT (5*CFG_HZ) +#define CFG_MAX_DATAFLASH_PART 1 +#define CFG_MAX_DATAFLASH_BANKS 1 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash, if populated */ +#if 0 +#define CFG_NO_FLASH 1 +#else +#define CFG_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_SECT 256 +#define CFG_MAX_FLASH_BANKS 1 +#endif + +/* NAND flash */ +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 +#define CFG_NAND_DBW_8 1 + +/* PSRAM */ +#define PHYS_PSRAM 0x70000000 +#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_OHCI_NEW 1 +#define LITTLEENDIAN 1 +#define CONFIG_DOS_PARTITION 1 +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_USB_OHCI_SLOT_NAME "at91sam9263" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CFG_LOAD_ADDR 0x22000000 /* load address */ + +#define CFG_MEMTEST_START PHYS_SDRAM +#define CFG_MEMTEST_END 0x23e00000 + +#define CFG_USE_FLASH 1 +#undef CFG_USE_DATAFLASH +#undef CFG_USE_NANDFLASH + +#ifdef CFG_USE_DATAFLASH + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) "\ + "rw rootfstype=jffs2" + +#elif defined(CFG_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#elif defined(CFG_USE_FLASH) /* CFG_USE_FLASH */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 + +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_ROOTPATH /ronetix/rootfs +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" + +#define CONFIG_CON_ROT "fbcon=rotate:3 " +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "256k(u-boot)ro," \ + "64k(u-boot-env)ro," \ + "1408k(kernel)," \ + "-(rootfs);" \ + "nand:-(nand)" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + CONFIG_CON_ROT \ + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x22000000 vmImage;" \ + "run ramargs;run addip;bootm 22000000\0" \ + "nfsboot=tftpboot 0x22000000 vmImage;" \ + "run nfsargs;run addip;bootm 22000000\0" \ + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ + "" + +#else +#error "Undefined memory device" +#endif + +#define CONFIG_IPADDR 192.168.3.222 +#define CONFIG_GATEWAYIP 192.168.3.1 +#define CONFIG_ETHADDR 02:DE:AD:BE:EF:01 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.3.1 +#define CONFIG_HOSTNAME PM9263 + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CFG_PROMPT "u-boot-pm9263> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/tools/Makefile b/tools/Makefile index 9e9ee15..fbc64ba 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -47,6 +47,9 @@ endif ifeq ($(VENDOR),atmel) LOGO_BMP= logos/atmel.bmp endif +ifeq ($(VENDOR),ronetix) +LOGO_BMP= logos/ronetix.bmp +endif #------------------------------------------------------------------------- diff --git a/tools/logos/ronetix.bmp b/tools/logos/ronetix.bmp new file mode 100644 index 0000000000000000000000000000000000000000..f956813915c7822ba11a3ab81ad9f48fa2849a5c GIT binary patch literal 5638 zc%03cKU~{J6vq!FPL^XEQ4<1A027nM#06YR5|^g@OKA-xvFpaEo7M?2RUxKo5Z8f` zk&)3OBO@bYMn*=D9z8NL_UZmevTPuqe43=c5AXA&)4g|Jo$j7w=AYmmM1|WCii6(= zi-NTwAG^>E=VQ$NLCl!oy3YrH8uDqD^&-u(Udy7W*Rp67MXAM6G#*FscoM~vNt8^c zP%@Q5DQdGQH9L!Dsio0uI*roQvXJKlrL$R-rB;A^Cty{SEfgSU6&1i23M-Hsj#pOD z3RpZ@1;36~*4JT-Dq07hqJ9&`0l&G4Ho<1oRq)#|4)|^G*(%xwzrDSKws&@5j2hYj zU!Z;$?d<NNU21!ftA=*>_Rt>K`eqIC)Zn;+_9_*Kub~R~N@X8a_V>{~wF8K&qy2*e zbU^J89ULB_L$FGv4*m!o9a;7cuGP`eJMf2f^bY)?<&TfiG1$@3Dfkm;2Y+&cPN-F( z?G#n3RXDbM4OMGk)l*ahU#r)_pP{<t>y`&QJw>O~&d}M}8G1<m-%=+&H^IdU$jQ%* zaG`>V<efpIqzjeIa%O(6QS(bh==6GeZf-j3idvp#m#6c@n4f8gn3*fnE{j$(4Jy+f zGYdNJIbCuCJj-w`l}J!k<?#l*)vy|1x`LBSAuM@?)lrkA+a#&&h7&a-uA)(*E1rn9 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[U-Boot] [PATCH 1/2][for v2008.10] Revert "85xx: Using proper I2C source clock divider for MPC8544"
by Kumar Gala 20 Oct '08

20 Oct '08

This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. The fix introduced by this patch is not correct. The problem is that the documentation is not correct for the MPC8544 with regards to which bit in PORDEVSR2 is for the SEC_CFG. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/speed.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 70dfad0..485ba20 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 2; - else gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; -- 1.5.5.1

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[U-Boot] Atmel AT91RM9200: U-Boot refuses to copy to a particular sector of flash memory
by Ki Chi Leung 20 Oct '08

20 Oct '08

Hello list, I am trying to load a Linux 2.6.22 kernel uimage on the flash memory of a custom Atmel AT91RM9200 board. From U-Boot the flash memory map is as follows: U-Boot> flinfo DataFlash:AT45DB161 Nb pages: 4096 Page Size: 528 Size= 2162688 bytes Logical address: 0xC0000000 Area 0: C0000000 to C0007FFF (RO) Area 1: C0008000 to C001FFFF (RO) Area 2: C0020000 to C0027FFF Area 3: C0028000 to C020FFFF Bank # 1: Atmel: AT49BV163D (16Mbit) Size: 2 MB in 39 Sectors Sector Start Addresses: 10000000 (RO) 10002000 (RO) 10004000 (RO) 10006000 10008000 1000A000 1000C000 1000E000 (RO) 10010000 (RO) 10020000 10030000 10040000 10050000 10060000 10070000 10080000 10090000 100A0000 100B0000 100C0000 100D0000 100E0000 100F0000 10100000 10110000 10120000 10130000 10140000 10150000 10160000 10170000 10180000 10190000 101A0000 101B0000 101C0000 101D0000 101E0000 101F0000 I also have 2x 48LC8M16A2 modules (32MB, SDRAM, address 0x20000000 - 0x21ffffff) which I download the kernel to before copying to flash. I have to copy the kernel into the flash starting at address 0x10020000 (lower addresses reserved by U-Boot apparently). However, when I try to copy the 1018KB uimage, the copy always fails with "flash not erased", even after the sectors have been unprotected and erased. I found that if I copy anything into the sector starting at 0x10100000, U-Boot will fail to start from the flash. The sector in question can be unprotected and erased without problems. Is there any way to find out why U-Boot will not let me copy to this sector, and why erasing and/or trying to copying to it would cause U-Boot not to start anymore? Thanks in advance. P.S. This is my first post here, apologies if I missed out any important info.

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[U-Boot] Load a kernel image
by Ivan Llopard 20 Oct '08

20 Oct '08

Hi list, I'm working with an embeded system. I'm sure you know about the microprocessor NIOS2. I have chose u-boot and it runs perfectly in my platform. But it can't read my memory SD card how i have it configured. I would like to know how to load the kernel image (uclinux) in memory correctly by myself, i mean without u-boot, or where i can find some information about it. I got the image of kernel uclinux in elf format and i get errors with gzip magic numbers when i try to load my image at his linked address. I would like also to develop a SPI driver for u-boot in order to read SD cards memory, i don't know if it's already developed. Regards, Iván.

1 0

[U-Boot] [PATCH] Handle environment variables like commands
by Stefano Babic 20 Oct '08

20 Oct '08

The command interpreter checks always if an environment variable for that name exists and in this case the content of the variable is executed. It becomes possible to redefine all U-Boot commands. A new "builtin" command is added to be able to run builtin U-boot commands even if they are redefined. For this reason, builtin is a reserved word an no environment variable can be set with this name. Signed-off-by : Stefano Babic <sbabic(a)denx.de> --- common/cmd_nvedit.c | 8 ++++++++ common/hush.c | 9 ++++++++- common/main.c | 37 +++++++++++++++++++++++++++++++++++++ tools/env/fw_env.c | 8 ++++++++ 4 files changed, 61 insertions(+), 1 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 637d6c9..c6e4ec7 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -161,6 +161,14 @@ int _do_setenv (int flag, int argc, char *argv[]) } /* + * Check for reserved words + */ + if (strcmp(name, "builtin") == 0) { + printf ("## Error: builtin is a reserved word. You cannot set a variable with this name\n"); + return 1; + } + + /* * search if variable with this name already exists */ oldval = -1; diff --git a/common/hush.c b/common/hush.c index 093c428..bd7b223 100644 --- a/common/hush.c +++ b/common/hush.c @@ -1677,9 +1677,16 @@ static int run_pipe_real(struct pipe *pi) child->argv[i]); return -1; } - /* Look up command in command table */ + /* Check if exists a variable with that name, builtin is forbidden */ + if ((strcmp (child->argv[i], "builtin") != 0) && (p = getenv (child->argv[i])) != NULL ) { + int rcode; + rcode = (parse_string_outer(p, + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0); + return rcode; + } + /* Look up command in command table */ if ((cmdtp = find_cmd(child->argv[i])) == NULL) { printf ("Unknown command '%s' - try 'help'\n", child->argv[i]); return -1; /* give up after bad command */ diff --git a/common/main.c b/common/main.c index c06ea07..d2be2ac 100644 --- a/common/main.c +++ b/common/main.c @@ -1289,6 +1289,7 @@ int run_command (const char *cmd, int flag) int argc, inquotes; int repeatable = 1; int rc = 0; + char *runenv; #ifdef DEBUG_PARSER printf ("[RUN_COMMAND] cmd[%p]=\"", cmd); @@ -1357,6 +1358,13 @@ int run_command (const char *cmd, int flag) continue; } + if ((strcmp (argv[0], "builtin") != 0) && ((runenv = getenv (argv[0])) != NULL )) { + if (run_command(runenv,flag) == -1) { + rc = -1; + } + continue; + } + /* Look up command in command table */ if ((cmdtp = find_cmd(argv[0])) == NULL) { printf ("Unknown command '%s' - try 'help'\n", argv[0]); @@ -1433,3 +1441,32 @@ int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } #endif + +int do_builtin (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Look up command in command table */ + if ((cmdtp = find_cmd(argv[1])) == NULL) { + printf ("Unknown builtin command '%s' - try 'help'\n", argv[1]); + return 1; + } + + /* Remove builtin from arg list */ + argc--; + + /* OK - call function to do the command */ + if ((cmdtp->cmd) (cmdtp, flag, argc, &argv[1]) != 0) { + return 1; + } +} + +U_BOOT_CMD( + builtin, CFG_MAXARGS, 1, do_builtin, + "builtin - run builtin commands\n", +); diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 6e9c34f..cc31b79 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -353,6 +353,14 @@ int fw_setenv (int argc, char *argv[]) name = argv[1]; /* + * Check for reserved words + */ + if (strcmp(name, "builtin") == 0) { + errno = EINVAL; + return -1; + } + + /* * search if variable with this name already exists */ for (nxt = env = environment.data; *env; env = nxt + 1) { -- 1.5.4.3

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[U-Boot] [PATCH] TQM8260: environment in flash instead EEPROM, baudrate 115k
by Heiko Schocher 20 Oct '08

20 Oct '08

Hello Wolfgang, Wolfgang Denk wrote: > Several customers have reported problems with the environment in > EEPROM, including corrupted content after board reset. Probably the > code to prevent I2C Enge Conditions is not working sufficiently. Is this somewhere reproducible? Maybe we can try my patch from: http://lists.denx.de/pipermail/u-boot/2008-October/041817.html also for this board. The I2C deblocking is in i2c_make_abort () ... If this works better, maybe we use this I2C deblocking mechanism as new standard? > We move the environment to flash now, which allows to have a backup > copy plus gives much faster boot times. [...] > --- a/board/tqc/tqm8260/flash.c > +++ b/board/tqc/tqm8260/flash.c Couldnt use this board also the CFI driver? bye Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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