October 2008 - U-Boot

[U-Boot] [PATCH] [83xx] Removed #ifdef CONFIG_MPC834X dependency on upmconfig function
by richardretanubun 17 Oct '08

17 Oct '08

Removed #ifdef CONFIG_MPC834X dependency on upmconfig function. Signed-off-by: Richard Retanubun <RichardRetanubun(a)RugggedCom.com> --- cpu/mpc83xx/cpu.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 99ab216..848b8fd 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -147,7 +147,6 @@ int checkcpu(void) */ void upmconfig (uint upm, uint *table, uint size) { -#if defined(CONFIG_MPC834X) volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile lbus83xx_t *lbus = &immap->lbus; volatile uchar *dummy = NULL; @@ -181,10 +180,6 @@ void upmconfig (uint upm, uint *table, uint size) /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ *mxmr &= 0xCFFFFFC0; -#else - printf("Error: %s() not defined for this configuration.\n", __FUNCTION__); - hang(); -#endif } -- 1.5.5.GIT

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[U-Boot] [POWERPC v2] mgsuvd: fix coding style
by Heiko Schocher 17 Oct '08

17 Oct '08

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/keymile/mgsuvd/mgsuvd.c | 98 +++++++++++++---------------------------- include/configs/mgsuvd.h | 10 ++--- 2 files changed, 35 insertions(+), 73 deletions(-) diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c index 912e177..d74cb92 100644 --- a/board/keymile/mgsuvd/mgsuvd.c +++ b/board/keymile/mgsuvd/mgsuvd.c @@ -20,11 +20,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - -#if 0 -#define DEBUG -#endif - #include <common.h> #include <mpc8xx.h> @@ -154,83 +149,52 @@ int hush_init_var (void) } #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) + +#define FDT_SET_NODE_VALUE(nodename, reg, var, size) \ + nodeoffset = fdt_path_offset (blob, nodename); \ + if (nodeoffset >= 0) { \ + ret = fdt_setprop (blob, nodeoffset, reg, var, \ + size); \ + if (ret < 0) \ + printf("ft_blob_update(): cannot set %s/%s " \ + "property err:%s\n", nodename, reg, \ + fdt_strerror (ret)); \ + } else { \ + printf("ft_blob_update(): cannot find %s node " \ + "err:%s\n", nodename, fdt_strerror (nodeoffset)); \ + } + /* * update "memory" property in the blob */ -void ft_blob_update(void *blob, bd_t *bd) +void ft_blob_update (void *blob, bd_t *bd) { int ret, nodeoffset = 0; ulong brg_data[1] = {0}; ulong memory_data[2] = {0}; ulong flash_data[4] = {0}; - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); - - nodeoffset = fdt_path_offset (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /memory/reg " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); - } - - flash_data[2] = cpu_to_be32(bd->bi_flashstart); - flash_data[3] = cpu_to_be32(bd->bi_flashsize); - nodeoffset = fdt_path_offset (blob, "/localbus"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, - sizeof(flash_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /localbus/ranges " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /localbus node " - "err:%s\n", fdt_strerror(nodeoffset)); - } + memory_data[0] = cpu_to_be32 (bd->bi_memstart); + memory_data[1] = cpu_to_be32 (bd->bi_memsize); + FDT_SET_NODE_VALUE("/memory", "reg", memory_data, sizeof (memory_data)) + + flash_data[2] = cpu_to_be32 (bd->bi_flashstart); + flash_data[3] = cpu_to_be32 (bd->bi_flashsize); + FDT_SET_NODE_VALUE("/localbus", "ranges", flash_data, + sizeof (flash_data)) /* BRG */ - brg_data[0] = cpu_to_be32(bd->bi_busfreq); - nodeoffset = fdt_path_offset (blob, "/soc/cpm"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data, - sizeof(brg_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /soc/cpm node " - "err:%s\n", fdt_strerror(nodeoffset)); - } + brg_data[0] = cpu_to_be32 (bd->bi_busfreq); + FDT_SET_NODE_VALUE("/soc/cpm", "brg-frequency", brg_data, + sizeof (brg_data)) /* MAC Adresse */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, - sizeof(uchar) * 6); - if (ret < 0) - printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror(nodeoffset)); - } + FDT_SET_NODE_VALUE("/soc/cpm/ethernet", "mac-address", + bd->bi_enetaddr, sizeof (uchar) * 6) } void ft_board_setup(void *blob, bd_t *bd) { - ft_cpu_setup( blob, bd); - ft_blob_update(blob, bd); + ft_cpu_setup (blob, bd); + ft_blob_update (blob, bd); } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index 7a80dad..416e4db 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -359,18 +359,16 @@ #define I2C_READ i2c_soft_read_pin () #define I2C_SDA(bit) if(bit) { \ *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; \ - } \ - else { \ + } else { \ *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \ *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \ - } + } #define I2C_SCL(bit) if(bit) { \ *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; \ - } \ - else { \ + } else { \ *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \ *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \ - } + } #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */ #define CONFIG_I2C_MULTI_BUS 1 -- 1.5.6.1 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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Re: [U-Boot] [PATCH 01/10] Fix IP alignement problem
by Ben Warren 17 Oct '08

17 Oct '08

Hi Olav, On Fri, Oct 10, 2008 at 11:53 AM, Olav Morken <olavmrk(a)gmail.com> wrote: > On Fri, Oct 10, 2008 at 7:01 PM, Ben Warren <biggerbadderben(a)gmail.com> > wrote: > > Olav Morken wrote: > >> > >> This patch removes volatile from: > >> volatile IP_t *ip = (IP_t *)xip; > >> > >> Due to a bug, avr32-gcc will assume that ip is aligned on a word > boundary > >> when > >> using volatile, which causes an exception since xip isn't aligned on a > >> word > >> boundary. > >> > > > > What other architectures have you tried this on? > > None, as we don't have any other boards to test on. I do however believe > that this change should have no side-effects. If any architectures > relied on this function working as some sort of memory/io barrier, they > would have problems with other functions such as ArpRequest, which > doesn't have anything that will work as a memory/io barrier before the > eth_send function. > > Of course, I could be wrong. I would certainly not suggest including > this change without some more testing. > > The bug which causes this problem is in avr32-gcc, which makes > assumptions about the alignement of IP_t when using volatile, and this > change shouldn't be necessary once that bug is fixed. Until that bug > is fixed, this change is needed for anyone trying to run U-Boot on > this microcontroller. > I don't mean to be a pain, it's just that this code is shared by everything, so we need to be really careful. I agree with Haavard that the volatile keyword is probably used much more than it should be in the networking library. I'll pull this into the net/testing branch in the next couple of days, and hopefully we'll get some volunteers to try it out on different architectures. regards, Ben

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[U-Boot] [PATCH] ppc4xx: PPC44x MQ initialization
by Stefan Roese 17 Oct '08

17 Oct '08

From: Yuri Tikhonov <yur(a)emcraft.com> Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov <yur(a)emcraft.com> Signed-off-by: Stefan Roese <sr(a)denx.de> --- Yuri, I changed the patch description a little bit. Please let me know if you have any objections or if this is ok with you. Thanks. cpu/ppc4xx/44x_spd_ddr2.c | 10 ++++++---- include/asm-ppc/ppc4xx-sdram.h | 5 +++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f1d7684..995d5fe 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated, /* * Set optimal value for Memory Queue HB/LL Configuration registers */ - mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | - SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); - mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | - SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) | + SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE | + SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL); + mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) | + SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE | + SDRAM_CONF1LL_RPLM); mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); #endif } diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..98faced 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -272,8 +272,11 @@ #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ +#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ @@ -284,8 +287,10 @@ #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -- 1.6.0.2

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[U-Boot] [PATCH] 440spe MQ initialization
by Yuri Tikhonov 17 Oct '08

17 Oct '08

Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Signed-off-by: Yuri Tikhonov <yur(a)emcraft.com> --- cpu/ppc4xx/44x_spd_ddr2.c | 10 ++++++---- include/asm-ppc/ppc4xx-sdram.h | 5 +++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index f1d7684..995d5fe 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2261,10 +2261,12 @@ static void program_memory_queue(unsigned long *dimm_populated, /* * Set optimal value for Memory Queue HB/LL Configuration registers */ - mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | - SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); - mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | - SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) | + SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE | + SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL); + mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) | + SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE | + SDRAM_CONF1LL_RPLM); mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); #endif } diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..98faced 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -272,8 +272,11 @@ #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ +#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ @@ -284,8 +287,10 @@ #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -- 1.5.6.1 Regards, Yuri -- Yuri Tikhonov, Senior Software Engineer Emcraft Systems, www.emcraft.com

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[U-Boot] [POWERPC] mgsuvd: fix codingstyle
by Heiko Schocher 17 Oct '08

17 Oct '08

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/keymile/mgsuvd/mgsuvd.c | 67 +++++++++++++++++----------------------- include/configs/mgsuvd.h | 10 ++---- 2 files changed, 33 insertions(+), 44 deletions(-) diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c index 912e177..de4668c 100644 --- a/board/keymile/mgsuvd/mgsuvd.c +++ b/board/keymile/mgsuvd/mgsuvd.c @@ -20,11 +20,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - -#if 0 -#define DEBUG -#endif - #include <common.h> #include <mpc8xx.h> @@ -157,80 +152,76 @@ int hush_init_var (void) /* * update "memory" property in the blob */ -void ft_blob_update(void *blob, bd_t *bd) +void ft_blob_update (void *blob, bd_t *bd) { int ret, nodeoffset = 0; ulong brg_data[1] = {0}; ulong memory_data[2] = {0}; ulong flash_data[4] = {0}; - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); + memory_data[0] = cpu_to_be32 (bd->bi_memstart); + memory_data[1] = cpu_to_be32 (bd->bi_memsize); - nodeoffset = fdt_path_offset (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); + nodeoffset = fdt_path_offset (blob, "/memory"); + if (nodeoffset >= 0) { + ret = fdt_setprop (blob, nodeoffset, "reg", memory_data, + sizeof (memory_data)); if (ret < 0) printf("ft_blob_update(): cannot set /memory/reg " - "property err:%s\n", fdt_strerror(ret)); - } - else { + "property err:%s\n", fdt_strerror (ret)); + } else { /* memory node is required in dts */ printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); + "err:%s\n", fdt_strerror (nodeoffset)); } - flash_data[2] = cpu_to_be32(bd->bi_flashstart); - flash_data[3] = cpu_to_be32(bd->bi_flashsize); + flash_data[2] = cpu_to_be32 (bd->bi_flashstart); + flash_data[3] = cpu_to_be32 (bd->bi_flashsize); nodeoffset = fdt_path_offset (blob, "/localbus"); if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, - sizeof(flash_data)); + ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data, + sizeof (flash_data)); if (ret < 0) printf("ft_blob_update(): cannot set /localbus/ranges " - "property err:%s\n", fdt_strerror(ret)); - } - else { + "property err:%s\n", fdt_strerror (ret)); + } else { /* memory node is required in dts */ printf("ft_blob_update(): cannot find /localbus node " - "err:%s\n", fdt_strerror(nodeoffset)); + "err:%s\n", fdt_strerror (nodeoffset)); } /* BRG */ - brg_data[0] = cpu_to_be32(bd->bi_busfreq); + brg_data[0] = cpu_to_be32 (bd->bi_busfreq); nodeoffset = fdt_path_offset (blob, "/soc/cpm"); if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data, - sizeof(brg_data)); + ret = fdt_setprop (blob, nodeoffset, "brg-frequency", brg_data, + sizeof (brg_data)); if (ret < 0) printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency " "property err:%s\n", fdt_strerror(ret)); - } - else { + } else { /* memory node is required in dts */ printf("ft_blob_update(): cannot find /soc/cpm node " - "err:%s\n", fdt_strerror(nodeoffset)); + "err:%s\n", fdt_strerror (nodeoffset)); } /* MAC Adresse */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, - sizeof(uchar) * 6); + ret = fdt_setprop (blob, nodeoffset, "mac-address", bd->bi_enetaddr, + sizeof (uchar) * 6); if (ret < 0) printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address " - "property err:%s\n", fdt_strerror(ret)); - } - else { + "property err:%s\n", fdt_strerror (ret)); + } else { /* memory node is required in dts */ printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror(nodeoffset)); + "err:%s\n", fdt_strerror (nodeoffset)); } } void ft_board_setup(void *blob, bd_t *bd) { - ft_cpu_setup( blob, bd); - ft_blob_update(blob, bd); + ft_cpu_setup (blob, bd); + ft_blob_update (blob, bd); } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index 7a80dad..416e4db 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -359,18 +359,16 @@ #define I2C_READ i2c_soft_read_pin () #define I2C_SDA(bit) if(bit) { \ *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; \ - } \ - else { \ + } else { \ *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \ *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \ - } + } #define I2C_SCL(bit) if(bit) { \ *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; \ - } \ - else { \ + } else { \ *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \ *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \ - } + } #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */ #define CONFIG_I2C_MULTI_BUS 1 -- 1.5.6.1 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] [POWERPC v2] mgcoge: Second Flash on CS5 not on CS1
by Heiko Schocher 17 Oct '08

17 Oct '08

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/keymile/mgcoge/mgcoge.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index 7d4d9e6..bf6ce87 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -334,7 +334,7 @@ void ft_blob_update (void *blob, bd_t *bd) /* update Flash addr, size */ flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE); flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE); - flash_data[4] = cpu_to_be32 (1); + flash_data[4] = cpu_to_be32 (5); flash_data[5] = cpu_to_be32 (0); flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1); flash_data[7] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE_1); -- 1.5.6.1 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] [POWERPC v3] mgsuvd: fix compiler warning when using soft_i2c driver
by Heiko Schocher 17 Oct '08

17 Oct '08

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/keymile/common/common.c | 3 ++- drivers/i2c/soft_i2c.c | 4 ++++ include/configs/mgsuvd.h | 24 +++++++++++++++--------- 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 61276d2..e47928d 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -34,6 +34,7 @@ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include <i2c.h> #endif +#include <asm/io.h> extern int i2c_soft_read_pin (void); @@ -400,7 +401,7 @@ static void set_scl (int state) static int get_sda (void) { - return i2c_soft_read_pin (); + return I2C_READ; } static int get_scl (void) diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 508d3d7..ebe60e2 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -28,6 +28,7 @@ #include <common.h> #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ #include <ioports.h> +#include <asm/io.h> #endif #ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ #include <asm/io.h> @@ -39,6 +40,9 @@ #ifdef CONFIG_LPC2292 #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_MPC866 /* only valid for MPC866 */ +#include <asm/io.h> +#endif #include <i2c.h> /* #define DEBUG_I2C */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index 416e4db..c4a0ed0 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -346,8 +346,8 @@ /* * Software (bit-bang) I2C driver configuration */ -#define I2C_BASE_DIR (CONFIG_SYS_PIGGY_BASE + 0x04) -#define I2C_BASE_PORT (CONFIG_SYS_PIGGY_BASE + 0x09) +#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04)) +#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09)) #define SDA_BIT 0x40 #define SCL_BIT 0x80 @@ -356,18 +356,24 @@ #define I2C_ACTIVE do {} while (0) #define I2C_TRISTATE do {} while (0) -#define I2C_READ i2c_soft_read_pin () +#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT) #define I2C_SDA(bit) if(bit) { \ - *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; \ + out_be16(I2C_BASE_DIR, \ + in_be16(I2C_BASE_DIR) & ~SDA_CONF); \ } else { \ - *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \ - *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \ + out_8(I2C_BASE_PORT, \ + in_8(I2C_BASE_PORT) & ~SDA_BIT); \ + out_be16(I2C_BASE_DIR, \ + in_be16(I2C_BASE_DIR) | SDA_CONF); \ } #define I2C_SCL(bit) if(bit) { \ - *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; \ + out_be16(I2C_BASE_DIR, \ + in_be16(I2C_BASE_DIR) & ~SCL_CONF); \ } else { \ - *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \ - *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \ + out_8(I2C_BASE_PORT, \ + in_8(I2C_BASE_PORT) & ~SCL_BIT); \ + out_be16(I2C_BASE_DIR, \ + in_be16(I2C_BASE_DIR) | SCL_CONF); \ } #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */ -- 1.5.6.1 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] Incorrect Chip ID for Micrel Nand Flash on AT91SAM9260 board
by Kevin Greer 17 Oct '08

17 Oct '08

Hello, I am working with a custom board based on the Atmel at91sam9260 arm processor with a Micrel 2 Gb Nand flash chip (mt29f2g08aadwp). However, when u-boot starts it reports the wrong Chip ID (0x01 instead of 0xda) and then I start getting Bad eraseblock messages during the rest of the boot process. The strange thing is that when I debug the board using a JTAG it gets the correct Chip ID and boots properly. I am hoping that someone else might have run into a similar problem, or might have an idea of how to proceed. Thanks, Kevin

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[U-Boot] [PATCH] ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directory
by Roman Mashak 17 Oct '08

17 Oct '08

OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory. It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap Signed-off-by: Roman Mashak <romez777(a)gmail.com> --- cpu/arm926ejs/Makefile | 2 +- cpu/arm926ejs/cpuinfo.c | 242 ------------------------------------------- cpu/arm926ejs/omap/Makefile | 2 +- 3 files changed, 2 insertions(+), 244 deletions(-) diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile index 0facce4..d5ac7d3 100644 --- a/cpu/arm926ejs/Makefile +++ b/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o cpuinfo.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm926ejs/cpuinfo.c b/cpu/arm926ejs/cpuinfo.c deleted file mode 100644 index 35ba7db..0000000 --- a/cpu/arm926ejs/cpuinfo.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * OMAP1 CPU identification code - * - * Copyright (C) 2004 Nokia Corporation - * Written by Tony Lindgren <tony(a)atomide.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <command.h> -#include <arm926ejs.h> - -#if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) - -#define omap_readw(x) *(volatile unsigned short *)(x) -#define omap_readl(x) *(volatile unsigned long *)(x) - -#define OMAP_DIE_ID_0 0xfffe1800 -#define OMAP_DIE_ID_1 0xfffe1804 -#define OMAP_PRODUCTION_ID_0 0xfffe2000 -#define OMAP_PRODUCTION_ID_1 0xfffe2004 -#define OMAP32_ID_0 0xfffed400 -#define OMAP32_ID_1 0xfffed404 - -struct omap_id { - u16 jtag_id; /* Used to determine OMAP type */ - u8 die_rev; /* Processor revision */ - u32 omap_id; /* OMAP revision */ - u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */ -}; - -/* Register values to detect the OMAP version */ -static struct omap_id omap_ids[] = { - { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, - { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, - { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, - { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, - { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, - { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, - { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00}, - { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00}, - { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, - { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, - { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000}, - { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00}, - { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00}, - { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300}, - { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300}, - { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300}, - { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000}, - { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000}, - { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000}, -}; - -/* - * Get OMAP type from PROD_ID. - * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM. - * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense. - * Undocumented register in TEST BLOCK is used as fallback; This seems to - * work on 1510, 1610 & 1710. The official way hopefully will work in future - * processors. - */ -static u16 omap_get_jtag_id(void) -{ - u32 prod_id, omap_id; - - prod_id = omap_readl(OMAP_PRODUCTION_ID_1); - omap_id = omap_readl(OMAP32_ID_1); - - /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */ - if (((prod_id >> 20) == 0) || (prod_id == omap_id)) - prod_id = 0; - else - prod_id &= 0xffff; - - if (prod_id) - return prod_id; - - /* Use OMAP32_ID_1 as fallback */ - prod_id = ((omap_id >> 12) & 0xffff); - - return prod_id; -} - -/* - * Get OMAP revision from DIE_REV. - * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID. - * Undocumented register in the TEST BLOCK is used as fallback. - * REVISIT: This does not seem to work on 1510 - */ -static u8 omap_get_die_rev(void) -{ - u32 die_rev; - - die_rev = omap_readl(OMAP_DIE_ID_1); - - /* Check for broken OMAP_DIE_ID on early 1710 */ - if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id()) - die_rev = 0; - - die_rev = (die_rev >> 17) & 0xf; - if (die_rev) - return die_rev; - - die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf; - - return die_rev; -} - -static unsigned long dpll1(void) -{ - unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG); - unsigned long rate; - - rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */ - if (pll_ctl_val & 0x10) { - /* PLL enabled, apply multiplier and divisor */ - if (pll_ctl_val & 0xf80) - rate *= (pll_ctl_val & 0xf80) >> 7; - rate /= ((pll_ctl_val & 0x60) >> 5) + 1; - } else { - /* PLL disabled, apply bypass divisor */ - switch (pll_ctl_val & 0xc) { - case 0: - break; - case 0x4: - rate /= 2; - break; - default: - rate /= 4; - break; - } - } - - return rate; -} - -static unsigned long armcore(void) -{ - unsigned short arm_ckctl = omap_readw(ARM_CKCTL); - - return (dpll1() >> ((arm_ckctl & 0x0030) >> 4)); -} - -int print_cpuinfo (void) -{ - int i; - u16 jtag_id; - u8 die_rev; - u32 omap_id; - u8 cpu_type; - u32 system_serial_high; - u32 system_serial_low; - u32 system_rev = 0; - - jtag_id = omap_get_jtag_id(); - die_rev = omap_get_die_rev(); - omap_id = omap_readl(OMAP32_ID_0); - -#ifdef DEBUG - printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0)); - printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n", - omap_readl(OMAP_DIE_ID_1), - (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf); - printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0)); - printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n", - omap_readl(OMAP_PRODUCTION_ID_1), - omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff); - printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0)); - printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1)); - printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev); -#endif - - system_serial_high = omap_readl(OMAP_DIE_ID_0); - system_serial_low = omap_readl(OMAP_DIE_ID_1); - - /* First check only the major version in a safe way */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == (omap_ids[i].jtag_id)) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Check if we can find the die revision */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Finally check also the omap_id */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == omap_ids[i].jtag_id - && die_rev == omap_ids[i].die_rev - && omap_id == omap_ids[i].omap_id) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */ - cpu_type = system_rev >> 24; - - switch (cpu_type) { - case 0x07: - system_rev |= 0x07; - break; - case 0x03: - case 0x15: - system_rev |= 0x15; - break; - case 0x16: - case 0x17: - system_rev |= 0x16; - break; - case 0x24: - system_rev |= 0x24; - break; - default: - printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type); - } - - printf("CPU: OMAP%04x", system_rev >> 16); - if ((system_rev >> 8) & 0xff) - printf("%x", (system_rev >> 8) & 0xff); -#ifdef DEBUG - printf(" revision %i handled as %02xxx id: %08x%08x", - die_rev, system_rev & 0xff, system_serial_low, system_serial_high); -#endif - printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n", - armcore() / 1000000, (armcore() / 100000) % 10, - dpll1() / 1000000, (dpll1() / 100000) % 10); - - return 0; -} - -#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */ diff --git a/cpu/arm926ejs/omap/Makefile b/cpu/arm926ejs/omap/Makefile index c335d5c..92913b5 100644 --- a/cpu/arm926ejs/omap/Makefile +++ b/cpu/arm926ejs/omap/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = timer.o +COBJS = timer.o cpuinfo.c SOBJS = reset.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -- 1.4.4.4 -- Roman Mashak

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