August 2006 - U-Boot

[U-Boot-Users] [PATCH 0/6] Add mpc8360epb board support
by Jiang Bo-r61859 17 Aug '06

17 Aug '06

These series of patches add support to MPC8360EPB board with QUICC Engine. QUICC Engine is new generation communication coprocessor of Freescale. It also includes patches for MPC8349EMDS and TQM834x. These patches unified variable names for 83xx. Here is the CHANGELOG entry: +* Add support for Freescale MPC8360EPB board. + Patch by Dave Liu and Tanya Jiang, Aug 17 2006 -------------------------- Signed-off-by: Dave liu <daveliu(a)freescale.com> Signed-off-by: Shlomi Gridish <gridish(a)freescale.com> Signed-off-by: Tanya Jiang <tanya.jiang(a)freescale.com>

1 0

[U-Boot-Users] [Patch] OMAP MPU timers fix
by Todd Allan 17 Aug '06

17 Aug '06

The OMAP OSK5912 board code assumes U-Boot is entered with MPU timer 1 stopped. If entered via the reset vector from OS code that left the timer running, the Load Timer Register value won't be loaded into the timer when the Control Timer Register value is set, as expected. Since the timer is placed into one-shot (not auto-reload) mode, the timer may reach zero and stay at zero, causing udelay() to hang. The attached patch is suggested for the 5912 OSK. It stops the timer, leaving the input reference clock enabled, prior to starting. A glance at the code would indicate that the 1610 Innovator and 730 P2 boards could use this fix as well; I can send patches if desired, but have no hardware on which to test.

1 0

[U-Boot-Users] Can a standalone app modify an environment variable?
by Edward Jubenville 16 Aug '06

16 Aug '06

Is it possible to modify environment variables from a standalone application in u-boot? I've written a standalone app that reads and prints a 48-bit ethernet MAC address from a Dallas/Maxim DS2502-E48 chip on a custom board. I would like the app to directly modify the "ethaddr" environment variable, rather than relying on the user to retype the printed MAC address into a setenv command. I looked at the standalone section of the readme, and at the exports.h file, but I didn't see any explicit hooks to read or write environment variables. I saw the secion on accessing u-boot environment variables in Linux, but that does seem to be applicable. Are environment variables somehow accessible through the "global_data" pointer declared in exports.h? I'm using u-boot 1.1.4. Ed Jubenville

4 3

[U-Boot-Users] How to include ML403 supported by U-boot
by Ming Liu 16 Aug '06

16 Aug '06

Dear wolfgang, Now I am trying to use u-boot to boot my Linux kernel image(2.6.16) using tftp and then mount the file system using NFS in ML403 board. But I noticed that in U-Boot 1.1.4, there is no ML403 supported.(There is only ML300 supported.) So can you tell me how to make ML403 supported by U-Boot? Shall I write the specific board configure by myself, or there is some patch for it? I have asked this question before but nobody give me an exact answer. So I think it's better to ask the author directly. Thanks for your help. Regards Ming _________________________________________________________________ 免费下载 MSN Explorer: http://explorer.msn.com/lccn/

1 0

[U-Boot-Users] Kernel hangs after enabling FCC in u-boot -mpc8560
by Junita Joseph 15 Aug '06

15 Aug '06

Hello all, I'm currently bringing up the FCC port in our MPC8560 based custom board which has one TSEC port and another FCC port. We use u-boot-1.1.4 as bootloader, where we have enabled FCC3. When I downlaod the kernel and filesystem images through FCC system boots-up to the prompt. Sametime , while I download the through TSEC port, kernel hangs at a strange point i.e before "Freeing the initrd memory". Any help would be greatly appreciated. Following are the changes done in u-boot to enable FCC3 include/net.h to u-boot-1.1.4 1. Port configuration in board/mpc8560_g8700/mpc8560_g8700.c 2. // #if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2) // For FCC3 support #if !defined(CONFIG_NET_MULTI) || defined(CONFIG_CPM2) #include <config.h> #if defined(CONFIG_ETHER_ON_FCC) #if defined(CONFIG_ETHER_ON_SCC) Is this the way to enable FCC in u-boot? Please find the screen-dump below. Thanks, Junita ######################################################################## In: serial Out: serial Err: serial Net: TSEC0, FCC3 ETHERNET Hit any key to stop autoboot: 0 RMCG8700_8560=> tftp 2000000 mpc8560/fcc/uImage Speed: 1000, full duplex Using TSEC0 device TFTP from server 192.168.201.11; our IP address is 192.168.201.191 Filename 'mpc8560/fcc/uImage'. Load address: 0x2000000 Loading: ################################################################# ################################################################# ################################################################# # done Bytes transferred = 998700 (f3d2c hex) RMCG8700_8560=> tftp 3000000 mpc8560/fcc/ramdisk.gz Speed: 1000, full duplex Using TSEC0 device TFTP from server 192.168.201.11; our IP address is 192.168.201.191 Filename 'mpc8560/fcc/ramdisk.gz'. Load address: 0x3000000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ###################################################### done Bytes transferred = 1935938 (1d8a42 hex) RMCG8700_8560=> bootm 2000000 3000000 ## Booting image at 02000000 ... Image Name: Linux-2.6.14 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 998636 Bytes = 975.2 kB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK ## Loading RAMDisk Image at 03000000 ... Image Name: GDA MPC8560 Image Type: PowerPC Linux RAMDisk Image (gzip compressed) Data Size: 1935874 Bytes = 1.8 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Loading Ramdisk to 0fdc4000, end 0ff9ca02 ... OK Memory CAM mapping: CAM0=256Mb, CAM1=0Mb, CAM2=0Mb residual: 0Mb Linux version 2.6.14 (root(a)crater.gdatech.com) (gcc version 3.3.3 (DENX ELDK 3.6Built 1 zonelists Kernel command line: OpenPIC Version 1.2 (1 CPUs and 60 IRQ sources) at fcf7d000 PID hash table entries: 2048 (order: 11, 32768 bytes) Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Memory: 255360k available (1740k kernel code, 448k data, 116k init, 0k highmem) Mount-cache hash table entries: 512 checking if image is initramfs...it isn't (no cpio magic); looks like an initrd

2 1

Re: [U-Boot-Users] tftp errors/times out on large files
by mitsy 15 Aug '06

15 Aug '06

Jerry, It looks like Redboot's tftp client and atftp's client both support large files. I am planning on studying up their code and see what they are doing. Thank you very much for the informative comment.

1 0

[U-Boot-Users] tftp errors/times out on large files
by mitsy 15 Aug '06

15 Aug '06

Hi all, I am having problem tftping large files (>30M.) The tftp will start download, and then immediately get an error, and it will say: Load address: 0x80100000 Loading: * TFTP error: 'Undefined error code' (0) Starting again or sometimes I get the 'T' (timeout) and it will repeat again. and repeat. I can download smaller files just fine. What could it be the problem? Increasing the MALLOC_LEN doesn't seem to help, and I need some advice. (FYI, I have 128M ram.) Any suggestions will be greatly appreciated!

4 4

Re: [U-Boot-Users] [DNX#2006081542000029] [Patch] Fix open #ifdef statement error , if compi [...]
by DENX Support System 15 Aug '06

15 Aug '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006081542000029] was created: <snip> > CHANGELOG: > > * Patch by Jens Scharsig (BuS Elektronik GmbH & Co. KG), 15 Aug. 2006: > > Fix:open #ifdef statement error, if compile with MCF5282 support </snip> Your U-Boot support team

1 0

Re: [U-Boot-Users] [DNX#2006081542000029] [Patch] Fix open #ifdef statement error , if compile with MC [...]
by U-Boot patch tracking system 15 Aug '06

15 Aug '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006081542000029]. Please keep this ticked ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

1 0

[U-Boot-Users] [Patch] Fix open #ifdef statement error , if compile with MCF5282 support
by Jens Scharsig 15 Aug '06

15 Aug '06

CHANGELOG: * Patch by Jens Scharsig (BuS Elektronik GmbH & Co. KG), 15 Aug. 2006: Fix:open #ifdef statement error, if compile with MCF5282 support diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index 6db6214..f9782e5 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -257,10 +257,7 @@ int eth_init (bd_t * bd) */ fecp->fec_ihash_table_high = 0; fecp->fec_ihash_table_low = 0; -#else - /* Clear multicast address hash table - */ -#ifdef CONFIG_M5282 +#elif defined(CONFIG_M5282) fecp->fec_ihash_table_high = 0; fecp->fec_ihash_table_low = 0; #else

1 0

Re: [U-Boot-Users] tftp errors/times out on large files
by mitsy 14 Aug '06

14 Aug '06

Andrew, Thank you so much for the help as always. I was wondering why it works with nfs but not tftp, if it was a memory issue. Mitsy

1 0

[U-Boot-Users] U-Boot on Xilinx ML403
by Ming Liu 14 Aug '06

14 Aug '06

Dear All, Now I am trying to use u-boot to boot my Linux kernel image(2.6.16) using tftp and then mount the file system using NFS in ML403 board. But I noticed that in U-Boot 1.1.4, there is no ML403 supported.(There is only ML300 supported.) So can anyone tell me how to include ML403 board supported in U-boot 1.1.4? Are there any patches to do that? Thanks for the help from anyone. Regards Ming _________________________________________________________________ 免费下载 MSN Explorer: http://explorer.msn.com/lccn/

1 0

Re: [U-Boot-Users] Looking for u-boot for omaph4
by Woodruff, Richard 13 Aug '06

13 Aug '06

> > Could anyone tell me where can I got well-builded u-boot.bin for > omap2420h4 ? What should be a buildable 242x-H4 & 243x-SDP images should be downloadable at http://linux.omap.com/pub/bootloader/2430sdp/u-boot.gz . If that image has issues I can fix it up. <make omap2420h4 , make > > The current U-Boot code is broken, and the board maintainer (Richard > Woodruff, on Cc:) did not care so far. Well, that is partially true. I have not tried to resync for many months now. Previous patches lagged commit so long that that it was not necessary workable by the time they were applied. The code has been pretty dynamic as perhaps a dozen versions of the board appeared in a very short time. Some of those issues dealt with the cfi_flash code and what was acceptable. That code has changed much since then and is perhaps worth trying against again. The NAND tree has also changed a lot and will take more effort to re-validate. Regards, Richard W.

3 6

Re: [U-Boot-Users] [DNX#2006081342000023] diheqVIjAjGRA
by U-Boot patch tracking system 13 Aug '06

13 Aug '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006081342000023]. Please keep this ticked ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

1 0

[U-Boot-Users] [PATCH] Fix control-c handing in CONFIG_CMDLINE_EDITING
by roger blofeld 13 Aug '06

13 Aug '06

Properly pass break code back from readline. -roger blofeld diff --git a/common/main.c b/common/main.c index 3788bd5..13d12a4 100644 --- a/common/main.c +++ b/common/main.c @@ -937,6 +937,7 @@ int readline (const char *const prompt) #ifdef CONFIG_CMDLINE_EDITING char *p = console_buffer; unsigned int len=MAX_CMDBUF_SIZE; + int rc; static int initted = 0; if (!initted) { @@ -946,8 +947,8 @@ #ifdef CONFIG_CMDLINE_EDITING puts (prompt); - cread_line(p, &len); - return len; + rc = cread_line(p, &len); + return rc < 0 ? rc : len; #else char *p = console_buffer; int n = 0; /* buffer index */ __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com diff --git a/common/main.c b/common/main.c index 3788bd5..13d12a4 100644 --- a/common/main.c +++ b/common/main.c @@ -937,6 +937,7 @@ int readline (const char *const prompt) #ifdef CONFIG_CMDLINE_EDITING char *p = console_buffer; unsigned int len=MAX_CMDBUF_SIZE; + int rc; static int initted = 0; if (!initted) { @@ -946,8 +947,8 @@ #ifdef CONFIG_CMDLINE_EDITING puts (prompt); - cread_line(p, &len); - return len; + rc = cread_line(p, &len); + return rc < 0 ? rc : len; #else char *p = console_buffer; int n = 0; /* buffer index */

2 1

Re: [U-Boot-Users] u-boot patches for mainstone
by Marco Cavallini 12 Aug '06

12 Aug '06

Brock Denson ha scritto: > Marco, > > I apologize for contacting you this way, but I couldn't find another > way. I am working on porting u-boot to a board closely based on the > pxa270 mainstone platform. I saw in the mailing lists that you > submitted a patch for mainstone support but do not see it in the latest > ftp tarballs (grep mainstone) and could not find the patches with the > DNX#2006040142001285 id given in the mailing list. Can you tell me how > to get this patch? I would really appreciate it. > Thank you, > > Brock Denson Hi, my patches seems aren't applied yet, however I published them here http://www.koansoftware.com/en/prd_svil_projects.htm Ciao -- Marco Cavallini Koan s.a.s. - Bergamo - ITALIA Embedded and Real-Time Software Engineering - Atmel Third Party Consultant Tel. +39-(0)35-255.235 - Fax +39-178-223.9748 www.KoanSoftware.com | www.KaeilOS.com Informativa D.Lgs 196/2003 (Privacy) http://www.koansoftware.com/it/prf_privacy.htm

1 0

[U-Boot-Users] u-boot for AT91rm9200-EK board.
by Leonid 11 Aug '06

11 Aug '06

Hi: I'm creating building environment for ATMEL AT91rm9200-EK board. My first goal is to build u-boot. Several questions: 1) The u-boot version I'm using (u-boot-2006-05-10-1800) doesn't have config for this board, but for AT91rm9200-DK instead. Is it OK to use -DK config? 2) I'm using Kegel crosstool, configured for arm-9tdmi and compiled in gcc-3.4.5-glibc-2.3.2 combination. I tried to compile u-boot for -DK board, but compilation failed with error ".../libgcc.a(_ashldi3.oS) uses hardware FP, whereas u-boot uses software FP". I figured out that it's because my cpu/arm920t/config.mk file has -msoft-float option while actual CPU uses hardware fp operation. I've changed config.mk by commenting out -msoft-float option: PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 # -msoft-float and compilation passed successfully. Is this it, or I must add some other options? 3) I understood that it's possible to use BDI2000 with this board, but does somebody have actual experience in this area? 4) Not exactly u-boot question, but I'll draw it: where is the best place to get root filesystem package for this board? I've got something from TimeSys, but that looks too big for my purposes. Thanks, Leonid.

1 0

[U-Boot-Users] [PATCH 02/07 v2]: mpc7448hpc2 platform support (part 2/4 board low level init)
by Zang Roy-r61911 11 Aug '06

11 Aug '06

Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The original one is too big and divided into 4 parts for review. board support low level init code . Signed-off-by: Alexandre Bounine <alexandreb(a)tundra.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> board/mpc7448hpc2/asm_init.S | 955 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 955 insertions(+), 0 deletions(-) diff --git a/board/mpc7448hpc2/asm_init.S b/board/mpc7448hpc2/asm_init.S new file mode 100644 index 0000000..8c15a3d --- /dev/null +++ b/board/mpc7448hpc2/asm_init.S @@ -0,0 +1,955 @@ +/********************************************************************** ******* + * (C) Copyright 2004-05; Tundra Semiconductor Corp. + * + * Added automatic detect of SDC settings + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * Maintainer tie-fei.zang(a)freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ************************************************************************ ****/ + +/*--------------------------------------------------------------------- ------- + * FILENAME: asm_init.s + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + * + *----------------------------------------------------------------------- ----*/ + +#include <config.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> + +#include <tsi108.h> + +/*===================================================================== ====== + * Build Configuration Options + */ + +/* #define DISABLE_PBM disables usage of PB Master */ +/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ +/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ + +/* ======================================================================== === + * Hardcoded SDC settings + */ + +#ifdef SDC_HARDCODED_INIT + +/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ + +#define VAL_SD_REFRESH (0x61A) +#define VAL_SD_TIMING (0x0308336b) +#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ +#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ + +#endif /* SDC_HARDCODED_INIT */ + +/*--------------------------------------------------------------------- ------ + CPU Configuration: + + CPU Address and Data Parity enables. + +#define CPU_AP +#define CPU_DP + +======================================================================= ==== + Macros + + !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are + expected to work correctly for the CSR space within 32KB range. + + LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. + These macros are absolutely identical except their names. This difference + is provided intentionally for better readable code. + ------------------------------------------------------------------------ -*/ + +#define LOAD_PTR(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +#define LOAD_U32(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +/* LOADMEM initializes a register with the contents of a specified 32-bit memory + location, usually a CSR value.*/ + +#define LOAD_MEM(reg,addr32) \ + addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) + +#ifndef SDC_HARDCODED_INIT +sdc_clk_sync: + /* MHz: 0,0,183,100,133,167,200,233 */ + .long 0,0, 6, 10, 8, 6, 5, 4 /* nSec */ +#endif + +/*===================================================================== ====== + board_asm_init() - early initialization function. Coded to be portable to + dual-CPU configuration. + Checks CPU number and performs board HW initialization if called for CPU0. + + Registers used: r3,r4,r5,r6,r19,r29 +======================================================================= ==== + +----------------------------------------------------------------------- ---- + NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 + and the rest of the board. Current implementation demonstrates two + possible ways to identify CPU number: + - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. + - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. +----------------------------------------------------------------------- ----*/ + + .globl board_asm_init +board_asm_init: + + mflr r19 /* Save LR to be able return later. */ + + bl icache_enable /* Enable icache to reduce reads from flash. */ + + /* Initialize pointer to Tsi108 register space + ------------------------------------------------------------------------ -*/ + + LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + ori r4,r29,TSI108_PB_REG_OFFSET + + /*---------------------------------------------------------------------- --- + Check Processor Version Number */ + + mfspr r3, PVR + rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ + + cmpli 0,0,r3,0x8000 /* MPC74xx */ + bne cont_brd_init + + /* ------------------------------------------ + For MPC744x/5x enable extended BATs[4-7] + Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 + to disable prefetch + */ + + mfspr r5, HID0 + oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ + ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ + mtspr HID0, r5 + isync + sync + + /* Adding code to disable external interventions in MPX bus mode */ + mfspr r3, 1014 + oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ + mtspr 1014, r3 + isync + sync + + /* Sri: code to enable FP unit */ + mfmsr r3 + ori r3, r3, 0x2000 + mtmsr r3 + isync + sync + +#if(1) /* def CONFIG_DUAL_CPU + ------------------------------------------------------------------------ - + For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. + */ + + mfspr r3,1014 /* read MSSCR0 */ + rlwinm. r3,r3,27,31,31 /* get processor ID number */ + mtspr SPRN_PIR,r3 /* Save CPU ID */ + sync + bne init_done + b do_tsi108_init + +cont_brd_init: + + /* An alternative method of checking the processor number (in addition + to configuration using MSSCR0[ID] bit on MPC74xx). + Good for IBM PPC750FX/GX. + */ + + lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ + rlwinm. r3,r3,24,31,31 /* get processor ID number */ + + bne init_done + +#else + +cont_brd_init: + +#endif /* CONFIG_DUAL_CPU */ + + /* Initialize Tsi108 chip + ------------------------------------------------------------------------ --- + */ + +do_tsi108_init: + + /*---------------------------------------------------------------------- ---- + Adjust HLP/Flash parameters. By default after reset the HLP port is set + to support slow devices. Better performance can be achived when an optimal + parameters are used for specific EPROM device. + NOTE: This should be performed ASAP for the emulation platform because + it has 5MHz HLP clocking. + */ + +#ifdef CONFIG_TSI108EMU + ori r4,r29,TSI108_HLP_REG_OFFSET + LOAD_U32(r5,0x434422c0) + stw r5,0x08(r4) /* set HLP B0_CTRL0 */ + sync + LOAD_U32(r5,0xd0012000) + stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ + sync +#endif + + /* ------------------------------------------------------------------------ - + * Initialize PB interface. + */ + + ori r4,r29,TSI108_PB_REG_OFFSET + +#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) + /* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR: + * Note we are in the 32-bit address mode. + */ + LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/ + stw r5,PB_REG_BAR(r4) + andis. r29,r5,0xFFFF + sync + + ori r4,r29,TSI108_PB_REG_OFFSET +#endif + + /* Set PB Slave configuration register */ + +/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */ + LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */ + lwz r3, PB_RSR(r4) /* get PB bus mode */ + xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ + rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ + stw r5,PB_SCR(r4) + sync + + /* Configure PB Arbiter */ + + lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ +#ifdef DISABLE_PBM + ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ +#endif + andc r5,r5,r3 /* Clear the masked bit fields */ +/* ori r5,r5,0x0040 Set pipeline depth 4 + ori r5,r5,0x0080 Set pipeline depth 8 + ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */ + ori r5,r5,0x0001 + stw r5,PB_ARB_CTRL(r4) + +#if (0) /* currently using the default settings for PBM after reset */ + LOAD_U32(r5,0x) /* value for PB_MCR */ + stw r5,PB_MCR(r4) + sync + + LOAD_U32(r5,0x) /* value for PB_MCMD */ + stw r5,PB_MCMD(r4) + sync +#endif + +/* Disable or enable PVT based on processor bus frequency + 1. Read CG_PWRUP_STATUS register field bits 18,17,16 + 2. See if the value is < or > 133mhz (18:16 = 100) + 3. If > enable PVT + */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,16,29,31 + + cmpi 0,0,r3,0x0004 + bgt sdc_init + +#ifndef CONFIG_TSI108EMU + /* FIXME: Disable PB calibration control for any real Tsi108 board */ + li r5,0x0101 /* disable calibration control */ + stw r5,PB_PVT_CTRL2(r4) + sync +#endif + +/*--------------------------------------------------------------------- ------ + Initialize SDRAM controller. +----------------------------------------------------------------------- -----*/ + +sdc_init: + +#ifndef SDC_HARDCODED_INIT + /* get SDC clock prior doing sdram controller autoconfig */ + ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ + lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ + rlwinm r3,r3,12,29,31 /* r3 - SD clk */ + lis r5,sdc_clk_sync@h + ori r5,r5,sdc_clk_sync@l + /* Sri: At this point check if r3 = 001. If yes, + * the memory frequency should be same as the + * MPX bus frequency + */ + cmpi 0,0,r3,0x0001 + bne get_nsec + lwz r6, CG_PWRUP_STATUS(r4) + rlwinm r6,r6,16,29,31 + mr r3,r6 + +get_nsec: + rlwinm r3,r3,2,0,31 + lwzx r9,r5,r3 /* get SD clk rate in nSec */ + /* ATTN: r9 will be used by SPD routine */ +#endif /* !SDC_HARDCODED_INIT */ + + ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ + + /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ + + LOAD_U32(r5,0x00) + stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ +#ifdef ENABLE_SDRAM_ECC + li r5, 0x01 +#endif /* ENABLE_SDRAM_ECC */ + stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ + sync + +#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ + + /* First read the CG_PWRUP_STATUS register to get the + memory speed from bits 22,21,20 */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,12,29,31 + + /* Now first check for 166, then 200, or default */ + + cmpi 0,0,r3,0x0005 + bne check_for_200mhz + + /* set values for 166 Mhz memory speed */ + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,0x00000515) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03073368) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +check_for_200mhz: + + cmpi 0,0,r3,0x0006 + bne set_default_values + + /* set values for 200Mhz memory speed */ + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,0x0000061a) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03083348) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +set_default_values: + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,VAL_SD_REFRESH) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,VAL_SD_TIMING) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + +#else /* !SDC_HARDCODED_INIT */ + + bl tsi108_sdram_spd /* automatically detect SDC settings */ + +#endif /* SDC_HARDCODED_INIT */ + +sdc_init_done: + +#ifdef DISABLE_PBM + LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ +#else + LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_TSI108EMU + oris r5,r5,0x0010 /* set EMULATION_MODE bit */ +#endif + + stw r5,SD_CTRL(r4) + eieio + sync + + /* Enable SDRAM access */ + + oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ + stw r5,SD_CTRL(r4) + sync + +wait_init_complete: + lwz r5,SD_STATUS(r4) + andi. r5,r5,0x0001 + beq wait_init_complete /* wait until SDRAM initialization is complete */ + +/*--------------------------------------------------------------------- ------ + Map SDRAM into the processor bus address space +----------------------------------------------------------------------- ----*/ + + ori r4,r29,TSI108_PB_REG_OFFSET + + /* Setup BARs associated with direct path PB<->SDRAM */ + + /* PB_SDRAM_BAR1: + provides a direct path to the main system memory (cacheable SDRAM) */ + + LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */ + stw r5,PB_SDRAM_BAR1(r4) + sync + + /* Make sure that PB_SDRAM_BAR1 decoder is set + (to allow following immediate read from SDRAM) */ + lwz r5,PB_SDRAM_BAR1(r4) + sync + + /* PB_SDRAM_BAR2: + provides non-cacheable alias (via the direct path) to main system memory. + Size = 512MB, ENable, Addr.Translation - ON, + BA = 0x0_40000000, TA = 0x0_00000000 */ + + LOAD_U32(r5, 0x40010011) + stw r5,PB_SDRAM_BAR2(r4) + sync + + /* Make sure that PB_SDRAM_BAR2 decoder is set + (to allow following immediate read from SDRAM) */ + lwz r5,PB_SDRAM_BAR2(r4) + sync + + +init_done: + + /* All done. Restore LR and return. */ + mtlr r19 + blr + +#if (0) +/*===================================================================== ====== + init_cpu1 + + This routine enables CPU1 on the dual-processor system. +======================================================================= ====*/ + + .global enable_cpu1 +enable_cpu1: + + lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ + addi r3,r3,Tsi108_Base@l + lwz r3,0(r3) /* R3 = CSR Base Addr */ + ori r4,r3,TSI108_PB_REG_OFFSET + lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + ori r3,r3,0x0200 /* Set M1_EN bit */ + stw r3,PB_ARB_CTRL(r4) + + blr +#endif + +/*===================================================================== ====== + enable_EI + + Enable CPU core external interrupt +======================================================================= ====*/ + + .global enable_EI +enable_EI: + mfmsr r3 + ori r3,r3,0x8000 /* set EE bit */ + mtmsr r3 + blr + +/*===================================================================== ====== + disable_EI + + Disable CPU core external interrupt +======================================================================= ====*/ + + .global disable_EI +disable_EI: + mfmsr r3 + li r4,-32768 /* aka "li r4,0x8000" */ + andc r3,r3,r4 /* clear EE bit */ + mtmsr r3 + blr + +#ifdef ENABLE_SDRAM_ECC +/*===================================================================== ====== + enable_ECC + + enables SDRAM ECC +======================================================================= ====*/ + + .global enable_ECC +enable_ECC: + ori r4,r29,TSI108_SD_REG_OFFSET + lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ + ori r3,r3,0x0001 /* Set ECC_EN bit */ + stw r3,SD_ECC_CTRL(r4) + blr + +/*===================================================================== ====== + clear_ECC_err + + Clears all pending SDRAM ECC errors + (normally after SDRAM scrubbing/initialization) +======================================================================= ====*/ + + .global clear_ECC_err +clear_ECC_err: + ori r4,r29,TSI108_SD_REG_OFFSET +/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */ + ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ + stw r3,SD_INT_STATUS(r4) + blr + +#endif /* ENABLE_SDRAM_ECC */ + +#ifndef SDC_HARDCODED_INIT + +/******************************************************************** + * SDRAM SPD Support + */ + +#define SD_I2C_CTRL1 (0x400) +#define SD_I2C_CTRL2 (0x404) +#define SD_I2C_RD_DATA (0x408) +#define SD_I2C_WR_DATA (0x40C) + +/* + * SDRAM SPD Support Macros + */ + +#define SPD_DIMM0 (0x00000100) +#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ + +#define SPD_RDIMM (0x01) +#define SPD_UDIMM (0x02) + +#define SPD_CAS_3 0x8 +#define SPD_CAS_4 0x10 +#define SPD_CAS_5 0x20 + +#define ERR_NO_DIMM_FOUND (0xdb0) +#define ERR_TRAS_FAIL (0xdb1) +#define ERR_TRCD_FAIL (0xdb2) +#define ERR_TRP_FAIL (0xdb3) +#define ERR_TWR_FAIL (0xdb4) +#define ERR_UNKNOWN_PART (0xdb5) +#define ERR_NRANK_INVALID (0xdb6) +#define ERR_DIMM_SIZE (0xdb7) +#define ERR_ADDR_MODE (0xdb8) +#define ERR_RFRSH_RATE (0xdb9) +#define ERR_DIMM_TYPE (0xdba) +#define ERR_CL_VALUE (0xdbb) +#define ERR_TRFC_FAIL (0xdbc) + +/* READ_SPD requirements: + * byte - byte address in SPD device (0 - 255) + * r3 = will return data read from I2C Byte location + * r4 - unchanged (SDC base addr) + * r5 - clobbered in routine (I2C status) + * r10 - number of DDR slot where first SPD device is detected + */ + +#define READ_SPD(byte_num) \ + addis r3, 0, byte_num@l;\ + or r3, r3, r10;\ + ori r3, r3, 0x0A;\ + stw r3, SD_I2C_CTRL1(r4);\ + li r3, I2C_CNTRL2_START;\ + stw r3, SD_I2C_CTRL2(r4);\ + eieio;\ + sync;\ + li r3, 0x100;\ +1: ;\ + addic. r3, r3, -1;\ + bne 1b;\ +2: ;\ + lwz r5, SD_I2C_CTRL2(r4);\ + rlwinm. r3,r5,0,23,23;\ + bne 2b;\ + rlwinm. r3,r5,0,3,3;\ + lwz r3, SD_I2C_RD_DATA(r4) + +#define SPD_MIN_RFRSH (0x80) +#define SPD_MAX_RFRSH (0x85) + +refresh_rates: /* in nSec */ + .long 15625 /* Normal (0x80) */ + .long 3900 /* Reduced 0.25x (0x81) */ + .long 7800 /* Reduced 0.5x (0x82) */ + .long 31300 /* Extended 2x (0x83) */ + .long 62500 /* Extended 4x (0x84) */ + .long 125000 /* Extended 8x (0x85) */ + +/*===================================================================== ====== + * tsi108_sdram_spd + * + * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data + * Uses registers: r4 - SDC base address (not changed) + * r9 - SDC clocking period in nSec + * Changes registers: r3,r5,r6,r7,r8,r10,r11 + *======================================================================= ===*/ + +tsi108_sdram_spd: + + li r10,SPD_DIMM0 + xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ + +do_first_dimm: + + /************************************** + * Program Refresh Rate Register + */ + + READ_SPD(12) /* get Refresh Rate */ + beq check_next_slot + li r5, ERR_RFRSH_RATE + cmpi 0,0,r3,SPD_MIN_RFRSH + ble spd_fail + cmpi 0,0,r3,SPD_MAX_RFRSH + bgt spd_fail + addi r3,r3,-SPD_MIN_RFRSH + rlwinm r3,r3,2,0,31 + lis r5,refresh_rates@h + ori r5,r5,refresh_rates@l + lwzx r5,r5,r3 /* get refresh rate in nSec */ + divwu r5,r5,r9 /* calculate # of SDC clocks */ + stw r5,SD_REFRESH(r4) /* Set refresh rate */ + sync + + /************************************** + * Program SD Timing Register + */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ + beq spd_read_fail + li r5, ERR_DIMM_TYPE + cmpi 0,0,r3,SPD_UDIMM + beq do_cl + cmpi 0,0,r3,SPD_RDIMM + bne spd_fail + oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ + +do_cl: + READ_SPD(18) /* Get CAS Latency */ + beq spd_read_fail + li r5,ERR_CL_VALUE + andi. r6,r3,SPD_CAS_3 + beq cl_4 + li r6,3 + b set_cl +cl_4: + andi. r6,r3,SPD_CAS_4 + beq cl_5 + li r6,4 + b set_cl +cl_5: + andi. r6,r3,SPD_CAS_5 + beq spd_fail + li r6,5 +set_cl: + rlwimi r7,r6,24,5,7 + + READ_SPD(30) /* Get tRAS */ + beq spd_read_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_tras + addi r6,r6,1 +set_tras: + li r5,ERR_TRAS_FAIL + cmpi 0,0,r6,0x0F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,16,12,15 + + READ_SPD(29) /* Get tRCD */ + beq spd_read_fail + rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trcd + addi r6,r6,1 +set_trcd: + li r5,ERR_TRCD_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,12,17,19 + + READ_SPD(27) /* Get tRP value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trp + addi r6,r6,1 +set_trp: + li r5,ERR_TRP_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,8,21,23 + + READ_SPD(36) /* Get tWR value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_twr + addi r6,r6,1 +set_twr: + addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ + li r5,ERR_TWR_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,5,24,26 + + READ_SPD(42) /* Get tRFC */ + beq spd_read_fail + li r5, ERR_TRFC_FAIL + /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ + addi r3,r3,1 + rlwinm. r3,r3,31,1,31 /* divide by 2 */ + beq spd_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trfc + addi r6,r6,1 +set_trfc: + cmpi 0,0,r6,0x1F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,0,27,31 + + stw r7,SD_TIMING(r4) + sync + + /*===================================================================== + * The following two registers are set on per-DIMM basis. + * The SD_REFRESH and SD_TIMING settings are common for both DIMMS + *===================================================================== + */ + +do_each_dimm: + + /***************************************** + * Program SDRAM DIMM Control Register + */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(13) /* Get Primary SDRAM Width */ + beq spd_read_fail + cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ + beq do_nbank + oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ + +do_nbank: + READ_SPD(17) /* Get Number of banks on SDRAM device */ + beq spd_read_fail + /* Grendel only distinguish betw. 4 or 8-bank memory parts */ + li r5,ERR_UNKNOWN_PART /* non-supported memory part */ + cmpi 0,0,r3,4 + beq do_nrank + cmpi 0,0,r3,8 + bne spd_fail + ori r7,r7,0x1000 + +do_nrank: + READ_SPD(5) /* Get # of Ranks */ + beq spd_read_fail + li r5,ERR_NRANK_INVALID + andi. r6,r3,0x7 /* Use bits [2..0] only */ + beq do_addr_mode + cmpi 0,0,r6,1 + bgt spd_fail + rlwimi r7,r6,8,23,23 + +do_addr_mode: + READ_SPD(4) /* Get # of Column Addresses */ + beq spd_read_fail + li r5, ERR_ADDR_MODE + andi. r3,r3,0x0f /* cut off reserved bits */ + cmpi 0,0,r3,8 + ble spd_fail + cmpi 0,0,r3,15 + bgt spd_fail + addi r6,r3,-8 /* calculate ADDR_MODE parameter */ + rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ + +set_dimm_ctrl: +#ifdef SDC_AUTOPRECH_EN + oris r7,r7,0x0001 /* set auto precharge EN bit */ +#endif + ori r7,r7,1 /* set ENABLE bit */ + cmpi 0,0,r10,SPD_DIMM0 + bne 1f + stw r7,SD_D0_CTRL(r4) + sync + b set_dimm_bar +1: + stw r7,SD_D1_CTRL(r4) + sync + + + /******************************************** + * Program SDRAM DIMMx Base Address Register + */ + +set_dimm_bar: + READ_SPD(5) /* get # of Ranks */ + beq spd_read_fail + andi.r7,r3,0x7 + addi r7,r7,1 + READ_SPD(31) /* Read DIMM rank density */ + beq spd_read_fail + rlwinm r5,r3,27,29,31 + rlwinm r6,r3,3,24,28 + or r5,r6,r5 /* r5 = Normalized Rank Density byte */ + lis r8, 0x0080 /* 128MB >> 4 */ + mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ + mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ + neg r7,r8 + rlwinm r7,r7,28,4,31 + or r7,r7,r11 /* set ADDR field */ + rlwinm r8,r8,12,20,31 + add r11,r11,r8 /* set Base Addr for next DIMM */ + + cmpi 0,0,r10,SPD_DIMM0 + bne set_dimm1_size + stw r7,SD_D0_BAR(r4) + sync + li r10,SPD_DIMM1 + READ_SPD(0) + bne do_each_dimm + b spd_done + +set_dimm1_size: + stw r7,SD_D1_BAR(r4) + sync +spd_done: + blr + +check_next_slot: + cmpi 0,0,r10,SPD_DIMM1 + beq spd_read_fail + li r10,SPD_DIMM1 + b do_first_dimm +spd_read_fail: + ori r3,r0,0xdead + b err_hung +spd_fail: + li r3,0x0bad + sync +err_hung: /* hang here for debugging */ + nop + nop + b err_hung + +#endif /* !SDC_HARDCODED_INIT */ + -- 1.4.0

1 0

[U-Boot-Users] New nand implementation and jffs2
by mitsy 11 Aug '06

11 Aug '06

I have a quick question on the latest source code. If I were to use the new nand flash support implementation and also wanted to add jffs2 support, I use fs/jffs2/jffs2_nand_1pass.c, and not fs/jffs2/jffs2_1pass.c by modifying the makefile in the directory, is that correct?

2 4

Re: [U-Boot-Users] [DNX#2006081142000091] [PATCH] CONFIG_PHY_ADDR is now supported by ether.c (at91rm9 [...]
by U-Boot patch tracking system 11 Aug '06

11 Aug '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006081142000091]. Please keep this ticked ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

1 0

Re: [U-Boot-Users] [DNX#2006081142000091] [PATCH] CONFIG_PHY_ADDR is now supported by ether. [...]
by DENX Support System 11 Aug '06

11 Aug '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006081142000091] was created: <snip> > Hi, > > the following patch adds support for using the CONFIG_PHY_ADDR macro in > the ethernet driver (ether.c) for the at91rm9200. All existing PHY > drivers (bcm5221, > dm9261 and lxt972) were adapted. > > Signed-off-by: Mirco Fuchs <mircofuchs(a)web.de> > > > diff --git a/cpu/arm920t/at91rm9200/bcm5221.c > b/cpu/arm920t/at91rm9200/bcm5221.c > index 6db1435..b881323 100644 > --- a/cpu/arm920t/at91rm9200/bcm5221.c > +++ b/cpu/arm920t/at91rm9200/bcm5221.c > @@ -34,6 +34,10 @@ #ifdef CONFIG_DRIVER_ETHER > > #if (CONFIG_COMMANDS & CFG_CMD_NET) > > +#ifndef CONFIG_PHY_ADDR > +#define CONFIG_PHY_ADDR 0 > +#endif > + > /* > * Name: > * bcm5221_IsPhyConnected > @@ -50,8 +54,8 @@ unsigned int bcm5221_IsPhyConnected (AT9 > unsigned short Id1, Id2; > > at91rm9200_EmacEnableMDIO (p_mac); > - at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1); > - at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2); > + at91rm9200_EmacReadPhy (p_mac, CONFIG_PHY_ADDR, BCM5221_PHYID1, &Id1); > + at91rm9200_EmacReadPhy (p_mac, CONFIG_PHY_ADDR, BCM5221_PHYID2, &Id2); > at91rm9200_EmacDisableMDIO (p_mac); > > if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) && > @@ -77,13 +81,15 @@ unsigned char bcm5221_GetLinkSpeed (AT91 > { > unsigned short stat1, stat2; > > - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1)) > + if (!at91rm9200_EmacReadPhy (p_mac, CONFIG_PHY_ADDR, BCM5221_BMSR, > + &stat1)) > return FALSE; > > if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */ > return FALSE; > > - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2)) > + if (!at91rm9200_EmacReadPhy (p_mac, CONFIG_PHY_ADDR, BCM5221_ACSR, > + &stat2)) > return FALSE; > > if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 > & BCM5221_FDX)) { > @@ -142,13 +148,15 @@ unsigned char bcm5221_InitPhy (AT91PS_EM > } > > /* Disable PHY Interrupts */ > - at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue); > + at91rm9200_EmacReadPhy (p_mac, CONFIG_PHY_ADDR, BCM5221_INTR, > + &IntValue); > /* clear FDX LED and INTR Enable */ > IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE); > /* set FDX, SPD, Link, INTR masks */ > IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK | > BCM5221_LINK_MASK | BCM5221_INTR_MASK); > - at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue); > + at91rm9200_EmacWritePhy (p_mac, CONFIG_PHY_ADDR, BCM5221_INTR, > + &IntValue); > at91rm9200_EmacDisableMDIO (p_mac); > > return (ret); > @@ -174,41 +182,48 @@ unsigned char bcm5221_AutoNegotiate (AT9 > unsigned short PhyAnalpar; > > /* Set bcm5221 control register */ > - if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value)) > + if (!at91rm9200_EmacReadPhy (p_mac, CONFIG_PHY_ADDR, BCM5221_BMCR, > + &value)) > return FALSE; > value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */ > value |= BCM5221_ISOLATE; /* Electrically isolate PHY */ > - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value)) > + if (!at91rm9200_EmacWritePhy (p_mac, CONFIG_PHY_ADDR, BCM5221_BMCR, > + &value)) > return FALSE; > > /* Set the Auto_negotiation Advertisement Register */ > /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE > 802.3 */ > PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX | > BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3; > - if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar)) > + if (!at91rm9200_EmacWritePhy (p_mac, CONFIG_PHY_ADDR, BCM5221_ANAR, > + &PhyAnar)) > return FALSE; > > /* Read the Control Register */ </snip> Your U-Boot support team

1 0

[U-Boot-Users] lan91c96 diagnostics - POST
by Ram 11 Aug '06

11 Aug '06

Hi, I have a lan91c96 chip which i need to test during u-boot startup. i have enabled promiscous mode. am able to recieve packets send by other machines on my network. (All broad cast packets sent by other machines - am able to see) if i send a packet with destination addess = broadcast address ; am not able to recieve the packet i have sent. why?. i tried the following; 1) Self Address = Self Ethernet Mac ; Destination = 0xffffffffffff (broadcast address) 2) Self Address = Self Ethernet Mac ; Destination = Self Ethernet mac. I dont know why i am not able to recieve the packets i tranmsit. Any advices?. Regards, sriram

2 1

[U-Boot-Users] Uboot drivers querry
by Ajay Jain 11 Aug '06

11 Aug '06

Hi, I have a very very elementary question regarding the drivers as implemented in uboot. This is regarding the uboot port that I am doing on my arm proprietary board. I take "at91rm9200" as my reference. I see that for serial drivers certain functions are exposed for eg. "serial_puts" or may be for timers "interrupt_init" or "reset_timer" etc. I see that all these functions are global. i) How does the bootloader core logic call these functions, are they registered somewhere? Which is that middle layer, that calls these functions? ii) Now I have to implement these functions for my board, so what do these functions expect? Are these expectations listed anywhere or reading codes of similar boards is the only alternative? I have gone through the whole Readme but could not find it. iii) How do I know which all functions to implement? Thanks a lot, Ajay

2 3

[U-Boot-Users] Uboot Relocation doubts
by Ajay Jain 11 Aug '06

11 Aug '06

Hi, I have a very basic doubt regarding uboot operation. I am seeing the file start.s in the directory cpu/arm920t/. As I understand, the code beginning from the section _start, should _typically_ start executing from the flash. In the end of this file, it relocates itself to TEXT_BASE, which is _typcially_ a RAM address. Since the boot-loader should be a fully resolved executable, how does the compiler generates jumps etc. in the _start section from the beginning of the flash address and then later for the RAM section from the RAM address. Regards, Ajay

2 1

[U-Boot-Users] problem while installing iso
by nilgosavi 11 Aug '06

11 Aug '06

i want to install eldk 4.0 i have given command ./install -d /elk ppc_74xx shell prompt shows the error message ; error: unpacking of archive failed on file /elk/usr/bin/rpm2cpio;44b37dec: cpio: read -- View this message in context: http://www.nabble.com/problem-while-installing-iso-tf2090029.html#a5760371 Sent from the Uboot - Users forum at Nabble.com.

2 1