August 2006 - U-Boot

[U-Boot-Users] Microkernel / Manufacturers
by William DUCK 26 Aug '06

26 Aug '06

Hello, I am currently involved into the UEFI project. I would want to build an Open Source UEFI firmware in the style of U-Boot/LinuxBIOS but to boot a microkernel. Which manufacturer could I contact to build a firmware ? ( to have the specs/datasheets of the hardware) If you want to contact me, my mail is guillaume_dot_fortaine_at_wanadoo_dot_fr I will set up a mailing-list, a web server, a wiki and an IRC Thank you for your answer, Best Regards, WIll

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[U-Boot-Users] PHY not connected!!
by Hong Tran Duc 26 Aug '06

26 Aug '06

I have PHY not connected when testing ethernet on AT91rm9200 board U-Boot> setenv ethaddr 52:0f:2d:17:62:27 U-Boot> set ipaddr 10.1.1.1 U-Boot> ping 10.10.11.222 PHY not connected!! host 10.10.11.222 is alive What happend w/ my board or my u-b00t ? -- nm. p/s : i attached my at91rm9200.h.

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Re: [U-Boot-Users] [DNX#2006082642000026] [PATCH] PCIE endpoint support for A [...]
by DENX Support System 26 Aug '06

26 Aug '06

Hello list, inside the automatic U-Boot patch tracking system a new ticket [DNX#2006082642000026] was created: <snip> > Added code to setup 440SPE as PCI-E endpoint device in u-boot. This code > has been tested with 2 yucca boards , one as endpoint device and other > as root point. > > Signed-off-by: Tirumala R Marri <tmarri(a)amcc.com> > > CHANGELOG: > > *Adding PCI-E endpoint device support to u-boot for AMCC yucca board > with SOC 440spe. > -------------------------------------------------------- > > CONFIDENTIALITY NOTICE: This e-mail message, including any attachments, > is for the sole use of the intended recipient(s) and contains > information that is confidential and proprietary to Applied Micro > Circuits Corporation or its subsidiaries. It is to be used solely for > the purpose of furthering the parties' business relationship. All > unauthorized review, use, disclosure or distribution is prohibited. If > you are not the intended recipient, please contact the sender by reply > e-mail and destroy all copies of the original message. </snip> Your U-Boot support team

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Re: [U-Boot-Users] [DNX#2006082642000026] [PATCH] PCIE endpoint support for AMCC yucca [...]
by U-Boot patch tracking system 26 Aug '06

26 Aug '06

Dear Mr. U. Boot, thank you for your contribution to the U-Boot project. Your e-mail was registered at our system under the ticket number [DNX#2006082642000026]. Please keep this ticket ID string in the subject line of any e-mail replies!!! Your U-Boot support team Powered by OTRS (http://otrs.org/)

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[U-Boot-Users] [PATCH] PCIE endpoint support for AMCC yucca 440spe in uboot
by Tirumala Reddy Marri 26 Aug '06

26 Aug '06

Added code to setup 440SPE as PCI-E endpoint device in u-boot. This code has been tested with 2 yucca boards , one as endpoint device and other as root point. Signed-off-by: Tirumala R Marri <tmarri(a)amcc.com> CHANGELOG: *Adding PCI-E endpoint device support to u-boot for AMCC yucca board with SOC 440spe. -------------------------------------------------------- CONFIDENTIALITY NOTICE: This e-mail message, including any attachments, is for the sole use of the intended recipient(s) and contains information that is confidential and proprietary to Applied Micro Circuits Corporation or its subsidiaries. It is to be used solely for the purpose of furthering the parties' business relationship. All unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply e-mail and destroy all copies of the original message.

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[U-Boot-Users] MPC8272 -- FLASH
by Lieng, Shee 25 Aug '06

25 Aug '06

Hi to whom it may concern, I have MPC8272 board and I am looking for the FLASH procedures. Currently, I am trying to FLASH this board but having problem to write on top of the FLASH from FFF0 0000 to FFF8 0000. If you have any information and ideas how to FLASH the chip could you please let me know. thanks Jack ____________________________ Software Development Engineer Mentor Graphics Embedded Systems Division 739 North University Blvd Mobile, AL 36608 (251) 208-3639 _______________________________

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[U-Boot-Users] Flash configuration
by Justin Clacherty 25 Aug '06

25 Aug '06

Hi, I've ported u-boot to my PXA270 board and have it working as a network boot loader. I'm now trying to get flash programming working so I can flash the kernel and root file system. Our board has two Intel 512Mib P30 flashes on it configured as 32-bit memory. The 512Mib parts are actually two 256Mib parts on the same die so u-boot should see two banks of 32-bit memory with two flash devices in each bank. After booting flinfo shows that u-boot has found four devices but the addresses seem to be wrong. It has bank 1 0x00000000 - 0x03ffffff bank 2 0x04000000 - 0x07ffffff bank3 0x00000000 - 0x03ffffff bank 4 0x00000000 - 0x03ffffff. Any ideas where I might have gone wrong? The relevant portions of my board header file are below. Regards, Justin. #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT #define CFG_FLASH_BASE_1 PHYS_FLASH_1 #define CFG_FLASH_BASE_2 PHYS_FLASH_2 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE_1, CFG_FLASH_BASE_2 } #define CFG_MONITOR_BASE 0 #define CFG_MONITOR_LEN 0x20000 #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT (4 + 255) /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ /* write flash less slowly */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Flash environment locations */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_FLASH_BASE_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */

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[U-Boot-Users] USB Lowlevel not defined when define CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_USB_STORAGE
by Hong Tran Duc 25 Aug '06

25 Aug '06

Dear *, I run u-b00t 2006 (1.14) on flavio At91 sbc board, I want to boot linux from usb disk, but i got build error when define CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_USB_STORAGE on at91rm9200dk.h arm-linux-gcc -g -Os -fno-strict-aliasing -fno-common -ffixed-r8 -msoft-float -mshort-load-bytes -D__KERNEL__ -DTEXT_BASE=0x21f00000 -I/home/tmp/u-boot-2006-06-30-2020/include -fno-builtin -ffreestanding -nostdinc -isystem /usr/lib/gcc-lib/arm-linux/3.3.5/include -pipe -DCONFIG_ARM -D__ARM__ -march=armv4 -mapcs-32 -Wall -Wstrict-prototypes -c -o cmd_usb.o cmd_usb.c In file included from /home/tmp/u-boot-2006-06-30-2020/include/config.h:2, from /home/tmp/u-boot-2006-06-30-2020/include/common.h:35, from cmd_usb.c:28: /home/tmp/u-boot-2006-06-30-2020/include/configs/at91rm9200dk.h:128:1: warning: "CONFIG_COMMANDS" redefined /home/tmp/u-boot-2006-06-30-2020/include/configs/at91rm9200dk.h:118:1: warning: this is the location of the previous definition In file included from cmd_usb.c:34: /home/tmp/u-boot-2006-06-30-2020/include/usb.h:185:2: #error USB Lowlevel not defined make[1]: *** [cmd_usb.o] Error 1 make[1]: Leaving directory `/home/tmp/u-boot-2006-06-30-2020/common' make: *** [common/libcommon.a] Error 2 Is it possible to define CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_USB_STORAGE together ? Thanks for your help, -- nm.

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Re: [U-Boot-Users] Cache issue on MPC8xx
by Qichen Huang 24 Aug '06

24 Aug '06

On 8/24/06, Wolfgang Denk <wd(a)denx.de> wrote: > In message <b4ebaa9d0608240832i212b01aey4fe1362002756833(a)mail.gmail.com> you wrote: > > > > I did so, but still couldn't get D-Cache enabled. > > Then you did something wrong. I have been trapped in this problem for a long time. Could you tell me some more details. Thanks. What I did is: - set msr to 0. - disable D-cache - enable D-cache <-- and it crashes here. What is the correct way? Qichen > > > ------=_Part_166562_33295880.1156433560418 > > Content-Type: text/html; charset=ISO-8859-1 > > DO NOT POST HTML ON THIS LIST!!! Sorry, I didn't realize that. > > > Wolfgang Denk > > -- > Software Engineering: Embedded and Realtime Systems, Embedded Linux > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de > Our way is peace. > -- Septimus, the Son Worshiper, "Bread and Circuses", > stardate 4040.7. >

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[U-Boot-Users] Cache issue on MPC8xx
by Qichen Huang 24 Aug '06

24 Aug '06

Hi, I want to apply some simple tests on MPC855T and need to turn on both instruction- and data-cache. I have used the codes in cpu/mpc8xx/start.S(as follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do I have to enable the MMU first? If so, how? I have tried the code in linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while trying to write MSR_DR|MSR_IR to msr. Any ideas? Thanks! Qichen /* ************** dcache_enable in start.S ************ */ .globl dcache_enable dcache_enable: #if 0 SYNC #endif #if 1 lis r3, 0x0400 /* Set cache mode with MMU off */ mtspr MD_CTR, r3 #endif lis r3, IDC_INVALL@h mtspr DC_CST, r3 #if 0 lis r3, DC_SFWT@h mtspr DC_CST, r3 #endif lis r3, IDC_ENABLE@h mtspr DC_CST, r3 blr /* ************ turn_on_mmu in head_8xx.S *********** */ bl initial_mmu /* We now have the lower 8 Meg mapped into TLB entries, and the caches * ready to work. */ turn_on_mmu: mfmsr r0 ori r0,r0,MSR_DR|MSR_IR mtspr SRR1,r0 blr initial_mmu: tlbia /* Invalidate all TLB entries */ #ifdef CONFIG_PIN_TLB lis r8, MI_RSV4I@h ori r8, r8, 0x1c00 #else li r8, 0 #endif mtspr MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB lis r10, (MD_RSV4I | MD_RESETVAL)@h ori r10, r10, 0x1c00 mr r8, r10 #else lis r10, MD_RESETVAL@h #endif #ifndef CONFIG_8xx_COPYBACK oris r10, r10, MD_WTDEF@h #endif mtspr MD_CTR, r10 /* Set data TLB control */ /* Now map the lower 8 Meg into the TLBs. For this quick hack, * we can load the instruction and data TLB registers with the * same values. */ lis r8, KERNELBASE@h /* Create vaddr for TLB */ ori r8, r8, MI_EVALID /* Mark it valid */ mtspr MI_EPN, r8 mtspr MD_EPN, r8 li r8, MI_PS8MEG /* Set 8M byte page */ ori r8, r8, MI_SVALID /* Make it valid */ mtspr MI_TWC, r8 mtspr MD_TWC, r8 li r8, MI_BOOTINIT /* Create RPN for address 0 */ mtspr MI_RPN, r8 /* Store TLB entry */ mtspr MD_RPN, r8 lis r8, MI_Kp@h /* Set the protection mode */ mtspr MI_AP, r8 mtspr MD_AP, r8 /* Map another 8 MByte at the IMMR to get the processor * internal registers (among other things). */ #ifdef CONFIG_PIN_TLB addi r10, r10, 0x0100 mtspr MD_CTR, r10 #endif mfspr r9, 638 /* Get current IMMR */ andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ mr r8, r9 /* Create vaddr for TLB */ ori r8, r8, MD_EVALID /* Mark it valid */ mtspr MD_EPN, r8 li r8, MD_PS8MEG /* Set 8M byte page */ ori r8, r8, MD_SVALID /* Make it valid */ mtspr MD_TWC, r8 mr r8, r9 /* Create paddr for TLB */ ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ mtspr MD_RPN, r8 #ifdef CONFIG_PIN_TLB /* Map two more 8M kernel data pages. */ addi r10, r10, 0x0100 mtspr MD_CTR, r10 lis r8, KERNELBASE@h /* Create vaddr for TLB */ addis r8, r8, 0x0080 /* Add 8M */ ori r8, r8, MI_EVALID /* Mark it valid */ mtspr MD_EPN, r8 li r9, MI_PS8MEG /* Set 8M byte page */ ori r9, r9, MI_SVALID /* Make it valid */ mtspr MD_TWC, r9 li r11, MI_BOOTINIT /* Create RPN for address 0 */ addis r11, r11, 0x0080 /* Add 8M */ mtspr MD_RPN, r8 addis r8, r8, 0x0080 /* Add 8M */ mtspr MD_EPN, r8 mtspr MD_TWC, r9 addis r11, r11, 0x0080 /* Add 8M */ mtspr MD_RPN, r8 #endif /* Since the cache is enabled according to the information we * just loaded into the TLB, invalidate and enable the caches here. * We should probably check/set other modes....later. */ lis r8, IDC_INVALL@h mtspr IC_CST, r8 mtspr DC_CST, r8 lis r8, IDC_ENABLE@h mtspr IC_CST, r8 #ifdef CONFIG_8xx_COPYBACK mtspr DC_CST, r8 #else /* For a debug option, I left this here to easily enable * the write through cache mode */ lis r8, DC_SFWT@h mtspr DC_CST, r8 lis r8, IDC_ENABLE@h mtspr DC_CST, r8 #endif blr

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