August 2006 - U-Boot

[U-Boot-Users] A couple of MIPS questions
by Hans Zuidam 30 Aug '06

30 Aug '06

Hi, A couple of questions about the MIPS implementation of U-Boot. Maybe someone can answer them: In cpu/mips/start.S a large branch table is defined from the symbol _start onward. What is the reason for this? (There are only a few exception vectors defined in the MIPS32 architecture, although you can move them elsewhere in memory.) The instruction sequence for initialising the GOT is somehwat redundant, unless I am missing something: move gp, ra lw t1, 0(ra) move gp, t1 can be replaced by: lw gp, 0(ra) Is there a reason as to why the MIPS code does not (attempt to) make a register dump when an exception occurs? (BTW, the branches romReserved and romExcHandle are missing a NOP in their delay slot.) Is it safe to run with caches enabled? I.e. do all drivers either flush the cache when doing I/O or is it safer to run with caches disabled. Is there a reason for the serial, ethernet and USB drivers to exist in cpu/mips other than that they be belong to MIPS based SoCs? Thanks in advance. Regards, Hans Zuidam -- Hans Zuidam Sen. Systems Engineer, BL DTS ICE, Philips Semiconductors Building A410, Room 3.40 High Tech Campus 41, 5656 AE Eindhoven, The Netherlands Tel. +31 (0)40 2746579 E-Mail: hans.zuidam(a)philips.com

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[U-Boot-Users] Can't get gigabit working on Vitesse/Cicada 8201 TSEC
by Timur Tabi 30 Aug '06

30 Aug '06

I'm working on support for the MPC8349E-mITX, a variant of the MDS. I cannot git gigabit ethernet working. The board uses a Vitesse 8201, which is the same thing as a Cicada 8201. If I connect TSEC0 to a gigabit switch, U-Boot will detect that its running a gigabit speeds: Speed: 1000, full duplex Using Freescale TSEC0 device but packets don't get sent out (verified with ethereal). Therefore, pings time out. Ethernet works if I connect to a 100Mbs switch. I know it's not a hardware problem, because I have an older version of U-Boot (based on 1.1.3) that was developed in-house that supports this board. This older version works at gigabit speeds. Obviously, one of the following is true: 1) Gigabit TSEC support is broken in the latest U-Boot. 2) I made a mistake porting my code from the in-house version. 3) There is some code or configuration that needs to be done in the latest U-boot code that wasn't necessary in 1.1.3. My belief is that I'm misconfiguring the device somehow, but I don't know enough about this hardware to know where to look. Is there anything special that I need to do get gigabit working on a Vitesse/Cicada 8201 TSEC? -- Timur Tabi Linux Kernel Developer @ Freescale

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[U-Boot-Users] Promblem encounted during code reading
by enorm 30 Aug '06

30 Aug '06

Hi, I met some problems when reading sourcecode of u-boot 1.1.4 (for mpc85xx) file /cpu/mpc85xx/start.s line 276 276. #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) 277. /* Special sequence needed to update CCSRBAR itself */ 278. lis r4, CFG_CCSRBAR_DEFAULT@h 279. ori r4, r4, CFG_CCSRBAR_DEFAULT@l 280. 281. lis r5, CFG_CCSRBAR@h 282. ori r5, r5, CFG_CCSRBAR@l 283. srwi r6,r5,12 284. stw r6, 0(r4) 285. isync 286. 287. lis r5, 0xffff 288. ori r5,r5,0xf000 289. lwz r5, 0(r5) 290. isync 291. 292. lis r3, CFG_CCSRBAR@h 293. lwz r5, CFG_CCSRBAR@l(r3) 294. isync 295. #endif I think it means if we don't use default CCSRBAR, we put the CCSRBAR addr actually used to the proper place in default CCSRBAR, so that it can jump to the addr we want to automatically.(line 276-286). But, I don't know what line 287-294 does. Can some one tell me pls? Thanks for your help.

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[U-Boot-Users] Look for mips-linux-gcc
by Jiang Wang 30 Aug '06

30 Aug '06

I want to migrate uBoot into Broadcom MIPS64 CPU, such as BCM1250, BCM 1125H. Who can tell me where I can download "mips-linux-gcc" toolchains? Thanks a lot. --------------------------------- 抢注雅虎免费邮箱-3.5G容量，20M附件！

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[U-Boot-Users] Based on x86 build out u-boot image up to 1G!! Help!!
by 李皓 29 Aug '06

29 Aug '06

Hi, all! I am trying to build u-boot on sc520_cdp board. I have read all missives about sc520_cdp board, but still can’t solve my problem on HUGE size of u-boot.bin. After reading Mr. Jon Loeliger’s missive about _Why objdump Creates 4G U-Boot Images_, I know how to check the reason of u-boot. bin’s size. But after reading u-boot.lds in board/sc520_cdp/, I feel that I cannot change the mapping addresses, such as TEXT_BASE= 0x387c0000, and .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }. According to Mr. Jon Loeliger’s missive, text section’s address(0x387c0000) and .bios section’s address(around 0) result in the huge size of u-boot.bin. But I know because after start up computer it is realmode in x86, .bios section should be mapped to low address. So I feel in dilemma right now. What should I do? Guys out there who have built out u-boot.bin based on x86 successfully please help me! Detailed information will be nice. David_leeh

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[U-Boot-Users] [PATCH 00/03] Add MPC8641HPCN board port
by jdl＠freescale.com 29 Aug '06

29 Aug '06

Wolfgang, This set of patches adds the MPC8641HPCN board port. Booting using the Flat Device Tree assumes that Matthew McClintock's patches of June 27 have been applied. All of these patches can be inspected in plain text and downloaded here: http://www.jdl.com/software/patches Furthermore these patches plus Matthew's, can be obtained directly from the u-boot-86xx.git tree found on jdl.com: Browse it: http://www.jdl.com/git_repos Clone it: git://www.jdl.com/software/u-boot-86xx.git http://www.jdl.com/software/u-boot-86xx.git Apologies for such a large encoded patch. There were single files that exceeded the list post length in plain text form. Thanks, jdl CHANGELOG: * Add MPC8641HPCN board port - Add base level mpc86xx CPU support - Add MPC8641 HPCN board support - Support Flat Device Tree booting via downloaded DTB file - Add AHCI S-ATA and PCI-Express - Supports reset into alternate flash bank MAINTAINERS | 2 Makefile | 11 board/mpc8641hpcn/Makefile | 49 + board/mpc8641hpcn/config.mk | 31 + board/mpc8641hpcn/init.S | 180 +++++ board/mpc8641hpcn/mpc8641hpcn.c | 426 ++++++++++++ board/mpc8641hpcn/pixis.c | 321 +++++++++ board/mpc8641hpcn/pixis.h | 33 + board/mpc8641hpcn/sys_eeprom.c | 256 +++++++ board/mpc8641hpcn/u-boot.lds | 148 ++++ common/Makefile | 2 common/cmd_boot.c | 2 common/cmd_mac.c | 66 ++ common/cmd_scsi.c | 7 cpu/mpc86xx/Makefile | 48 + cpu/mpc86xx/cache.S | 374 +++++++++++ cpu/mpc86xx/config.mk | 26 + cpu/mpc86xx/cpu.c | 307 +++++++++ cpu/mpc86xx/cpu_init.c | 117 +++ cpu/mpc86xx/i2c.c | 269 ++++++++ cpu/mpc86xx/interrupts.c | 204 ++++++ cpu/mpc86xx/pci.c | 146 ++++ cpu/mpc86xx/pcie_indirect.c | 199 ++++++ cpu/mpc86xx/resetvec.S | 2 cpu/mpc86xx/spd_sdram.c | 1332 ++++++++++++++++++++++++++++++++++++++ cpu/mpc86xx/speed.c | 127 ++++ cpu/mpc86xx/start.S | 1227 +++++++++++++++++++++++++++++++++++ cpu/mpc86xx/traps.c | 226 ++++++ doc/README.mpc8641hpcn | 123 ++++ drivers/Makefile | 2 drivers/ahci.c | 702 ++++++++++++++++++++ drivers/rtl8139.c | 1 drivers/tsec.c | 71 ++ drivers/tsec.h | 20 + include/ahci.h | 190 +++++ include/asm-ppc/immap_86xx.h | 1364 +++++++++++++++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 15 include/asm-ppc/processor.h | 18 - include/asm-ppc/u-boot.h | 2 include/common.h | 14 include/configs/MPC8641HPCN.h | 641 ++++++++++++++++++ include/mpc86xx.h | 116 +++ include/pci_ids.h | 3 lib_ppc/board.c | 6 net/eth.c | 16 45 files changed, 9424 insertions(+), 18 deletions(-)

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[U-Boot-Users] generic PHY for tsec
by David Updegraff 29 Aug '06

29 Aug '06

Hi. With such a patch, the TSEC driver can work with a skillion more kinds of PHY than is currently the case. Surely falling back to a 'generic' is preferable than simply giving up? -dbu.

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[U-Boot-Users] multicast tftp client?
by mitsy 29 Aug '06

29 Aug '06

Has anyone implemented a multicast support for tftp client on u-boot? If so, how did it go? Thanks, mitsy

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[U-Boot-Users] Apologies
by Jon Loeliger 29 Aug '06

29 Aug '06

Guys, Apologies for accidental double post problem, there. jdl

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[U-Boot-Users] [PATCH 03/03] Add MPC8641HPCN board port
by jdl＠freescale.com 29 Aug '06

29 Aug '06

Here is part 3/3

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