June 2024 - U-Boot

v2024.07-rc4 issues on VisionFive v2
by Conor Dooley 17 Jun '24

17 Jun '24

Hey, After going from Vendor SPL/OpenSBI/U-Boot to OpenSBI v1.4++ plus v2024.07-rc4 SPL/U-Boot I ran into a boot loop problem relating to PCI: U-Boot 2024.07-rc4 (Jun 13 2024 - 15:09:34 +0100) CPU: sifive,u74-mc Model: StarFive VisionFive 2 v1.2A DRAM: 4 GiB Core: 136 devices, 26 uclasses, devicetree: board WDT: Not starting watchdog@13070000 MMC: mmc@16010000: 0, mmc@16020000: 1 Loading Environment from SPIFlash... SF: Detected gd25lq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB OK StarFive EEPROM format v2 --------EEPROM INFO-------- Vendor : StarFive Technology Co., Ltd. Product full SN: VF7110A1-2249-D004E000-00000540 data version: 0x2 PCB revision: 0xa1 BOM revision: A Ethernet MAC0 address: 6c:cf:39:00:17:95 Ethernet MAC1 address: 6c:cf:39:00:17:96 --------EEPROM INFO-------- starfive_7110_pcie pcie@2b000000: Starfive PCIe bus probed. starfive_7110_pcie pcie@2c000000: Starfive PCIe bus probed. In: serial@10000000 Out: serial@10000000 Err: serial@10000000 Net: eth0: ethernet@16030000, eth1: ethernet@16040000 starting USB... Bus xhci_pci: Register 5000420 NbrPorts 5 Starting the controller USB XHCI 1.00 scanning bus xhci_pci for devices... U-Boot SPL 2024.07-rc4 (Jun 13 2024 - 15:09:34 +0100) DDR version: dc2e84f0. Trying to boot from SPI This only appeared after I refreshed the environment by running. `env default -a -f; env save`. Before that things worked "fine", I suppose because nothing actually touched PCI. I've just disabled PCI for now and things are working once more. I've not attempted to bisect/debug this, cos that's not the fastest process while running U-Boot out of flash. In case it is relevant, the board I have is one of the "super early bird" ones. Cheers, Conor.

4 3

[PATCH] ARM: stm32: Ping IWDG on exit from PSCI suspend code
by Marek Vasut 17 Jun '24

17 Jun '24

Make sure the OS would not get any spurious IWDG pretimeout IRQ right after the system wakes up. This may happen in case the SoC got woken up by another source than the IWDG pretimeout and the pretimeout IRQ arrived immediately afterward, but too late to be handled by the suspend main loop. In case either of the IWDG is enabled, ping it first and then return to the OS. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Igor Opaniuk <igor.opaniuk(a)foundries.io> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 4f2379df45f..e99103910d9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + /* + * Make sure the OS would not get any spurious IWDG pretimeout IRQ + * right after the system wakes up. This may happen in case the SoC + * got woken up by another source than the IWDG pretimeout and the + * pretimeout IRQ arrived immediately afterward, but too late to be + * handled by the main loop above. In case either of the IWDG is + * enabled, ping it first and then return to the OS. + */ + + /* Ping IWDG1 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(22)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(23)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + /* * The system has resumed successfully. Rewrite LR register stored * on stack with 'ep' value, so that on return from this PSCI call, -- 2.43.0

3 7

[PATCH 1/3] rockchip: rock-3a: rock5a: rock5b: add USB GADGET related configs
by FUKAUMI Naoki 17 Jun '24

17 Jun '24

add USB GADGET related configs for USB OTG port on ROCK 3A/5A/5B. Signed-off-by: FUKAUMI Naoki <naoki(a)radxa.com> --- configs/rock-3a-rk3568_defconfig | 6 ++++++ configs/rock5a-rk3588s_defconfig | 6 ++++++ configs/rock5b-rk3588_defconfig | 1 + 3 files changed, 13 insertions(+) diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 66ac2f6d7a..0568a73038 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -37,6 +37,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -50,6 +52,7 @@ CONFIG_SPL_SYSCON=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -90,4 +93,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index c09e6655f0..e06052cd80 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -27,6 +27,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -37,6 +39,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -67,4 +70,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index fc118cea7b..80a2f2fed5 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -- 2.43.0

2 5

[PATCH] mtd: nand: pxa3xx: Incorrect bitflip return on page read
by Ravi Minnikanti 16 Jun '24

16 Jun '24

Once a page is read with higher bitflips all subsequent reads are returning the same bitflip value even though they have none. max_bitflip variable is not being reset to 0 across page reads. This is causing problems like incorrectly marking erase blocks bad by UBI and causing read failures. Verified the change with both MTD reads and UBI. This change is inline with other NFC drivers. Sample error log where a block is marked bad incorrectly: ubi0: fixable bit-flip detected at PEB 125 ubi0: run torture test for PEB 125 ubi0: fixable bit-flip detected at PEB 125 ubi0 error: torture_peb: read problems on freshly erased PEB 125, must be bad ubi0 error: erase_worker: failed to erase PEB 125, error -5 ubi0: mark PEB 125 as bad Signed-off-by: rminnikanti <rminnikanti(a)marvell.com> --- drivers/mtd/nand/raw/pxa3xx_nand.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 1d9a6d107b..d2a4faad56 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -800,6 +800,11 @@ static void prepare_start_command(struct pxa3xx_nand_info *info, int command) info->ecc_err_cnt = 0; info->ndcb3 = 0; info->need_wait = 0; + /* + * Reset max_bitflips to zero. Once command is complete, + * max_bitflips for this READ is returned in ecc.read_page() + */ + info->max_bitflips = 0; switch (command) { case NAND_CMD_READ0: -- 2.17.1

3 9

[PATCH 0/7] watchdog_reset cleanup
by Rasmus Villemoes 16 Jun '24

16 Jun '24

watchdog_reset is no more. That is, it is no longer called from anywhere, so any leftover definitions are just dead weight, and references in comments need to be updated. I don't have access to any m68k, sh or powerpc boards. Only lightly compile-tested. Apart from the two sh4 patches, these are independent of each other and can be applied individually. Cc: Angelo Dureghello <angelo(a)kernel-space.org> Cc: Christophe Leroy <christophe.leroy(a)csgroup.eu> Cc: Huan Wang <alison.wang(a)nxp.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Rasmus Villemoes (7): m68k: remove dead code wdt-uclass: watchdog_reset cleanup serial: ns16550: fix comment to mention schedule instead of watchdog_reset sh4: move reset_cpu() from watchdog.c to cpu.c sh4: remove watchdog.c file powerpc: mpc83xx: remove unused watchdog_reset() function powerpc: mpc85xx: remove dead watchdog-related code arch/m68k/cpu/mcf52x2/cpu.c | 108 --------------------------------- arch/powerpc/cpu/mpc83xx/cpu.c | 15 ----- arch/powerpc/cpu/mpc85xx/cpu.c | 31 ---------- arch/sh/cpu/sh4/Makefile | 2 +- arch/sh/cpu/sh4/cpu.c | 10 +++ arch/sh/cpu/sh4/watchdog.c | 61 ------------------- drivers/serial/ns16550.c | 8 +-- drivers/watchdog/wdt-uclass.c | 19 +----- include/watchdog.h | 3 - 9 files changed, 17 insertions(+), 240 deletions(-) delete mode 100644 arch/sh/cpu/sh4/watchdog.c -- 2.40.1.1.g1c60b9335d

3 10

[PATCH v4 0/3] cyclic/watchdog patches
by Rasmus Villemoes 16 Jun '24

16 Jun '24

A bit of a mixed bag. I've been wanting to submit something like 3/3 for a while. So when I stumbled on Marek's patch https://lore.kernel.org/u-boot/20240316201416.211480-1-marek.vasut+renesas@… , I got reminded of that plan, and I think that patch could be more readable if we adopt this model. While actually doing those mostly mechanical changes, I stumbled on two separate issues that probably want fixing regardless of the fate of 3/3. Mostly just compile-tested, and now also checked that at least the sandbox test runs succesfully, and that it builds both with and without CONFIG_CYCLIC. v4: Make sure there's only one definition of struct cyclic_info, previous versions failed to move the full definition under #ifdef CONFIG_CYCLIC, breaking builds with !CONFIG_CYCLIC. v3: Also update the unit test according to the new API. v2: Add R-bs from Stefan. Fixup whitespace in the doc/ part. Rebase to current master (676903c1b97), fixing trivial conflict with 301bac6047c8. Rasmus Villemoes (3): cyclic: stop strdup'ing name in cyclic_register() wdt-uclass: prevent multiple cyclic_register calls cyclic: make clients embed a struct cyclic_info in their own data structure board/Marvell/octeon_nic23/board.c | 9 ++++--- cmd/cyclic.c | 12 ++++------ common/cyclic.c | 24 +++++-------------- doc/develop/cyclic.rst | 26 ++++++++++++-------- drivers/watchdog/wdt-uclass.c | 38 ++++++++++++++++-------------- include/cyclic.h | 37 +++++++++++++++-------------- test/common/cyclic.c | 19 +++++++++------ 7 files changed, 84 insertions(+), 81 deletions(-) -- 2.40.1.1.g1c60b9335d

3 10

[PATCH] efi: capsule: Improve capsule update porting to new boards
by Jonathan Humphreys 16 Jun '24

16 Jun '24

Add to the capsule update porting documentation that when capsule authentication is enabled (via EFI_CAPSULE_AUTHENTICATE), a public key certificate corresponding to the capsule signing key must be specified. Also add a config (EFI_CAPSULE_BOARD_INSECURE) that is set by default and causes a warning (info level) alerting a developer to consult this porting section to ensure the capsule update capability is secure for the platform. Once this section has been reviewed and confidence is established in the security of the capsule update implementation for this board, deselecting the EFI_CAPSULE_BOARD_INSECURE config will remove the warning. This config is to balance the desire to provide a reference implementation in upstream for capsule authentication but also provide some safeguards to prevent developers from overlooking the need to properly secure their implementation. Signed-off-by: Jonathan Humphreys <j-humphreys(a)ti.com> --- doc/develop/uefi/uefi.rst | 30 +++++++++++++++++++++++------- lib/efi_loader/Kconfig | 13 +++++++++++++ lib/efi_loader/efi_capsule.c | 5 +++++ 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index 985956ab85c..1c98c6e4ab4 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -526,6 +526,7 @@ following command can be issued --guid c1b629f1-ce0e-4894-82bf-f0a38387e630 \ optee.bin optee.capsule +.. _Enabling Capsule Authentication: Enabling Capsule Authentication ******************************* @@ -631,17 +632,32 @@ where version.dtso looks like:: The properties of image-type-id and image-index must match the value defined in the efi_fw_image array as image_type_id and image_index. -Porting Capsule Updates to new boards -************************************* +Porting Capsule Update to new boards +************************************ It is important, when using a reference board as a starting point for a custom board, that certain steps are taken to properly support Capsule Updates. -Capsule GUIDs need to be unique for each firmware and board. That is, if two -firmwares are built from the same source but result in different binaries -because they are built for different boards, they should have different GUIDs. -Therefore it is important when creating support for a new board, new GUIDs are -defined in the board's header file. *DO NOT* reuse capsule GUIDs. +Capsule GUIDs need to be unique for each firmware and board. That is, even +if two firmwares are built from the same source but result in different +binaries because they are built for different boards, they should have +different GUIDs. Therefore it is important when creating support for a new +board, new GUIDs are defined in the board's header file. *DO NOT* reuse +capsule GUIDs. + +When capsule authentication is enabled (via EFI_CAPSULE_AUTHENTICATE), it +is also very important to set the public key certificate corresponding to +the capsule signing key. See :ref:`Enabling Capsule Authentication` for +more information on signing capsules. *DO NOT* reuse the certificate file +from the reference board, which usually would be based on the development +board keys. + +By default, the EFI_CAPSULE_BOARD_INSECURE config is set to true and causes +a warning (info level) alerting a developer to consult this section to +ensure the capsule update capability is secure for the platform. Once this +section has been reviewed and confidence is established in the security of +the capsule update implementation for this board, deselecting +EFI_CAPSULE_BOARD_INSECURE config will remove the warning. Executing the boot manager ~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 23079a5709d..f4b1a20ee40 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -236,6 +236,19 @@ config EFI_CAPSULE_ON_DISK_EARLY executed as part of U-Boot initialisation so that they will surely take place whatever is set to distro_bootcmd. +config EFI_CAPSULE_BOARD_INSECURE + bool "Permit insecure capsule-on-disk support" + depends on EFI_HAVE_CAPSULE_SUPPORT + default y + help + Permit insecure capsule update support and emit a warning (info level) + when applying capsule updates, indicating that the configuration is + insecure and including a link to the capsule update porting guide in + U-Boot docs. Disabling this option removes the warning. A developer + configuration doesn't need to be secure, but before making a product + from the configuration, the intent is to developers alert of steps that + must be taken. + config EFI_CAPSULE_FIRMWARE bool diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 0937800e588..76ade2809d9 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -1329,6 +1329,11 @@ efi_status_t efi_launch_capsules(void) if (!nfiles) return EFI_SUCCESS; + if (IS_ENABLED(CONFIG_EFI_CAPSULE_BOARD_INSECURE)) { + log_info("WARNING: EFI Capsules might be insecure!\n"); + log_info("WARNING: Please check https://docs.u-boot.org/en/latest/develop/uefi/uefi.html#porting-capsule-up…"); + } + /* Launch capsules */ for (i = 0, ++index; i < nfiles; i++, index++) { log_debug("Applying %ls\n", files[i]); -- 2.34.1

4 3

[PATCH] tpm: measure DTB in PCR1 instead of PCR0
by Ilias Apalodimas 15 Jun '24

15 Jun '24

The PC client spec [0], doesn't describe measurements for DTBs. It does describe what do to for ACPI tables though. There is a description for ACPI in 3.3.4.1 PCR[0] – SRTM, POST BIOS, and Embedded Drivers and they explicitly mention ACPI in there. There's no mention of ACPI in 3.3.4.2 PCR[1] – Host Platform Configuration. However, in Figure 6 -- PCR Mapping of UEFI Components ACPI is shown in PCR1. The general description also mentions PCR0 is for code and PCR1 is for data such as ACPI and SMBIOS. So let's switch over the DTB measurements to PCR1 which seems a better fit. [0] https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firm… Reported-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- boot/bootm.c | 2 +- lib/efi_loader/efi_tcg2.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/boot/bootm.c b/boot/bootm.c index 6fa8edab021e..3de87eb185d7 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -963,7 +963,7 @@ int bootm_measure(struct bootm_headers *images) goto unmap_initrd; if (IS_ENABLED(CONFIG_MEASURE_DEVICETREE)) { - ret = tcg2_measure_data(dev, &elog, 0, images->ft_len, + ret = tcg2_measure_data(dev, &elog, 1, images->ft_len, (u8 *)images->ft_addr, EV_TABLE_OF_DEVICES, strlen("dts") + 1, diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 51264c1b998c..a8a54c9f131d 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -1328,7 +1328,7 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb) sha256_update(&hash_ctx, (u8 *)dtb + fdt_off_mem_rsvmap(dtb), rsvmap_size); sha256_finish(&hash_ctx, blob->data + blob->blob_description_size); - ret = measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob); + ret = measure_event(dev, 1, EV_POST_CODE, event_size, (u8 *)blob); free(blob); return ret; -- 2.45.1

2 2

[PATCH] board: imx8mn_s2: Update timing with production one
by Michael Trimarchi 14 Jun '24

14 Jun '24

The timing upstream was wrong corresponding to the production. This come evident after commit b614ddb5d33 (ddr: imx: Save the FW loading if it hasn't changed). This change fix booting from usb Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 23 ++++++++++++--------- board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 14 +++++++------ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c index 0da641834d..33452d2ad5 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610040 }, + { 0x3d400064, 0x300040 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -67,10 +67,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400498, 0x7ff }, { 0x3d40049c, 0xe00 }, { 0x3d4004a0, 0x7ff }, - { 0x3d402064, 0x28001b }, + { 0x3d402064, 0x14001b }, { 0x3d4020dc, 0x12200004 }, - { 0x3d4020e0, 0x0 }, - { 0x3d402100, 0x7090b07 }, + { 0x3d4020e0, 0x400000 }, + { 0x3d402100, 0x7090507 }, { 0x3d402104, 0x20209 }, { 0x3d402108, 0x3030407 }, { 0x3d40210c, 0x2006 }, @@ -680,12 +680,13 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x31f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1d70 }, { 0x54030, 0x4 }, - { 0x54031, 0x18 }, + { 0x54031, 0x58 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -700,11 +701,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +889,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, diff --git a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c index f845395ad9..ca14a47442 100644 --- a/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c +++ b/board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c @@ -18,15 +18,15 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x20 }, { 0x3d400000, 0xa1040001 }, - { 0x3d400064, 0x610068 }, + { 0x3d400064, 0x300068 }, { 0x3d4000d0, 0xc00200c5 }, { 0x3d4000d4, 0x1000b }, { 0x3d4000dc, 0x1d700004 }, - { 0x3d4000e0, 0x180000 }, + { 0x3d4000e0, 0x580000 }, { 0x3d4000e4, 0x90000 }, - { 0x3d4000f0, 0x0 }, + { 0x3d4000f0, 0x2 }, { 0x3d4000f4, 0xee5 }, - { 0x3d400100, 0xc101b0e }, + { 0x3d400100, 0xc100d0e }, { 0x3d400104, 0x30314 }, { 0x3d400108, 0x4060509 }, { 0x3d40010c, 0x2006 }, @@ -700,11 +700,13 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54006, 0x140 }, { 0x54007, 0x1000 }, { 0x54008, 0x101 }, + { 0x54009, 0x200 }, { 0x5400b, 0x21f }, { 0x5400c, 0xc8 }, { 0x54012, 0x1 }, { 0x5402f, 0x1220 }, { 0x54030, 0x4 }, + { 0x54031, 0x40 }, { 0x5403a, 0x1323 }, { 0xd0000, 0x1 }, }; @@ -886,11 +888,11 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, + { 0x2000b, 0x1c2 }, { 0x2000c, 0x64 }, { 0x2000d, 0x3e8 }, { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, + { 0x12000b, 0xbb }, { 0x12000c, 0x26 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, -- 2.43.0

2 1

[PATCH v6 00/24] EFI: ti: Enable EFI capsule updates
by Jonathan Humphreys 14 Jun '24

14 Jun '24

Enable on disk capsule updates, which includes defining the firmware components (tiboot3, spl, u-boot) and enabling processing of raw capsule updates. This is enabled for several TI SoC based platforms: AM64, AM62, AM62p, AM69, BeaglePlay, J7, and BeagleboneAI. The configs to enable this are in a single base config file. This will make it more scalable to add additional EFI capsule features (like authentication) across all TI boards that have capsules enabled. This series also includes enabling serial flash DFU for AM62 and MMC DFU for beagleplay. Changes from v1: - Added sysfw.itb capsule definition to beagleboneai64 - removed extra commas in structure definitions Changes from v2: - Added documentation on OSPI flash layouts - Improved comments for capsule GUIDs definitions - Defined board unique capsule GUIDs and put definitions in board specific files - Added a Capsule Update porting section to the documentation Changes from v3: - Added better commit messages based upon checkpatch warnings. - Remove conditional inclusion of capsule update firmware info - Converted OSPI layout diagram to svg format Link to v3: https://lore.kernel.org/r/20240419205701.163821-1-j-humphreys@ti.com Changes from v4: - Added am69 SK board - Corrected a few spelling mistakes and clarity improvements in k3 docs section - Added CONFIG_SET_DFU_ALT_INFO guard around set_dfu_alt_info() Link to v4: https://lore.kernel.org/r/20240509164123.1753050-1-j-humphreys@ti.com Changes from v5: - Created an EFI capsule base config for TI boards, making adding additional capsule features on TI boards more scalable. Link to v5: https://lore.kernel.org/r/20240531222118.2618041-1-j-humphreys@ti.com Jonathan Humphreys (24): doc: uefi: capsules: Add Capsule Update porting section doc: ti: k3: Correct spelling mistakes and improve clarity configs: ti: Create base EFI capsule configs for TI K3 devices board: am64x: Define capsule update firmware info configs: am64x: Enable EFI capsule update doc: board: ti: am64x: document OSPI layout board: j721e: Define capsule update firmware info configs: j721e: Enable EFI capsule update doc: board: ti: j721e: document OSPI layout board: beagleplay: Define capsule update firmware info configs: beagleplay: Enable DFU for MMC configs: beagleplay: Enable EFI capsule update board: am62x: Define capsule update firmware info configs: am62x: Enable EFI capsule update doc: board: ti: am62x: document OSPI layout board: am62px: Define capsule update firmware info configs: am62px: Enable EFI capsule update doc: board: ti: am62px: document OSPI layout board: beagleboneai64: Define capsule update firmware info configs: beagleboneai64: Enable EFI capsule update configs: j784s4_evm: Enable serial flash DFU support board: sk-am69: Define capsule update firmware info configs: j784s4: Enable EFI capsule update doc: board: ti: j784s4: document OSPI NOR layout board/beagle/beagleboneai64/Kconfig | 4 +- board/beagle/beagleboneai64/beagleboneai64.c | 39 + board/beagle/beagleplay/Kconfig | 4 +- board/beagle/beagleplay/beagleplay.c | 34 + board/ti/am62px/evm.c | 34 + board/ti/am62x/evm.c | 34 + board/ti/am64x/evm.c | 34 + board/ti/j721e/evm.c | 40 + board/ti/j784s4/evm.c | 34 + configs/am62px_evm_a53_defconfig | 2 + configs/am62x_beagleplay_a53_defconfig | 4 + configs/am62x_evm_a53_defconfig | 1 + configs/am64x_evm_a53_defconfig | 2 + configs/j721e_beagleboneai64_a72_defconfig | 2 + configs/j721e_evm_a72_defconfig | 2 + configs/j784s4_evm_a72_defconfig | 5 + configs/k3_efi_capsule.config | 2 + doc/board/ti/am62px_sk.rst | 24 + doc/board/ti/am62x_sk.rst | 24 + doc/board/ti/am64x_evm.rst | 24 + doc/board/ti/img/ospi_sysfw-am64.svg | 802 ++++++++++ doc/board/ti/img/ospi_sysfw.svg | 1464 ++++++++++-------- doc/board/ti/img/ospi_sysfw2.svg | 802 ++++++++++ doc/board/ti/img/ospi_sysfw3.svg | 802 ++++++++++ doc/board/ti/j721e_evm.rst | 58 +- doc/board/ti/j784s4_evm.rst | 28 + doc/board/ti/k3.rst | 10 +- doc/develop/uefi/uefi.rst | 12 + include/configs/am62px_evm.h | 24 + include/configs/am62x_evm.h | 24 + include/configs/am64x_evm.h | 24 + include/configs/beagleboneai64.h | 55 + include/configs/beagleplay.h | 41 + include/configs/j721e_evm.h | 29 + include/configs/j784s4_evm.h | 24 + 35 files changed, 3864 insertions(+), 684 deletions(-) create mode 100644 configs/k3_efi_capsule.config create mode 100644 doc/board/ti/img/ospi_sysfw-am64.svg create mode 100644 doc/board/ti/img/ospi_sysfw2.svg create mode 100644 doc/board/ti/img/ospi_sysfw3.svg create mode 100644 include/configs/beagleboneai64.h create mode 100644 include/configs/beagleplay.h -- 2.34.1

3 30

[PATCH] configs: j784s4: Enable basic EFI CMD support
by Jonathan Humphreys 14 Jun '24

14 Jun '24

Enable basic configs for EFI CMD support. Signed-off-by: Jonathan Humphreys <j-humphreys(a)ti.com> --- configs/j784s4_evm_a72_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index bb9603bef0f..665aa39a6bf 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -53,12 +53,15 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y -- 2.34.1

2 1

[PATCH] configs: j784s4: Enable RTC emulation
by Jonathan Humphreys 14 Jun '24

14 Jun '24

Enable RTC emulation for System Ready IR tests. Signed-off-by: Jonathan Humphreys <j-humphreys(a)ti.com> --- configs/j784s4_evm_a72_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 665aa39a6bf..8ef50f690fb 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -138,6 +138,8 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_RESET_TI_SCI=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -150,3 +152,4 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_DM_THERMAL=y +CONFIG_EFI_SET_TIME=y -- 2.34.1

2 1

[PULL] Pull request for u-boot master / v2024.07 = u-boot-stm32-20240614
by Patrice CHOTARD 14 Jun '24

14 Jun '24

Hi Tom Please pull the STM32 related fixes for u-boot/master, v2024.07: u-boot-stm32-20240614 CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/21116 The following changes since commit ca6a992e09441d6cca73439c63c3735f86b36ea4: cmd: sound: fix help text (2024-06-13 09:31:56 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20240614 for you to fetch changes up to 55df13d930f4f191f458a6454f4b8e614e19c215: ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM (2024-06-14 13:25:06 +0200) ---------------------------------------------------------------- STM32MP1: _ Fix spl compilation warning _ Fix optee_get_reserved_memory() _ Fix livetree conversion on STM32MP15xx DHSOM ---------------------------------------------------------------- Marek Vasut (1): ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM Patrice Chotard (2): stm32mp1: spl: Fix compilation warnings stm32mp1: spl: Update optee_get_reserved_memory() return value arch/arm/mach-stm32mp/stm32mp1/spl.c | 4 ++-- board/dhelectronics/dh_stm32mp1/board.c | 15 +++++++++++++--

2 1

[PATCH v7] test/py: net_boot: Add test cases for net boot
by Love Kumar 14 Jun '24

14 Jun '24

Add tests for booting image using tftpboot/pxe boot commands, tftpboot boot case loads the FIT image into DDR and boots using bootm command whereas pxe boot cases downloads the pxe configuration file from the TFTP server and interprets it to boot the images mentioned in the pxe configurations file. This test relies on boardenv_* containing configuration values including the parameter 'pattern'. tftpboot/pxe boot cases boots the Linux till the boot log pattern value is matched. For example, if the parameter 'pattern' is defined as 'login:', it will boot till login prompt. Signed-off-by: Love Kumar <love.kumar(a)amd.com> --- Changes in v2: - Expand commit message Changes in v3: - Add the config option to skip the test - Remove imi command to check FIT image config - Configure static networking only if DHCP fails Changes in v4: - Use configured timeout for tftpboot Changes in v5: - Add pre-req for boot test to enable error check - Merged boot and boot config test Changes in v6: - Use common setup_networking function for tftp and pxe cases - Check for bootfile env variable for pxe config name Changes in v7: - Set pxefile_addr_r env variable to use the same address for loading and running pxe config --- test/py/tests/test_net_boot.py | 403 +++++++++++++++++++++++++++++++++ 1 file changed, 403 insertions(+) create mode 100644 test/py/tests/test_net_boot.py diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py new file mode 100644 index 000000000000..4729ccf07feb --- /dev/null +++ b/test/py/tests/test_net_boot.py @@ -0,0 +1,403 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +import pytest +import u_boot_utils +import test_net +import re + +""" +Note: This test relies on boardenv_* containing configuration values to define +which the network environment available for testing. Without this, this test +will be automatically skipped. + +For example: + +# Details regarding a boot image file that may be read from a TFTP server. This +# variable may be omitted or set to None if TFTP boot testing is not possible +# or desired. +env__net_tftp_bootable_file = { + 'fn': 'image.ub', + 'addr': 0x10000000, + 'size': 5058624, + 'crc32': 'c2244b26', + 'pattern': 'Linux', + 'config': 'config@2', + 'timeout': 50000, + 'check_type': 'boot_error', + 'check_pattern': 'ERROR', +} + +# False or omitted if a TFTP boot test should be tested. +# If TFTP boot testing is not possible or desired, set this variable to True. +# For example: If FIT image is not proper to boot +env__tftp_boot_test_skip = False + +# Here is the example of FIT image configurations: +configurations { + default = "config@1"; + config@1 { + description = "Boot Linux kernel with config@1"; + kernel = "kernel@0"; + fdt = "fdt@0"; + ramdisk = "ramdisk@0"; + hash@1 { + algo = "sha1"; + }; + }; + config@2 { + description = "Boot Linux kernel with config@2"; + kernel = "kernel@1"; + fdt = "fdt@1"; + ramdisk = "ramdisk@1"; + hash@1 { + algo = "sha1"; + }; + }; +}; + +# Details regarding a file that may be read from a TFTP server. This variable +# may be omitted or set to None if PXE testing is not possible or desired. +env__net_pxe_bootable_file = { + 'fn': 'default', + 'addr': 0x10000000, + 'size': 74, + 'timeout': 50000, + 'pattern': 'Linux', + 'valid_label': '1', + 'invalid_label': '2', + 'exp_str_invalid': 'Skipping install for failure retrieving', + 'local_label': '3', + 'exp_str_local': 'missing environment variable: localcmd', + 'empty_label': '4', + 'exp_str_empty': 'No kernel given, skipping boot', + 'check_type': 'boot_error', + 'check_pattern': 'ERROR', +} + +# False or omitted if a PXE boot test should be tested. +# If PXE boot testing is not possible or desired, set this variable to True. +# For example: If pxe configuration file is not proper to boot +env__pxe_boot_test_skip = False + +# Here is the example of pxe configuration file ordered based on the execution +# flow: +1) /tftpboot/pxelinux.cfg/default-arm-zynqmp + + menu include pxelinux.cfg/default-arm + timeout 50 + + default Linux + +2) /tftpboot/pxelinux.cfg/default-arm + + menu title Linux boot selections + menu include pxelinux.cfg/default + + label install + menu label Invalid boot + kernel kernels/install.bin + append console=ttyAMA0,38400 debug earlyprintk + initrd initrds/uzInitrdDebInstall + + label local + menu label Local boot + append root=/dev/sdb1 + localboot 1 + + label boot + menu label Empty boot + +3) /tftpboot/pxelinux.cfg/default + + label Linux + menu label Boot kernel + kernel Image + fdt system.dtb + initrd rootfs.cpio.gz.u-boot +""" + +def setup_networking(u_boot_console): + test_net.test_net_dhcp(u_boot_console) + if not test_net.net_set_up: + test_net.test_net_setup_static(u_boot_console) + +def setup_tftpboot_boot(u_boot_console): + f = u_boot_console.config.env.get('env__net_tftp_bootable_file', None) + if not f: + pytest.skip('No TFTP bootable file to read') + + setup_networking(u_boot_console) + addr = f.get('addr', None) + if not addr: + addr = u_boot_utils.find_ram_base(u_boot_console) + + fn = f['fn'] + timeout = f.get('timeout', 50000) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert expected_text in output + + expected_crc = f.get('crc32', None) + output = u_boot_console.run_command('crc32 %x $filesize' % addr) + if expected_crc: + assert expected_crc in output + + pattern = f.get('pattern') + chk_type = f.get('check_type', 'boot_error') + chk_pattern = re.compile(f.get('check_pattern', 'ERROR')) + config = f.get('config', None) + + return addr, timeout, pattern, chk_type, chk_pattern, config + +(a)pytest.mark.buildconfigspec('cmd_net') +def test_net_tftpboot_boot(u_boot_console): + """Boot the loaded image + + A boot file (fit image) is downloaded from the TFTP server and booted using + bootm command with the default fit configuration, its boot log pattern are + validated. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__tftp_boot_test_skip', True): + pytest.skip('TFTP boot test is not enabled!') + + addr, timeout, pattern, chk_type, chk_pattern, imcfg = setup_tftpboot_boot( + u_boot_console + ) + + if imcfg: + bootcmd = 'bootm %x#%s' % (addr, imcfg) + else: + bootcmd = 'bootm %x' % addr + + with u_boot_console.enable_check( + chk_type, chk_pattern + ), u_boot_console.temporary_timeout(timeout): + try: + # wait_for_prompt=False makes the core code not wait for the U-Boot + # prompt code to be seen, since it won't be on a successful kernel + # boot + u_boot_console.run_command(bootcmd, wait_for_prompt=False) + + # Wait for boot log pattern + u_boot_console.wait_for(pattern) + finally: + # This forces the console object to be shutdown, so any subsequent + # test will reset the board back into U-Boot. We want to force this + # no matter whether the kernel boot passed or failed. + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +def setup_pxe_boot(u_boot_console): + f = u_boot_console.config.env.get('env__net_pxe_bootable_file', None) + if not f: + pytest.skip('No PXE bootable file to read') + + setup_networking(u_boot_console) + bootfile = u_boot_console.run_command('echo $bootfile') + if not bootfile: + bootfile = '<NULL>' + + return f, bootfile + +(a)pytest.mark.buildconfigspec('cmd_net') +(a)pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot(u_boot_console): + """Test the pxe boot command. + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f, bootfile = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + + if addr: + u_boot_console.run_command('setenv pxefile_addr_r %x' % addr) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert f"Config file '{bootfile}' found" in output + + pattern = f.get('pattern') + chk_type = f.get('check_type', 'boot_error') + chk_pattern = re.compile(f.get('check_pattern', 'ERROR')) + + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.enable_check( + chk_type, chk_pattern + ), u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +(a)pytest.mark.buildconfigspec('cmd_net') +(a)pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot_config(u_boot_console): + """Test the pxe boot command by selecting different combination of labels + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f, bootfile = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + local_label = f['local_label'] + empty_label = f['empty_label'] + exp_str_local = f['exp_str_local'] + exp_str_empty = f['exp_str_empty'] + + if addr: + u_boot_console.run_command('setenv pxefile_addr_r %x' % addr) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert f"Config file '{bootfile}' found" in output + + pattern = f.get('pattern') + chk_type = f.get('check_type', 'boot_error') + chk_pattern = re.compile(f.get('check_pattern', 'ERROR')) + + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.enable_check( + chk_type, chk_pattern + ), u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + + # pxe config is loaded where multiple labels are there and need to + # select particular label to boot and check for expected string + # In this case, local label is selected and it should look for + # localcmd env variable and if that variable is not defined it + # should not boot it and come out to u-boot prompt + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(local_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_local]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_local} did not match!' + + # In this case, empty label is selected and it should look for + # kernel image path and if it is not set it should fail it and load + # default label to boot + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(empty_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_empty]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_empty} did not match!' + + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() + +(a)pytest.mark.buildconfigspec('cmd_net') +(a)pytest.mark.buildconfigspec('cmd_pxe') +def test_net_pxe_boot_config_invalid(u_boot_console): + """Test the pxe boot command by selecting invalid label + + A pxe configuration file is downloaded from the TFTP server and interpreted + to boot the images mentioned in pxe configuration file. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + if u_boot_console.config.env.get('env__pxe_boot_test_skip', True): + pytest.skip('PXE boot test is not enabled!') + + f, bootfile = setup_pxe_boot(u_boot_console) + addr = f.get('addr', None) + timeout = f.get('timeout', u_boot_console.p.timeout) + fn = f['fn'] + invalid_label = f['invalid_label'] + exp_str_invalid = f['exp_str_invalid'] + + if addr: + u_boot_console.run_command('setenv pxefile_addr_r %x' % addr) + + with u_boot_console.temporary_timeout(timeout): + output = u_boot_console.run_command('pxe get') + + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert 'TIMEOUT' not in output + assert expected_text in output + assert f"Config file '{bootfile}' found" in output + + pattern = f.get('pattern') + if not addr: + pxe_boot_cmd = 'pxe boot' + else: + pxe_boot_cmd = 'pxe boot %x' % addr + + with u_boot_console.temporary_timeout(timeout): + try: + u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False) + + # pxe config is loaded where multiple labels are there and need to + # select particular label to boot and check for expected string + # In this case invalid label is selected, it should load invalid + # label and if it fails it should load the default label to boot + u_boot_console.wait_for('Enter choice:') + u_boot_console.run_command(invalid_label, wait_for_prompt=False) + expected_str = u_boot_console.p.expect([exp_str_invalid]) + assert ( + expected_str == 0 + ), f'Expected string: {exp_str_invalid} did not match!' + + u_boot_console.wait_for(pattern) + finally: + u_boot_console.drain_console() + u_boot_console.cleanup_spawn() -- 2.25.1

2 2

[PATCH] test/py: Add support to enable check for bad pattern
by Love Kumar 14 Jun '24

14 Jun '24

Executing a u-boot command may raise an error or extra bad pattern, beyond the default bad patterns. Providing a way to enable the console output error check in test. For example, description for OS boot test: import re check_type = 'kernel_boot_error' check_pattern = re.compile('ERROR -2: can't get kernel image!') with u_boot_console.enable_check(check_type, check_pattern): u_boot_console.run_command('<boot command>') Signed-off-by: Love Kumar <love.kumar(a)amd.com> --- test/py/u_boot_console_base.py | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 26b6de07f88f..2f882fb53fc5 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -57,6 +57,32 @@ class ConsoleDisableCheck(object): self.console.disable_check_count[self.check_type] -= 1 self.console.eval_bad_patterns() +class ConsoleEnableCheck(object): + """Context manager (for Python's with statement) that temporarily enables + the specified console output error check. This is useful when executing a + command that might raise an extra bad pattern, beyond the default bad + patterns, in order to validate that the extra bad pattern is actually + detected. This class is used internally by ConsoleBase::enable_check(); it + is not intended for direct usage.""" + + def __init__(self, console, check_type, check_pattern): + self.console = console + self.check_type = check_type + self.check_pattern = check_pattern + + def __enter__(self): + global bad_pattern_defs + self.default_bad_patterns = bad_pattern_defs + bad_pattern_defs += ((self.check_type, self.check_pattern),) + self.console.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs} + self.console.eval_bad_patterns() + + def __exit__(self, extype, value, traceback): + global bad_pattern_defs + bad_pattern_defs = self.default_bad_patterns + self.console.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs} + self.console.eval_bad_patterns() + class ConsoleSetupTimeout(object): """Context manager (for Python's with statement) that temporarily sets up timeout for specific command. This is useful when execution time is greater @@ -499,6 +525,24 @@ class ConsoleBase(object): return ConsoleDisableCheck(self, check_type) + def enable_check(self, check_type, check_pattern): + """Temporarily enable an error check of U-Boot's output. + + Create a new context manager (for use with the "with" statement) which + temporarily enables a particular console output error check. The + arguments form a new element of bad_pattern_defs defined above. + + Args: + check_type: The type of error-check or bad pattern to enable. + check_pattern: The regexes for text error pattern or bad pattern + to be checked. + + Returns: + A context manager object. + """ + + return ConsoleEnableCheck(self, check_type, check_pattern) + def temporary_timeout(self, timeout): """Temporarily set up different timeout for commands. -- 2.25.1

2 2

[PATCH] cmd: bcb: Fix bcb compilation when CONFIG_CMD_BCB=n
by Mattijs Korpershoek 14 Jun '24

14 Jun '24

commit dfeb4f0d7935 ("cmd: bcb: extend BCB C API to allow read/write the fields") introduced the bcb_get() function. When CONFIG_CMD_BCB=n, that function is stubbed. The stubbed function has a wrong prototype: value_size arg is missing. Add the missing argument to fix build when CONFIG_CMD_BCB=n. Fixes: dfeb4f0d7935 ("cmd: bcb: extend BCB C API to allow read/write the fields") Signed-off-by: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> --- include/bcb.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/bcb.h b/include/bcb.h index 1941d8c28b4f..a56b547595a6 100644 --- a/include/bcb.h +++ b/include/bcb.h @@ -58,7 +58,8 @@ static inline int bcb_set(enum bcb_field field, const char *value) return -EOPNOTSUPP; } -static inline int bcb_get(enum bcb_field field, char *value_out) +static inline int bcb_get(enum bcb_field field, + char *value_out, size_t value_size) { return -EOPNOTSUPP; } --- base-commit: ea722aa5eb33740ae77e8816aeb72b385e621cd0 change-id: 20240603-bcb-compil-d8eaf7074475 Best regards, -- Mattijs Korpershoek <mkorpershoek(a)baylibre.com>

5 4

[PATCH] bcmgenet: fix Rx buffer corruption caused by lack of cache flush
by Yasuharu Shibata 14 Jun '24

14 Jun '24

When bcmgenet complete to write Rx buffer with the DMA, some U-Boot commands write data to the buffer directly. Those write data will become dirty in CPU cache. After this driver calls free_pkt to the buffer, the buffer is assigned as the future Rx buffer. At some point, if bcmgenet writes to a buffer with DMA and CPU cache flushes dirty data to the buffer, the buffer is corrupted. This patch calls flush_dcache_range in free_pkt to immediately flush the data written by U-Boot command and prevent data corruption. This issue can be reproduced using wget on Raspberry Pi4. If wget receives data larger than RX_BUF_LENGTH * RX_DESCS = 2048 * 256 bytes, it will timeout due to data corruption. In addition, if LOG_DEBUG is enabled in net/tcp.c, the following error log is output. TCP RX TCP xSum Error Signed-off-by: Yasuharu Shibata <yasuharu.shibata(a)gmail.com> --- drivers/net/bcmgenet.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c index 4e1f8ed7a4..a0264dc386 100644 --- a/drivers/net/bcmgenet.c +++ b/drivers/net/bcmgenet.c @@ -360,6 +360,10 @@ static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, int length) { struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; + u32 addr = readl(desc_base + DMA_DESC_ADDRESS_LO); + + flush_dcache_range(addr, addr + RX_BUF_LENGTH); /* Tell the MAC we have consumed that last receive buffer. */ priv->c_index = (priv->c_index + 1) & 0xFFFF; -- 2.25.1

2 1

[PATCH v1] imxtract: add support for zstd-compressed images
by Dmitry Gerasimov 14 Jun '24

14 Jun '24

Allow extraction of zstd-compressed images from FIT using imxtract command. This is especially useful when one has to load an image via some interface (e.g. SPI) rather that just to the memory. Signed-off-by: Dmitry Gerasimov <di.gerasimov(a)gmail.com> --- cmd/ximg.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/cmd/ximg.c b/cmd/ximg.c index 0e7eead8d1..25a15fa184 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -16,6 +16,9 @@ #include <cpu_func.h> #include <env.h> #include <gzip.h> +#if IS_ENABLED(CONFIG_ZSTD) +#include <linux/zstd.h> +#endif #include <image.h> #include <malloc.h> #include <mapmem.h> @@ -238,6 +241,26 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } break; #endif /* CONFIG_BZIP2 */ +#if IS_ENABLED(CONFIG_ZSTD) + case IH_COMP_ZSTD: + { + int ret; + struct abuf in, out; + + printf(" Uncompressing part %d ... ", part); + + abuf_init_set(&in, (void *)data, len); + abuf_init_set(&out, (void *)dest, unc_len); + ret = zstd_decompress(&in, &out); + if (ret < 0) { + printf("ZSTD ERROR %d - " + "image not loaded\n", ret); + return 1; + } + len = ret; + } + break; +#endif default: printf("Unimplemented compression type %d\n", comp); return 1; -- 2.45.1

2 1

[PATCH] configs: j784s4: Enable OSPI NOR boot
by Jonathan Humphreys 14 Jun '24

14 Jun '24

Set necessary configs to enable the j784s4 device to boot from OSPI NOR flash. Signed-off-by: Jonathan Humphreys <j-humphreys(a)ti.com> --- configs/j784s4_evm_a72_defconfig | 2 ++ configs/j784s4_evm_r5_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 8ef50f690fb..e999a25319d 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -49,6 +49,8 @@ CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index f5fe7432206..71b39b876e9 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -56,6 +56,8 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y -- 2.34.1

2 1

[PATCH] spl: Kconfig: ARCH_K3: Set default SPL_STACK_R_MALLOC_SIMPLE_LEN for R5 build
by Vignesh Raghavendra 14 Jun '24

14 Jun '24

All ARCH_K3 platforms need about of 2MB of malloc space post reallocation. Since, this space is allocated from SDRAM, provide a generous 2MB space by default. Platforms requiring more than 2MB can override in defconfig as needed. Signed-off-by: Vignesh Raghavendra <vigneshr(a)ti.com> --- common/spl/Kconfig | 1 + configs/am62px_evm_r5_defconfig | 1 - configs/am62x_evm_r5_defconfig | 1 - configs/j721s2_evm_r5_defconfig | 1 - configs/j784s4_evm_r5_defconfig | 1 - configs/phycore_am62x_r5_defconfig | 1 - configs/verdin-am62_r5_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6405374bcc12..46bacad2d81b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -409,6 +409,7 @@ config SPL_STACK_R_MALLOC_SIMPLE_LEN depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE hex "Size of malloc_simple heap after switching to DRAM SPL stack" default 0x400000 if ARCH_K3 && ARM64 + default 0x200000 if ARCH_K3 && CPU_V7R default 0x100000 help Specify the amount of the stack to use as memory pool for diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index b365c7ea902f..ace55696737a 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c4b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3C000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 CONFIG_SPL_FS_FAT=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 648241488ed0..4b2e57b13a09 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 5ef5247a3e00..0352f940041c 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index f5fe7432206b..d6a702cdfe96 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 389672d52271..05f8ace748b7 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 06c63fa64880..8266a7f6e8f1 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -23,7 +23,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000 CONFIG_SPL_SIZE_LIMIT=0x3A7F0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_LIBDISK_SUPPORT=y -- 2.45.1

3 2

[PATCH] arm: dts: k3-*-binman: Make default DM file optional
by Neha Malcom Francis 14 Jun '24

14 Jun '24

The default DM firmware path is non-optional as of now. Make it optional so that users that choose to provide DM via TI_DM argument instead of BINMAN_INDIRS can do so without build errors. Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- arch/arm/dts/k3-am625-sk-binman.dtsi | 1 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 1 + arch/arm/dts/k3-am62p-sk-binman.dtsi | 1 + arch/arm/dts/k3-j7200-binman.dtsi | 1 + arch/arm/dts/k3-j721e-binman.dtsi | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 1 + arch/arm/dts/k3-j784s4-binman.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index dfd38d64f63..eddf05594d5 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -149,6 +149,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index ec3bf7ce913..6f82f26bf85 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -152,6 +152,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index dea14945bf5..2233921d320 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -72,6 +72,7 @@ blob-ext { filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index e8020fec2dc..a524b246187 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -281,6 +281,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 1514d897634..0483fc5dd3f 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -310,6 +310,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 46297ebef9e..d121d8c0c54 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -149,6 +149,7 @@ filename = "ti-dm.bin"; blob-ext { filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; ti-spl { diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index e4dd6e14a66..146cd7652c9 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -170,6 +170,7 @@ blob-ext { filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; }; }; -- 2.34.1

3 2

[PATCH] env: ti: k3_dfu: Drup mmcpart for rootfs
by Neha Malcom Francis 14 Jun '24

14 Jun '24

According to [0], raw access to mmc should not have mmcpart in the entry. This was fixed in k3_dfu_combined.env but k3_dfu.env had been overlooked. [0] doc/usage/dfu.rst Fixes: 53b406369e9d ("DFU: Check the number of arguments and argument string strictly") Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- Boot Logs: https://gist.github.com/nehamalcom/163122d2b9d63607cbb383475978364a include/env/ti/k3_dfu.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/env/ti/k3_dfu.env b/include/env/ti/k3_dfu.env index 201529636cc..b42cf21d986 100644 --- a/include/env/ti/k3_dfu.env +++ b/include/env/ti/k3_dfu.env @@ -9,7 +9,7 @@ dfu_alt_info_mmc= dfu_alt_info_emmc= rawemmc raw 0 0x800000 mmcpart 1; - rootfs part 0 1 mmcpart 0; + rootfs part 0 1; tiboot3.bin.raw raw 0x0 0x400 mmcpart 1; tispl.bin.raw raw 0x400 0x1000 mmcpart 1; u-boot.img.raw raw 0x1400 0x2000 mmcpart 1; -- 2.34.1

2 1

[PATCH] arm: dts: k3-j721s2-r5: Change GTC clock parent
by Neha Malcom Francis 14 Jun '24

14 Jun '24

MAIN_PLL0 has a flag set in DM (Device Manager) that removes its capability to re-initialise clock frequencies. A72 CPU clock (GTC) and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs re-initialization to default frequency to be able to get 250MHz with its divider, GTC can not get its required 200MHz with its dividers. Thus move GTC clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. This was already done on CPTS node in kernel which was similarly affected (linked). Link: https://lore.kernel.org/all/20230605110443.84568-1-n-francis@ti.com/ Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- Boot logs: https://gist.github.com/nehamalcom/70676857dc3816a415af9861c38c76eb arch/arm/dts/k3-j721s2-r5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index eb0df42583a..40272abfc7c 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -22,7 +22,7 @@ resets = <&k3_reset 202 0>; clocks = <&k3_clks 61 1>; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; - assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-parents = <&k3_clks 61 3>; assigned-clock-rates = <200000000>, <2000000000>; ti,sci = <&sms>; ti,sci-proc-id = <32>; -- 2.34.1

2 1

[PATCH 1/1] mmc: consider cd-gpios in Synopsys DesignWare driver
by Heinrich Schuchardt 14 Jun '24

14 Jun '24

The JH7110 SoC uses a GPIO for card detect. * In the of_to_plat function check if a cd-gpios definition exists and request the GPIO. * In the getcd function return the GPIO value in this case. Reported-by: Conor Dooley <conor.dooley(a)microchip.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/mmc/snps_dw_mmc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 9bdbe5070b1..2f0133f22c9 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -12,6 +12,7 @@ #include <dwmmc.h> #include <errno.h> #include <fdtdec.h> +#include <asm/gpio.h> #include <dm/device_compat.h> #include <linux/libfdt.h> #include <linux/err.h> @@ -29,6 +30,7 @@ struct snps_dwmci_plat { struct snps_dwmci_priv_data { struct dwmci_host host; u32 f_max; + struct gpio_desc cd_gpio; }; static int snps_dwmmc_clk_setup(struct udevice *dev) @@ -106,6 +108,8 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) if (!ret && priv->f_max < CLOCK_MIN) return -EINVAL; + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + host->fifo_mode = dev_read_bool(dev, "fifo-mode"); host->name = dev->name; host->dev_index = 0; @@ -119,6 +123,9 @@ int snps_dwmmc_getcd(struct udevice *dev) struct snps_dwmci_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + if (dm_gpio_is_valid(&priv->cd_gpio)) + return dm_gpio_get_value(&priv->cd_gpio); + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); } -- 2.43.0

1 0

[PATCH v2] doc: describe UEFI measured boot
by Ilias Apalodimas 14 Jun '24

14 Jun '24

We currently only describe the process to enable measured boot using bootm. Describe the UEFI requirements as well which predate bootm. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Changes since v1: - fixed remarks from Heinrich on titling and DTB measured PCR doc/usage/measured_boot.rst | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 9691904a9d8a..b5f7b05aeb02 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -7,19 +7,39 @@ U-Boot can perform a measured boot, the process of hashing various components of the boot process, extending the results in the TPM and logging the component's measurement in memory for the operating system to consume. +The functionality is available when booting via the EFI subsystem or 'bootm' +command. + +UEFI measured boot +------------------ +The EFI subsystem implements the `EFI TCG protocol +<https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/>`_ +and the `TCG PC Client Specific Platform Firmware Profile Specification +<https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firm…>`_ +which defines the binaries to be measured and the corresponding PCRs to be used. + +Requirements +~~~~~~~~~~~~ +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_EFI_TCG2_PROTOCOL=y +* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y +* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB in PCR 1 + +Measured legacy boot with bootm command +---------------------------------------- By default, U-Boot will measure the operating system (linux) image, the initrd image, and the "bootargs" environment variable. By enabling -CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. +CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image in PCR1. The operating system typically would verify that the hashes found in the TPM PCRs match the contents of the event log. This can further be checked against the hash results of previous boots. Requirements ------------- +~~~~~~~~~~~~ -* A hardware TPM 2.0 supported by the U-Boot drivers -* CONFIG_TPM=y +* A hardware TPM 2.0 supported by an enabled U-Boot driver +* CONFIG_TPMv2=y * CONFIG_MEASURED_BOOT=y * Device-tree configuration of the TPM device to specify the memory area for event logging. The TPM device node must either contain a phandle to -- 2.45.1

2 2

[PATCH] video: Add support for NewVision NV3052C SPI panels
by John Watts 14 Jun '24

14 Jun '24

This driver is mostly copied from the Linux kernel and includes support for two physical panels that use this driver. Signed-off-by: John Watts <contact(a)jookia.org> --- This patch is a straightforward port of the kernel NV3052C SPI driver to U-Boot, keeping full compatibility with mainline device tree bindings. --- drivers/video/Kconfig | 6 + drivers/video/Makefile | 1 + drivers/video/newvision-nv3052c.c | 608 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 615 insertions(+) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index e9d069d440..67409a39d2 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -612,6 +612,12 @@ config VIDEO_LCD_HITACHI_TX18D42VM lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. +config VIDEO_LCD_NEWVISION_NV3052C + bool "NewVision NV3052C RGB/SPI panel support" + select VIDEO_MIPI_DBI + ---help--- + Support for panels built around the NewVision NV3052C controller. + config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM diff --git a/drivers/video/Makefile b/drivers/video/Makefile index ad77c60973..c82588ba0b 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o +obj-$(CONFIG_VIDEO_LCD_NEWVISION_NV3052C) += newvision-nv3052c.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o diff --git a/drivers/video/newvision-nv3052c.c b/drivers/video/newvision-nv3052c.c new file mode 100644 index 0000000000..2ffa6ae9ed --- /dev/null +++ b/drivers/video/newvision-nv3052c.c @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NewVision NV3052C IPS LCD panel driver + * + * Copyright (C) 2020, Paul Cercueil <paul(a)crapouillou.net> + * Copyright (C) 2022, Christophe Branchereau <cbranchereau(a)gmail.com> + */ + +#include <asm/gpio.h> +#include <backlight.h> +#include <dm/device_compat.h> +#include <dm.h> +#include <linux/delay.h> +#include <mipi_dbi.h> +#include <panel.h> +#include <power/regulator.h> + +struct nv3052c_reg { + u8 cmd; + u8 val; +}; + +struct nv3052c_panel_info { + struct display_timing default_timing; + const struct nv3052c_reg *panel_regs; + unsigned int panel_regs_len; +}; + +struct nv3052c { + const struct nv3052c_panel_info *panel_info; + struct udevice *supply; + struct gpio_desc reset_gpio; + struct udevice *backlight; + struct spi_slave *spi; + struct mipi_dbi dbi; +}; + +static const struct nv3052c_reg ltk035c5444t_panel_regs[] = { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0xa0 }, + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0xcc }, // VCOM_ADJ1 + { 0x39, 0xd7 }, // VCOM_ADJ2 + { 0x3a, 0x4a }, // VCOM_ADJ3 + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x77 }, // EXTPW_CTRL2 + { 0x92, 0x77 }, // EXTPW_CTRL3 + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x33 }, + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers + { 0x01, 0x01 }, + { 0x02, 0xda }, + { 0x03, 0xba }, + { 0x04, 0xa8 }, + { 0x05, 0x9a }, + { 0x06, 0x70 }, + { 0x07, 0xff }, + { 0x08, 0x91 }, + { 0x09, 0x90 }, + { 0x0a, 0xff }, + { 0x0b, 0x8f }, + { 0x0c, 0x60 }, + { 0x0d, 0x58 }, + { 0x0e, 0x48 }, + { 0x0f, 0x38 }, + { 0x10, 0x2b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 +}; + +static const struct nv3052c_reg fs035vg158_panel_regs[] = { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t + { 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t + { 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t + { 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x03 }, // Unknown, different to ltk035c5444 + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers + { 0x01, 0x01 }, + { 0x02, 0xda }, + { 0x03, 0xba }, + { 0x04, 0xa8 }, + { 0x05, 0x9a }, + { 0x06, 0x70 }, + { 0x07, 0xff }, + { 0x08, 0x91 }, + { 0x09, 0x90 }, + { 0x0a, 0xff }, + { 0x0b, 0x8f }, + { 0x0c, 0x60 }, + { 0x0d, 0x58 }, + { 0x0e, 0x48 }, + { 0x0f, 0x38 }, + { 0x10, 0x2b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr = 1, ss = 1, gs = 0 +}; + +static const struct nv3052c_panel_info ltk035c5444t_panel_info = { + .default_timing = { + .pixelclock.typ = 24000000, + .hactive.typ = 640, + .hfront_porch.typ = 96, + .hback_porch.typ = 16, + .hsync_len.typ = 48, + .vactive.typ = 480, + .vfront_porch.typ = 5, + .vback_porch.typ = 2, + .vsync_len.typ = 13, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, + }, + .panel_regs = ltk035c5444t_panel_regs, + .panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs), +}; + +static const struct nv3052c_panel_info fs035vg158_panel_info = { + .default_timing = { + .pixelclock.typ = 21000000, + .hactive.typ = 640, + .hfront_porch.typ = 34, + .hback_porch.typ = 20, + .hsync_len.typ = 4, + .vactive.typ = 480, + .vfront_porch.typ = 12, + .vback_porch.typ = 6, + .vsync_len.typ = 4, + .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, + }, + .panel_regs = fs035vg158_panel_regs, + .panel_regs_len = ARRAY_SIZE(fs035vg158_panel_regs), +}; + +static const struct nv3052c_panel_info *panel_infos[] = { + &ltk035c5444t_panel_info, + &fs035vg158_panel_info, +}; + +static int nv3052c_panel_enable_backlight(struct udevice *dev) +{ + struct nv3052c *priv = dev_get_priv(dev); + struct mipi_dbi *dbi = &priv->dbi; + int err; + + err = mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); + if (err) { + dev_err(dev, "Unable to enable display: %d\n", err); + return err; + } + + if (priv->backlight) { + /* Wait for the picture to be ready before enabling backlight */ + mdelay(120); + err = backlight_enable(priv->backlight); + } + + return err; +} + +static int nv3052c_panel_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + struct nv3052c *priv = dev_get_priv(dev); + const struct nv3052c_panel_info *info = priv->panel_info; + const struct display_timing *our_timing = &info->default_timing; + + memcpy(timing, our_timing, sizeof(*our_timing)); + + return 0; +} + +static int nv3052c_panel_of_to_plat(struct udevice *dev) +{ + struct nv3052c *priv = dev_get_priv(dev); + int panel_info_index = dev_get_driver_data(dev); + int err; + + priv->spi = dev_get_parent_priv(dev); + priv->panel_info = panel_infos[panel_info_index]; + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + err = device_get_supply_regulator(dev, "power-supply", + &priv->supply); + if (err) { + dev_err(dev, "Failed to get power supply: %d\n", err); + return err; + } + } + + err = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (err) { + dev_err(dev, "Failed to get reset GPIO: %d\n", err); + return err; + } + + err = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (err) { + dev_err(dev, "Failed to get backlight: %d\n", err); + return err; + } + + return 0; +} + +static int nv3052c_panel_probe(struct udevice *dev) +{ + struct nv3052c *priv = dev_get_priv(dev); + const struct nv3052c_reg *panel_regs = priv->panel_info->panel_regs; + unsigned int panel_regs_len = priv->panel_info->panel_regs_len; + struct mipi_dbi *dbi = &priv->dbi; + unsigned int i; + int err; + + err = mipi_dbi_spi_init(priv->spi, &priv->dbi, NULL); + if (err) { + dev_err(dev, "MPI DBI init failed: %d\n", err); + return err; + } + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + err = regulator_set_enable(priv->supply, true); + if (err) { + dev_err(dev, "Failed to enable power supply: %d\n", err); + return err; + } + } + + /* Reset the chip */ + dm_gpio_set_value(&priv->reset_gpio, true); + mdelay(1); + dm_gpio_set_value(&priv->reset_gpio, false); + mdelay(150); + + for (i = 0; i < panel_regs_len; i++) { + err = mipi_dbi_command(dbi, panel_regs[i].cmd, + panel_regs[i].val); + + if (err) { + dev_err(dev, "Unable to set register: %d\n", err); + goto err_disable_regulator; + } + } + + err = mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); + if (err) { + dev_err(dev, "Unable to exit sleep mode: %d\n", err); + goto err_disable_regulator; + } + + return 0; + +err_disable_regulator: + if (CONFIG_IS_ENABLED(DM_REGULATOR)) + regulator_set_enable(priv->supply, false); + + return err; +} + +static const struct panel_ops nv3052c_panel_ops = { + .enable_backlight = nv3052c_panel_enable_backlight, + .get_display_timing = nv3052c_panel_get_display_timing, +}; + +static const struct udevice_id nv3052c_panel_ids[] = { + { .compatible = "leadtek,ltk035c5444t", .data = 0 }, + { .compatible = "fascontek,fs035vg158", .data = 1 }, + { } +}; + +U_BOOT_DRIVER(nv3052c_panel) = { + .name = "nv3052c_panel", + .id = UCLASS_PANEL, + .of_match = nv3052c_panel_ids, + .ops = &nv3052c_panel_ops, + .of_to_plat = nv3052c_panel_of_to_plat, + .probe = nv3052c_panel_probe, + .priv_auto = sizeof(struct nv3052c), +}; --- base-commit: 0cc0eab0a140b5e660c25a27e116c9be538c1c12 change-id: 20240601-panel_nv3052c-76bab2b2c358 Best regards, -- John Watts <contact(a)jookia.org>

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[PATCH 0/2] sunxi: video: Fix lcdc polarity display flags
by John Watts 14 Jun '24

14 Jun '24

The current LCD controller driver has incorrect polarity masks, so I've provided a fix for that. While I was there I also added support for two new display flags related to polarities. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (2): sunxi: video: Properly invert hsync and vsync polarity sunxi: video: Support DE_LOW and PIXDATA_NEGEDGE display flags arch/arm/include/asm/arch-sunxi/lcdc.h | 2 ++ drivers/video/sunxi/lcdc.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) --- base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420 change-id: 20240614-sunxipolarities-a9a21c30c82b Best regards, -- John Watts <contact(a)jookia.org>

1 2

[PATCH] sunxi: video: Support driver model LCDs
by John Watts 14 Jun '24

14 Jun '24

Currently the LCD code only supports reading panel timings from the device tree. Change that so it can use a real panel. Signed-off-by: John Watts <contact(a)jookia.org> --- I've been working on a panel driver port from Linux for the T113 and found I need this code to have the panel boot correctly. --- drivers/video/sunxi/sunxi_lcd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 7a01cc343c..605ea90de1 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -8,6 +8,7 @@ #include <common.h> #include <display.h> #include <log.h> +#include <panel.h> #include <video_bridge.h> #include <backlight.h> #include <dm.h> @@ -45,6 +46,7 @@ static int sunxi_lcd_enable(struct udevice *dev, int bpp, (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; struct sunxi_lcd_priv *priv = dev_get_priv(dev); struct udevice *backlight; + struct udevice *panel; int clk_div, clk_double, ret; /* Reset off */ @@ -60,6 +62,12 @@ static int sunxi_lcd_enable(struct udevice *dev, int bpp, priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE); lcdc_enable(lcdc, priv->panel_bpp); + ret = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (ret == 0) { + if (panel_enable_backlight(panel) == 0) + return 0; + } + ret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight); if (!ret) backlight_enable(backlight); @@ -116,6 +124,11 @@ static int sunxi_lcd_probe(struct udevice *dev) return ret; } + if (panel_get_display_timing(cdev, &priv->timing) == 0) { + priv->panel_bpp = 32; + return 0; + } + if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev), 0, &priv->timing)) { debug("%s: Failed to decode display timing\n", __func__); --- base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420 change-id: 20240601-sunxi_lcd-d39a4fb81c94 Best regards, -- John Watts <contact(a)jookia.org>

1 0

[PATCH 0/5] video: add support for MIPI DBI interface
by John Watts 14 Jun '24

14 Jun '24

Many simple RGB panels use a MIPI DBI interface over SPI, so this patch adds support for this interface using an API compatible with Linux. The MIPI DBI interface works similar to SPI using 8-bit words in the format of: COMMAND DATA1 DATA2 ... However the interface has two variations on this. The first variation is implemented by this patch series: Using 9-bit words, with the first bit signalling whether the word is a COMMAND or DATA. The second variation is not implemented by this series: A GPIO is held at a value during an 8-bit word to indicate if it's a COMMAND or WORD. Adding support for this wouldn't be too hard, but I don't have any hardware to test it on. Linux seems to not implement the specification correctly: It sets CS inactive between words instead of keeping it active for the entire transaction. I'm copying this behaviour to keep compatibility in porting panels across from the kernel. Signed-off-by: John Watts <contact(a)jookia.org> --- John Watts (5): spi: Return old wordlen in spit_set_wordlen spi: Limit spi_set_wordlen to SPI_DEFAULT_WORDLEN spi: Implement spi_set_wordlen for driver model spi: softspi: Support setting wordlen video: add support for MIPI DBI interface drivers/spi/soft_spi.c | 7 +++++ drivers/spi/spi-uclass.c | 29 +++++++++++++++++++ drivers/spi/spi.c | 6 ++-- drivers/video/Kconfig | 6 ++++ drivers/video/Makefile | 1 + drivers/video/mipi_dbi.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ include/mipi_dbi.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++ include/spi.h | 2 +- 8 files changed, 191 insertions(+), 3 deletions(-) --- base-commit: c0ea27bccfb7d2d37fd36806ac2a2f7389099420 change-id: 20240601-mipi_dbi-aeda98f2f9d5 Best regards, -- John Watts <contact(a)jookia.org>

1 5

[PATCH] doc: describe UEFI measured boot
by Ilias Apalodimas 14 Jun '24

14 Jun '24

We currently only describe the process to enable measured boot using bootm. Describe the UEFI requirements as well which predate bootm. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- doc/usage/measured_boot.rst | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 9691904a9d8a..1b5dd1dcc438 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -7,6 +7,26 @@ U-Boot can perform a measured boot, the process of hashing various components of the boot process, extending the results in the TPM and logging the component's measurement in memory for the operating system to consume. +The functionality is available when booting via the EFI subsystem or 'bootm' +command. + +UEFI subsystem +-------------- +The EFI subsystem implements the `EFI TCG protocol +<https://trustedcomputinggroup.org/resource/tcg-efi-protocol-specification/>`_ +and the `TCG PC Client Specific Platform Firmware Profile Specification +<https://trustedcomputinggroup.org/resource/pc-client-specific-platform-firm…>`_ +which defines the binaries to be measured and the corresponding PCRs used. + +UEFI requirements +~~~~~~~~~~~~~~~~~ +* A hardware TPM 2.0 supported by the U-Boot drivers +* CONFIG_EFI_TCG2_PROTOCOL=y +* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y +* optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB in PCR 0 + +bootm +----- By default, U-Boot will measure the operating system (linux) image, the initrd image, and the "bootargs" environment variable. By enabling CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. @@ -15,8 +35,8 @@ The operating system typically would verify that the hashes found in the TPM PCRs match the contents of the event log. This can further be checked against the hash results of previous boots. -Requirements ------------- +bootm requirements +~~~~~~~~~~~~~~~~~~ * A hardware TPM 2.0 supported by the U-Boot drivers * CONFIG_TPM=y -- 2.45.1

2 4

[PATCH] ARM: dts: stm32: Auto-detect second MAC on STM32MP15xx DH electronics DHCOM
by Marek Vasut 14 Jun '24

14 Jun '24

Test whether this system is compatible with STM32MP15xx DHCOM SoM, if so, test whether R292 pull up is populated on pin PC3, which is an indication that the second MAC chip, KS8851-16MLL, is populated. Use this information to patch 'status' DT property into the second ethernet MAC DT node and enable/disable the MAC on systems where the chip is/isn't populated respectively. Use spl_perform_fixups() to patch the U-Boot proper DT from SPL and ft_board_setup() to patch Linux DT from U-Boot proper. This way both software components are configured the same way. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 1 + board/dhelectronics/dh_stm32mp1/board.c | 65 ++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 1b445619325..d7b78cdcfa9 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -26,6 +26,7 @@ u-boot,error-led = "error"; dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; + dh,mac-coding-gpios = <&gpioc 3 0>; }; }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 20c9d70737e..ebd45f9053f 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -37,6 +37,7 @@ #include <power/regulator.h> #include <remoteproc.h> #include <reset.h> +#include <spl.h> #include <syscon.h> #include <usb.h> #include <usb/dwc2_udc.h> @@ -672,12 +673,69 @@ void board_quiesce_devices(void) #endif } +static void dh_stm32_ks8851_fixup(void *blob) +{ + struct gpio_desc ks8851intrn; + bool compatible = false; + int ks8851intrn_value; + const char *prop; + ofnode node; + int idx = 0; + int offset; + int ret; + + /* Do nothing if not STM32MP15xx DHCOM SoM */ + while ((prop = fdt_stringlist_get(blob, 0, "compatible", idx++, NULL))) { + if (!strstr(prop, "dhcom-som")) + continue; + compatible = true; + break; + } + + if (!compatible) + return; + + /* + * Read state of INTRN pull up resistor, if this pull up is populated, + * KS8851-16MLL is populated as well and should be enabled, otherwise + * it should be disabled. + */ + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return; + + ret = gpio_request_by_name_nodev(node, "dh,mac-coding-gpios", 0, + &ks8851intrn, GPIOD_IS_IN); + if (ret) + return; + + ks8851intrn_value = dm_gpio_get_value(&ks8851intrn); + + dm_gpio_free(NULL, &ks8851intrn); + + /* Set the 'status' property into KS8851-16MLL DT node. */ + offset = fdt_path_offset(blob, "ethernet1"); + ret = fdt_node_check_compatible(blob, offset, "micrel,ks8851-mll"); + if (ret) /* Not compatible */ + return; + + /* Add a bit of extra space for new 'status' property */ + ret = fdt_shrink_to_minimum(blob, 4096); + if (!ret) + return; + + fdt_setprop_string(blob, offset, "status", + ks8851intrn_value ? "okay" : "disabled"); +} + #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { const char *buck3path = "/soc/i2c@5c002000/stpmic@33/regulators/buck3"; int buck3off, ret, uv; + dh_stm32_ks8851_fixup(blob); + ret = board_get_regulator_buck3_nvm_uv_av96(&uv); if (ret) /* Not Avenger96 board, do not patch Buck3 in DT. */ return 0; @@ -698,6 +756,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image)); +} +#endif + static void board_copro_image_process(ulong fw_image, size_t fw_size) { int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */ -- 2.43.0

2 2

[PATCH] ARM: dts: stm32: Add generic SoM compatible to STM32MP15xx DH electronics DHSOM
by Marek Vasut 14 Jun '24

14 Jun '24

Add generic SoM compatible string into machine compatible string for all STM32MP15xx based DH electronics DHSOM. This way, common board code can match on this compatible. No functional change. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 4 +++- arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts | 4 +++- arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts | 4 +++- arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 4 +++- arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts | 4 +++- arch/arm/dts/stm32mp15xx-dhcor-testbench.dts | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index 1ef9ac29cea..90625bf6b60 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -11,5 +11,7 @@ / { model = "DH Electronics STM32MP15xx DHCOM DRC02"; - compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcom-drc02", + "dh,stm32mp15xx-dhcom-som", + "st,stm32mp1xx"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts index e2e01e2146c..b2e450aa13b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts @@ -11,5 +11,7 @@ / { model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; - compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x"; + compatible = "dh,stm32mp15xx-dhcom-pdk2", + "dh,stm32mp15xx-dhcom-som", + "st,stm32mp15x"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts index 06770b47873..3e908102f61 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts @@ -11,5 +11,7 @@ / { model = "DH Electronics STM32MP15xx DHCOM PicoITX"; - compatible = "dh,stm32mp15xx-dhcom-picoitx", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcom-picoitx", + "dh,stm32mp15xx-dhcom-som", + "st,stm32mp1xx"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index 76ac5a873c1..dd8fcecbca5 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -14,5 +14,7 @@ / { model = "Arrow Electronics STM32MP15xx Avenger96 board"; - compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x"; + compatible = "arrow,stm32mp15xx-avenger96", + "dh,stm32mp15xx-dhcor-som", + "st,stm32mp15x"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts index 77dd944ff53..c1f99c1685e 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts @@ -12,5 +12,7 @@ / { model = "DH electronics STM32MP15xx DHCOR DRC Compact"; - compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcor-drc-compact", + "dh,stm32mp15xx-dhcor-som", + "st,stm32mp1xx"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts index c9163e1c028..5fdd762ddbf 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts @@ -9,7 +9,9 @@ / { model = "DH electronics STM32MP15xx DHCOR Testbench"; - compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx"; + compatible = "dh,stm32mp15xx-dhcor-testbench", + "dh,stm32mp15xx-dhcor-som", + "st,stm32mp1xx"; aliases { ethernet0 = &ethernet0; -- 2.43.0

2 2

[PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK
by Heesub Shin 14 Jun '24

14 Jun '24

Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively. Signed-off-by: Heesub Shin <heesub(a)gmail.com> --- arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e..d07fdcf4bc 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; }; - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; + cfg = < 3 124 5 9 9 PQR(1,1,1) >; bootph-all; }; }; -- 2.34.1

2 15

[PATCH v2 1/2] ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
by Marek Vasut 14 Jun '24

14 Jun '24

Add new pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board. The following pinmux nodes are added: - ADC pins - ADC CC pins - ETH1 pins - ETH2 pins - I2C5 pins - MCAN1 pins - MCAN2 pins - PWM13 pins - PWM5 pins - QSPI pins - SAI1 pins - SDMMC2 D4..D7 pins - SPI2 pins - SPI3 pins - UART4 pins - UART7 pins - USART1 pins - USART2 pins Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: u-boot(a)dh-electronics.com Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- V2: Squash the pinmux patches into one megapatch --- arch/arm/dts/stm32mp13-pinctrl.dtsi | 483 ++++++++++++++++++++++++++++ 1 file changed, 483 insertions(+) diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index 27e0c382678..c01d39f03ea 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,12 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + adc1_pins_a: adc1-pins-0 { + pins { + pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ + }; + }; + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ @@ -13,6 +19,104 @@ }; }; + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -47,6 +151,63 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ + }; + }; + + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_a: m_can1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ + <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ + }; + }; + mcp23017_pins_a: mcp23017-0 { pins { pinmux = <STM32_PINMUX('G', 12, GPIO)>; @@ -84,6 +245,21 @@ }; }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ @@ -99,6 +275,21 @@ }; }; + pwm13_pins_a: pwm13-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm13_sleep_pins_a: pwm13-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ + }; + }; + pwm14_pins_a: pwm14-0 { pins { pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ @@ -114,6 +305,89 @@ }; }; + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ + }; + }; + + qspi_bk1_pins_a: qspi-bk1-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + sai1a_pins_a: sai1a-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ + <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ + <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ + <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ + <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ + }; + }; + + sai1b_pins_a: sai1b-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ + bias-disable; + }; + }; + + sai1b_sleep_pins_a: sai1b-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -216,6 +490,73 @@ }; }; + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ + <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + spi2_pins_a: spi2-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ + <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_sleep_pins_a: spi2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ + <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ + <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ + }; + }; + + spi3_pins_a: spi3-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ + <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ + <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ + }; + }; + spi5_pins_a: spi5-0 { pins1 { pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ @@ -276,6 +617,77 @@ }; }; + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_idle_pins_b: uart4-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_sleep_pins_b: uart4-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ + <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ + <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ + bias-disable; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ + <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -347,6 +759,36 @@ }; }; + usart1_pins_b: usart1-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ @@ -387,4 +829,45 @@ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ }; }; + + usart2_pins_b: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_b: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; }; -- 2.43.0

2 4

[PATCH V2] arm: dts: k3-am625-beagleplay: Add symlinks for boot binaries
by Dhruva Gole 14 Jun '24

14 Jun '24

Add symlinks for tiboot3.bin, tispl.bin & u-boot.img because a user has to anyway rename these files to get the platform to boot up. This just makes it more intuitive and convenient. Signed-off-by: Dhruva Gole <d-gole(a)ti.com> --- Changes: Add symlink for u-boot.img as well as per Manorit's suggestion. Link to prev. patch: https://lore.kernel.org/u-boot/20240614084052.4029849-1-d-gole@ti.com/ Cc: Manorit Chawdhry <m-chawdhry(a)ti.com> Cc: Nishant Menon <nm(a)ti.com> Cc: Robert Nelson <robertcnelson(a)gmail.com> arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 2 ++ arch/arm/dts/k3-am625-r5-beagleplay.dts | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index fb2032068d1c..77e6292d790f 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -71,6 +71,7 @@ ti-spl_unsigned { filename = "tispl.bin_unsigned"; + symlink = "tispl.bin"; pad-byte = <0xff>; fit { @@ -157,6 +158,7 @@ u-boot_unsigned { filename = "u-boot.img_unsigned"; + symlink = "u-boot.img"; pad-byte = <0xff>; fit { diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9db58f093c8c..da6746e009d5 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -79,6 +79,7 @@ &binman { tiboot3-am62x-gp-evm.bin { filename = "tiboot3-am62x-gp-evm.bin"; + symlink = "tiboot3.bin"; ti-secure-rom { content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; base-commit: 1ebd659cf020843fd8e8ef90d85a66941cbab6ec -- 2.34.1

1 1

[PATCH] arm: dts: k3-am625-beagleplay: Package TIFS Stub
by Dhruva Gole 14 Jun '24

14 Jun '24

Add support for packaging the TIFS Stub as it's required for basic Low Power Modes like Deep Sleep. Signed-off-by: Dhruva Gole <d-gole(a)ti.com> --- arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 33 +++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index fb2032068d1c..5e2248a4a668 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -69,6 +69,23 @@ }; }; + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl_unsigned { filename = "tispl.bin_unsigned"; pad-byte = <0xff>; @@ -105,6 +122,19 @@ }; }; + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { description = "DM binary"; type = "firmware"; @@ -148,7 +178,8 @@ conf-0 { description = "k3-am625-beagleplay"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "dm", "spl", + "tifsstub-gp"; fdt = "fdt-0"; }; }; -- 2.34.1

2 1

silent u-boot not working
by Jonas Kvinge 14 Jun '24

14 Jun '24

Hi, I'm running openSUSE Tumbleweed on an RPI CM4, I'm trying to silence u- boot boot messages, with the default configuration there is an u-boot logo on the top right corner and boot text, I'd like to get rid of the logo and all text if possible. The keyboard is not working before the Linux kernel is loaded, so I can not interrupt u-boot and enter any commands, so where should I put "set env silent 1"? I've followed the guide on https://github.com/ARM-software/u-boot/blob/master/doc/README.silent I have built u-boot from source using `make rpi_4_defconfig` configuration modified the configuration with make menuconfig, and verified this in .config before builing. CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y CONFIG_SILENT_CONSOLE_UPDATE_ON_SET=y CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y CONFIG_SILENT_CONSOLE_UNTIL_ENV=y Copied the binary to /boot/efi/u-boot.bin and /boot/vc/u-boot.bin I've also tried to define CONFIG_EXTRA_ENV_SETTINGS in include/configs/rpi.h according to: https://stackoverflow.com/questions/34356844/how-to-disable-serial-consolen… and rebuilt and copied to binary again, still not working. The text and logo is still present during boot, what am I doing wrong here? Jonas

3 5

[PATCH 1/2] ARM: dts: stm32: add PWR regulators support on stm32mp131
by Marek Vasut 14 Jun '24

14 Jun '24

This patch adds STM32 PWR regulators DT support on stm32mp131. This requires TFA to clear RCC_SECCFGR, is disabled by default and can only be enabled on board DT level. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp131.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 81d99a7582b..ad331b73d18 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -1092,6 +1092,30 @@ <&scmi_clk CK_SCMI_LSI>; }; + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + status = "disabled"; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp13-exti", "syscon"; interrupt-controller; -- 2.43.0

2 7

[PATCH] arm: dts: k3-am625-beagleplay: Add symlinks for tiboot3 and tispl
by Dhruva Gole 14 Jun '24

14 Jun '24

Add symlinks for both tiboot3.bin and tispl.bin because a user has to anyway rename these files to get the platform to boot up. This just makes it more intuitive and convenient. Signed-off-by: Dhruva Gole <d-gole(a)ti.com> --- arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 1 + arch/arm/dts/k3-am625-r5-beagleplay.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index fb2032068d1c..bd48af8d186a 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -71,6 +71,7 @@ ti-spl_unsigned { filename = "tispl.bin_unsigned"; + symlink = "tispl.bin"; pad-byte = <0xff>; fit { diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9db58f093c8c..da6746e009d5 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -79,6 +79,7 @@ &binman { tiboot3-am62x-gp-evm.bin { filename = "tiboot3-am62x-gp-evm.bin"; + symlink = "tiboot3.bin"; ti-secure-rom { content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; base-commit: 1ebd659cf020843fd8e8ef90d85a66941cbab6ec -- 2.34.1

2 2

[PATCH v2] stm32mp: Reserve OPTEE area in EFI memory map
by Patrice Chotard 14 Jun '24

14 Jun '24

Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory") memory region above ram_top is tagged in EFI memory map as EFI_BOOT_SERVICES_DATA. In case of STM32MP1/STM32MP13 platforms, above ram_top, there is one reserved-memory region tagged "no-map" dedicated to OP-TEE : _ addr=de000000 size=2000000 for stm32mp157x-dkx and stm32mp135f-dk _ addr=fe000000 size=2000000 for stm32mp157c-ev1 Before booting kernel, EFI memory map is first built, the OPTEE region is tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE is used. Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions() which try to add again the same OPTEE region (addr=de000000 size=2000000 in case of stm32mp157x-dkx / stm32mp135f-dk or addr=fe000000 size=2000000 in case for stm2mp157c-ev1) but now with LMB_NOMAP tag which produces the following error message : _ for stm32mp157x-dkx / stm32mp135f-dk : "ERROR: reserving fdt memory region failed (addr=de000000 size=2000000 flags=4)" _ for stm32mp157c-ev1 : "ERROR: reserving fdt memory region failed (addr=fe000000 size=2000000 flags=4)" To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark it as reserved. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- Changes in v2: _ update commit message by adding information about memory area dedicated for OPTEE for various STM32MP1/STM32MP13 boards. arch/arm/mach-stm32mp/dram_init.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index fb1208fc5d5..f67f54f2ae0 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <efi_loader.h> #include <image.h> #include <init.h> #include <lmb.h> @@ -75,3 +76,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return reg + size; } + +void efi_add_known_memory(void) +{ + if (IS_ENABLED(CONFIG_EFI_LOADER)) + /* + * Memory over ram_top is reserved to OPTEE. + * Declare to EFI only memory area below ram_top + */ + efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base, + EFI_CONVENTIONAL_MEMORY); +} -- 2.25.1

3 2

[PATCH v2 0/1] xilinx: Add option to load environment from outside of
by Vasileios Amoiridis 14 Jun '24

14 Jun '24

From: Vasileios Amoiridis <vasileios.amoiridis(a)cern.ch> Changes in v2: - Remove duplication of custom hardcoded env_locations[] code. - Add implementation with general arch_env_get_location(op, prio) v1: https://lore.kernel.org/u-boot/20240522174738.73522-1-vassilisamir@gmail.co… Vasileios Amoiridis (1): xilinx: Add option to load environment from outside of boot media board/xilinx/versal-net/board.c | 47 ++++++++++++++-------------- board/xilinx/versal/board.c | 47 ++++++++++++++-------------- board/xilinx/zynq/board.c | 49 +++++++++++++++-------------- board/xilinx/zynqmp/zynqmp.c | 55 +++++++++++++++++---------------- 4 files changed, 101 insertions(+), 97 deletions(-) -- 2.34.1

4 9

[PATCH] ARM: stm32: Fix livetree conversion on STM32MP15xx DHSOM
by Marek Vasut 14 Jun '24

14 Jun '24

Unlike fdt_node_check_compatible() which returns 0 if node is compatible, ofnode_device_is_compatible() return true which is non-zero if node is compatible. The intention of the code is to exit from the function in case the node is not compatible with "micrel,ks8851-mll". Add the missing invert into the conditional to reinstate original behavior. This exposes a follow up problem caused by conversion to DM based FMC2 EBI driver, where the FMC2 EBI is not configured when accessed by this code. Probe the KS8851 MAC, which also configures the FMC2 EBI as a dependency, so that the KS8851 MAC CCR register can be accessed over the FMC2 EBI bus and checked for EEPROM present bit. Fixes: 5a605b7c8615 ("board: dhelectronics: stm32mp1: convert to livetree") Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> Cc: u-boot(a)dh-electronics.com Cc: u-boot(a)lists.denx.de Cc: uboot-stm32(a)st-md-mailman.stormreply.com --- board/dhelectronics/dh_stm32mp1/board.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index ebd45f9053f..4f4f537fee5 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -76,14 +76,25 @@ static bool dh_stm32_mac_is_in_ks8851(void) { - ofnode node; + struct udevice *udev; u32 reg, cider, ccr; + char path[256]; + ofnode node; + int ret; node = ofnode_path("ethernet1"); if (!ofnode_valid(node)) return false; - if (ofnode_device_is_compatible(node, "micrel,ks8851-mll")) + ret = ofnode_get_path(node, path, sizeof(path)); + if (ret) + return false; + + ret = uclass_get_device_by_of_path(UCLASS_ETH, path, &udev); + if (ret) + return false; + + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) return false; /* -- 2.43.0

2 2

[PATCH 1/2] stm32mp1: spl: Fix compilation warnings
by Patrice Chotard 14 Jun '24

14 Jun '24

Fix the following compilation warnings : ../arch/arm/mach-stm32mp/stm32mp1/spl.c: In function 'stm32_init_tzc_for_optee': ../arch/arm/mach-stm32mp/stm32mp1/spl.c:148:37: warning: 'optee_size' may be used uninitialized [-Wmaybe-uninitialized] 148 | tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE; | ~~~~~~~~~~~^~~~~~~~~~~~ ../arch/arm/mach-stm32mp/stm32mp1/spl.c:137:30: note: 'optee_size' was declared here 137 | uint32_t optee_base, optee_size, tee_shmem_base; | ^~~~~~~~~~ ../arch/arm/mach-stm32mp/stm32mp1/spl.c:148:37: warning: 'optee_base' may be used uninitialized [-Wmaybe-uninitialized] 148 | tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE; | ~~~~~~~~~~~^~~~~~~~~~~~ ../arch/arm/mach-stm32mp/stm32mp1/spl.c:137:18: note: 'optee_base' was declared here 137 | uint32_t optee_base, optee_size, tee_shmem_base; | ^~~~~~~~~~ Fix also the following checkpatch "check" : CHECK: Prefer kernel type 'u32' over 'uint32_t' 37: FILE: arch/arm/mach-stm32mp/stm32mp1/spl.c:137: + uint32_t optee_base = 0, optee_size = 0, tee_shmem_base; Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- arch/arm/mach-stm32mp/stm32mp1/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 6c79259b2c8..10abbed87f0 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -134,7 +134,7 @@ void stm32_init_tzc_for_optee(void) { const uint32_t dram_size = stm32mp_get_dram_size(); const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); - uint32_t optee_base, optee_size, tee_shmem_base; + u32 optee_base = 0, optee_size = 0, tee_shmem_base; const uintptr_t tzc = STM32_TZC_BASE; int ret; -- 2.25.1

3 5

[PATCH 0/2] rockchip: puma-rk3399/ringneck-px30: make closer to Jaguar/Tiger defconfigs
by Quentin Schulz 14 Jun '24

14 Jun '24

To ease maintenance, limit test scenarios and variations, let's enable a few things: - full bootstd - a handful of CLI commands like gpio, squashfs, erofs, pmic, regulator, and the likes. This also disables support for non-Linux OSes as Linux is the primary target, we may revisit this in the future if necessary. Also disables support for zImage on Puma since those aren't supported on Aarch64, one is supposed to use Image.gz (or any other supported compression format) with booti instead. Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> --- Quentin Schulz (2): rockchip: ringneck-px30: get closer to other Theobroma defconfigs rockchip: puma-rk3399: get closer to other Theobroma defconfigs configs/puma-rk3399_defconfig | 9 ++++++++- configs/ringneck-px30_defconfig | 16 +++++++++++----- 2 files changed, 19 insertions(+), 6 deletions(-) --- base-commit: 787eaa9c8df2660c748358eb689de916f991e22e change-id: 20240612-ringneck-bootd-ea9126a0e108 Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

2 4

[PATCH next v2 0/8] rockchip: px30: migrate to common bss and stack addresses and OF_UPSTREAM
by Quentin Schulz 14 Jun '24

14 Jun '24

Following up on migrating PX30 Ringneck to the new common bss and stack addresses as done in https://lore.kernel.org/u-boot/20240523-px30-2024-07-rc-v2-0-e46782d5520c@c… let's migrate all other px30 boards to this new memory layout so that it aligns with other Rockchip SoCs (TPL excluded). This also migrates all (but firefly-px30) PX30-based boards to use OF_UPSTREAM. firefly-px30 doesn't have an upstream kernel device tree so it is left untouched. All but Odroid-Go2 were straightforward to migrate. While at it, also fix a few issues related to UART on the PX30 Mini EVB I could test. This was boot tested on PX30 Ringneck and PX30 Mini EVB, U-Boot CLI and Linux kernel userspace are reached. This is based on next + https://lore.kernel.org/u-boot/20240523-px30-2024-07-rc-v2-0-e46782d5520c@c… To: Kever Yang <kever.yang(a)rock-chips.com> To: Tom Rini <trini(a)konsulko.com> To: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> To: Jagan Teki <jagan(a)amarulasolutions.com> To: Suniel Mahesh <sunil(a)amarulasolutions.com> To: Simon Glass <sjg(a)chromium.org> To: Philipp Tomsich <philipp.tomsich(a)vrull.eu> To: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> To: Klaus Goger <klaus.goger(a)theobroma-systems.com> Cc: u-boot(a)lists.denx.de Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> Changes in v2: - remove px30-base and ringneck patches, they were sent for master - migrate boards to OF_UPSTREAM - Link to v1: https://lore.kernel.org/r/20240521-px30-2024-07-rc-v1-0-62109c84d44f@cherry… independently: https://lore.kernel.org/u-boot/20240523-px30-2024-07-rc-v2-0-e46782d5520c@c… --- Quentin Schulz (8): rockchip: evb-px30: Use common bss and stack addresses rockchip: firefly-px30: Use common bss and stack addresses rockchip: odroid-go2: Use common bss and stack addresses rockchip: px30-core-*: Use common bss and stack addresses rockchip: px30: make UART pinmux accessible to TPL/SPL DTB rockchip: evb-px30: do not remove pinctrl nodes from SPL DTB rockchip: evb-px30: make UART5 the debug UART rockchip: px30/rk3326: migrate to OF_UPSTREAM arch/arm/dts/Makefile | 8 - arch/arm/dts/px30-engicam-common.dtsi | 129 ----- arch/arm/dts/px30-engicam-ctouch2.dtsi | 30 - arch/arm/dts/px30-engicam-edimm2.2.dtsi | 66 --- .../dts/px30-engicam-px30-core-ctouch2-of10.dts | 77 --- arch/arm/dts/px30-engicam-px30-core-ctouch2.dts | 22 - arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts | 43 -- arch/arm/dts/px30-engicam-px30-core.dtsi | 241 -------- arch/arm/dts/px30-evb.dts | 634 -------------------- arch/arm/dts/px30-ringneck-haikou.dts | 232 -------- arch/arm/dts/px30-ringneck.dtsi | 382 ------------ arch/arm/dts/px30-u-boot.dtsi | 16 + arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 15 + arch/arm/dts/rk3326-odroid-go2.dts | 642 --------------------- arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-px30_defconfig | 24 +- configs/firefly-px30_defconfig | 19 +- configs/odroid-go2_defconfig | 20 +- configs/px30-core-ctouch2-of10-px30_defconfig | 20 +- configs/px30-core-ctouch2-px30_defconfig | 20 +- configs/px30-core-edimm2.2-px30_defconfig | 20 +- configs/ringneck-px30_defconfig | 2 +- 22 files changed, 59 insertions(+), 2604 deletions(-) --- base-commit: 5e9aa577480ffbb6d3d0af6b972f227e087eef49 change-id: 20240508-px30-of_upstream-18bdbae87c98 Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

2 9

[PATCH] rockchip: mkimage: fix mkimage -l for header v1
by Quentin Schulz 14 Jun '24

14 Jun '24

From: Quentin Schulz <quentin.schulz(a)cherry.de> There are two paths to reach this function, either through mkimage -l or through dumpimage -l. The latter passes a NULL imagename while the former passes an empty string. Therefore, let's make both tools behave the same by handling the empty string the same way as for NULL. Without this, the only way to get some information out of mkimage -l is to provide "-n rk3399" for example, which isn't documented in the usage of the tool. Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> --- tools/rkcommon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 12c27b34eaa..3e52236b15a 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -470,7 +470,7 @@ int rkcommon_verify_header(unsigned char *buf, int size, * If no 'imagename' is specified via the commandline (e.g. if this is * 'dumpimage -l' w/o any further constraints), we accept any spl_info. */ - if (params->imagename == NULL) + if (params->imagename == NULL || !strlen(params->imagename)) return 0; /* Match the 'imagename' against the 'spl_hdr' found */ --- base-commit: 4b992573b34b1586e323e27b177680a6efec1c76 change-id: 20240606-rkcommon-dumpimage-mkimage-58610cf07340 Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

2 1

[PATCH next v3 0/8] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
by Quentin Schulz 14 Jun '24

14 Jun '24

This has a dependency on https://lore.kernel.org/u-boot/20240528170406.353616-1-liujianfeng1994@gmai… Changes in v3: - rebased on top of next, - changed patch series dependency from DRAM ATAGS (merged) to RK3588 upstream DTS cherry-picks from 6.10-rc1 (USB nodes), - cherry-picked kernel DTS commits for Tiger between v6.9 and v6.10-rc2, note that the "arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards" commit triggered some git auto-merging while cherry-picking, - support for Q7 USB P1 (micro-USB OTG) has been dropped, it requires extcon USB GPIO driver that isn't supported in U-Boot (yet?), - Link to v2: https://lore.kernel.org/r/20240423-tiger-v2-1-4a3fa0a01b5e@theobroma-system… Changes in v2: - removed uart controller muxing patch as not necessary until we get open-source DRAM init, - disabled DEBUG_UART_BOARD_INIT as it's only used for muxing the UART controller and it's not necessary since DDR bin does this for us already, - added missing uart2 mux bootph in U-Boot dtsi (though not required yet), - switched to USB_DWC3_GENERIC from USB_XHCI_DWC3 as requested by Jonas, - Link to v1: https://lore.kernel.org/r/20240422-tiger-v1-0-8816b070d748@theobroma-system… Signed-off-by: Quentin Schulz <quentin.schulz(a)cherry.de> --- Heiko Stuebner (6): arm64: dts: rockchip: enable gpu on rk3588-tiger arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger arm64: dts: rockchip: fix comment for upper usb3 port arm64: dts: rockchip: add usb-id extcon on rk3588 tiger arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou Jing Luo (1): arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards Quentin Schulz (1): rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 37 +++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 31 ++++++ board/theobroma-systems/tiger_rk3588/Kconfig | 16 +++ board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +++ board/theobroma-systems/tiger_rk3588/Makefile | 10 ++ .../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++++++++++ configs/tiger-rk3588_defconfig | 113 +++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++++++++++++++++++ .../src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 2 +- .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 2 +- dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts | 2 +- .../src/arm64/rockchip/rk3588-tiger-haikou.dts | 65 +++++++++++- dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi | 29 +++++- .../src/arm64/rockchip/rk3588-turing-rk1.dtsi | 2 +- .../src/arm64/rockchip/rk3588s-coolpi-4b.dts | 2 +- .../src/arm64/rockchip/rk3588s-indiedroid-nova.dts | 2 +- .../src/arm64/rockchip/rk3588s-orangepi-5.dts | 2 +- .../src/arm64/rockchip/rk3588s-rock-5a.dts | 2 +- include/configs/tiger_rk3588.h | 15 +++ 21 files changed, 488 insertions(+), 14 deletions(-) --- base-commit: b9bc39042dbc5d9e3bc84c0d63a54a4f6f5819d4 change-id: 20240418-tiger-d1531308c9a0 Best regards, -- Quentin Schulz <quentin.schulz(a)cherry.de>

3 11

Shutting down of the git-daemon (git protocol, https and ssh still remain)
by Claudius Heine 14 Jun '24

14 Jun '24

Hi everyone, in the past we used cgit, which provided cloning the u-boot repo via http, https, ssh and the git protocol. When we migrated to gitlab, which doesn't support the git protocol, we implemented some additional service files to continue to support it for some of our git repositories. We just noticed that cloning via the git protocol is currently broken, likely some changes in gitlab happened and we would need to recreate the symlinks on the server to point to the right repositories again. Since that is another thing to maintain and keep up, we would like to just shut the git protocol down. AFAIK most projects moved to use https for cloning anyway, since there were not many reports of broken cloning. What are your thoughts? Is it worth the effort to keep the git protocol up? regards, Claudius -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-54 Fax: (+49)-8142-66989-80 Email: ch(a)denx.de

4 8

[PATCH v3 0/4] Enable OSPI boot for j721s2
by Manorit Chawdhry 13 Jun '24

13 Jun '24

The series enables ospi boot for j721s2. Test logs: https://gist.github.com/manorit2001/6bb91885c608e3a8cb0267ab2c614781 Signed-off-by: Manorit Chawdhry <m-chawdhry(a)ti.com> --- Changes in v3: - Rebase on top of -next - Remove SF_DEFAULT_MODE as it's default 0 - Add new properties in correct location as per savedefconfig - Link to v2: https://lore.kernel.org/r/20240528-b4-upstream-j721s2-ospi-support-v2-0-b2e… --- Manorit Chawdhry (3): arch: arm: dts: k3-j721s2-r5: Override ospi and fss for 32-bit mode arch: arm: dts: k3-j721s2-*-u-boot.dtsi: Enable the ospi0 node configs: j721s2_evm_*_defconfig: Enable OSPI configs Pratyush Yadav (1): mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode .../dts/k3-j721s2-common-proc-board-u-boot.dtsi | 4 +- arch/arm/dts/k3-j721s2-r5.dtsi | 13 +++++ configs/j721s2_evm_a72_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + drivers/mtd/spi/spi-nor-core.c | 59 ++++++++++++++++++++-- 5 files changed, 73 insertions(+), 5 deletions(-) --- base-commit: 15d0dcc0ec1f424199dff2a3cbe037bc3a7d8749 change-id: 20240322-b4-upstream-j721s2-ospi-support-d45dfaa926dc Best regards, -- Manorit Chawdhry <m-chawdhry(a)ti.com>

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[PATCH] Fix typo in NVME show command
by Thomas Perl 13 Jun '24

13 Jun '24

Foramt -> Format Signed-off-by: Thomas Perl <m(a)thp.io> --- drivers/nvme/nvme_show.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c index 72cbac82bc..8dc03fe5bb 100644 --- a/drivers/nvme/nvme_show.c +++ b/drivers/nvme/nvme_show.c @@ -68,7 +68,7 @@ static void print_formats(struct nvme_id_ns *id, struct nvme_ns *ns) printf("Blk device %d: LBA Format Support:\n", ns->devnum); for (i = 0; i < id->nlbaf; i++) { - printf("\tLBA Foramt %d Support: ", i); + printf("\tLBA Format %d Support: ", i); if (i == ns->flbas) printf("(current)\n"); else -- 2.45.0

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