June 2024 - U-Boot

[PATCH v2] clk: Revise help text for clk_get_parent_rate()
by Alexander Dahl 02 Aug '24

02 Aug '24

The function returns the rate of the parent clock, the previous text made no sense at all. Fixes: 4aa78300a025 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Alexander Dahl <ada(a)thorsis.com> Reviewed-by: Sean Anderson <seanga2(a)gmail.com> --- Notes: v2: - Collected tags include/clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/clk.h b/include/clk.h index af23e4f3475..045e923a529 100644 --- a/include/clk.h +++ b/include/clk.h @@ -444,7 +444,7 @@ ulong clk_get_rate(struct clk *clk); struct clk *clk_get_parent(struct clk *clk); /** - * clk_get_parent_rate() - Get parent of current clock rate. + * clk_get_parent_rate() - Get rate of current clock's parent. * @clk: A clock struct that was previously successfully requested by * clk_request/get_by_*(). * base-commit: c92d48f8b2909d08584f17612a23d959467f14b8 -- 2.39.2

2 1

[PATCH] clk: Fix error message in clk_get_bulk
by Jan Kiszka 02 Aug '24

02 Aug '24

From: Jan Kiszka <jan.kiszka(a)siemens.com> Fix a logical inversion of the printed text. Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc484..78d8ea94c65 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -180,7 +180,7 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) bulk_get_err: err = clk_release_all(bulk->clks, bulk->count); if (err) - debug("%s: could release all clocks for %p\n", + debug("%s: could not release all clocks for %p\n", __func__, dev); return ret; -- 2.35.3

4 3

[PATCH 00/12] clk: mediatek: add OPs to support OF_UPSTREAM
by Christian Marangi 02 Aug '24

02 Aug '24

This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM. While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID. Upstream reference clock by names and clock are handled by the CCF (Common Clock Framework). The same can't be used here as we would quickly reach the max space allocated before relocation. The current mediatek clock driver reference all the parents and clocks with offset from the clk ID related to the different tables. Discrepancy between clock ID and the order in the clocks table cause one clock referenced for another or even crash for trying to access a clock at an offset that doesn't exist. To handle this and permit use of OF_UPSTREAM, various measure and changes are done to the mediatek clock driver to support it. This series have all the generic clock changes. Once this is merged, series for each SoC will came that will just change files in their dedicated clock driver. This is to prevent massive patch and to permit to split series, one for each SoC. As said at the start, these changes doesn't cause regression and are just expansion to the current API. Current behaviour is saved in every possible way (aside from the first 2 patch that fixes latent bugs) World compile tested in Azure Pipeline test Christian Marangi (12): clk: mediatek: return XTAL rate directly for gates with XTAL parent clk: mediatek: return XTAL rate for infrasys get_mux_rate clk: mediatek: add support for gates in clk_tree for infrasys clk: mediatek: add support for gate ID at offset clk: mediatek: add support for parent mux from different source clk: mediatek: add support for parent mux from different source for topckgen clk: mediatek: add support for gate clock to reference topckgen clock clk: mediatek: provide common clk init function for infrasys clk: mediatek: add support for remapping clock ID clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro clk: mediatek: add support for GATEs for APMIXED OPs clk: mediatek: add support for APMIXED parent in infra MUX drivers/clk/mediatek/clk-mtk.c | 433 ++++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mtk.h | 74 +++++- 2 files changed, 392 insertions(+), 115 deletions(-) -- 2.45.1

2 14

[PATCH v2 1/1] net: dwc_eth_qos: mdio: Implement clause 45
by Philip Oberfichtner 01 Aug '24

01 Aug '24

Bevor this commit, only clause 22 access was possible. After this commit, clause 45 direct access will available as well. Note that there is a slight change of behavior: Before this commit, the C45E bit was set to whatever value was left in the register from the previous access. After this commit, we adopt the common practice of discerning C45 from C22 using the devad argument. Signed-off-by: Philip Oberfichtner <pro(a)denx.de> --- Notes: Attention: There is a slight change of behavior introduced by this commit (see commit message). Please test and review if this works for everybody. My implementation is tested on an Intel Elkhart lake SOC, patch submitted here: https://patchwork.ozlabs.org/project/uboot/list/?series=405358 Changes in V2: - Use FIELD_PREP() instead of manual '<<' shifting - Fix whitespace errors drivers/net/dwc_eth_qos.c | 66 ++++++++++++++++++++++++++------------- drivers/net/dwc_eth_qos.h | 9 +++--- 2 files changed, 49 insertions(+), 26 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index cb329e0cef..6bc9b8fca4 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -51,6 +51,7 @@ #include <asm/arch/clock.h> #include <asm/mach-imx/sys_proto.h> #endif +#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/printk.h> @@ -184,6 +185,25 @@ static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 1000000, true); } +/* Bitmask common for mdio_read and mdio_write */ +#define EQOS_MDIO_BITFIELD(pa, rda, cr) \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_PA_MASK, pa) | \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_RDA_MASK, rda) | \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_CR_MASK, cr) | \ + EQOS_MAC_MDIO_ADDRESS_GB + +static u32 eqos_mdio_bitfield(struct eqos_priv *eqos, int addr, int devad, int reg) +{ + int cr = eqos->config->config_mac_mdio; + bool c22 = devad == MDIO_DEVAD_NONE ? true : false; + + if (c22) + return EQOS_MDIO_BITFIELD(addr, reg, cr); + else + return EQOS_MDIO_BITFIELD(addr, devad, cr) | + EQOS_MAC_MDIO_ADDRESS_C45E; +} + static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg) { @@ -201,15 +221,17 @@ static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, } val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_READ << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; + val &= EQOS_MAC_MDIO_ADDRESS_SKAP; + + val |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, + EQOS_MAC_MDIO_ADDRESS_GOC_READ); + + if (val & EQOS_MAC_MDIO_ADDRESS_C45E) { + writel(FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg), + &eqos->mac_regs->mdio_data); + } + writel(val, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); @@ -232,7 +254,8 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg, u16 mdio_val) { struct eqos_priv *eqos = bus->priv; - u32 val; + u32 v_addr; + u32 v_data; int ret; debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, @@ -244,20 +267,19 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, return ret; } - writel(mdio_val, &eqos->mac_regs->mdio_data); + v_addr = readl(&eqos->mac_regs->mdio_address); + v_addr &= EQOS_MAC_MDIO_ADDRESS_SKAP; - val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; - writel(val, &eqos->mac_regs->mdio_address); + v_addr |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, + EQOS_MAC_MDIO_ADDRESS_GOC_WRITE); + + v_data = mdio_val; + if (v_addr & EQOS_MAC_MDIO_ADDRESS_C45E) + v_data |= FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg); + writel(v_data, &eqos->mac_regs->mdio_data); + writel(v_addr, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); ret = eqos_mdio_wait_idle(eqos); diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8b3d0d464d..a06390a698 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -79,19 +79,20 @@ struct eqos_mac_regs { #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3 -#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 -#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 -#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define EQOS_MAC_MDIO_ADDRESS_PA_MASK GENMASK(25, 21) +#define EQOS_MAC_MDIO_ADDRESS_RDA_MASK GENMASK(20, 16) +#define EQOS_MAC_MDIO_ADDRESS_CR_MASK GENMASK(11, 8) #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) -#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 +#define EQOS_MAC_MDIO_ADDRESS_GOC_MASK GENMASK(3, 2) #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) +#define EQOS_MAC_MDIO_DATA_RA_MASK GENMASK(31, 16) #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff #define EQOS_MTL_REGS_BASE 0xd00 -- 2.39.2

3 2

[PATCH 0/9] Bug-fixes for a few boards
by Simon Glass 31 Jul '24

31 Jul '24

This series includes fixes to get some rockchip and nvidia boards working again. It also provides a fix (revert) for Beaglebone Black and a devicetree fix for coral (x86). Simon Glass (9): nvidia: nyan-big: Disable debug UART tpm: Avoid code bloat when not using EFI_TCG2_PROTOCOL rockchip: veyron: Add logging for power init power: regulator: Handle autoset in regulators_enable_boot_on() fdt: Correct condition for bloblist existing spl: Allow ATF to work when dcache is disabled rockchip: bob: kevin: Disable dcache in SPL regulator: rk8xx: Fix incorrect parameter Revert "arm: am335x: Enable SPL_OF_CONTROL on some configs" board/google/veyron/veyron.c | 27 ++++++++++------------ common/spl/spl_atf.c | 3 ++- configs/am335x_boneblack_vboot_defconfig | 1 - configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/nyan-big_defconfig | 1 - drivers/power/regulator/regulator-uclass.c | 2 +- drivers/power/regulator/rk8xx.c | 2 +- lib/Kconfig | 8 +++---- lib/fdtdec.c | 12 ++++++++-- 10 files changed, 32 insertions(+), 26 deletions(-) -- 2.34.1

7 44

[PATCH RFC] gpio: Fix probing of gpio-hogs
by Chris Webb 31 Jul '24

31 Jul '24

48b3ecbe replumbed the gpio-hog probing to use DM_FLAG_PROBE_AFTER_BIND. Unfortunately gpio_post_bind is called after the non-preloc recursive dm_probe_devices completes, so setting this flag does not have the intended effect and the gpio-hogs never get probed. With instrumentation: [...] CPU: MediaTek MT7981 Model: GL.iNet GL-X3000 DRAM: 512 MiB <mtk_pinctrl_mt7981_bind called> <dm_probe_devices called: root root_driver root_driver [+] [ ]> <dm_probe_devices called: clk fixed_clock gpt_dummy20m [ ] [ ]> [...] <dm_probe_devices called: led gpio_led signal-4 [ ] [ ]> Core: 34 devices, 14 uclasses, devicetree: separate MMC: <gpio_post_bind called> mmc@11230000: 0 [...] Probe them directly in gpio_post_bind instead. Signed-off-by: Chris Webb <chris(a)arachsys.com> --- drivers/gpio/gpio-uclass.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 4234cd91..1c6e1715 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1539,7 +1539,9 @@ static int gpio_post_bind(struct udevice *dev) * since hogs can be essential to the hardware * system. */ - dev_or_flags(child, DM_FLAG_PROBE_AFTER_BIND); + ret = device_probe(child); + if (ret) + return ret; } } }

3 12

[PATCH 0/6] video: pixel format handling fixes and improvements
by Jiaxun Yang 28 Jul '24

28 Jul '24

Hi all, This series fixes endian related problem I found in general video system when testing my fresh virtio-gpu driver on big endian target. It also removed a lot of duplicated code on pixel handling, and make implementation of new pixel formats easier. Further more, it removed limitation on bpc for BMP display, now we can display any image depth on any target display controller. Please review. Thanks Signed-off-by: Jiaxun Yang <jiaxun.yang(a)flygoat.com> --- Jiaxun Yang (6): video: Move generated bmp headers to include/generated video: Add gitignore for u_boot_logo.S video: Rework pixel format handling video: bmp: Rework with video_rgb_to_pixel_* video: sandbox_sdl: Implement more pixel formats video: bochs: Setup framebuffer endian Makefile | 2 +- arch/sandbox/cpu/sdl.c | 58 +++++++++-- arch/sandbox/include/asm/sdl.h | 17 ++-- board/aristainetos/aristainetos.c | 2 +- board/toradex/common/tdx-common.c | 2 +- common/splash.c | 4 +- drivers/video/.gitignore | 1 + drivers/video/bochs.c | 8 ++ drivers/video/console_truetype.c | 4 +- drivers/video/sandbox_sdl.c | 16 +-- drivers/video/simplefb.c | 2 +- drivers/video/video-uclass.c | 38 ++----- drivers/video/video_bmp.c | 201 +++++++++++--------------------------- include/dm/test.h | 2 + include/video.h | 31 +----- include/video_format.h | 161 ++++++++++++++++++++++++++++++ lib/efi_loader/efi_gop.c | 2 +- test/dm/video.c | 18 ++-- tools/Makefile | 4 +- 19 files changed, 332 insertions(+), 241 deletions(-) --- base-commit: ad7dce5abd49ef3b5c93da5303e15449c8c162b4 change-id: 20240516-rework-video-format-ae8afadc45a5 Best regards, -- Jiaxun Yang <jiaxun.yang(a)flygoat.com>

4 10

[PATCH v2 0/8] Add support for Qualcomm SA8155-ADP board
by Volodymyr Babchuk 27 Jul '24

27 Jul '24

This patch series adds support for Qualcomm SA8155-ADP development board. Main motivation for this series is to allow running virtualization software on this board and U-Boot is a good way to break Qualcomm's boot chain at EL2 with more convenient ways for uploading and running the code. With this patches applied it is possible to upload and run Xen on this board. KVM probably should work too. I added myself as a maintainer for this board, but my abilities to maintain it are quite limited as I have no access to Qualcomm documentation. I used mostly Linux drivers as the source for device-specific information, like register addresses and offsets. If anyone wants to maintain this, I will gladly agree. This is the second version of the series. It is now rebased onto qcom-next branch. Changes in v2: - New patch in v2 - Clear loopback bit explicitly - Reworked qcom_cc_bind() function - Added timeout to qcom_power_set() - Minor fixes in register names and formatting - Renamed GPLL7_MAIN to just GPLL7 (while I like idea to use Linux naming convention, such rework needs to be done in a separate commit) - Removed unnecessary include - Fixed GDSCR register values for couple of devices - Enable GPLL7 only when RGMII clock is enabled - Rebased onto qcom-next branch - Removed unnecessary files thanks to generic qualcomm board support - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the readme) Volodymyr Babchuk (8): qcom: board: validate fdt before trying to use it clk: qcom: clear div mask before assigning a new divider net: dw_eth_qos: add support for Qualcomm SM8150 SoC clk: qcom: add support for power domains uclass clk: qcom: add driver for SM8150 SoC pinctrl: qcom: pass pin number to get_function_mux callback pinctrl: qcom: add driver for SM8150 SoC board: add support for Qualcomm SA8155P-ADP board arch/arm/dts/sa8155p-adp-u-boot.dtsi | 30 ++ arch/arm/mach-snapdragon/board.c | 5 +- board/qualcomm/sa8155p-adp/MAINTAINERS | 5 + configs/sa8155p_adp_defconfig | 35 ++ doc/board/qualcomm/index.rst | 1 + doc/board/qualcomm/sa8155p-adp.rst | 87 ++++ drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-qcom.c | 131 +++++- drivers/clk/qcom/clock-qcom.h | 7 + drivers/clk/qcom/clock-sm8150.c | 237 ++++++++++ drivers/net/dwc_eth_qos.c | 4 + drivers/net/dwc_eth_qos.h | 2 + drivers/net/dwc_eth_qos_qcom.c | 46 +- drivers/pinctrl/qcom/Kconfig | 7 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-apq8016.c | 3 +- drivers/pinctrl/qcom/pinctrl-apq8096.c | 3 +- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 3 +- drivers/pinctrl/qcom/pinctrl-qcom.c | 4 +- drivers/pinctrl/qcom/pinctrl-qcom.h | 3 +- drivers/pinctrl/qcom/pinctrl-qcs404.c | 3 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 3 +- drivers/pinctrl/qcom/pinctrl-sm8150.c | 589 +++++++++++++++++++++++++ 24 files changed, 1186 insertions(+), 32 deletions(-) create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS create mode 100644 configs/sa8155p_adp_defconfig create mode 100644 doc/board/qualcomm/sa8155p-adp.rst create mode 100644 drivers/clk/qcom/clock-sm8150.c create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c -- 2.43.0

4 31

[PATCH v2 00/40] mmc: dw_mmc: Enable eMMC on E850-96 board
by Sam Protsenko 26 Jul '24

26 Jul '24

Bring 64-bit support to dw_mmc core and Exynos dw_mmc drivers, and enable it on E850-96 board. Additionally do some related cleanups and device tree updates. 64-bit version of DesignWare MMC can be often found on modern ARM64 chips. It's different from its older 32-bit version (which is already implemented in U-Boot): some new registers were added, existing register addresses are changed, DMA descriptor table is different, etc. Next Exynos chips are known to have 64-bit DW MMC block: - Exynos3475 - Exynos5433 - Exynos7420 - Exynos7570 - Exynos7580 - Exynos7870 - Exynos7872 - Exynos7880 - Exynos7885 - Exynos7890 - Exynos850 (Exynos3830) Exynos DW MMC driver was updated too: ARM64 Exynos chips implement their clock drivers using CCF framework, pinmux configuration is done at startup in DM capable pinctrl drivers, device tree properties were changed w.r.t. their upstream (Linux kernel) counterparts. CLKSEL register address is also different on 64-bit Exynos platforms. The patch series was tested on E850-96 board by running mainline Linux kernel with Debian rootfs from eMMC ("boot" partition) with these commands: 8<-------------------------------------------------------------------->8 env set fdtaddr 0x8a000000 env set bootaddr 0x94000000 env set boot_kerneladdr 0x94000800 part start mmc 0 boot boot_start part size mmc 0 boot boot_size mmc read $bootaddr $boot_start $boot_size abootimg addr $bootaddr abootimg get dtb --index=0 dtb_start dtb_size cp.b $dtb_start $fdtaddr $dtb_size fdt addr $fdtaddr 0x100000 cp.b $boot_kerneladdr $loadaddr 2aaaa00 env set bootargs console=ttySAC0,115200n8 printk.devkmsg=on \ root=/dev/mmcblk0p12 rootwait rw booti $loadaddr - $fdtaddr 8<-------------------------------------------------------------------->8 For E850-96 eMMC to function properly in DDR mode, the pending patch [1] has to be applied. Otherwise it won't be possible for exynos_dw_mmc driver to change CIU clock rate from 200 MHz up to 400 MHz, and MMC will fall back to SDR mode, which makes eMMC throughput twice as slower. With patch [1] applied, 'mmc info' reports this: Bus Speed: 52000000 Mode: MMC DDR52 (52MHz) and 'clk dump' shows CIU clock rate to be ~400 MHz (after first mmc operation, e.g. 'part start' or 'mmc read'): 399750000 gout_mmc_embd_sdclkin Which makes sense, because dw_mmc requests to set CCLKIN = 52 MHz (with DDR/8-bit mode), and exynos_dw_mmc tries to set CIU clock rate to: SDCLKIN = 2 * ciu_div * CCLKIN = 2 * 4 * 52 MHz = 416 MHz, and the closest possible value the clock driver can set is 399.75 MHz, which works just fine. For Exynos4 and Exynos5 (ARM32) boards, this patch series was only build tested (manually and with buildman). The build is clean (no errors or warnings), but I don't have any Exynos4/Exynos5 boards at my disposal, so I can't actually verify MMC operation there. Changes in v2: - Rebased on top of the most recent U-Boot/master - Added pending R-b tags from the mailing list - Addressed the comment from Quentin about CONFIG_IS_ENABLED() not playing nice in SPL case: 1. Dropped [PATCH 35/42] ("mmc: exynos_dw_mmc: Use CONFIG_IS_ENABLED() to check config options") 2. Dropped [PATCH 14/42] ("mmc: dw_mmc: Use CONFIG_IS_ENABLED() to check config options") 3. Got rid of all other CONFIG_IS_ENABLED() changes (used #ifdef for now) - Addressed the comment from Quentin about incorrect logic for divider update in [PATCH 06/40] - Guarded exynos_dwmmc_of_to_plat() with #ifded CONFIG_DM_MMC in [PATCH 22/40] - Added list of Exynos chips implementing 64-bit IDMAC descriptor (in [PATCH 00/40]) [1] https://lists.denx.de/pipermail/u-boot/2024-March/547719.html Sam Protsenko (40): mmc: dw_mmc: Remove common.h mmc: dw_mmc: Remove unused version field from struct dwmci_host mmc: dw_mmc: Move struct idmac to dw_mmc.c mmc: dw_mmc: Extract waiting for data busy into a separate routine mmc: dw_mmc: Extract FIFO init into a separate routine mmc: dw_mmc: Extract divider update to a separate function mmc: dw_mmc: Extract FIFO data transfer into a separate routine mmc: dw_mmc: Extract DMA transfer handling code into a separate routine mmc: dw_mmc: Extract setting the DMA descriptor into a separate routine mmc: dw_mmc: Improve 32-bit IDMAC descriptor namings mmc: dw_mmc: Add support for 64-bit IDMAC mmc: dw_mmc: Replace fifoth_val property with fifo-depth mmc: dw_mmc: Fix kernel-doc comments in dwmmc.h mmc: dw_mmc: Improve coding style arm: dts: exynos: Add upstream DW MMC properties to all Exynos dts dt-bindings: exynos: Update bindings doc for DW MMC controller arm: exynos: Add header guard for dwmmc.h mmc: exynos_dw_mmc: Fix obtaining the base address of controller mmc: exynos_dw_mmc: Fix getting private data in exynos_dwmci_board_init() mmc: exynos_dw_mmc: Don't call pinmux functions on ARM64 chips mmc: exynos_dw_mmc: Obtain and use CIU clock via CCF API mmc: exynos_dw_mmc: Use .of_to_plat for device tree parsing mmc: exynos_dw_mmc: Convert to use livetree API mmc: exynos_dw_mmc: Read upstream SDR timing properties mmc: exynos_dw_mmc: Abstract CLKSEL register mmc: exynos_dw_mmc: Refactor fixed CIU clock divider mmc: exynos_dw_mmc: Read common bus-width property mmc: exynos_dw_mmc: Read common clock-frequency property mmc: exynos_dw_mmc: Move quirks from struct dwmci_host to chip data mmc: exynos_dw_mmc: Read and use DDR timing when available mmc: exynos_dw_mmc: Set requested freq in get_mmc_clk() callback mmc: exynos_dw_mmc: Add support for ARM64 Exynos chips mmc: exynos_dw_mmc: Remove common.h mmc: exynos_dw_mmc: Pull all init code into probe function mmc: exynos_dw_mmc: Don't call dwmci_setup_cfg() after add_dwmci() mmc: exynos_dw_mmc: Use dev->name as driver's displayed name mmc: exynos_dw_mmc: Improve coding style arm: dts: exynos: Remove outdated DW MMC properties in all Exynos dts configs: e850-96: Enable MMC doc: samsung: Mention enabled eMMC in E850-96 board doc arch/arm/dts/exynos4210-origen.dts | 3 +- arch/arm/dts/exynos4210-trats.dts | 6 +- arch/arm/dts/exynos4210-universal_c210.dts | 6 +- arch/arm/dts/exynos4412-odroid.dts | 14 +- arch/arm/dts/exynos4412-trats2.dts | 20 +- arch/arm/dts/exynos5250-arndale.dts | 10 +- arch/arm/dts/exynos5250-smdk5250.dts | 13 +- arch/arm/dts/exynos5250-snow.dts | 13 +- arch/arm/dts/exynos5250-spring.dts | 7 +- arch/arm/dts/exynos5420-smdk5420.dts | 13 +- arch/arm/dts/exynos5422-odroidxu3.dts | 4 +- arch/arm/dts/exynos54xx.dtsi | 13 +- arch/arm/mach-exynos/include/mach/dwmmc.h | 40 +- configs/e850-96_defconfig | 10 +- doc/board/samsung/e850-96.rst | 5 +- doc/device-tree-bindings/exynos/dwmmc.txt | 46 +- drivers/mmc/ca_dw_mmc.c | 2 +- drivers/mmc/dw_mmc.c | 550 +++++++++++++-------- drivers/mmc/exynos_dw_mmc.c | 358 +++++++++----- drivers/mmc/ftsdc010_mci.h | 1 - drivers/mmc/hi6220_dw_mmc.c | 7 +- drivers/mmc/nexell_dw_mmc.c | 5 +- drivers/mmc/rockchip_dw_mmc.c | 5 +- drivers/mmc/s5p_sdhci.c | 2 +- drivers/mmc/snps_dw_mmc.c | 6 +- drivers/mmc/socfpga_dw_mmc.c | 4 +- include/dwmmc.h | 242 +++++---- 27 files changed, 868 insertions(+), 537 deletions(-) -- 2.39.2

6 49

[PATCH v3 1/5] clock: qcom: ipq4019: add ESS clock
by Robert Marko 26 Jul '24

26 Jul '24

ESS clock is the Ethernet Subsystem clock, so lets add it as its already configured by SBL1. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- drivers/clk/qcom/clock-ipq4019.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 72f235eab2..09be203d4b 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -44,6 +44,9 @@ static int ipq4019_clk_enable(struct clk *clk) case GCC_USB2_MOCK_UTMI_CLK: /* These clocks is already initialized by SBL1 */ return 0; + case GCC_ESS_CLK: + /* This clock is already initialized by SBL1 */ + return 0; default: return -EINVAL; } -- 2.45.1

3 7