June 2024 - U-Boot

[PATCH v3 0/6] Add Binman code-coverage test to CI
by Simon Glass 15 Jul '24

15 Jul '24

Binman has 100% code coverage to ensure that future changes and refactors do not break existing entry types. This is a critical feature, given that it is relied on to produce images for all sorts of different SoCs and vendors. With the NXP additions the 'binman test -T' step was missed, so the Binman coverage test is currently failing. This series provides a means to close the testing gap. It cannot be applied until the tests are added, which should happen before -next is applied to -master Changes in v3: - Drop the PATH modification altogether Changes in v2: - Add new patch to fix a few typos in toolchain code - Add to azure also (oops) - Add to buildman requirements instead Simon Glass (6): buildman: Add python3-coverage buildman: Add python3-pycryptodome buildman: Fix a few typos in toolchain code buildman: Always use the full path in CROSS_COMPILE u_boot_pylib: Use correct coverage tool within venv CI: Run code-coverage test for Binman .azure-pipelines.yml | 5 ++- .gitlab-ci.yml | 4 +- tools/buildman/bsettings.py | 3 ++ tools/buildman/builder.py | 5 +-- tools/buildman/builderthread.py | 4 +- tools/buildman/cmdline.py | 2 - tools/buildman/control.py | 6 +-- tools/buildman/requirements.txt | 2 + tools/buildman/test.py | 75 +++++++++++++++++++++++++++++++++ tools/buildman/toolchain.py | 24 +++++------ tools/u_boot_pylib/test_util.py | 11 +++-- 11 files changed, 111 insertions(+), 30 deletions(-) -- 2.34.1

3 18

[PATCH] arm: dts: mvebu: Migrate to upstream DT for Synology DS116 (Armada 385) board
by Tony Dinh 15 Jul '24

15 Jul '24

Enable OF_UPSTREAM to use upstream DT and add marvell/ prefix to the DEFAULT_DEVICE_TREE in DS116 defconfig. Remove current DTS in arch/arm/dts/ directory. Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- arch/arm/dts/Makefile | 1 - arch/arm/dts/armada-385-synology-ds116.dts | 291 --------------------- configs/ds116_defconfig | 3 +- 3 files changed, 2 insertions(+), 293 deletions(-) delete mode 100644 arch/arm/dts/armada-385-synology-ds116.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a5c82ebf7a..75f7e616b4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -155,7 +155,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-385-atl-x530.dtb \ armada-385-atl-x530DP.dtb \ armada-385-db-88f6820-amc.dtb \ - armada-385-synology-ds116.dtb \ armada-385-thecus-n2350.dtb \ armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ diff --git a/arch/arm/dts/armada-385-synology-ds116.dts b/arch/arm/dts/armada-385-synology-ds116.dts deleted file mode 100644 index 82a0373f7f..0000000000 --- a/arch/arm/dts/armada-385-synology-ds116.dts +++ /dev/null @@ -1,291 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Synology DS116 NAS - * - * Copyright (C) 2017 Willy Tarreau <w(a)1wt.eu> - */ - -/dts-v1/; -#include "armada-385.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Synology DS116"; - compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 - MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 - MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - serial@12100 { - /* A PIC16F1829 is connected to uart1 at 9600 bps, - * and takes single-character orders : - * "1" : power off // already handled by the poweroff node - * "2" : short beep - * "3" : long beep - * "4" : turn the power LED ON - * "5" : flash the power LED - * "6" : turn the power LED OFF - * "7" : turn the status LED OFF - * "8" : turn the status LED ON - * "9" : flash the status LED - * "A" : flash the motherboard LED (D8) - * "B" : turn the motherboard LED OFF - * "C" : hard reset - */ - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - ethernet@70000 { - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - status = "okay"; - }; - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <&reg_5v_sata0>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - usb3@f0000 { - usb-phy = <&usb3_0_phy>; - status = "okay"; - }; - - usb3@f8000 { - usb-phy = <&usb3_1_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>, - <&gpio1 17 GPIO_ACTIVE_HIGH>, - <&gpio1 16 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1500 1 - 2500 2 - 3000 3 - 3400 4 - 3700 5 - 3900 6 - 4000 7>; - #cooling-cells = <2>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - /* The green part is on gpio0.20 which is also used by - * sata0, and accesses to SATA disk 0 make it blink so it - * doesn't need to be declared here. - */ - orange { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - label = "ds116:orange:disk"; - default-state = "off"; - }; - }; - }; - - usb3_0_phy: usb3_0_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&reg_usb3_0_vbus>; - #phy-cells = <0>; - }; - - usb3_1_phy: usb3_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&reg_usb3_1_vbus>; - #phy-cells = <0>; - }; - - reg_usb3_0_vbus: usb3-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus0"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_usb3_1_vbus: usb3-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus1"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci1_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&reg_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&reg_sata0>; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "macronix,mx25l6405d", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - - /* Note: there is a redboot partition table despite u-boot - * being used. The names presented here are the same as those - * found in the FIS directory. There is also a small device - * tree in the last 64kB of the RedBoot partition which is not - * enumerated. The MAC address and the serial number are listed - * in the "vendor" partition. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x000f0000>; - read-only; - }; - - partition@c0000 { - label = "zImage"; - reg = <0x000f0000 0x002d0000>; - }; - - partition@390000 { - label = "rd.gz"; - reg = <0x003c0000 0x00410000>; - }; - - partition@7d0000 { - label = "vendor"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; - read-only; - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&pinctrl { - /* use only one pin for UART1, as mpp20 is used by sata0 */ - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "ua1"; - }; - - xhci0_vbus_pins: xhci0_vbus_pins { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - xhci1_vbus_pins: xhci1_vbus_pins { - marvell,pins = "mpp59"; - marvell,function = "gpio"; - }; -}; diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig index 1fc7380216..bcc5f00fe5 100644 --- a/configs/ds116_defconfig +++ b/configs/ds116_defconfig @@ -16,7 +16,7 @@ CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x7E0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="armada-385-synology-ds116" +CONFIG_DEFAULT_DEVICE_TREE="marvell/armada-385-synology-ds116" CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x4002c000 @@ -56,6 +56,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(u-boot),7040k(kernel),64k(u-boot-env),-(data)" +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y -- 2.39.2

3 4

[PATCH] arm: sunxi: add support for I2C1 on V3s-based SoCs
by Tobias Schramm 15 Jul '24

15 Jul '24

Previously enabling I2C1 when using a V3s-based SoC had no effect. Set pinmux on PE21 and PE22 to I2C1 function when enabling I2C1 on V3s-based SoCs. Signed-off-by: Tobias Schramm <t.schramm(a)manjaro.org> --- board/sunxi/board.c | 4 ++++ include/sunxi_gpio.h | 1 + 2 files changed, 5 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1313b01dce..df2faba3e5 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -98,6 +98,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN8I_V3S) + sunxi_gpio_set_cfgpin(SUNXI_GPE(21), SUN8I_V3S_GPE_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPE(22), SUN8I_V3S_GPE_TWI1); + clock_twi_onoff(1, 1); #elif defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index db3742c039..175b13a887 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -113,6 +113,7 @@ enum sunxi_gpio_number { #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 #define SUN8I_V3S_GPB_TWI0 2 +#define SUN8I_V3S_GPE_TWI1 3 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 -- 2.30.2

2 1

[PATCH v2 0/2] sunxi, usb: UDC/DM gadget model support
by Sam Edwards 15 Jul '24

15 Jul '24

Happy Thursday, U-Boot list! Here is attempt 2 at making this USB controller driver compatible with DM's gadget model, following what most of the other musb variants do. v2 removes the unwanted printfs in the probe func, per feedback from Marek. I received no other feedback against v1 of this patch. Cheers, Sam Sam Edwards (2): usb: musb-new: sunxi: remove unwanted printfs usb: musb-new: sunxi: make compatible with UDC/DM gadget model drivers/usb/musb-new/sunxi.c | 52 +++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 21 deletions(-) -- 2.39.2

3 9

[RFC] usb: xhci: Some USB devices fail to initialize
by Elena Popa 14 Jul '24

14 Jul '24

Hello, We've noticed that, at least, on the i.MX8M* platforms, some USB devices (especially USB2.0 sticks) fail to initialize with one of the following errors: - scanning bus usb@38200000 for devices... Device not responding to set address. USB device not accepting new address (error=80000000) - scanning bus usb@38200000 for devices... WARN halted endpoint, queueing URB anyway. Unexpected XHCI event TRB, skipping... (fcf1a5f0 00000000 13000000 01008401) BUG at drivers/usb/host/xhci-ring.c:530/abort_td()! BUG! resetting ... It seems to be a timing problem, since if we enable the debug messages, the USB device initializes correctly. We found out that if we add a small delay of 5 milliseconds at the beginning of the _xhci_submit_control_msg() function from the drivers/usb/host/xhci.c file, all devices initialize properly. Essentially, each control message is delayed by 5ms. We tried a smaller delay (1ms), but it is not enough. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer, int length, struct devrequest *setup, int root_portnr) { + mdelay(5); struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); int ret = 0; ... } We went a little further, and this delay seems to only be necessary for the requests of type: - USB_REQ_GET_STATUS (for the communication with the root) - USB_REQ_GET_DESCRIPTOR ( for the communication with the device) I don't have too much know-how about the USB, so I would appreciate your opinion related to this issue, and how can we find the root cause. I found several reports on the internet with the same problem on other boards. Maybe some of the USB timing specs are not implemented correctly? U-Boot is maybe sending control messages too aggressively? If you give me some suggestions of where to look, I could do some debugging myself. Of course, since printing debug messages makes the initialization work, complicates the debugging. Thank you, Elena

2 6

[PATCH] part: efi: Rely on a definition to specify the primary GPT position
by Roman Stratiienko 14 Jul '24

14 Jul '24

Use GPT_PRIMARY_PARTITION_TABLE_LBA as the only source for a primary GPT location instead of hardcoding it every time. Sometimes, we need to shift the primary GPT location. Having the location in the single place simplifies such shifting. Signed-off-by: Roman Stratiienko <r.stratiienko(a)gmail.com> --- disk/part_efi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 4ce9243ef2..b55e251ea1 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -387,7 +387,7 @@ int write_gpt_table(struct blk_desc *desc, gpt_header *gpt_h, gpt_entry *gpt_e) gpt_h->header_crc32 = cpu_to_le32(calc_crc32); /* Write the First GPT to the block right after the Legacy MBR */ - if (blk_dwrite(desc, 1, 1, gpt_h) != 1) + if (blk_dwrite(desc, (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1, gpt_h) != 1) goto err; if (blk_dwrite(desc, le64_to_cpu(gpt_h->partition_entry_lba), @@ -534,7 +534,7 @@ int gpt_fill_pte(struct blk_desc *desc, static uint32_t partition_entries_offset(struct blk_desc *desc) { - uint32_t offset_blks = 2; + uint32_t offset_blks = GPT_PRIMARY_PARTITION_TABLE_LBA + 1; uint32_t __maybe_unused offset_bytes; int __maybe_unused config_offset; @@ -572,8 +572,8 @@ static uint32_t partition_entries_offset(struct blk_desc *desc) * The earliest LBA this can be at is LBA#2 (i.e. right behind * the (protective) MBR and the GPT header. */ - if (offset_blks < 2) - offset_blks = 2; + if (offset_blks < (GPT_PRIMARY_PARTITION_TABLE_LBA + 1)) + offset_blks = GPT_PRIMARY_PARTITION_TABLE_LBA + 1; return offset_blks; } @@ -584,7 +584,7 @@ int gpt_fill_header(struct blk_desc *desc, gpt_header *gpt_h, char *str_guid, gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE_UBOOT); gpt_h->revision = cpu_to_le32(GPT_HEADER_REVISION_V1); gpt_h->header_size = cpu_to_le32(sizeof(gpt_header)); - gpt_h->my_lba = cpu_to_le64(1); + gpt_h->my_lba = cpu_to_le64(GPT_PRIMARY_PARTITION_TABLE_LBA); gpt_h->alternate_lba = cpu_to_le64(desc->lba - 1); gpt_h->last_usable_lba = cpu_to_le64(desc->lba - 34); gpt_h->partition_entry_lba = -- 2.40.1

2 4

[PATCH] clk: imx8mn: add video clocks support
by Michael Trimarchi 14 Jul '24

14 Jul '24

Add clocks support for the video subsystem. Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- drivers/clk/imx/clk-imx8mn.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 457acb8a40..baac79dd29 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -23,6 +23,7 @@ static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -30,6 +31,10 @@ static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; +static const char *imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext4", }; + static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; @@ -139,6 +144,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MN_VIDEO_PLL1_REF_SEL, + imx_clk_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MN_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", @@ -155,6 +163,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll)); + clk_dm(IMX8MN_VIDEO_PLL1, + imx_clk_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll)); /* PLL bypass out */ clk_dm(IMX8MN_DRAM_PLL_BYPASS, @@ -183,6 +194,12 @@ static int imx8mn_clk_probe(struct udevice *dev) ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT)); + clk_dm(IMX8MN_VIDEO_PLL1_BYPASS, + imx_clk_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT)); + /* PLL out gate */ clk_dm(IMX8MN_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", @@ -199,6 +216,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11)); + clk_dm(IMX8MN_VIDEO_PLL1_OUT, + imx_clk_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13)); /* SYS PLL fixed output */ clk_dm(IMX8MN_SYS_PLL1_40M, @@ -275,6 +295,9 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80)); + + clk_dm(IMX8MN_CLK_DISP_PIXEL, + imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500)); clk_dm(IMX8MN_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00)); clk_dm(IMX8MN_CLK_I2C2, -- 2.40.1

3 5

[PATCH] eth: asix88179: reset during probe
by Caleb Connolly 13 Jul '24

13 Jul '24

In some cases (consistently in my case with an embedded board) the ethernet controller will time out on the first init but always succeed after reset. Let's reset the controller during probe so we always start with it in a known state, and don't have wait for the first asix_wait_link() to time out. Signed-off-by: Caleb Connolly <caleb.connolly(a)linaro.org> --- I see this behaviour consistently across three Qualcomm platforms that use this controller. --- drivers/usb/eth/asix88179.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 7bfd285b3aa4..a0aa5c25e428 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -628,8 +628,14 @@ static int ax88179_eth_probe(struct udevice *dev) usb_dev = priv->ueth.pusb_dev; priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT]; + ret = asix_basic_reset(&priv->ueth, priv); + if (ret) { + printf("Failed to reset ethernet device\n"); + return ret; + } + /* Get the MAC address */ ret = asix_read_mac(&priv->ueth, pdata->enetaddr); if (ret) return ret; -- 2.45.0

3 5

[RESEND PATCH v2 0/5] net: dwc_eth_qos: Add glue driver for Intel MAC
by Philip Oberfichtner 13 Jul '24

13 Jul '24

This patch series implements the dwc_eth_qos glue driver for Intel SOCs. Before doing that, a few general adaptions to the dwc_eth_qos.c main driver are required. Most notably, the preparation for PCI based driver instances, which do not necessarily use a device tree. This patch series depends on: "net: dwc_eth_qos: mdio: Implement clause 45": https://patchwork.ozlabs.org/project/uboot/patch/20240507094237.168238-1-pr… Changes in V2: Improve coding-style in PATCH 5/5 Philip Oberfichtner (5): x86: provide mb() macro net: dwc_eth_qos: Fix header to be self-contained net: dwc_eth_qos: Adapt probe() for PCI devices net: dwc_eth_qos: Implement bind() for PCI devices net: dwc_eth_qos: Add glue driver for Intel MAC arch/x86/include/asm/io.h | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 44 ++- drivers/net/dwc_eth_qos.h | 8 +- drivers/net/dwc_eth_qos_imx.c | 1 + drivers/net/dwc_eth_qos_intel.c | 446 +++++++++++++++++++++++++++++ drivers/net/dwc_eth_qos_intel.h | 58 ++++ drivers/net/dwc_eth_qos_qcom.c | 1 + drivers/net/dwc_eth_qos_rockchip.c | 1 + drivers/net/dwc_eth_qos_starfive.c | 1 + drivers/net/dwc_eth_qos_stm32.c | 1 + include/pci_ids.h | 9 + 13 files changed, 575 insertions(+), 4 deletions(-) create mode 100644 drivers/net/dwc_eth_qos_intel.c create mode 100644 drivers/net/dwc_eth_qos_intel.h -- 2.39.2

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[PATCH 0/6] Add Turris 1.x board
by Marek Mojík 13 Jul '24

13 Jul '24

Hello all, this is a continuation of previous work by Pali to add support for the Turris 1.x board. As the patches were based on u-boot v2022.04, a nontrivial rebasing was needed. Some notes: - Some options that are in SD defconfig are disabled in NOR defconfig because over the years u-boot grew and the old NOR defconfig will not fit into NOR memory. - SD boot with RAM larger than 2GB will only allocate 2GB of RAM (We were not able to fix this yet) Marek Mojík (2): powerpc: mpc85xx: use CONFIG_VAL() for SYS_MONITOR_BASE in start.s powerpc: use CONFIG_IS_ENABLED() when checking for DM_SERIAL in include/asm/config.h This contributor prefers not to receive mails (4): board_f: Add support for CONFIG_OF_BOARD_FIXUP for XIP images board: freescale: p1_p2_rdb_pc: Add weak function p1_p2_rdb_pc_fix_fdt_model() for fixing DT model string powerpc: mpc8xxx: Extend find_law() to find_law_by_addr_id() powerpc: Add support for CZ.NIC Turris 1.x routers arch/powerpc/cpu/mpc85xx/Kconfig | 7 + arch/powerpc/cpu/mpc85xx/start.S | 2 +- arch/powerpc/cpu/mpc8xxx/law.c | 5 +- arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/turris1x-u-boot.dtsi | 17 + arch/powerpc/dts/turris1x.dts | 511 ++++++++++++++++++ arch/powerpc/include/asm/config.h | 2 +- arch/powerpc/include/asm/fsl_law.h | 8 +- board/CZ.NIC/turris_1x/Kconfig | 155 ++++++ board/CZ.NIC/turris_1x/MAINTAINERS | 13 + board/CZ.NIC/turris_1x/Makefile | 15 + board/CZ.NIC/turris_1x/ddr.c | 28 + board/CZ.NIC/turris_1x/law.c | 13 + board/CZ.NIC/turris_1x/tlb.c | 143 +++++ board/CZ.NIC/turris_1x/turris_1x.c | 571 ++++++++++++++++++++ board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +- boot/Kconfig | 2 +- common/board_f.c | 8 +- configs/turris_1x_nor_defconfig | 87 +++ configs/turris_1x_sdcard_defconfig | 106 ++++ dts/Kconfig | 6 + include/configs/turris_1x.h | 335 ++++++++++++ 22 files changed, 2041 insertions(+), 7 deletions(-) create mode 100644 arch/powerpc/dts/turris1x-u-boot.dtsi create mode 100644 arch/powerpc/dts/turris1x.dts create mode 100644 board/CZ.NIC/turris_1x/Kconfig create mode 100644 board/CZ.NIC/turris_1x/MAINTAINERS create mode 100644 board/CZ.NIC/turris_1x/Makefile create mode 100644 board/CZ.NIC/turris_1x/ddr.c create mode 100644 board/CZ.NIC/turris_1x/law.c create mode 100644 board/CZ.NIC/turris_1x/tlb.c create mode 100644 board/CZ.NIC/turris_1x/turris_1x.c create mode 100644 configs/turris_1x_nor_defconfig create mode 100644 configs/turris_1x_sdcard_defconfig create mode 100644 include/configs/turris_1x.h -- 2.45.1

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