December 2024 - U-Boot

[PATCH v2 0/6] ufs: core: initial cleanup and defines sync with Linux v6.12
by Neil Armstrong 30 Dec '24

30 Dec '24

This serie fixes the build and checkpatch warnings, and does a split of the ufs.h into a separate ufshci.h which helps syndhronizing the defines from Linux v6.12. No functional changes intended, tests on hardware are welcome. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Changes in v2: - Colect tested & review tags - drop EXPORT SYMBOL of ufshcd_map_desc_id_to_length in patch 2 - Link to v1: https://lore.kernel.org/r/20241120-topic-ufs-cleanup-v1-0-a5cef54b1cdc@lina… --- Neil Armstrong (6): ufs: core: include missing include/ufs.h ufs: core: mark unexported functions as static ufs: core: cosmetic fixups ufs: core: move ufshci defines in a separate header ufs: core: sync unipro.h with Linux v6.12 ufs: core: sync ufshci.h with Linux v6.12 drivers/ufs/ufs.c | 44 +++-- drivers/ufs/ufs.h | 335 +----------------------------------- drivers/ufs/ufshci.h | 469 +++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/ufs/unipro.h | 128 ++++++++------ 4 files changed, 571 insertions(+), 405 deletions(-) --- base-commit: d580a013cca67a8115fb88d260498bde181709a1 change-id: 20241120-topic-ufs-cleanup-23671e3fc9e9 Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

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[PATCH] board: odroid-n2: Add script and update docs for signing
by Baltazár Radics 30 Dec '24

30 Dec '24

The previous instructions resulted in a bootloader that wouldn't fit in an mbr gap. I have updated the docs based on upstream's build process. Note that the script should be compatible with other g12 based odroid boards, but I'm unable to test those boards. Signed-off-by: Baltazár Radics <baltazar.radics(a)gmail.com> --- doc/board/amlogic/odroid-n2.rst | 71 ++------------------------------- tools/amlogic-odroidg12-sign.sh | 67 +++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+), 68 deletions(-) create mode 100755 tools/amlogic-odroidg12-sign.sh diff --git a/doc/board/amlogic/odroid-n2.rst b/doc/board/amlogic/odroid-n2.rst index 883720f8fb..f81e8222f8 100644 --- a/doc/board/amlogic/odroid-n2.rst +++ b/doc/board/amlogic/odroid-n2.rst @@ -54,10 +54,9 @@ image so it is necessary to obtain binaries from sources published by the board $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - $ DIR=odroid-n2 - $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 $DIR + $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 odroidg12 - $ cd odroid-n2 + $ cd odroidg12 $ make odroidn2_defconfig $ make $ export UBOOTDIR=$PWD @@ -66,71 +65,7 @@ Go back to the mainline U-Boot source tree then: .. code-block:: bash - $ mkdir fip - - $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/… -O fip/blx_fix.sh - $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - $ cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/ - $ cp $UBOOTDIR/fip/g12b/bl2.bin fip/ - $ cp $UBOOTDIR/fip/g12b/bl30.bin fip/ - $ cp $UBOOTDIR/fip/g12b/bl31.img fip/ - $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ - $ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ - $ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ - $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ - $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ - $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ - $ cp $UBOOTDIR/fip/g12b/piei.fw fip/ - $ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ - $ cp u-boot.bin fip/bl33.bin - - $ sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - $ sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --level v3 + $ ./tools/amlogic-odroidg12-sign.sh "$UBOOTDIR" Then write U-Boot to SD or eMMC with: diff --git a/tools/amlogic-odroidg12-sign.sh b/tools/amlogic-odroidg12-sign.sh new file mode 100755 index 0000000000..30a81e0374 --- /dev/null +++ b/tools/amlogic-odroidg12-sign.sh @@ -0,0 +1,67 @@ +#!/bin/sh -e +# SPDX-License-Identifier: GPL-2.0+ + +error() { + echo "$@" >&2 + exit 1 +} + +[ $# -lt 1 ] && error "usage: $0 <built u-boot odroidg12> [out dir] [binary]" + +src=$1 # hardkernel's u-boot tree (built) +out=${2:-fip} +bl33=${3:-u-boot.bin} + +. "$src/build/include/config/auto.conf" +SOC=$CONFIG_SYS_SOC +BOARDDIR=board/$CONFIG_SYS_VENDOR/$CONFIG_SYS_BOARD +[ "$CONFIG_ODROID_N2L" = y ] && ddr='lp' + +fix_blx() { + [ "$(wc -c <"$1")" -gt "$2" ] && error "Error: $1 too big." + [ "$(wc -c <"$3")" -gt "$4" ] && error "Error: $2 too big." + + cat "$1" /dev/zero | head -c "$2" + cat "$3" /dev/zero | head -c "$4" +} + +encrypt_step() { + "$src/fip/$SOC/aml_encrypt_$SOC" "$@" +} + +mkdir -p "$out" + +fix_blx \ + "$src/fip/$SOC/bl30.bin" 40960 \ + "$src/build/scp_task/bl301.bin" 13312 \ + >"$out/bl30_new.bin" +fix_blx \ + "$src/fip/$SOC/bl2.bin" 57344 \ + "$src/build/$BOARDDIR/firmware/acs.bin" 4096 \ + >"$out/bl2_new.bin" + +encrypt_step --bl30sig --level v3 \ + --input "$out/bl30_new.bin" \ + --output "$out/bl30_new.bin.g12.enc" +encrypt_step --bl3sig --level v3 --type bl30 \ + --input "$out/bl30_new.bin.g12.enc" \ + --output "$out/bl30_new.bin.enc" +encrypt_step --bl3sig --level v3 --type bl31 \ + --input "$src/fip/$SOC/bl31.img" \ + --output "$out/bl31.img.enc" +encrypt_step --bl3sig --level v3 --type bl33 --compress lz4 \ + --input "$bl33" \ + --output "$out/bl33.bin.enc" +encrypt_step --bl2sig \ + --input "$out/bl2_new.bin" \ + --output "$out/bl2.n.bin.sig" +encrypt_step --bootmk --level v3 \ + --bl2 "$out/bl2.n.bin.sig" \ + --bl30 "$out/bl30_new.bin.enc" \ + --bl31 "$out/bl31.img.enc" \ + --bl33 "$out/bl33.bin.enc" \ + --ddrfw1 "$src/fip/$SOC/${ddr}ddr4_1d.fw" \ + --ddrfw2 "$src/fip/$SOC/${ddr}ddr4_2d.fw" \ + --ddrfw4 "$src/fip/$SOC/piei.fw" \ + --ddrfw8 "$src/fip/$SOC/aml_ddr.fw" \ + --output "$out/u-boot.bin" -- 2.47.1

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[PATCH v5] mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled
by Venkatesh Yadav Abbarapu 30 Dec '24

30 Dec '24

Update the spi_nor_read() function based on the config SPI_FLASH_BAR and update the length and bank calculation by spliting the memory of 16MB size banks only when the address width is 3byte. Fix the read issue for 4byte address width by passing the entire length to the read function. Also update the size when the configuration is stacked. Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- Changes in v2: - Update the nor read for parallel configuration and for other case keep the code as is. - Fixed the commit description. - Tested the changes with s25fl128s flash Zynq> sf probe 0 0 0 SF: Detected s25fl128s with page size 256 Bytes, erase size 64 KiB, total 16 MiB Zynq> time sf erase 0x0 0x1000000;mw.b 0x8000 aabbccdd 0x1000000;time Zynq> sf write 0x8000 0x0 0x1000000;mw.b 0x8008000 0x0 0x1000000;time Zynq> sf read 0x8008000 0x0 0x1000000;cmp.b 0x8000 0x8008000 0x1000000 SF: 16777216 bytes @ 0x0 Erased: OK time: 32.464 seconds device 0 whole chip SF: 16777216 bytes @ 0x0 Written: OK time: 15.515 seconds device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK time: 1.557 seconds Total of 16777216 byte(s) were the same Changes in v3: - Compile out the parallel code in spi_nor_erase() if the SPI_STACKED_PARALLEL is enabled. Changes in v4: - Update the bank calculation only when SPL_FLASH_BAR is enabled. Changes in v5: - Update the parallel code in the spi_nor_read() only if the SPI_STACKED_PARALLEL config is enabled. --- drivers/mtd/spi/spi-nor-core.c | 76 ++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 30 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ec841fb13bd..2e41cf74430 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1130,17 +1130,19 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) goto erase_err; } offset = addr; - if (nor->flags & SNOR_F_HAS_PARALLEL) - offset /= 2; - - if (nor->flags & SNOR_F_HAS_STACKED) { - if (offset >= (mtd->size / 2)) - nor->spi->flags |= SPI_XFER_U_PAGE; - else - nor->spi->flags &= ~SPI_XFER_U_PAGE; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + + if (nor->flags & SNOR_F_HAS_STACKED) { + if (offset >= (mtd->size / 2)) + nor->spi->flags |= SPI_XFER_U_PAGE; + else + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } } #ifdef CONFIG_SPI_FLASH_BAR - ret = write_bar(nor, addr); + ret = write_bar(nor, offset); if (ret < 0) goto erase_err; #endif @@ -1152,7 +1154,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { ret = spi_nor_erase_chip(nor); } else { - ret = spi_nor_erase_sector(nor, addr); + ret = spi_nor_erase_sector(nor, offset); } if (ret < 0) goto erase_err; @@ -1576,11 +1578,12 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - int ret; loff_t offset = from; - u32 read_len = 0; u32 rem_bank_len = 0; + u32 stack_shift = 0; + size_t read_len; u8 bank; + int ret; bool is_ofst_odd = false; dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); @@ -1593,35 +1596,48 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } while (len) { - bank = (u32)from / SZ_16M; - if (nor->flags & SNOR_F_HAS_PARALLEL) - bank /= 2; - - rem_bank_len = SZ_16M * (bank + 1); - if (nor->flags & SNOR_F_HAS_PARALLEL) - rem_bank_len *= 2; - rem_bank_len -= from; - + read_len = len; offset = from; - if (nor->flags & SNOR_F_HAS_STACKED) { - if (offset >= (mtd->size / 2)) { - offset = offset - (mtd->size / 2); - nor->spi->flags |= SPI_XFER_U_PAGE; - } else { - nor->spi->flags &= ~SPI_XFER_U_PAGE; + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) { + bank = (u32)from / SZ_16M; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + bank /= 2; + } + rem_bank_len = SZ_16M * (bank + 1); + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + rem_bank_len *= 2; } + rem_bank_len -= from; } - if (nor->flags & SNOR_F_HAS_PARALLEL) - offset /= 2; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_STACKED) { + stack_shift = 1; + if (offset >= (mtd->size / 2)) { + offset = offset - (mtd->size / 2); + nor->spi->flags |= SPI_XFER_U_PAGE; + } else { + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + } + } + + if (nor->addr_width == 4) + rem_bank_len = (mtd->size >> stack_shift) - offset; + + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + } #ifdef CONFIG_SPI_FLASH_BAR ret = write_bar(nor, offset); if (ret < 0) return log_ret(ret); #endif - if (len < rem_bank_len) read_len = len; else -- 2.34.1

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iMX8MN: SPL not starting U-Boot
by Ayrton Leyssens 30 Dec '24

30 Dec '24

Hi I am having troubles booting an iMX8M Nano board. I compiled U-Boot and flashed it to an SD-card using Buildroot. The board starts my SPL, does the DRAM init, goes back to BOOTROM and eventually goes to the SPL stage where it should jump to U-Boot (common/spl/spl.c - board_init_r os == IH_OS_U_BOOT). It proceeds to 'spl_board_prepare_for_boot();' and finally to 'jump_to_image_no_args(&spl_image);' After which nothing happens. I added some print statements to see the contents at the address it wants to jump to (0x960000). The contents of my BL31.bin are showed on that address, is that correct? Any help would be appreciated. Ayrton Leyssens Embedded Software Engineer

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[PATCH] net: phy: Add RGMII RX/TX delay handling to DP83822 PHY
by Marek Vasut 29 Dec '24

29 Dec '24

The TI DP83822 does have support for configurable RGMII RX/TX clock shift, add support for parsing DT properties which describe the RX/TX clock shift configuration and configuration of the matching bits in RCSR register. The shift is only configurable on DP83822, the other PHYs supported by this PHY driver, namely DP83825/DP83826 variants, do not implement this functionality and the RCSR bits used to configure the clock shift are missing from those PHYs. The shift is configurable separately for RX and TX path. Each path can either enable the shift or disable the shift using single bit. In case the shift is disabled, a delay of 0ns is added to the path, otherwise a delay of 3.5ns is added to the path. Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12 enables RX internal shift when SET, while RCSR bit 11 enables TX shift when UNSET. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/net/phy/ti_phy_init.c | 48 ++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c index a0878193ac0..850c0cbec96 100644 --- a/drivers/net/phy/ti_phy_init.c +++ b/drivers/net/phy/ti_phy_init.c @@ -10,12 +10,58 @@ #include <phy.h> #include "ti_phy_init.h" +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_RCSR 0x17 + +/* RCSR bits */ +#define DP83822_RX_CLK_SHIFT BIT(12) +#define DP83822_TX_CLK_SHIFT BIT(11) + +/* DP83822 specific RGMII RX/TX delay configuration. */ +static int dp83822_config(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 rgmii_delay = 0; + u32 rx_delay = 0; + u32 tx_delay = 0; + int ret; + + ret = ofnode_read_u32(node, "rx-internal-delay-ps", &rx_delay); + if (ret) { + rx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID; + } + + ret = ofnode_read_u32(node, "tx-internal-delay-ps", &tx_delay); + if (ret) { + tx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID; + } + + /* Bit set means Receive path internal clock shift is ENABLED */ + if (rx_delay) + rgmii_delay |= DP83822_RX_CLK_SHIFT; + + /* Bit set means Transmit path internal clock shift is DISABLED */ + if (!tx_delay) + rgmii_delay |= DP83822_TX_CLK_SHIFT; + + ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, + rgmii_delay); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + U_BOOT_PHY_DRIVER(dp83822) = { .name = "TI DP83822", .uid = 0x2000a240, .mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, - .config = &genphy_config_aneg, + .config = &dp83822_config, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; -- 2.45.2

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[PATCH v15 00/11] net: tcp: improve tcp support in legacy stack
by Mikhail Kshevetskiy 28 Dec '24

28 Dec '24

Legacy TCP stack is bad. Here are some of the known issues: * tcp packet from other connection can break a current one * tcp send sequence always starts from zero * bad tcp options processing * strange assumptions on packet size for selective acknowledge * tcp interface assumes one of the two scenarios: - data downloading from remote host to a board - request-response exchange with a small packets so it's not possible to upload large amount of data from the board to remote host. * wget test generate bad tcp stream, test should fail but it passes instead This series of patches fixes all of the above issues. The benefits: * A lot of bug was fixed * Better and more reliable TCP state machine * Tcp clients becomes smaller/simpler * Data uploading was fixed (now it's possible to transmit a huge amount of data from the board to remote host) Modification was verified with * firmware downloading via u-boot wget command * fastboot over tcp * netcat linux client using test netcat implementation (not included to this patch series) * Firefox/Chrome/Edge using test web-server implementation (not included to this patch series) Changes v2: * cover letter was added * some patches were removed Changes v3: * better cover letter Changes v4: * fix bug in debug output * add more comments * code style fixes Changes v5: * old patches were occasionally sent with v4 * add back web-server patches * fix bug in debug output * add more comments * code style fixes Changes v6: * fix the wget test * improve description of "simplify tcp header filling code" patch Changes v7: * fix include ordering * improve option descriptions * fix a lot of extra brackets and comparisons against NULL / 0 * add empty lines before final returns * fixed a bug with zero size httpd uploads Changes v8: * [tcp] add function to restart rx inactivity timeout. This may help in the cases where remote peer waits for u-boot data, but u-boot is busy with long executing action * [httpd] add function returning underlying tcp stream from request id. This (with the above change) allows avoid connection break for the long processing post requests. Changes v9: * rebase all changes on top of origin/next * update test/cmd/wget patch description (bad tcp ack/seq issue was already fixed in origin/next) * tcp: add rx/tx packet counters to a tcp_stream structure * wget: use tcp rx packet counter instead of own one * netcat: use tcp rx/tx packet counters instead of own one Changes v10: * netcat: fix bug appeared after rx/tx packet counter addition * rebased on top of v2024.10 Changes v11: * fix spelling in cover letter Changes v12: * rebase on top of master branch (3df6145db0e) * slightly change tcp->rx() & tcp->tx() callback declarations, this allow us to terminate a connection if something goes wrong in rx/tx paths. * set net_boot_file_size variable in httpd_upload * set filesize env variable to a proper value netcat and httpd_upload Changes v13: * rebase on top of master branch (8573ea41058) * remove netcat support * remove example httpd server implementation Changes v14: * fix issues found by github CI Changes v15: * Rebase on top of next branch (5947cd76acd) * Add support of HTTP HEAD request to wget command. Thus it should work the same way as original wget from the next branch. Seems this is needed for efi http booting. * Parse HTTP status line in wget the same way as implemented in original wget from the next branch. Seems this is needed for efi http booting. * Fix bogus server response with an actual response from the HTTP server in test/cmd/wget. This makes a test more correct and beautifull. * Some debug messages were improved * Minor patches clenup Mikhail Kshevetskiy (11): net/tcp: fix TCP options processing net/tcp: fix selective acknowledge net/tcp: put connection specific data into a tcp_stream structure net/tcp: add connection info to tcp_stream structure net/tcp: rename ack_edge and seq_init to more common rcv_nxt and irs net/tcp: improve tcp framework, use better state machine test/cmd/wget: fix the test test/cmd/wget: replace bogus response with an actual response from the HTTP server net/tcp: simplify tcp header filling code net/tcp: define a fallback value for rcv_wnd size net/net: fix include ordering arch/sandbox/include/asm/eth.h | 4 + include/net-legacy.h | 5 +- include/net/tcp.h | 257 ++++++- include/net/wget.h | 8 - net/fastboot_tcp.c | 193 ++--- net/net.c | 45 +- net/tcp.c | 1297 ++++++++++++++++++++++---------- net/wget.c | 551 +++++--------- test/cmd/wget.c | 81 +- 9 files changed, 1504 insertions(+), 937 deletions(-) -- 2.45.2

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[PATCH v4 00/19] vbe: Series part E
by Simon Glass 28 Dec '24

28 Dec '24

This includes various patches towards implementing the VBE abrec bootmeth in U-Boot. It mostly focuses on SPL tweaks and adjusting what fatures are available in VPL. Changes in v4: - Add an option to avoid code bloat with rcar3_salvator-x for example Changes in v3: - Add new patch to avoid size growth in spl_mmc_find_device() debug - Use strlcpy() instead of strncpy() - Rebase to master Changes in v2: - Add field names into the message - Fix 'depends on SPL' to depend on TPL - Depend on TPL/VPL as well - Drop patch 'serial: ns16550: Allow clocks to be missing' Simon Glass (19): spl: mmc: Avoid size growth in spl_mmc_find_device() debug image: Add a prototype for fit_image_get_phase() boot: Allow FIT to fall back from best-match option bootstd: Avoid sprintf() in SPL when creating bootdevs boot: Respect the load_op in fit_image_load() malloc: Show amount of used space when memory runs out malloc: Provide a simple malloc for VPL Support setting a maximum size for the VPL image spl: Report a loader failure spl: Allow serial to be disabled in any XPL phase spl: Support a relocated stack in any XPL phase spl: Drop use of uintptr_t spl: Drop a duplicate variable in boot_from_devices() spl: Add some more debugging to load_simple_fit() spl: lib: Allow for decompression in any SPL build boot: Allow use of FIT in TPL and VPL lib: Allow crc8 in TPL and VPL boot: Imply CRC8 with VBE hash: Plumb crc8 into the hash functions boot/Kconfig | 71 ++++++++++++++++++++++++++++++++++- boot/bootdev-uclass.c | 10 ++++- boot/image-fit.c | 29 ++++++++------ common/Kconfig | 8 ++++ common/hash.c | 8 ++++ common/malloc_simple.c | 3 +- common/spl/Kconfig.vpl | 17 +++++++++ common/spl/spl.c | 15 +++++--- common/spl/spl_atf.c | 36 +++++++++--------- common/spl/spl_fit.c | 12 +++++- common/spl/spl_legacy.c | 8 ++-- common/spl/spl_mmc.c | 6 ++- configs/sandbox_vpl_defconfig | 2 + include/image.h | 16 +++++++- include/spl.h | 28 +++++++------- include/u-boot/crc.h | 3 ++ lib/Kconfig | 53 ++++++++++++++++++++++++++ lib/Makefile | 12 +++--- lib/crc8.c | 6 +++ 19 files changed, 275 insertions(+), 68 deletions(-) -- 2.34.1

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[PATCH] board: gateworks: venice: rename GW7905 to GW7500
by Tim Harvey 28 Dec '24

28 Dec '24

The GW7905 was renamed to GW7500 before release. Change the various names in the dt files and references. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- ...w7905-0x-u-boot.dtsi => imx8mm-venice-gw75xx-0x-u-boot.dtsi} | 0 ...w7905-2x-u-boot.dtsi => imx8mp-venice-gw75xx-2x-u-boot.dtsi} | 0 board/gateworks/venice/spl.c | 2 +- 3 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/dts/{imx8mm-venice-gw7905-0x-u-boot.dtsi => imx8mm-venice-gw75xx-0x-u-boot.dtsi} (100%) rename arch/arm/dts/{imx8mp-venice-gw7905-2x-u-boot.dtsi => imx8mp-venice-gw75xx-2x-u-boot.dtsi} (100%) diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw75xx-0x-u-boot.dtsi similarity index 100% rename from arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi rename to arch/arm/dts/imx8mm-venice-gw75xx-0x-u-boot.dtsi diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw75xx-2x-u-boot.dtsi similarity index 100% rename from arch/arm/dts/imx8mp-venice-gw7905-2x-u-boot.dtsi rename to arch/arm/dts/imx8mp-venice-gw75xx-2x-u-boot.dtsi diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index fe538ec58332..275f9d3453ea 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -80,7 +80,7 @@ static int power_init_board(const char *model, struct udevice *gsc) if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || (!strncmp(model, "GW73", 4)) || - (!strncmp(model, "GW7905", 6))) { + (!strncmp(model, "GW75", 4))) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); -- 2.25.1

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DT subtree sync for v6.12
by Sumit Garg 27 Dec '24

27 Dec '24

Hi Tom, Do you plan to perform DT subtree sync for v6.12 which seems to be due for some time now? -Sumit

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[PATCH 4/4] board: vexpress64: enable bloblist for SPL handoff
by Harrison Mutai 27 Dec '24

27 Dec '24

Enable bloblist on vexpress64 platforms to facilitate information passing from TF-A using the firmware handoff framework. Signed-off-by: Harrison Mutai <harrison.mutai(a)arm.com> --- board/armltd/vexpress64/Makefile | 3 ++- board/armltd/vexpress64/vexpress64.c | 4 ++++ configs/vexpress_fvp_bloblist_defconfig | 5 +++++ doc/board/armltd/vexpress64.rst | 16 ++++++++++++++++ 4 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 configs/vexpress_fvp_bloblist_defconfig diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile index 1878fbed4e..4729787c5e 100644 --- a/board/armltd/vexpress64/Makefile +++ b/board/armltd/vexpress64/Makefile @@ -3,5 +3,6 @@ # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -obj-y := vexpress64.o lowlevel_init.o +obj-y := vexpress64.o +obj-$(CONFIG_OF_HAS_PRIOR_STAGE) := lowlevel_init.o obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 0119f54f0d..f8bd5fbcf8 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -100,7 +100,9 @@ int dram_init_banksize(void) * Push the variable into the .data section so that it * does not get cleared later. */ +#ifdef CONFIG_OF_HAS_PRIOR_STAGE unsigned long __section(".data") prior_stage_fdt_address[2]; +#endif #ifdef CONFIG_OF_BOARD @@ -151,6 +153,7 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname) } #endif +#ifdef CONFIG_OF_HAS_PRIOR_STAGE /* * Filter for a valid DTB, as TF-A happens to provide a pointer to some * data structure using the DTB format, which we cannot use. @@ -206,6 +209,7 @@ void *board_fdt_blob_setup(int *err) return NULL; } #endif +#endif /* Actual reset is done via PSCI. */ void reset_cpu(void) diff --git a/configs/vexpress_fvp_bloblist_defconfig b/configs/vexpress_fvp_bloblist_defconfig new file mode 100644 index 0000000000..dcc87db872 --- /dev/null +++ b/configs/vexpress_fvp_bloblist_defconfig @@ -0,0 +1,5 @@ +#include <configs/vexpress_fvp_defconfig> + +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_PASSAGE=y +CONFIG_BLOBLIST_SIZE_RELOC=0x10000 diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst index a7f771d266..4dadadb53d 100644 --- a/doc/board/armltd/vexpress64.rst +++ b/doc/board/armltd/vexpress64.rst @@ -43,6 +43,22 @@ Juno is an Arm development board with the following features: More details can be found in the board documentation [3]_. +Bloblist Support +---------------- + +The ``vexpress_fvp_bloblist_defconfig`` configures U-Boot to be compiled for +Vexpress64 with Bloblist as the primary method for information handoff between +boot stages. U-Boot offers three methods to set up a bloblist: using a +predefined bloblist at a specified address, dynamically allocating memory for a +bloblist, or utilizing a standard passage-provided bloblist with automatic size +detection. + +By default, ``vexpress_fvp_bloblist_defconfig`` uses the standard passage method +(CONFIG_BLOBLIST_PASSAGE) because TF-A provides a Transfer List in non-secure +memory that U-Boot can utilise. This Bloblist, which is referred to as a Transfer List in +TF-A, contains all necessary data for the handoff process, including DT and ACPI +tables. + References ---------- -- 2.46.2

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