December 2024 - U-Boot

[PATCH v1 1/2] net: phy: Add driver for Motorcomm YT8531S Gigabit ethernet phy
by Frank Sae 01 Jan '25

01 Jan '25

Add driver for Motorcomm YT8531S Gigabit ethernet phy. Signed-off-by: Frank Sae <Frank.Sae(a)motor-comm.com> --- drivers/net/phy/motorcomm.c | 96 ++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 4d67203ee7..a1d5eac7bf 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Motorcomm 8531 PHY driver. + * Motorcomm YT8511/YT8531/YT8531S/YT8821 PHY driver. * - * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Copyright (C) 2024 Motorcomm Electronic Technology Co., Ltd. */ #include <config.h> @@ -13,6 +13,7 @@ #define PHY_ID_YT8511 0x0000010a #define PHY_ID_YT8531 0x4f51e91b #define PHY_ID_YT8821 0x4f51ea19 +#define PHY_ID_YT8531S 0x4f51e91a #define PHY_ID_MASK GENMASK(31, 0) /* Extended Register's Address Offset Register */ @@ -1114,6 +1115,86 @@ static int yt8821_startup(struct phy_device *phydev) return 0; } +static int yt8531s_config(struct phy_device *phydev) +{ + struct ytphy_plat_priv *priv = phydev->priv; + u16 mask, val; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + ytphy_dt_parse(phydev); + switch (priv->clk_out_frequency) { + case YTPHY_DTS_OUTPUT_CLK_DIS: + mask = YT8531_SCR_SYNCE_ENABLE; + val = 0; + break; + case YTPHY_DTS_OUTPUT_CLK_25M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_REF_25M); + break; + case YTPHY_DTS_OUTPUT_CLK_125M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_PLL_125M); + break; + default: + pr_warn("Freq err:%u\n", priv->clk_out_frequency); + return -EINVAL; + } + + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, + val); + if (ret < 0) + return ret; + + ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + return ret; + + if (priv->flag & AUTO_SLEEP_DISABLED) { + /* disable auto sleep */ + ret = ytphy_modify_ext(phydev, + YT8531_EXTREG_SLEEP_CONTROL1_REG, + YT8531_ESC1R_SLEEP_SW, 0); + if (ret < 0) + return ret; + } + + if (priv->flag & KEEP_PLL_ENABLED) { + /* enable RXC clock when no wire plug */ + ret = ytphy_modify_ext(phydev, + YT8531_CLOCK_GATING_REG, + YT8531_CGR_RX_CLK_EN, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int yt8531s_startup(struct phy_device *phydev) +{ + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + ret = yt8531_parse_status(phydev); + if (ret) + return ret; + + return 0; +} + U_BOOT_PHY_DRIVER(motorcomm8511) = { .name = "YT8511 Gigabit Ethernet", .uid = PHY_ID_YT8511, @@ -1145,3 +1226,14 @@ U_BOOT_PHY_DRIVER(motorcomm8821) = { .startup = &yt8821_startup, .shutdown = &genphy_shutdown, }; + +U_BOOT_PHY_DRIVER(motorcomm8531S) = { + .name = "YT8531S Gigabit Ethernet Transceiver", + .uid = PHY_ID_YT8531S, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .probe = &yt8531_probe, + .config = &yt8531s_config, + .startup = &yt8531s_startup, + .shutdown = &genphy_shutdown, +}; -- 2.34.1

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[PATCH 1/1] net: correct the description of ip_to_string()
by Heinrich Schuchardt 01 Jan '25

01 Jan '25

The output of ip_to_string() is a string. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- include/net-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net-common.h b/include/net-common.h index b7a519e36db..ed3d0a4a185 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -427,7 +427,7 @@ void string_to_enetaddr(const char *addr, uint8_t *enetaddr); struct in_addr string_to_ip(const char *s); /** - * ip_to_string() - Convert a string to ip address + * ip_to_string() - Convert an IPv4 address to a string * * Implemented in lib/net_utils.c (built unconditionally) * -- 2.45.2

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[PATCH] Bitbanging MDIO driver for DM framework.
by Tom Rini 01 Jan '25

01 Jan '25

From: Markus Gothe <markus.gothe(a)genexis.eu> Linux DTS compatible MDIO bitbanging driver. Both clause 22 and clause 45 MDIO supported and validated. Heavily based on the Linux drivers (more or less the same code base). Signed-off-by: Markus Gothe <markus.gothe(a)genexis.eu> --- drivers/net/Kconfig | 6 + drivers/net/Makefile | 1 + drivers/net/mdio_gpio.c | 313 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 320 insertions(+) create mode 100644 drivers/net/mdio_gpio.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 576cd2d50ad9..5e862158c566 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1007,6 +1007,12 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config MDIO_GPIO_BITBANG + bool "GPIO bitbanging MDIO driver" + depends on DM_MDIO && DM_GPIO + help + Driver for bitbanging MDIO + config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" depends on DM_MDIO_MUX && DM_I2C diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f5ab1f5dedf6..e51a917933eb 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o +obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o diff --git a/drivers/net/mdio_gpio.c b/drivers/net/mdio_gpio.c new file mode 100644 index 000000000000..a2a41f95190c --- /dev/null +++ b/drivers/net/mdio_gpio.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPIO based MDIO bitbang driver. + * + * Copyright 2024 Markus Gothe <markus.gothe(a)genexis.eu> + * + * This file is based on the Linux kernel drivers drivers/net/phy/mdio-gpio.c + * and drivers/net/phy/mdio-bitbang.c which have the following copyrights: + * + * Copyright (c) 2008 CSE Semaphore Belgium. + * by Laurent Pinchart <laurentp(a)cse-semaphore.com> + * + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas(a)teltonika.lt> + * + * Author: Scott Wood <scottwood(a)freescale.com> + * Copyright (c) 2007 Freescale Semiconductor + * + * Copyright (c) 2003 Intracom S.A. + * by Pantelis Antoniou <panto(a)intracom.gr> + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug(a)ru.mvista.com> + */ + +#include <dm.h> +#include <log.h> +#include <miiphy.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/mdio.h> + +#define MDIO_READ 2 +#define MDIO_WRITE 1 + +#define MDIO_C45 BIT(15) +#define MDIO_C45_ADDR (MDIO_C45 | 0) +#define MDIO_C45_READ (MDIO_C45 | 3) +#define MDIO_C45_WRITE (MDIO_C45 | 1) + +/* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY + * is done twice per period. + */ +#define MDIO_DELAY 250 + +/* The PHY may take up to 300 ns to produce data, plus some margin + * for error. + */ +#define MDIO_READ_DELAY 350 + +#define MDIO_GPIO_MDC 0 +#define MDIO_GPIO_MDIO 1 +#define MDIO_GPIO_MDO 2 + +struct mdio_gpio_priv { + struct gpio_desc mdc, mdio, mdo; +}; + +static void mdio_dir(struct udevice *mdio_dev, int dir) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) { + /* Separate output pin. Always set its value to high + * when changing direction. If direction is input, + * assume the pin serves as pull-up. If direction is + * output, the default value is high. + */ + dm_gpio_set_value(&priv->mdo, 1); + return; + } + + if (dir) + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + else + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_IN); +} + +static int mdio_get(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + return dm_gpio_get_value(&priv->mdio); +} + +static void mdio_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) + dm_gpio_set_value(&priv->mdo, what); + else + dm_gpio_set_value(&priv->mdio, what); +} + +static void mdc_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + dm_gpio_set_value(&priv->mdc, what); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_bit(struct udevice *mdio_dev, int val) +{ + mdio_set(mdio_dev, val); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 0); +} + +/* MDIO must already be configured as input. */ +static int mdio_gpio_get_bit(struct udevice *mdio_dev) +{ + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_READ_DELAY); + mdc_set(mdio_dev, 0); + + return mdio_get(mdio_dev); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_num(struct udevice *mdio_dev, u16 val, int bits) +{ + int i; + + for (i = bits - 1; i >= 0; i--) + mdio_gpio_send_bit(mdio_dev, (val >> i) & 1); +} + +/* MDIO must already be configured as input. */ +static u16 mdio_gpio_get_num(struct udevice *mdio_dev, int bits) +{ + int i; + u16 ret = 0; + + for (i = bits - 1; i >= 0; i--) { + ret <<= 1; + ret |= mdio_gpio_get_bit(mdio_dev); + } + + return ret; +} + +/* Utility to send the preamble, address, and + * register (common to read and write). + */ +static void mdio_gpio_cmd(struct udevice *mdio_dev, int op, u8 phy, u8 reg) +{ + int i; + + mdio_dir(mdio_dev, 1); + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good + * measure. The IEEE spec says this is a PHY optional + * requirement. The AMD 79C874 requires one after power up and + * one after a MII communications error. This means that we are + * doing more preambles than we need, but it is safer and will be + * much more robust. + */ + for (i = 0; i < 32; i++) + mdio_gpio_send_bit(mdio_dev, 1); + + /* + * Send the start bit (01) and the read opcode (10) or write (01). + * Clause 45 operation uses 00 for the start and 11, 10 for + * read/write. + */ + mdio_gpio_send_bit(mdio_dev, 0); + if (op & MDIO_C45) + mdio_gpio_send_bit(mdio_dev, 0); + else + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, (op >> 1) & 1); + mdio_gpio_send_bit(mdio_dev, (op >> 0) & 1); + + mdio_gpio_send_num(mdio_dev, phy, 5); + mdio_gpio_send_num(mdio_dev, reg, 5); +} + +/* + * In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the + * lower 16 bits of the 21 bit address. This transfer is done identically to a + * MDIO_WRITE except for a different code. To enable clause 45 mode or + * MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices + * can exist on the same bus. Normal devices should ignore the MDIO_ADDR + * phase. + */ +static int mdio_gpio_cmd_addr(struct udevice *mdio_dev, int phy, u32 dev_addr, u32 reg) +{ + mdio_gpio_cmd(mdio_dev, MDIO_C45_ADDR, phy, dev_addr); + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, reg, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return dev_addr; +} + +static int mdio_gpio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + int ret, i; + + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_READ, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_READ, addr, reg); + } + + mdio_dir(mdio_dev, 0); + + /* check the turnaround bit: the PHY should be driving it to zero. + */ + if (mdio_gpio_get_bit(mdio_dev) != 0) { + /* PHY didn't drive TA low -- flush any bits it + * may be trying to send. + */ + for (i = 0; i < 32; i++) + mdio_gpio_get_bit(mdio_dev); + + return 0xffff; + } + + ret = mdio_gpio_get_num(mdio_dev, 16); + mdio_gpio_get_bit(mdio_dev); + + return ret; +} + +static int mdio_gpio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_WRITE, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_WRITE, addr, reg); + } + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, val, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return 0; +} + +static const struct mdio_ops mdio_gpio_ops = { + .read = mdio_gpio_read, + .write = mdio_gpio_write, + .reset = NULL, +}; + +/* + * Name the device, we use the device tree node name. + * This can be overwritten by MDIO class code if device-name property is + * present. + */ +static int mdio_gpio_bind(struct udevice *mdio_dev) +{ + if (ofnode_valid(dev_ofnode(mdio_dev))) + device_set_name(mdio_dev, ofnode_get_name(dev_ofnode(mdio_dev))); + + return 0; +} + +static int mdio_gpio_probe(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + int ret = 0; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDC, &priv->mdc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDIO, &priv->mdio, GPIOD_IS_IN); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDO, &priv->mdo, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) + return ret; + + return 0; +} + +static const struct udevice_id mdio_gpio_ids[] = { + { .compatible = "virtual,mdio-gpio" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gpio_mdio) = { + .name = "gpio_mdio", + .id = UCLASS_MDIO, + .of_match = mdio_gpio_ids, + .bind = mdio_gpio_bind, + .probe = mdio_gpio_probe, + .ops = &mdio_gpio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), + .priv_auto = sizeof(struct mdio_gpio_priv), +}; -- 2.34.1

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[PATCH] Revert "net: phy: marvell 88e151x: Fix handling of bare RGMII interface type"
by Rufus Segar 01 Jan '25

01 Jan '25

From 2f97d889cecfa2ba06652469765f31c70a68e867 Mon Sep 17 00:00:00 2001 From: Rufus Segar <rufuss(a)carallon.com> Date: Tue, 3 Dec 2024 14:35:10 +0000 Subject: [PATCH] Revert "net: phy: marvell 88e151x: Fix handling of bare RGMII interface type" This reverts commit 431be621c6cbc72efd1d45fa36686a682cbb470a. This change is erroneous, the RX/TX delay should only be added when in RGMII-ID mode. RGMII mode should have no RX/TX delay. --- drivers/net/phy/marvell.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b0a0b7fcb3..08608a99b9 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -461,9 +461,7 @@ static int m88e151x_config(struct phy_device *phydev) reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) reg |= MIIM_88E151x_RGMII_RXTX_DELAY; else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) reg |= MIIM_88E151x_RGMII_RX_DELAY; -- 2.47.0

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[PATCH v2 0/3] Add 'trace wipe'
by Jerome Forissier 01 Jan '25

01 Jan '25

This short series adds the 'trace wipe' command which clears the trace buffer, allowing to re-start a capture from scratch. Jerome Forissier (3): trace: add support for 'trace wipe' test: test_trace.py: test 'trace wipe' trace: document 'trace wipe' cmd/trace.c | 5 ++++ doc/develop/trace.rst | 11 +++++++++ include/trace.h | 2 ++ lib/trace.c | 47 ++++++++++++++++++++++++++----------- test/py/tests/test_trace.py | 30 +++++++++++++++++++++++ 5 files changed, 81 insertions(+), 14 deletions(-) v2: - Change 'trace clear' to 'trace wipe' - Add doc patch - Minor edits to the patch descriptions v1: - Added patch: 'test: test_trace.py: test "trace clear" command' v0: - Sent as a single patch: https://lists.denx.de/pipermail/u-boot/2024-December/574148.html -- 2.43.0

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[PATCH] trace: proftool: dump-ftrace should write funcgraph times in ns not us
by Jerome Forissier 01 Jan '25

01 Jan '25

When converting a U-Boot trace records file to ftrace function graph format for use by trace-cmd ('proftool -f funcgraph dump-ftrace'), the time associated to each function is incorrectly saved in microseconds instead of nanoseconds. Multuply the value by 1000 to fix the issue. With this change, the trace-cmd output looks consistent. Here is an example with udelay(25) added to mem_malloc_init() as a test case: $ ./tools/proftool -m System.map -t /tmp/trace.bin -f funcgraph \ dump-ftrace -o /tmp/trace.dat $ trace-cmd report /tmp/trace.dat >/tmp/trace.log $ vi /tmp/trace.log [...] u-boot-1 [000] 6.719659: funcgraph_entry: | mem_malloc_init() { u-boot-1 [000] 6.719659: funcgraph_entry: | udelay() { u-boot-1 [000] 6.719660: funcgraph_entry: | schedule() { u-boot-1 [000] 6.719660: funcgraph_entry: | cyclic_run() { u-boot-1 [000] 6.719660: funcgraph_entry: 1.000 us | cyclic_get_list(); u-boot-1 [000] 6.719661: funcgraph_exit: 1.000 us | } u-boot-1 [000] 6.719661: funcgraph_exit: 1.000 us | } u-boot-1 [000] 6.719661: funcgraph_entry: | __udelay() { u-boot-1 [000] 6.719662: funcgraph_entry: 0.000 us | usec_to_tick(); u-boot-1 [000] 6.719687: funcgraph_exit: + 26.000 us | } u-boot-1 [000] 6.719687: funcgraph_exit: + 28.000 us | } u-boot-1 [000] 6.719687: funcgraph_entry: # 37971.000 us | memset(); u-boot-1 [000] 6.757658: funcgraph_exit: # 37999.000 us | } u-boot-1 [000] 6.757658: funcgraph_exit: # 38000.000 us | } In the above dump, the udelay() call is reported as taking 26 us which is consistent with the timestamps (6.719687 - 6.719659 = 0.000026). Without this patch we would have "0.026 us" instead of "+ 26.000 us". Signed-off-by: Jerome Forissier <jerome.forissier(a)linaro.org> --- tools/proftool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/proftool.c b/tools/proftool.c index c2e38099354..af2cdb6d584 100644 --- a/tools/proftool.c +++ b/tools/proftool.c @@ -1456,8 +1456,8 @@ static int write_pages(struct twriter *tw, enum out_format_t out_format, } tw->ptr += tputl(fout, 0); /* overrun */ tw->ptr += tputq(fout, 0); /* calltime */ - /* rettime */ - tw->ptr += tputq(fout, func_duration); + /* rettime (nanoseconds) */ + tw->ptr += tputq(fout, func_duration * 1000); } } -- 2.43.0

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[PATCH v2 0/4] Fix OSPI boot for J722S
by Prasanth Babu Mantena 01 Jan '25

01 Jan '25

This series fixes OSPI boot for J722S. It contains fixes for DMSC communication, R5 regmap for ospi and dma specific overrides for ospi. Test log: https://gist.github.com/PrasanthBabuMantena/ad469dd09ab7263f85f87dadda46c86d v2 <==> v1 * Add Fixes tag wherever required. * Improve commit message. Vaishnav Achath (4): mailbox: k3-sec-proxy: Add DM to DMSC communication thread for J722S arm: dts: k3-j722s-r5-evm: Fix DM2TIFS secproxy thread ID arm: mach-k3: j722_spl: Add FAST XSPI boot mode arm: dts: k3-j722s*: Add overrides specific to OSPI arch/arm/dts/k3-j722s-evm-u-boot.dtsi | 4 ++++ arch/arm/dts/k3-j722s-r5-evm.dts | 17 +++++++++++++++-- arch/arm/mach-k3/include/mach/j722s_spl.h | 1 + arch/arm/mach-k3/j722s/j722s_init.c | 2 ++ drivers/mailbox/k3-sec-proxy.c | 2 +- 5 files changed, 23 insertions(+), 3 deletions(-) -- 2.34.1

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[PATCH] arm: dts: k3-j721e-beagleboneai: Move to OF_UPSTREAM
by Udit Kumar 01 Jan '25

01 Jan '25

Move to using OF_UPSTREAM config and thus using the devicetree subtree and remove unused device tree files. Signed-off-by: Udit Kumar <u-kumar1(a)ti.com> --- Bootlog https://gist.github.com/uditkumarti/2f56822bab854cb9dcc06c69a8d1003a arch/arm/dts/Makefile | 1 - .../dts/k3-j721e-beagleboneai64-u-boot.dtsi | 4 +- arch/arm/dts/k3-j721e-beagleboneai64.dts | 993 ------------------ configs/j721e_beagleboneai64_a72_defconfig | 3 +- 4 files changed, 4 insertions(+), 997 deletions(-) delete mode 100644 arch/arm/dts/k3-j721e-beagleboneai64.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6ad59aeed5..e64725441b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1164,7 +1164,6 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \ k3-j7200-r5-common-proc-board.dtb \ k3-j721e-r5-sk.dtb \ - k3-j721e-beagleboneai64.dtb \ k3-j721e-r5-beagleboneai64.dtb dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index 27851b7d08..8cefa39290 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -206,10 +206,10 @@ #ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64 #define SPL_NODTB "spl/u-boot-spl-nodtb.bin" -#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb" +#define SPL_J721E_BBAI64_DTB "spl/dts/ti/k3-j721e-beagleboneai64.dtb" #define UBOOT_NODTB "u-boot-nodtb.bin" -#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb" +#define J721E_BBAI64_DTB "dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dtb" &binman { ti-dm { diff --git a/arch/arm/dts/k3-j721e-beagleboneai64.dts b/arch/arm/dts/k3-j721e-beagleboneai64.dts deleted file mode 100644 index 2f954729f3..0000000000 --- a/arch/arm/dts/k3-j721e-beagleboneai64.dts +++ /dev/null @@ -1,993 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * https://beagleboard.org/ai-64 - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation - * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> - -/ { - compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; - model = "BeagleBoard.org BeagleBone AI-64"; - - aliases { - serial0 = &wkup_uart0; - serial2 = &main_uart0; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - i2c0 = &wkup_i2c0; - i2c1 = &main_i2c6; - i2c2 = &main_i2c2; - i2c3 = &main_i2c4; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&sw_pwr_pins_default>; - - button-1 { - label = "BOOT"; - linux,code = <BTN_0>; - gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; - }; - - button-2 { - label = "POWER"; - linux,code = <KEY_POWER>; - gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_default>; - - led-0 { - gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_DISK_ACTIVITY; - linux,default-trigger = "mmc0"; - }; - - led-2 { - gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_CPU; - linux,default-trigger = "cpu"; - }; - - led-3 { - gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_DISK_ACTIVITY; - linux,default-trigger = "mmc1"; - }; - - led-4 { - gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_WLAN; - default-state = "off"; - }; - }; - - evm_12v0: regulator-0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: regulator-1 { - /* Output of LMS140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: regulator-2 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pwr_en_pins_default>; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vsys_3v3>; - gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv_alt: regulator-4 { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; - regulator-name = "tlv71033"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vsys_5v0>; - gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - dp_pwr_3v3: regulator-5 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_3v3_en_pins_default>; - regulator-name = "dp-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ - enable-active-high; - }; - - dp0: connector { - compatible = "dp-connector"; - label = "DP0"; - type = "full-size"; - dp-pwr-supply = <&dp_pwr_3v3>; - - port { - dp_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; -}; - -&main_pmx0 { - led_pins_default: led-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ - J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ - J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ - J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ - J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ - J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ - >; - }; - - sd_pwr_en_pins_default: sd-pwr-en-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ - >; - }; - - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ - >; - }; - - main_usbss0_pins_default: main-usbss0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ - >; - }; - - main_usbss1_pins_default: main-usbss1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ - >; - }; - - dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ - >; - }; - - dp0_pins_default: dp0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c2_pins_default: main-i2c2-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ - J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ - J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ - J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ - J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ - J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ - J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ - >; - }; - - main_i2c5_pins_default: main-i2c5-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ - J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ - >; - }; - - main_i2c6_pins_default: main-i2c6-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ - J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ - J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ - J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ - >; - }; - - csi0_gpio_pins_default: csi0-gpio-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ - J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ - >; - }; - - csi1_gpio_pins_default: csi1-gpio-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ - J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ - >; - }; - - pcie1_rst_pins_default: pcie1-rst-default-pins { - pinctrl-single,pins = < - J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ - >; - }; -}; - -&wkup_pmx0 { - eeprom_wp_pins_default: eeprom-wp-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ - >; - }; - - mcu_adc0_pins_default: mcu-adc0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ - J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ - J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ - J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ - J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ - J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ - J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ - >; - }; - - mcu_adc1_pins_default: mcu-adc1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ - >; - }; - - mikro_bus_pins_default: mikro-bus-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ - J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ - J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ - J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ - - J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ - J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ - J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ - J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ - - J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ - J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ - - J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ - J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ - J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ - J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ - J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ - >; - }; - - sw_pwr_pins_default: sw-pwr-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ - >; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ - J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ - >; - }; - - mcu_usbss1_pins_default: mcu-usbss1-default-pins { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by TIFS firmware. */ - status = "reserved"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_sdhci0 { - /* eMMC */ - status = "okay"; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD Card */ - status = "okay"; - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv_alt>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; -}; - -&main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; -}; - -&main_i2c2 { - /* BBB Header: P9.19 and P9.20 */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c2_pins_default>; - clock-frequency = <100000>; -}; - -&main_i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; -}; - -&main_i2c4 { - /* BBB Header: P9.24 and P9.26 */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c4_pins_default>; - clock-frequency = <100000>; -}; - -&main_i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default>; - clock-frequency = <400000>; -}; - -&main_i2c6 { - /* BBB Header: P9.17 and P9.18 */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c6_pins_default>; - clock-frequency = <100000>; - status = "okay"; -}; - -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&eeprom_wp_pins_default>; - }; -}; - -&wkup_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, - <&mikro_bus_pins_default>; -}; - -&main_gpio0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; -}; - -&main_gpio1 { - status = "okay"; -}; - -&usb_serdes_mux { - idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ -}; - -&serdes_ln_ctrl { - idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, - <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, - <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, - <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, - <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, - <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&serdes4 { - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&serdes_wiz4 1>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <5400>; - #phy-cells = <0>; - }; -}; - -&mhdp { - phys = <&torrent_phy_dp>; - phy-names = "dpphy"; - pinctrl-names = "default"; - pinctrl-0 = <&dp0_pins_default>; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "peripheral"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&serdes2 { - serdes2_usb_link: phy@1 { - reg = <1>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_USB3>; - resets = <&serdes_wiz2 2>; - }; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; - ti,vbus-divider; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes2_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&tscadc0 { - status = "okay"; - /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ - adc { - ti,adc-channels = <0 1 2 3 4 5 6>; - }; -}; - -&tscadc1 { - status = "okay"; - /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ - adc { - ti,adc-channels = <0>; - }; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default>; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mdio_pins_default>; - - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - - assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ - <&k3_clks 152 4>, /* VP 2 pixel clock */ - <&k3_clks 152 9>, /* VP 3 pixel clock */ - <&k3_clks 152 13>; /* VP 4 pixel clock */ - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* PLL19_HSDIV0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* PLL23_HSDIV0 */ -}; - -&dss_ports { - port { - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp_connector_in>; - }; - }; -}; - -&serdes0 { - serdes0_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - serdes1_pcie_link: phy@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&pcie1_rc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_rst_pins_default>; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - max-link-speed = <3>; - reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; -}; - -&ufs_wrapper { - status = "disabled"; -}; - -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index ed75f7ee05..a5d95975fb 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -13,7 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-beagleboneai64" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j721e-beagleboneai64" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y @@ -173,5 +173,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 CONFIG_SPL_DFU=y CONFIG_LZO=y CONFIG_EFI_SET_TIME=y +CONFIG_OF_UPSTREAM=y #include <configs/k3_efi_capsule.config> -- 2.34.1

3 2

[PATCH] drivers: firmware: ti_sci: Add DM_FLAG_PRE_RELOC to driver
by Manorit Chawdhry 01 Jan '25

01 Jan '25

Currently the driver relies on bootph flag to probe it during PRE_RELOC stage but with the upcoming cleanup of v6.13, we don't have the bootph property in the parent nodes anymore and ti_sci driver being one of the parent nodes required during SPL stage would end up hampering the probe model [0]. Add DM_FLAG_PRE_RELOC to ti_sci driver for mitigating this issue. [0]: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/21 Suggested-by: Vignesh Raghavendra <vigneshr(a)ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry(a)ti.com> --- Test logs with current DT: https://gist.github.com/manorit2001/b28bebd8229818412ff74e40d4a53f71 Test logs with 6.13-rc3 DT: https://gist.github.com/manorit2001/b91691b59581d445c301e2608ce5931a --- drivers/firmware/ti_sci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 719cfa771b4198159a305a08a044c7a8aaf7a14f..190a1e3f5fc3713464b0cbf3ae8c35e3f185a353 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -3077,6 +3077,7 @@ U_BOOT_DRIVER(ti_sci) = { .of_match = ti_sci_ids, .probe = ti_sci_probe, .priv_auto = sizeof(struct ti_sci_info), + .flags = DM_FLAG_PRE_RELOC, }; #if IS_ENABLED(CONFIG_K3_DM_FW) --- base-commit: 9bc62c980d418f0a67632ab29cd3501072cdb6f0 change-id: 20241216-b4-upstream-dm-pre-reloc-583134d2a340 Best regards, -- Manorit Chawdhry <m-chawdhry(a)ti.com>

3 6

[PATCH] arm: dts: k3-am62p-sk-binman: add SE security variant builds
by Bryan Brattlof 01 Jan '25

01 Jan '25

The Texas Instruments Foundational Security (TIFS) firmware must match the security level configured on the SoC. To boot Security Enforced (SE) variants of the AM62Px, add another tiboot3 build which packages the Security Enforced (SE) firmware variant for AM62Px SoCs. Signed-off-by: Bryan Brattlof <bb(a)ti.com> --- arch/arm/dts/k3-am62p-sk-binman.dtsi | 49 ++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 2177d5428d4f9..797644a7e0d5f 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -57,6 +57,55 @@ type = "blob-ext"; }; }; + + tiboot3-am62px-hs-evm.bin { + filename = "tiboot3-am62px-hs-evm.bin"; + + ti-secure-rom { + content = <&u_boot_spl_hs>, <&ti_fs_enc_hs>, <&combined_tifs_cfg_hs>, + <&combined_dm_cfg_hs>, <&sysfw_inner_cert_hs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_hs>; + content-sysfw = <&ti_fs_enc_hs>; + content-sysfw-data = <&combined_tifs_cfg_hs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; + content-dm-data = <&combined_dm_cfg_hs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + + u_boot_spl_hs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_hs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_hs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_hs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_hs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; }; #include "k3-binman-capsule-r5.dtsi" --- base-commit: 45f05f681224d88d1b170063001b59edc8fc24cf change-id: 20240617-am62px-hs-binman-b866e39957f6 Best regards, -- Bryan Brattlof <bb(a)ti.com>

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