September 2023 - U-Boot

[PATCH v2] binman: doc: fix reference tag placement for Logging section
by Massimo Pegorer 15 Sep '23

15 Sep '23

Move BinmanLogging reference tag after section "Signing FIT container with private key in an image" and just before section "Logging". Remove meaningless line with incomplete sentence. Fixes: 0f40e23fd22 ("binman: add documentation for binman sign option") Signed-off-by: Massimo Pegorer <massimo.pegorer+oss(a)gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- Changes in v2: - Removed incomplete sentence (confirmed by Simon) tools/binman/binman.rst | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index aeea33fddb..020988d955 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -1480,9 +1480,6 @@ as set in stone, so Binman will ensure it doesn't change. Without this feature, repacking an entry might cause it to disobey the original constraints provided when it was created. - Repacking an image involves - -.. _`BinmanLogging`: Signing FIT container with private key in an image -------------------------------------------------- @@ -1501,6 +1498,7 @@ If you want to sign and replace FIT container in place:: which will sign FIT container with private key and replace it immediately inside your image. +.. _`BinmanLogging`: Logging ------- -- 2.34.1

2 1

[PATCH] sunxi: board: provide CPU idle states to loaded OS
by Andrey Skvortsov 14 Sep '23

14 Sep '23

When using SCPI as the PSCI backend, firmware can wake up the CPUs and cluster from sleep, so CPU idle states are available for loaded OS to use. TF-A modifies DTB to advertise available CPU idle states, when SCPI is detected. This change copies nodes added by TF-A to any new dtb that is used for loaded OS. Signed-off-by: Andrey Skvortsov <andrej.skvortzov(a)gmail.com> --- board/sunxi/board.c | 120 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index f321cd58a6..e88bd11a99 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -870,6 +870,125 @@ int board_late_init(void) return 0; } +static int cpuidle_dt_fixup_copy_node(ofnode src, int dst_offset, void *dst_blob, + u32 *count, u32 *phandle) +{ + int offs, len, ret; + struct ofprop prop; + ofnode subnode; + + ofnode_for_each_prop(prop, src) { + const char *name; + const char *val; + + val = ofprop_get_property(&prop, &name, &len); + if (!val) + return -EINVAL; + if (!strcmp(name, "phandle")) { + if (ofnode_device_is_compatible(src, "arm,idle-state")) { + fdt_setprop_u32(dst_blob, dst_offset, name, *phandle); + (*phandle)++; + (*count)++; + } else { + log_err("Unexpected phandle node: %s\n", name); + return -EINVAL; + } + } else { + ret = fdt_setprop(dst_blob, dst_offset, name, val, len); + if (ret < 0) + return ret; + } + } + + ofnode_for_each_subnode(subnode, src) { + const char *name = ofnode_get_name(subnode); + + if (!name) + return -EINVAL; + offs = fdt_add_subnode(dst_blob, dst_offset, name); + if (offs < 0) + return offs; + ret = cpuidle_dt_fixup_copy_node(subnode, offs, dst_blob, count, phandle); + if (ret < 0) + return ret; + } + return 0; +} + +static int cpuidle_dt_fixup(void *blob) +{ + ofnode idle_states_node; + ofnode subnode; + u32 count, phandle; + const struct property *prop; + int offs, len, ret; + + idle_states_node = ofnode_path("/cpus/idle-states"); + if (!ofnode_valid(idle_states_node)) { + log_err("No idle-states node in old fdt, nothing to do"); + return 0; + } + + /* + * Do not proceed if the target dt already has an idle-states node. + * In this case assume that the system knows better somehow, + * so do not interfere. + */ + if (fdt_path_offset(blob, "/cpus/idle-states") >= 0) { + log_err("idle-states node already exists in target"); + return 0; + } + + offs = fdt_path_offset(blob, "/cpus"); + if (offs < 0) + return offs; + + offs = fdt_add_subnode(blob, offs, "idle-states"); + if (offs < 0) + return offs; + + /* copy "/cpus/idle-states" node to destination fdt */ + ret = fdt_find_max_phandle(blob, &phandle); + if (ret < 0) + return ret; + phandle++; + count = 0; + ret = cpuidle_dt_fixup_copy_node(idle_states_node, offs, blob, &count, &phandle); + if (ret < 0) + return ret; + + /* copy "cpu-idle-state" property for all cpus */ + ofnode_for_each_subnode(subnode, ofnode_path("/cpus")) { + char path[32]; + fdt32_t *value; + + prop = ofnode_get_property(subnode, "cpu-idle-states", &len); + if (!prop) + continue; + + /* find the same node in a new device-tree */ + ret = ofnode_get_path(subnode, path, sizeof(path)); + if (ret) + return ret; + + offs = fdt_path_offset(blob, path); + if (offs < 0) + return offs; + + /* Allocate space for the list of phandles. */ + ret = fdt_setprop_placeholder(blob, offs, "cpu-idle-states", + count * sizeof(phandle), + (void **)&value); + if (ret < 0) + return ret; + + /* Fill in the phandles of the idle state nodes. */ + for (u32 i = 0U; i < count; ++i) + value[i] = cpu_to_fdt32(phandle - count + i); + } + return 0; +} + static void bluetooth_dt_fixup(void *blob) { /* Some devices ship with a Bluetooth controller default address. @@ -914,6 +1033,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) setup_environment(blob); fdt_fixup_ethernet(blob); + cpuidle_dt_fixup(blob); bluetooth_dt_fixup(blob); #ifdef CONFIG_VIDEO_DT_SIMPLEFB -- 2.40.1

2 6

[PATCH] andes: rearrange defconfig and dts and memory layout for SPL.
by Randolph 14 Sep '23

14 Sep '23

Modify "CONFIG_AE350" to "CONFIG_ANDES_AE350" Unify the memory layout for u-boot SPL. Signed-off-by: Randolph <randolph(a)andestech.com> --- arch/riscv/Kconfig | 4 +- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/ae350-u-boot.dtsi | 1 + arch/riscv/dts/ae350_32.dts | 61 ++++++++++++++-------------- arch/riscv/dts/ae350_64.dts | 1 - board/AndesTech/ae350/Kconfig | 28 ++++++++++++- configs/ae350_rv32_defconfig | 3 +- configs/ae350_rv32_spl_defconfig | 21 ++++------ configs/ae350_rv32_spl_xip_defconfig | 18 ++++---- configs/ae350_rv32_xip_defconfig | 3 +- configs/ae350_rv64_defconfig | 3 +- configs/ae350_rv64_spl_defconfig | 19 ++++----- configs/ae350_rv64_spl_xip_defconfig | 16 ++++---- configs/ae350_rv64_xip_defconfig | 3 +- 14 files changed, 101 insertions(+), 82 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6771d8d919..aff1f33665 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AE350 - bool "Support ae350" +config TARGET_ANDES_AE350 + bool "Support Andes ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f1525cb668..be6c8a4227 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi index aef9159b7a..ff5725501f 100644 --- a/arch/riscv/dts/ae350-u-boot.dtsi +++ b/arch/riscv/dts/ae350-u-boot.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) +#include CONFIG_SPL_LOAD_FIT_CONFIG / { cpus { diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 61af6d5465..3dde0e1dfa 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -2,12 +2,11 @@ /dts-v1/; -#include "binman.dtsi" #include "ae350-u-boot.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "andestech,a25"; model = "andestech,a25"; @@ -115,7 +114,7 @@ compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; - reg = <0xe0500000 0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; andes,inst-prefetch = <3>; andes,data-prefetch = <3>; /* The value format is <XRAMOCTL XRAMICTL> */ @@ -125,12 +124,12 @@ memory@0 { device_type = "memory"; - reg = <0x00000000 0x40000000>; + reg = <0x0 0x00000000 0x0 0x40000000>; }; soc { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "simple-bus"; ranges; @@ -138,7 +137,7 @@ compatible = "riscv,plic0"; #interrupt-cells = <2>; interrupt-controller; - reg = <0xe4000000 0x2000000>; + reg = <0x0 0xe4000000 0x0 0x2000000>; riscv,ndev=<71>; interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 @@ -148,9 +147,9 @@ plicsw: interrupt-controller@e6400000 { compatible = "andestech,plicsw"; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-controller; - reg = <0xe6400000 0x400000>; + reg = <0x0 0xe6400000 0x0 0x400000>; riscv,ndev=<2>; interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 @@ -164,7 +163,7 @@ &CPU1_intc 7 &CPU2_intc 7 &CPU3_intc 7>; - reg = <0xe6000000 0x100000>; + reg = <0x0 0xe6000000 0x0 0x100000>; }; }; @@ -176,7 +175,7 @@ timer0: timer@f0400000 { compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; + reg = <0x0 0xf0400000 0x0 0x1000>; clock-frequency = <60000000>; interrupts = <3 4>; interrupt-parent = <&plic0>; @@ -184,7 +183,7 @@ serial0: serial@f0300000 { compatible = "andestech,uart16550", "ns16550a"; - reg = <0xf0300000 0x1000>; + reg = <0x0 0xf0300000 0x0 0x1000>; interrupts = <9 4>; clock-frequency = <19660800>; reg-shift = <2>; @@ -195,7 +194,7 @@ mac0: mac@e0100000 { compatible = "andestech,atmac100"; - reg = <0xe0100000 0x1000>; + reg = <0x0 0xe0100000 0x0 0x1000>; interrupts = <19 4>; interrupt-parent = <&plic0>; }; @@ -205,7 +204,7 @@ max-frequency = <100000000>; clock-freq-min-max = <400000 100000000>; fifo-depth = <0x10>; - reg = <0xf0e00000 0x1000>; + reg = <0x0 0xf0e00000 0x0 0x1000>; interrupts = <18 4>; cap-sd-highspeed; interrupt-parent = <&plic0>; @@ -213,7 +212,7 @@ dma0: dma@f0c00000 { compatible = "andestech,atcdmac300"; - reg = <0xf0c00000 0x1000>; + reg = <0x0 0xf0c00000 0x0 0x1000>; interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; dma-channels = <8>; interrupt-parent = <&plic0>; @@ -221,19 +220,19 @@ lcd0: lcd@e0200000 { compatible = "andestech,atflcdc100"; - reg = <0xe0200000 0x1000>; + reg = <0x0 0xe0200000 0x0 0x1000>; interrupts = <20 4>; interrupt-parent = <&plic0>; }; smc0: smc@e0400000 { compatible = "andestech,atfsmc020"; - reg = <0xe0400000 0x1000>; + reg = <0x0 0xe0400000 0x0 0x1000>; }; snd0: snd@f0d00000 { compatible = "andestech,atfac97"; - reg = <0xf0d00000 0x1000>; + reg = <0x0 0xf0d00000 0x0 0x1000>; interrupts = <17 4>; interrupt-parent = <&plic0>; }; @@ -245,71 +244,71 @@ virtio_mmio@fe007000 { interrupts = <0x17 0x4>; interrupt-parent = <0x2>; - reg = <0xfe007000 0x1000>; + reg = <0x0 0xfe007000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe006000 { interrupts = <0x16 0x4>; interrupt-parent = <0x2>; - reg = <0xfe006000 0x1000>; + reg = <0x0 0xfe006000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe005000 { interrupts = <0x15 0x4>; interrupt-parent = <0x2>; - reg = <0xfe005000 0x1000>; + reg = <0x0 0xfe005000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe004000 { interrupts = <0x14 0x4>; interrupt-parent = <0x2>; - reg = <0xfe004000 0x1000>; + reg = <0x0 0xfe004000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe003000 { interrupts = <0x13 0x4>; interrupt-parent = <0x2>; - reg = <0xfe003000 0x1000>; + reg = <0x0 0xfe003000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe002000 { interrupts = <0x12 0x4>; interrupt-parent = <0x2>; - reg = <0xfe002000 0x1000>; + reg = <0x0 0xfe002000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe001000 { interrupts = <0x11 0x4>; interrupt-parent = <0x2>; - reg = <0xfe001000 0x1000>; + reg = <0x0 0xfe001000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe000000 { interrupts = <0x10 0x4>; interrupt-parent = <0x2>; - reg = <0xfe000000 0x1000>; + reg = <0x0 0xfe000000 0x0 0x1000>; compatible = "virtio,mmio"; }; nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "cfi-flash"; - reg = <0x88000000 0x4000000>; + reg = <0x0 0x88000000 0x0 0x4000000>; bank-width = <2>; device-width = <1>; }; spi: spi@f0b00000 { compatible = "andestech,atcspi200"; - reg = <0xf0b00000 0x1000>; + reg = <0x0 0xf0b00000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 8c7db29b4f..9d5f6c743c 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -2,7 +2,6 @@ /dts-v1/; -#include "binman.dtsi" #include "ae350-u-boot.dtsi" / { diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 75815bf99a..3b0d4c1733 100644 --- a/board/AndesTech/ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AE350 +if TARGET_ANDES_AE350 config SYS_CPU default "andesv5" @@ -41,4 +41,30 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SPL_RAM_DEVICE imply OF_HAS_PRIOR_STAGE +choice + prompt "Fit type" + default SPL_LOAD_FIT_NORMAL + +config SPL_LOAD_FIT_NORMAL + bool "Enable SPL applying u-boot proper from FIT" + depends on SPL_LOAD_FIT + help + Use fw_dynamic from the FIT image. Normal mode means that CPU will execute + u-boot proper in next step. + +config SPL_LOAD_FIT_DYNAMIC + bool "Enable SPL (dynamic mode) applying linux from FIT" + depends on SPL_LOAD_FIT + help + Use fw_dynamic from the FIT image. Dynamic mode means that CPU will execute + linux in the next step. + +endchoice + +config SPL_LOAD_FIT_CONFIG + string "Default FIT configuration" + depends on SPL_LOAD_FIT + help + Specify corresponding FIT configuration for each modes. + endif diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06a683d986..eea919249d 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -9,7 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 75e55ba724..1479eb256e 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 @@ -7,25 +8,23 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" # CONFIG_AVAILABLE_HARTS is not set +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 +CONFIG_PHYS_64BIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 CONFIG_SYS_MONITOR_BASE=0x88000000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -36,7 +35,6 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y @@ -45,7 +43,6 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index c2221b891e..142c5e29f2 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 @@ -8,25 +9,24 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" CONFIG_SPL_XIP=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -37,7 +37,6 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y @@ -46,7 +45,6 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 6d19400c2d..1b01b881ed 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -9,7 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" CONFIG_XIP=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 0d7f0a552e..cd13fc58a5 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -8,7 +8,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" CONFIG_ARCH_RV64I=y CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 6a72b5a047..f48838ddf9 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 @@ -7,25 +8,23 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" # CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 -CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 +CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -36,7 +35,6 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y @@ -45,7 +43,6 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 43581c79b1..15de9d9ef6 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 @@ -8,25 +9,24 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" CONFIG_SPL_XIP=y +# CONFIG_AVAILABLE_HARTS is not set CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 -CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_CACHE=y +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y @@ -37,7 +37,6 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y @@ -46,7 +45,6 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 02d7694489..88c3869f75 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -8,7 +8,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y +CONFIG_SPL_LOAD_FIT_CONFIG="binman.dtsi" CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_FIT=y -- 2.34.1

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[PATCH RFC 0/2] board: visionfive2: Select fdtfile based on revision
by Jami Kettunen 14 Sep '23

14 Sep '23

From: Jami Kettunen <jami.kettunen(a)protonmail.com> Currently booting a mainline Linux kernel via extlinux with fdtdir set doesn't load a proper DTB but passes on the U-Boot one to the kernel which as far as I know is very incorrect and prevents user (normally distro) provided DTB usage in a sensible/generic way. A uEnv.txt or similar manual environment changes were not used and should not be required to boot the board as per: https://u-boot.readthedocs.io/en/latest/develop/distro.html This also currently needs a kernel patch[1] for my board to have the full 8GB of memory available to Linux instead of just 4GB it shows with these patches alone. [1] https://gitlab.alpinelinux.org/nmeum/alpine-visionfive/-/blob/main/starfive… Jami Kettunen (2): board: visionfive2: Select fdtfile based on revision configs: visionfive2: Enable MISC_INIT_R .../visionfive2/starfive_visionfive2.c | 25 +++++++++++++++++++ configs/starfive_visionfive2_defconfig | 1 + 2 files changed, 26 insertions(+) -- 2.42.0

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[PATCH 0/3] trace: Fix flyrecord alignment issue
by Michal Simek 14 Sep '23

14 Sep '23

Hi, sandbox is getting bigger and bigger and I have reached the case that adding some more functions ends up in CI loop failure. After some investigation I found that flyrecord header have incorrect information about data offset which is caused by incorrect alignment calculation. That's why this series is fixing alignment calculation. I have done it via 3 patches where the first two are just preparing code for actual fixup. Thanks, Michal Michal Simek (3): trace: Use 64bit variable for start and len trace: Move trace_clocks description above record offset calculation trace: Fix alignment logic in flyrecord header tools/proftool.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) -- 2.36.1

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UEFI update files missing on sandbox?
by Simon Glass 14 Sep '23

14 Sep '23

Hi Sughosh, I thought that all your patches were merged but now when I build sandbox I don't see the capsule-update files generated. Is there something missing? Regards, Simon

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[PATCH] spi: zynqmp_qspi: Change flush cache to invalidate cache
by Venkatesh Yadav Abbarapu 14 Sep '23

14 Sep '23

From: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Before DMA read, ideally cache should be invalidated, so that data from memory will be updated to cache after DMA is completed. But flush_dcache_range is being used which is incorrect. Change flush_dcache_range to invalidate_dcache_range. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/spi/zynqmp_gqspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index c4aee279aa..a506d15227 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -690,7 +690,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; size = roundup(priv->len, GQSPI_DMA_ALIGN); - flush_dcache_range(addr, addr + size); + invalidate_dcache_range(addr, addr + size); while (priv->len) { zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); -- 2.17.1

1 0

[PATCH v1] rockchip: include: asm: fix entering download mode rk3066
by Johan Jonker 14 Sep '23

14 Sep '23

When a Rockchip rk3066 board download key is pressed it hangs. The rk3066 BROM doesn't have support to check the return to BROM, so when a key is pressed the loop that reads data must be broken by writing a "-1" to the variable that points to the next page address. It then goes in download mode and waits for data on USB OTG and UART0. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/include/asm/arch-rockchip/boot0.h | 32 +++++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 0c375e543a5e..305461ce3751 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -3,6 +3,8 @@ * Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include <asm/arch-rockchip/boot_mode.h> + /* * Execution starts on the instruction following this 4-byte header * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This @@ -23,17 +25,39 @@ * the first one may be overwritten, if this is the first stage * contained in the final image created with mkimage)... */ - b 1f /* if overwritten, entry-address is at the next word */ + b 1f /* if overwritten, entry-address is at the next word */ 1: #endif #if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) - adr r3, entry_counter +#if IS_ENABLED(CONFIG_ROCKCHIP_RK3066) +/* + * Unlike newer Rockchip SoC models the rk3066 BROM code does not have + * built-in support to enter download mode after return to BROM code. + * Before a return the boot mode register must be checked for the + * BOOT_BROM_DOWNLOAD flag. Writing '-1' to a location in SRAM + * where the BROM stores the next page address breaks the loop + * that reads boot blocks. The boot ROM code then goes into a + * download mode and waits for data on USB OTG and UART0. + */ + ldr r1, =BOOT_BROM_DOWNLOAD + ldr r0, =CONFIG_ROCKCHIP_BOOT_MODE_REG + ldr r0, [r0] + cmp r0, r1 /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) == */ + bne counter_check /* BOOT_BROM_DOWNLOAD) { */ + ldr r1, =0xffffffff + ldr r0, =0x10080028 + str r1, [r0] /* writel(0xffffffff, 0x10080028); */ + mov r0, #1 /* return 1; */ + bx lr /* } */ +counter_check: +#endif + adr r3, entry_counter ldr r0, [r3] cmp r0, #1 /* check if entry_counter == 1 */ beq reset /* regular bootup */ - add r0, #1 + add r0, #1 str r0, [r3] /* increment the entry_counter in memory */ - mov r0, #0 /* return 0 to the BROM to signal 'OK' */ + mov r0, #0 /* return 0 to the BROM to signal 'OK' */ bx lr /* return control to the BROM */ entry_counter: .word 0 -- 2.39.2

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[PATCH v3 0/7] Port gen_compile_commands.py from Linux to U-Boot
by Joao Marcos Costa 14 Sep '23

14 Sep '23

Hello U-Boot community, I'm submitting a patch series that ports the gen_compile_commands.py script from the Linux kernel's sources to U-Boot. This script, originally located in scripts/clang-tools/gen_compile_commands.py, enables the generation of compile_commands.json file for improved code navigation and analysis. The series consists of the initial script import, the necessary modifications for U-Boot compatibility, and finally some documentation. Your feedback on these contributions would be greatly appreciated. Best regards, Changes in v3: - Add documentation to index and fix syntax issues - Add reference to documentation in doc/build/tools Changes in v2: - Add compile_commands.json to gitignore - Add documentation Joao Marcos Costa (7): scripts: Port Linux's gen_compile_commands.py to U-Boot scripts/gen_compile_commands.py: adapt _LINE_PATTERN scripts/gen_compile_commands.py: fix docstring scripts/gen_compile_commands.py: add acknowledgments .gitignore: add compile_commands.json doc: add documentation for gen_compile_commands.py doc: add new section to build/tools .gitignore | 3 + doc/build/gen_compile_commands.rst | 47 ++++++ doc/build/index.rst | 1 + doc/build/tools.rst | 13 ++ scripts/gen_compile_commands.py | 230 +++++++++++++++++++++++++++++ 5 files changed, 294 insertions(+) create mode 100644 doc/build/gen_compile_commands.rst create mode 100755 scripts/gen_compile_commands.py -- 2.41.0

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[PATCH v4 00/13] firmware: scmi: add SCMI base protocol support
by AKASHI Takahiro 14 Sep '23

14 Sep '23

This patch series allows users to access SCMI base protocol provided by SCMI server (platform). It will also be utilized in separate patches in the future to add sanity/validity checks for other protocols. See SCMI specification document v3.2 beta[1] for more details about SCMI base protocol. What is currently not implemented is - SCMI_BASE_NOTIFY_ERRORS command and notification callback mechanism This feature won't be very useful in the current U-Boot environment. [1] https://developer.arm.com/documentation/den0056/e/?lang=en Test ==== The patch series was tested on the following platforms: * sandbox * qemu-arm64 with OPTEE as SCMI server Prerequisite: ============= * This patch series is based on v2023.10-rc4. Patches: ======== Patch#1-#4,#7-#8: Add SCMI base protocol driver Patch#5-#6,#9-#10: Add SCMI base protocol device unit test Patch#11-#13: Add scmi command Change history: =============== v4 (Sep 12, 2023) * shuffle the patch order (patch#5,6 prior to patch#7) * several improvements/cleanup thanks to Etienne (Each commit message has more details.) v3 (Sep 8, 2023) * import patch#6 (protocol availability check) from my followup patch * fix an issue on ST board (reported by Etienne) (patch#1) * minor code improvements * fix various typos pointed out by Etienne * revise function descriptions/comments (Each commit message has more details.) v2 (Jul, 26, 2023) * refactor devm_scmi_of_get_channel()/process_msg(), removing uses of ops (patch#1) * use helper functions, removing uses of ops (patch#2,#9,#10) * add more descriptions in scmi command doc (patch#11) * remove 'scmi base' sub-command (patch#10,#12) v1 (Jun, 28, 2023) * initial release AKASHI Takahiro (13): scmi: refactor the code to hide a channel from devices firmware: scmi: implement SCMI base protocol firmware: scmi: move scmi_bind_protocols() backward firmware: scmi: framework for installing additional protocols firmware: scmi: fake base protocol commands on sandbox test: dm: simplify SCMI unit test on sandbox firmware: scmi: install base protocol to SCMI agent firmware: scmi: add a check against availability of protocols sandbox: remove SCMI base node definition from test.dts test: dm: add SCMI base protocol test cmd: add scmi command for SCMI firmware doc: cmd: add documentation for scmi test: dm: add scmi command test arch/sandbox/dts/test.dts | 4 - arch/sandbox/include/asm/scmi_test.h | 7 +- cmd/Kconfig | 9 + cmd/Makefile | 1 + cmd/scmi.c | 337 +++++++++++ configs/sandbox_defconfig | 1 + doc/usage/cmd/scmi.rst | 126 ++++ drivers/clk/clk_scmi.c | 27 +- drivers/firmware/scmi/Makefile | 1 + drivers/firmware/scmi/base.c | 656 +++++++++++++++++++++ drivers/firmware/scmi/sandbox-scmi_agent.c | 379 +++++++++++- drivers/firmware/scmi/scmi_agent-uclass.c | 411 +++++++++++-- drivers/power/regulator/scmi_regulator.c | 26 +- drivers/reset/reset-scmi.c | 19 +- include/dm/uclass-id.h | 1 + include/scmi_agent-uclass.h | 81 ++- include/scmi_agent.h | 29 +- include/scmi_protocols.h | 351 +++++++++++ test/dm/scmi.c | 228 +++++-- 19 files changed, 2500 insertions(+), 194 deletions(-) create mode 100644 cmd/scmi.c create mode 100644 doc/usage/cmd/scmi.rst create mode 100644 drivers/firmware/scmi/base.c -- 2.34.1

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