September 2023 - U-Boot

[PATCH v3] board: rockchip: Add Bananapi R2Pro Board
by Frank Wunderlich 17 Sep '23

17 Sep '23

From: Frank Wunderlich <frank-w(a)public-files.de> Add Bananapi R2 Pro board. Till now evb dts could be used, but iodomain is different (evb has 1v8 on vccio2 and vccio4 which are 3v3 on r2pro) and with iodomain driver this can cause hardware fault. Devicetree in mainline-Linux: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arc… Signed-off-by: Frank Wunderlich <frank-w(a)public-files.de> --- v3: - disable gmac0 as switch-driver is not yet ready to attach to the mac v2: - drop switch-node for now as u-boot driver works differently to linux --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi | 23 + arch/arm/dts/rk3568-bpi-r2pro.dts | 549 ++++++++++++++++++++++ configs/bpi-r2pro-rk3568_defconfig | 101 ++++ 4 files changed, 675 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-bpi-r2pro.dts create mode 100644 configs/bpi-r2pro-rk3568_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bd518064f35f..767bf9db39fb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -182,7 +182,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-nanopi-r5s.dtb \ rk3568-odroid-m1.dtb \ rk3568-radxa-e25.dtb \ - rk3568-rock-3a.dtb + rk3568-rock-3a.dtb \ + rk3568-bpi-r2pro.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ diff --git a/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi b/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi new file mode 100644 index 000000000000..382a52a28b10 --- /dev/null +++ b/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; + }; +}; + +&sdmmc0 { + status = "okay"; +}; + +&uart2 { + clock-frequency = <24000000>; + bootph-pre-ram; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-bpi-r2pro.dts b/arch/arm/dts/rk3568-bpi-r2pro.dts new file mode 100644 index 000000000000..e4fcbb8a1174 --- /dev/null +++ b/arch/arm/dts/rk3568-bpi-r2pro.dts @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Author: Frank Wunderlich <frank-w(a)public-files.de> + * + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; + compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin &green_led_pin>; + + blue_led: led-0 { + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + green_led: led-1 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0 { + /* used for USB3 */ + status = "okay"; +}; + +&combphy1 { + /* used for USB3 */ + status = "okay"; +}; + +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x0f>; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c5 { + /* pin 3 (SDA) + 4 (SCL) of header con2 */ + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pinctrl { + leds { + blue_led_pin: blue-led-pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + green_led_pin: green-led-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + /* debug-uart */ + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + diff --git a/configs/bpi-r2pro-rk3568_defconfig b/configs/bpi-r2pro-rk3568_defconfig new file mode 100644 index 000000000000..e8936261eab3 --- /dev/null +++ b/configs/bpi-r2pro-rk3568_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2pro" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +#CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2pro" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET=n +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_ERRNO_STR=y +CONFIG_SYS_PROMPT="BPI-R2PRO> " +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_BOOTDEV=y +CONFIG_BOOTSTD_FULL=y +CONFIG_CMD_EFICONFIG=n +CONFIG_EFI_LOADER=n +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_CMD_USB=y +CONFIG_AHCI=y +CONFIG_DWC_AHCI=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_CMD_SCSI=y -- 2.34.1

4 8

[PATCH v2 0/2] riscv: starfive: generate u-boot-spl.bin.normal.out
by Heinrich Schuchardt 17 Sep '23

17 Sep '23

The StarFive JH7110 base boards require a header to be prefixed to the SPL binary image. This has previously done with a vendor tool 'spl_tool' published under a GPL-2-or-later license. Integrate this capability into mkimage. Add a binman task into the VisionFive 2 build to build the prefixed U-Boot SPL file u-boot-spl.bin.normal.out. v2: Fix a typo in a comment in tools/sfspl.c Add Tested-by credits Heinrich Schuchardt (2): tools: mkimage: Add StarFive SPL image support riscv: dts: starfive: generate u-boot-spl.bin.normal.out .../jh7110-starfive-visionfive-2-u-boot.dtsi | 10 + boot/image.c | 1 + doc/board/starfive/visionfive2.rst | 14 +- include/image.h | 1 + tools/Makefile | 1 + tools/sfspl.c | 174 ++++++++++++++++++ 6 files changed, 189 insertions(+), 12 deletions(-) create mode 100644 tools/sfspl.c -- 2.40.1

4 9

[PULL] u-boot-usb/next
by Marek Vasut 17 Sep '23

17 Sep '23

The following changes since commit 2fe4b54556ea6271237b35de68dc458bfceab94c: Merge branch '2023-09-14-remove-NEEDS_MANUAL_RELOC' into next (2023-09-14 16:23:49 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git next for you to fetch changes up to 2caf974b5fac69a1b778e64503f2c107a8d7c3a3: board: usb: Replace legacy usb_gadget_handle_interrupts() (2023-09-15 23:38:02 +0200) ---------------------------------------------------------------- Marek Vasut (17): dm: usb: udc: Factor out plain udevice handler functions usb: sandbox: Add DM_USB_GADGET support configs: sandbox: Enable DM_USB_GADGET cmd: fastboot: Use plain udevice for UDC controller interaction cmd: rockusb: Use plain udevice for UDC controller interaction cmd: sdp: Reorder variable declaration cmd: thordown: Reorder variable declaration cmd: ums: Use plain udevice for UDC controller interaction dfu: Detach the controller on error dfu: Use plain udevice for UDC controller interaction spl: sdp: Detach the controller on error sdp: Use plain udevice for UDC controller interaction thordown: Use plain udevice for UDC controller interaction usb: gadget: acm: Use plain udevice for UDC controller interaction usb: gadget: ether: Use plain udevice for UDC controller interaction dm: usb: udc: Drop legacy udevice handler functions board: usb: Replace legacy usb_gadget_handle_interrupts() arch/arm/mach-rockchip/board.c | 4 +- board/purism/librem5/spl.c | 4 +- board/samsung/common/exynos5-dt.c | 4 +- board/st/stih410-b2260/board.c | 4 +- board/ti/am43xx/board.c | 6 +-- cmd/fastboot.c | 7 ++-- cmd/rockusb.c | 7 ++-- cmd/thordown.c | 24 ++++++------ cmd/usb_gadget_sdp.c | 15 +++++--- cmd/usb_mass_storage.c | 10 +++-- common/dfu.c | 19 ++++++---- common/spl/spl_sdp.c | 20 ++++++---- configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_noinst_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + configs/sandbox_vpl_defconfig | 1 + drivers/usb/dwc3/core.c | 6 +-- drivers/usb/dwc3/dwc3-omap.c | 8 ++-- drivers/usb/gadget/at91_udc.c | 2 +- drivers/usb/gadget/atmel_usba_udc.c | 3 +- drivers/usb/gadget/ci_udc.c | 4 +- drivers/usb/gadget/dwc2_udc_otg.c | 12 +----- drivers/usb/gadget/ether.c | 20 +++++----- drivers/usb/gadget/f_acm.c | 13 ++++--- drivers/usb/gadget/f_mass_storage.c | 8 ++-- drivers/usb/gadget/f_sdp.c | 10 ++--- drivers/usb/gadget/f_thor.c | 74 +++++++++++++++++++------------------ drivers/usb/gadget/udc/Makefile | 2 +- drivers/usb/gadget/udc/udc-uclass.c | 57 ++++++++++++++-------------- drivers/usb/host/usb-sandbox.c | 6 ++- drivers/usb/musb-new/musb_uboot.c | 2 +- include/dwc3-omap-uboot.h | 2 +- include/dwc3-uboot.h | 2 +- include/linux/usb/gadget.h | 32 ++++++++-------- include/sdp.h | 6 +-- include/thor.h | 4 +- include/usb_mass_storage.h | 2 +- 39 files changed, 214 insertions(+), 191 deletions(-)

2 1

[PATCH v1 2/2] board: visionfive2: Fixup memory size passed to kernel
by Shengyu Qu 16 Sep '23

16 Sep '23

Use fdt_fixup_memory to make the memory size data from dtb match the actual size. Signed-off-by: Shengyu Qu <wiagn233(a)outlook.com> Tested-by: Milan P. Stanić <mps(a)arvanta.net> --- board/starfive/visionfive2/starfive_visionfive2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 9847e0efdb..700b60ac74 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -12,7 +12,9 @@ #include <linux/bitops.h> #include <asm/arch-jh7110/eeprom.h> #include <env.h> +#include <fdt_support.h> +DECLARE_GLOBAL_DATA_PTR; #define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000 #define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000 @@ -76,3 +78,8 @@ void *board_fdt_blob_setup(int *err) return (ulong *)&_end; } + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return fdt_fixup_memory(blob, 0x40000000, gd->ram_size); +} -- 2.42.0

1 0

[PATCH v1 1/2] configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP
by Shengyu Qu 16 Sep '23

16 Sep '23

Enable CONFIG_OF_BOARD_SETUP, so we could use ft_board_setup() to fixup memory size passed to kernel. Signed-off-by: Shengyu Qu <wiagn233(a)outlook.com> Tested-by: Milan P. Stanić <mps(a)arvanta.net> --- configs/starfive_visionfive2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 2376dad538..4d1459a3c2 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000 CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y +CONFIG_OF_BOARD_SETUP=y # CONFIG_OF_BOARD_FIXUP is not set CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y -- 2.42.0

1 0

[PATCH v1 0/2] Fix memory size problem on Visionfive 2
by Shengyu Qu 16 Sep '23

16 Sep '23

Currently, we pass u-boot device tree to kernel on Starfive Visionfive 2 , and this is wrong since u-boot dts is not sync with Linux for this board. Jami's patch[1] fixes this problem, but we are still sending unmodified version to kernel that doesn't have a correct memory size info. This series are based on Jami's work and provide a fix for that. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230911153253.20701-1-jam… Shengyu Qu (2): configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP board: visionfive2: Fixup memory size passed to kernel board/starfive/visionfive2/starfive_visionfive2.c | 7 +++++++ configs/starfive_visionfive2_defconfig | 1 + 2 files changed, 8 insertions(+) -- 2.42.0

1 0

bootstd: CACHE Misaligned operation errors (Marvell Armada 385)
by Tony Dinh 16 Sep '23

16 Sep '23

I've been testing the boostd for a few Marvell boards and seeing this error on the Thecus N2350 (Marvell Armada 385, dual-core CPU). The "bootflow scan scsi" command triggered the "CACHE: Misaligned operation at range" error. However, this error did not affect the result of the scan, i.e. the bootflow for scsi partition was created correctly, and u-boot is running normally. Enabling CONFIG_SYS_DCACHE_OFF got rid of the errors altogether. Perhaps this is a case where the DCACHE is not required and should be turned off? Please see the log after the break below. All the best, Tony ======== U-Boot 2023.10-rc4-tld-1-00036-gbb16283b81-dirty (Sep 11 2023 - 11:56:18 -0700) Thecus N2350 SoC: MV88F6820-A0 at 1066 MHz DRAM: 1 GiB (533 MHz, 32-bit, ECC not enabled) Core: 65 devices, 23 uclasses, devicetree: separate NAND: 512 MiB MMC: Loading Environment from SPIFlash... SF: Detected mx25l3205d with page size 256 Bytes, erase size 4 KiB, total 4 MiB *** Warning - bad CRC, using default environment Model: Thecus N2350 Net: Warning: ethernet@70000 (eth0) using random MAC address - be:13:ae:99:49:ab eth0: ethernet@70000 Hit any key to stop autoboot: 0 N2350 > env def -a ## Resetting to default environment N2350 > bootdev l Seq Probed Status Uclass Name --- ------ ------ -------- ------------------ 0 [ ] OK ethernet ethernet(a)70000.bootdev --- ------ ------ -------- ------------------ (1 bootdev) N2350 > bootdev hunt scsi Hunting with: scsi pcie0.0: Link down pcie1.0: Link down scanning bus for devices... SATA link 0 timeout. Target spinup took 0 ms. AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode flags: 64bit ncq led only pmp fbss pio slum part sxs Device 0: (1:0) Vendor: ATA Prod.: ST750LX003-1AC15 Rev: SM12 Type: Hard Disk Capacity: 715404.8 MB = 698.6 GB (1465149168 x 512) N2350 > bootflow scan usb Bus usb@58000: USB EHCI 1.00 Bus usb3@f0000: MVEBU XHCI INIT controller @ 0xf10f4000 Register 2000120 NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb3@f8000: MVEBU XHCI INIT controller @ 0xf10fc000 Register 2000120 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb@58000 for devices... 1 USB Device(s) found scanning bus usb3@f0000 for devices... 1 USB Device(s) found scanning bus usb3@f8000 for devices... 2 USB Device(s) found ** File not found /boot/boot.bmp ** N2350 > bootflow scan scsi CACHE: Misaligned operation at range [3fb7fe48, 3fb80248] CACHE: Misaligned operation at range [3fb7fe48, 3fb80248] CACHE: Misaligned operation at range [3fb7fe48, 3fb80248] ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3fb7fe48 ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3fb80248 ** File not found /boot/boot.bmp ** ** File not found /boot/boot.bmp ** N2350 > bootflow scan scsi CACHE: Misaligned operation at range [3fb88a88, 3fb88e88] CACHE: Misaligned operation at range [3fb88a88, 3fb88e88] CACHE: Misaligned operation at range [3fb88a88, 3fb88e88] ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3fb88a88 ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3fb88e88 ** File not found /boot/boot.bmp ** ** File not found /boot/boot.bmp ** N2350 > bootflow l Showing all bootflows Seq Method State Uclass Part Name Filename --- ----------- ------ -------- ---- ------------------------ ---------------- 0 script ready scsi 1 ahci_scsi.id1lun0.bootdev /boot/boot.scr 1 script ready usb_mass_ 1 usb_mass_storage.lun0.boo /boot/boot.scr --- ----------- ------ -------- ---- ------------------------ ---------------- (2 bootflows, 2 valid) N2350 > boot Scanning for bootflows in all bootdevs Seq Method State Uclass Part Name Filename --- ----------- ------ -------- ---- ------------------------ ---------------- Scanning global bootmeth 'efi_mgr': Hunting with: mmc Scanning bootdev 'ahci_scsi.id1lun0.bootdev': CACHE: Misaligned operation at range [3fb91d08, 3fb92108] CACHE: Misaligned operation at range [3fb91d08, 3fb92108] CACHE: Misaligned operation at range [3fb91d08, 3fb92108] ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x3fb91d08 ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x3fb92108 ** File not found /boot/boot.bmp ** 0 script ready scsi 1 ahci_scsi.id1lun0.bootdev /boot/boot.scr ** Booting bootflow 'ahci_scsi.id1lun0.bootdev.part_1' with script Booting with distro boot script loading uImage from scsi 0:1 ... 5118888 bytes read in 120 ms (40.7 MiB/s) loading uInitrd from scsi 0:1 ... 7355687 bytes read in 197 ms (35.6 MiB/s) loading DTB file from scsi 0:1 ... 20906 bytes read in 16 ms (1.2 MiB/s) ## Booting kernel from Legacy Image at 01000000 ... Image Name: Linux-6.4.11-mvebu-tld-1 Created: 2023-08-20 17:34:55 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 5118824 Bytes = 4.9 MiB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 02200000 ... Image Name: initramfs-6.4.11-mvebu-tld-1 Created: 2023-08-20 17:34:57 UTC Image Type: ARM Linux RAMDisk Image (gzip compressed) Data Size: 7355623 Bytes = 7 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 02000000 Booting using the fdt blob at 0x2000000 Working FDT set to 2000000 Starting kernel ... Loading Kernel Image Loading Ramdisk to 0f8fc000, end 0ffffce7 ... OK Loading Device Tree to 0f8f3000, end 0f8fb1a9 ... OK Working FDT set to f8f3000 Starting kernel ...

3 9

[PATCH] USB: gadget: atmel: fix transfer of queued requests
by Artur Rojek 16 Sep '23

16 Sep '23

In the existing implementation, multiple requests queued up on an endpoint are subject to getting evicted without transmission. For both control and bulk endpoints, their respective logic found in usba_control_irq()/usba_ep_irq() guarantees that TX FIFO is empty before data is sent out, and that request_complete() gets called once the transaction has been finished. At this point however, if any additional requests are found on the endpoint queue, they will be processed by submit_next_request(), which makes no checks against the above conditions, trashing data on a busy FIFO and neglecting completion handlers. Fix the above issues by removing the calls to submit_next_request(), and thus forcing the pending requests to be processed on the next pass of the respective endpoint logic. While at it, remove a DBG message, as that branch becomes part of regular flow. This restores mass storage mode operation on Microchip ATSAMA5D27 SoC. Signed-off-by: Artur Rojek <artur(a)conclusive.pl> --- drivers/usb/gadget/atmel_usba_udc.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index 7d51821497b4..e6b458d940d8 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -57,13 +57,9 @@ static void submit_request(struct usba_ep *ep, struct usba_request *req) req->submitted = 1; next_fifo_transaction(ep, req); - if (req->last_transaction) { - usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); - usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); - } else { + if (ep_is_control(ep)) usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); - usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); - } + usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); } static void submit_next_request(struct usba_ep *ep) @@ -889,7 +885,6 @@ restart: if (req) { list_del_init(&req->queue); request_complete(ep, req, 0); - submit_next_request(ep); } usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); ep->state = WAIT_FOR_SETUP; @@ -1036,7 +1031,6 @@ static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep) DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name); if (list_empty(&ep->queue)) { - DBG(DBG_INT, "ep_irq: queue empty\n"); usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); return; } @@ -1050,7 +1044,6 @@ static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep) if (req->last_transaction) { list_del_init(&req->queue); - submit_next_request(ep); request_complete(ep, req, 0); } -- 2.42.0

2 1

Binman how to build using Rockchip BL32 binary as OP-TEE
by Massimo Pegorer 16 Sep '23

16 Sep '23

Hi, Is there any way for binman to package FIT with U-Boot TF-A and OP-TEE, using bl32 binary provided by Rockchip as TEE? I've tried with TEE=/path/to/rkbin/bin/rk33/xxx_bl32_vX.YZ.bin, but binman failed. In my poor understanding of Python code, it seems binman accepts only ELF format or a binary format starting with optee_v1_header, but binaries provided by Rockchip in rkbin repository do not have this header. Thanks in advance for any hints! Massimo

3 9

[PATCH 0/4] spl: atf: Fix potential bug on getting FIT data
by Massimo Pegorer 16 Sep '23

16 Sep '23

If both fit_image_get_entry() and fit_image_get_load() calls fail, an uninitialized variable value is passed to TF-A as BL3-2 and/or BL3-3 entry point in spl_invoke_atf(). In real world of current SPL flow this is not expected to occur because a fit_image_get_load() failure should break boot during images loading phase, and thus before entering spl_invoke_atf(). Update improve and fix comments. A minor rework slightly reduces SPL code size up to 72 bytes. Note: I am not enough confident about uintptr_t and ulong sizes matching within all architectures, otherwise straightforward pass of bl3x_entry reference to fit_image_get_xxx would be fine. Massimo Pegorer (4): spl: atf: Improve comments and code readability image: fit: Improve functions description comments spl: atf: Fix potential but not occurring bug spl: atf: Reduce SPL code size boot/image-fit.c | 12 +++---- common/spl/spl_atf.c | 75 +++++++++++++++++++------------------------- 2 files changed, 38 insertions(+), 49 deletions(-) -- 2.34.1

1 0