December 2023 - U-Boot

[PATCH] board: rockchip: Add support for FriendlyARM NanoPi R2C Plus
by Tianling Shen 18 Jan '24

18 Jan '24

The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board eMMC flash (8G) included. The device tree is taken from the kernel v6.5. Signed-off-by: Tianling Shen <cnsztl(a)gmail.com> --- arch/arm/dts/Makefile | 1 + .../dts/rk3328-nanopi-r2c-plus-u-boot.dtsi | 9 ++ arch/arm/dts/rk3328-nanopi-r2c-plus.dts | 33 +++++ board/rockchip/evb_rk3328/MAINTAINERS | 6 + configs/nanopi-r2c-plus-rk3328_defconfig | 114 ++++++++++++++++++ 5 files changed, 163 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts create mode 100644 configs/nanopi-r2c-plus-rk3328_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9d28a485bec..6909f95e084 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2c-plus.dtb \ rk3328-nanopi-r2s.dtb \ rk3328-orangepi-r1-plus.dtb \ rk3328-orangepi-r1-plus-lts.dtb \ diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi new file mode 100644 index 00000000000..f8adb9e5e1f --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rk3328-nanopi-r2c-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus.dts b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts new file mode 100644 index 00000000000..16a1958e457 --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl(a)gmail.com> + */ + +/dts-v1/; +#include "rk3328-nanopi-r2c.dts" + +/ { + model = "FriendlyElec NanoPi R2C Plus"; + compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; + + aliases { + mmc1 = &emmc; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io_33>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 8a19eb373d0..5fc114a63f6 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -11,6 +11,12 @@ S: Maintained F: configs/nanopi-r2c-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi +NANOPI-R2C-PLUS-RK3328 +M: Tianling Shen <cnsztl(a)gmail.com> +S: Maintained +F: configs/nanopi-r2c-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi + NANOPI-R2S-RK3328 M: David Bauer <mail(a)david-bauer.net> S: Maintained diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig new file mode 100644 index 00000000000..320ed8b434a --- /dev/null +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.43.0

2 3

[PATCH] mmc: Unconditionally call mmc_deinit()
by Marek Vasut 18 Jan '24

18 Jan '24

Place the SDR104/HS200/HS400 checks into the mmc_deinit() and always call it. This simplifies the code and removes ifdeffery. No functional change is expected. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Peng Fan <peng.fan(a)nxp.com> --- drivers/mmc/mmc-uclass.c | 13 +------------ drivers/mmc/mmc.c | 9 +++++---- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 328456831dd..cdead044177 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -494,10 +494,7 @@ static int mmc_blk_probe(struct udevice *dev) if (ret) { debug("Probing %s failed (err=%d)\n", dev->name, ret); - if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || - CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || - CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) - mmc_deinit(mmc); + mmc_deinit(mmc); return ret; } @@ -505,9 +502,6 @@ static int mmc_blk_probe(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) static int mmc_blk_remove(struct udevice *dev) { struct udevice *mmc_dev = dev_get_parent(dev); @@ -516,7 +510,6 @@ static int mmc_blk_remove(struct udevice *dev) return mmc_deinit(mmc); } -#endif static const struct blk_ops mmc_blk_ops = { .read = mmc_bread, @@ -532,12 +525,8 @@ U_BOOT_DRIVER(mmc_blk) = { .id = UCLASS_BLK, .ops = &mmc_blk_ops, .probe = mmc_blk_probe, -#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) .remove = mmc_blk_remove, .flags = DM_FLAG_OS_PREPARE, -#endif }; #endif /* CONFIG_BLK */ diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d96db7a0f83..eb5010c1465 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3010,13 +3010,15 @@ int mmc_init(struct mmc *mmc) return err; } -#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) int mmc_deinit(struct mmc *mmc) { u32 caps_filtered; + if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) && + !CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) && + !CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) + return 0; + if (!mmc->has_init) return 0; @@ -3034,7 +3036,6 @@ int mmc_deinit(struct mmc *mmc) return mmc_select_mode_and_width(mmc, caps_filtered); } } -#endif int mmc_set_dsr(struct mmc *mmc, u16 val) { -- 2.42.0

2 1

[PATCH v2 RESEND] mmc: dw_mmc: reset controller after data error
by Eugen Hristev 18 Jan '24

18 Jan '24

From: Ziyuan Xu <xzy.xu(a)rock-chips.com> Per dw_mmc databook, it's recommended to reset the host controller if some data-related error occurred. Implement a reset mechanism. Signed-off-by: Ziyuan Xu <xzy.xu(a)rock-chips.com> Co-developed-by: Jason Zhu <jason.zhu(a)rock-chips.com> Signed-off-by: Jason Zhu <jason.zhu(a)rock-chips.com> [eugen.hristev(a)collabora.com: modified a bit the variables initialization] Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- drivers/mmc/dw_mmc.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 5085a3b491da..d6cad998b0cd 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -138,7 +138,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) { struct mmc *mmc = host->mmc; int ret = 0; - u32 timeout, mask, size, i, len = 0; + u32 timeout, reset_timeout = 100, status, ctrl, mask, size, i, len = 0; u32 *buf = NULL; ulong start = get_timer(0); u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> @@ -159,6 +159,24 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) /* Error during data transfer. */ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { debug("%s: DATA ERROR!\n", __func__); + + dwmci_wait_reset(host, DWMCI_RESET_ALL); + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | + DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + + do { + status = dwmci_readl(host, DWMCI_CMD); + if (!reset_timeout--) + break; + udelay(100); + } while (status & DWMCI_CMD_START); + + if (!host->fifo_mode) { + ctrl = dwmci_readl(host, DWMCI_BMOD); + ctrl |= DWMCI_BMOD_IDMAC_RESET; + dwmci_writel(host, DWMCI_BMOD, ctrl); + } + ret = -EINVAL; break; } -- 2.34.1

4 6

[PATCH v2 1/1] lib: smbios: remove redundant next_header()
by Heinrich Schuchardt 17 Jan '24

17 Jan '24

next_header() and get_next_header() only differ in how the const attribute is used. One function taking a const parameter and returning a non-const is good enough. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- v2: remove Fixes tag as the code redundancy is not an actual bug --- lib/smbios-parser.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/lib/smbios-parser.c b/lib/smbios-parser.c index b578c30840..f4de350e6e 100644 --- a/lib/smbios-parser.c +++ b/lib/smbios-parser.c @@ -50,14 +50,7 @@ static u8 *find_next_header(u8 *pos) return pos; } -static struct smbios_header *get_next_header(struct smbios_header *curr) -{ - u8 *pos = ((u8 *)curr) + curr->length; - - return (struct smbios_header *)find_next_header(pos); -} - -static const struct smbios_header *next_header(const struct smbios_header *curr) +static struct smbios_header *get_next_header(const struct smbios_header *curr) { u8 *pos = ((u8 *)curr) + curr->length; @@ -73,7 +66,7 @@ const struct smbios_header *smbios_header(const struct smbios_entry *entry, int if (header->type == type) return header; - header = next_header(header); + header = get_next_header(header); } return NULL; -- 2.43.0

2 1

[PATCH] arm: dts: k3-j721e-binman: Add support for HS-SE 2.0
by Neha Malcom Francis 17 Jan '24

17 Jan '24

Add support for J721E HS-SE 2.0 device. Make use of the existing templates and override the phandles for sysfw.itb so that builds do not fail. Signed-off-by: Neha Malcom Francis <n-francis(a)ti.com> --- Boot log: https://gist.github.com/nehamalcom/44082b0c94059737e8d5d1ab16b2f55f arch/arm/dts/k3-j721e-binman.dtsi | 83 +++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index dbc385a852..9707ea3085 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -20,6 +20,20 @@ no-expanded; }; }; + + tiboot3-j721e_sr2-hs-evm.bin { + filename = "tiboot3-j721e_sr2-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl_sr2>; + core = "public"; + load = <CONFIG_SPL_TEXT_BASE>; + keyfile = "custMpk.pem"; + }; + u_boot_spl_sr2: u-boot-spl { + no-expanded; + }; + }; + sysfw { filename = "sysfw.bin"; ti-secure-rom { @@ -40,10 +54,79 @@ optional; }; }; + + sysfw_sr2 { + filename = "sysfw.bin_sr2"; + ti-secure-rom { + content = <&ti_fs_cert_sr2>; + core = "secure"; + load = <0x40000>; + keyfile = "custMpk.pem"; + countersign; + }; + ti_fs_cert_sr2: ti-fs-cert.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + ti-fs-firmware-j721e_sr2-hs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + itb { filename = "sysfw-j721e_sr1_1-hs-evm.itb"; insert-template = <&itb_template>; }; + + itb_sr2 { + filename = "sysfw-j721e_sr2-hs-evm.itb"; + insert-template = <&itb_template>; + fit { + images { + sysfw.bin { + blob-ext { + filename = "sysfw.bin_sr2"; + }; + }; + board-cfg.bin { + ti-secure { + content = <&board_cfg_sr2>; + }; + board_cfg_sr2: board-cfg { + filename = "board-cfg.bin"; + }; + }; + pm-cfg.bin { + ti-secure { + content = <&pm_cfg_sr2>; + }; + pm_cfg_sr2: pm-cfg { + filename = "pm-cfg.bin"; + }; + }; + rm-cfg.bin { + ti-secure { + content = <&rm_cfg_sr2>; + }; + rm_cfg_sr2: rm-cfg { + filename = "rm-cfg.bin"; + }; + }; + sec-cfg.bin { + ti-secure { + content = <&sec_cfg_sr2>; + }; + sec_cfg_sr2: sec-cfg { + filename = "sec-cfg.bin"; + }; + }; + + }; + }; + }; }; &binman { -- 2.34.1

2 1

[PATCH v2 0/2] smbios: copy QEMU tables
by Heinrich Schuchardt 17 Jan '24

17 Jan '24

QEMU provides SMBIOS tables with detailed information. We should not try to replicate them in U-Boot. With this series we add code to copy the QEMU generated SMBIOS tables to RAM. efi_smbios_register() later installs the SMBIOS table as EFI configuration table for the OS to pick it up. If we want to inform about U-Boot, we can add a Firmware Inventory Information (type 45) table in future. With 32bit ARM I did not see a correct SMBIOS table being transferred. We need to check if our code in qfw_read_entry() is 32bit compliant. For providing SMBIOS support in QEMU for RISC-V I have sent a patch upstream: [PATCH 1/1] target/riscv: SMBIOS support for RISC-V virt machine https://lore.kernel.org/qemu-riscv/9183a3fb-b9f7-470c-b9a6-8d8cc6dce7c3@can… Currently we have a predefined constant TABLE_SIZE = SZ_4K in lib/efi_loader/efi_smbios.c. We should strive to refactor the code in future to provide the length of the SMBIOS tables in global data. But that is beyond the scope of this series. Further we should find a matainer for drivers/misc/qfw*. It would be plausible to add it to 'ACPI' maintenance. A test via a new SMBIOS command is supplied in [PATCH 0/5] cmd: provide command to display SMBIOS information https://lore.kernel.org/u-boot/20231223004429.247301-1-xypron.glpk@gmx.de/T… v2: fix parsing of SMBIOS anchor enable copying on x86 and 32bit ARM/RISC-V Heinrich Schuchardt (2): smbios: SMBIOS 3.0 (64-bit) Entry Point structure smbios: copy QEMU tables arch/x86/lib/tables.c | 2 +- drivers/misc/Kconfig | 7 ++ drivers/misc/Makefile | 1 + drivers/misc/qfw_smbios.c | 197 ++++++++++++++++++++++++++++++++++++ include/smbios.h | 26 +++++ lib/efi_loader/efi_smbios.c | 4 +- 6 files changed, 235 insertions(+), 2 deletions(-) create mode 100644 drivers/misc/qfw_smbios.c -- 2.43.0

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[PATCH V4] ARM add initial support for the Phytium Pe2201 Board.
by TracyMg_Li＠outlook.com 17 Jan '24

17 Jan '24

From: TracyMg_Li <TracyMg_Li(a)outlook.com> Add pe2201 platform code and the device tree of pe2201 platform board. The initial support comprises the UART and PCIe. Signed-off-by: TracyMg_Li <TracyMg_Li(a)outlook.com> Changes since v1: fix space corrupt. Changes since v2: switch to bootstd and text environment. Changes since v3: add environment variables. --- arch/arm/Kconfig | 7 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pe2201.dts | 43 +++++++ board/phytium/pe2201/Kconfig | 12 ++ board/phytium/pe2201/MAINTAINERS | 8 ++ board/phytium/pe2201/Makefile | 12 ++ board/phytium/pe2201/cpu.h | 64 +++++++++++ board/phytium/pe2201/ddr.c | 190 +++++++++++++++++++++++++++++++ board/phytium/pe2201/pcie.c | 60 ++++++++++ board/phytium/pe2201/pe2201.c | 92 +++++++++++++++ board/phytium/pe2201/pe2201.env | 25 ++++ board/phytium/pe2201/pll.c | 75 ++++++++++++ board/phytium/pe2201/sec.c | 37 ++++++ configs/pe2201_defconfig | 42 +++++++ include/configs/pe2201.h | 16 +++ 15 files changed, 684 insertions(+) create mode 100644 arch/arm/dts/phytium-pe2201.dts create mode 100644 board/phytium/pe2201/Kconfig create mode 100644 board/phytium/pe2201/MAINTAINERS create mode 100644 board/phytium/pe2201/Makefile create mode 100644 board/phytium/pe2201/cpu.h create mode 100644 board/phytium/pe2201/ddr.c create mode 100644 board/phytium/pe2201/pcie.c create mode 100644 board/phytium/pe2201/pe2201.c create mode 100644 board/phytium/pe2201/pe2201.env create mode 100644 board/phytium/pe2201/pll.c create mode 100644 board/phytium/pe2201/sec.c create mode 100644 configs/pe2201_defconfig create mode 100644 include/configs/pe2201.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c98..358c515a93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2060,6 +2060,12 @@ config TARGET_POMELO Support for pomelo platform. It has 8GB Sdram, uart and pcie. +config TARGET_PE2201 + bool "Support Phytium PE2201 Platform" + select ARM64 + help + Support for pe2201 platform.It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2336,6 +2342,7 @@ source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" source "board/phytium/pomelo/Kconfig" +source "board/phytium/pe2201/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5fc888680b..ce2fc626b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1469,6 +1469,7 @@ dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb +dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pe2201.dts b/arch/arm/dts/phytium-pe2201.dts new file mode 100644 index 0000000000..959584fbbb --- /dev/null +++ b/arch/arm/dts/phytium-pe2201.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium pe2201 board + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium pe2201 Board"; + compatible = "phytium,pe2201"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + uart0: serial@2800c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800c000 0x0 0x1000>; + clock = <100000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + }; +}; diff --git a/board/phytium/pe2201/Kconfig b/board/phytium/pe2201/Kconfig new file mode 100644 index 0000000000..f2f222b5d3 --- /dev/null +++ b/board/phytium/pe2201/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PE2201 + +config SYS_BOARD + default "pe2201" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pe2201" + +endif diff --git a/board/phytium/pe2201/MAINTAINERS b/board/phytium/pe2201/MAINTAINERS new file mode 100644 index 0000000000..f583d631d2 --- /dev/null +++ b/board/phytium/pe2201/MAINTAINERS @@ -0,0 +1,8 @@ +PE2201 BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pe2201/* +F: include/configs/pe2201.h +F: configs/pe2201_defconfig +F: arch/arm/dts/phytium-pe2201.dts diff --git a/board/phytium/pe2201/Makefile b/board/phytium/pe2201/Makefile new file mode 100644 index 0000000000..5350f0f818 --- /dev/null +++ b/board/phytium/pe2201/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023, Phytium Technology Co., Ltd. +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pe2201.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o diff --git a/board/phytium/pe2201/cpu.h b/board/phytium/pe2201/cpu.h new file mode 100644 index 0000000000..01adbb0a17 --- /dev/null +++ b/board/phytium/pe2201/cpu.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_PE2201_H +#define _FT_PE2201_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/* CPU RESET */ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460020 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460021 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define X1X1X1X1 0x2 +#define X1X1 0x0 +#define EP_MODE 0x0 +#define RC_MODE 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460024 +#define PARAM_MCU_VERSION 0x3 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x1 + +#define RDIMM_TYPE 0x1 +#define UDIMM_TYPE 0x2 +#define LPDDR4_TYPE 0x10 +#define DIMM_X8 0x1 +#define DIMM_X16 0x2 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_PE2201_H */ diff --git a/board/phytium/pe2201/ddr.c b/board/phytium/pe2201/ddr.c new file mode 100644 index 0000000000..549d211ccd --- /dev/null +++ b/board/phytium/pe2201/ddr.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /***************** read from spd ******************/ + u8 dimm_type; /* 1: RDIMM; 2: UDIMM; 3: SODIMM; 4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16; 3: x32 */ + u8 mirror_type; /* 0: standard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1: ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /* DDR4/DDR5 */ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; /* only DDR3/DDR4 */ + + u16 trrd_smin; /* only DDR4 */ + u16 trrd_lmin; /* only DDR4 */ + u16 tccd_lmin; /* only DDR4 */ + u16 twrmin; + + u16 twtr_smin; /* only DDR4 */ + u16 twtr_lmin; /* only DDR4 */ + u32 trfc1min; + + u32 trfc2min; + u32 trfc4_rfcsbmin; /* DDR4: tRFC4min; DDR5: tRFCsbmin */ + u8 resv[8]; + + /***************** RCD control words ******************/ + u8 f0rc03; /* bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /* bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /* bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 rcd_num; /* Registers used on RDIMM */ + + u8 lrdimm_resv[4]; + u8 lrdimm_resv1[8]; + u8 lrdimm_resv2[8]; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 resv1[7]; + + u64 misc_enable; + + u8 train_debug; + u8 train_recover; + u8 train_param_type; + u8 train_param_1; /* DDR4: cpu_odt */ + u8 train_param_2; /* DDR4: cpu_drv */ + u8 train_param_3; /* DDR4: mr_drv */ + u8 train_param_4; /* DDR4: rtt_nom */ + u8 train_param_5; /* DDR4: rtt_park */ + + u8 train_param_6; /* DDR4: rtt_wr */ + u8 resv2[7]; + + /***************** for LPDDR4 dq swap ******************/ + u32 data_byte_swap; + u32 slice0_dq_swizzle; + + u32 slice1_dq_swizzle; + u32 slice2_dq_swizzle; + + u32 slice3_dq_swizzle; + u32 slice4_dq_swizzle; + + u32 slice5_dq_swizzle; + u32 slice6_dq_swizzle; + + u32 slice7_dq_swizzle; + u8 resv3[4]; + u8 resv4[8]; + + struct ddr_spd ddr_spd_info; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; +} + +static u8 init_dimm_param(struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->misc_enable = 0x2001; + pm->train_debug = 0x0; + pm->train_recover = 0x0; + pm->train_param_type = 0x0; + pm->train_param_1 = 0x0; + pm->train_param_2 = 0x0; + pm->train_param_3 = 0x0; + pm->train_param_4 = 0x0; + pm->train_param_5 = 0x0; + pm->train_param_6 = 0x0; + + pm->data_byte_swap = 0x76543210; + pm->slice0_dq_swizzle = 0x3145726; + + pm->slice1_dq_swizzle = 0x54176230; + pm->slice2_dq_swizzle = 0x57604132; + + pm->slice3_dq_swizzle = 0x20631547; + pm->slice4_dq_swizzle = 0x16057423; + + pm->slice5_dq_swizzle = 0x16057423; + pm->slice6_dq_swizzle = 0x16057423; + + pm->slice7_dq_swizzle = 0x16057423; + + pm->ddr_spd_info.dimm_type = RDIMM_TYPE; + pm->ddr_spd_info.data_width = DIMM_X16; + pm->ddr_spd_info.mirror_type = NO_MIRROR; + pm->ddr_spd_info.ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info.dram_type = LPDDR4_TYPE; + pm->ddr_spd_info.rank_num = 0x1; + pm->ddr_spd_info.row_num = 0x10; + pm->ddr_spd_info.col_num = 0xa; + pm->ddr_spd_info.bg_num = 0x0; + pm->ddr_spd_info.bank_num = 0x8; + pm->ddr_spd_info.taamin = 0x0; + pm->ddr_spd_info.trcdmin = 0x0; + + pm->ddr_spd_info.trpmin = 0x0; + pm->ddr_spd_info.trasmin = 0x0; + pm->ddr_spd_info.trcmin = 0x0; + pm->ddr_spd_info.tfawmin = 0x0; + + pm->ddr_spd_info.trrd_smin = 0x0; + pm->ddr_spd_info.trrd_lmin = 0x0; + pm->ddr_spd_info.tccd_lmin = 0x0; + pm->ddr_spd_info.twrmin = 0x0; + + pm->ddr_spd_info.twtr_smin = 0x0; + pm->ddr_spd_info.twtr_lmin = 0x0; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + init_dimm_param(mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pe2201/pcie.c b/board/phytium/pe2201/pcie.c new file mode 100644 index 0000000000..34c38d2aee --- /dev/null +++ b/board/phytium/pe2201/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[4]; + u32 equalization[4]; + u8 rev[72]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x4, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X1X1X1X1 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X1X1 << 1))), + .ctr_cfg[0].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c new file mode 100644 index 0000000000..0e837b0f50 --- /dev/null +++ b/board/phytium/pe2201/pe2201.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <asm/u-boot.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int dram_init(void) +{ + debug("Phytium ddr init\n"); + ddr_init(); + + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +static struct mm_region pe2201_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NS | PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pe2201_mem_map; + +int last_stage_init(void) +{ + return 0; +} diff --git a/board/phytium/pe2201/pe2201.env b/board/phytium/pe2201/pe2201.env new file mode 100644 index 0000000000..d57b82d23b --- /dev/null +++ b/board/phytium/pe2201/pe2201.env @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + */ + +/* Initial environment variables */ + +image=Image +scriptaddr=0x90100000 +script_offset_f=0xc00000 +script_size_f=0x2000 +kernel_addr_r=0x90200000 +fdt_addr_r=0x90000000 +boot_fit=no +fdtfile=phytium-pe2201.dtb +ft_fdt_name=boot/dtb/pe2201.dtb +fdtoverlay_addr_r=0x95100000 +kernel_comp_addr_r=0x96000000 +kernel_comp_size=0x2000000 +pxefile_addr_r=0x9A000000 +ramdisk_addr_r=0x95000000 +load_kernel=ext4load scsi 0:2 $kernel_addr_r boot/uImage-2004 +load_initrd=ext4load scsi 0:2 $ramdisk_addr_r initrd.img-4.19.0.pe2201 +load_fdt=ext4load scsi 0:2 $fdt_addr_r $ft_fdt_name +distro_bootcmd=run load_kernel; run load_initrd; run load_fdt; run boot_os diff --git a/board/phytium/pe2201/pll.c b/board/phytium/pe2201/pll.c new file mode 100644 index 0000000000..f46435c74b --- /dev/null +++ b/board/phytium/pe2201/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 clust0_pll; + u32 clust1_pll; + u32 clust2_pll; + u32 noc_pll; + u32 dmu_pll; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x2, + .size = 0x100, + .clust0_pll = 2000, + .clust1_pll = 2000, + .clust2_pll = 2000, + .noc_pll = 1800, + .dmu_pll = 600, +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pe2201/sec.c b/board/phytium/pe2201/sec.c new file mode 100644 index 0000000000..6a980d6ea6 --- /dev/null +++ b/board/phytium/pe2201/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig new file mode 100644 index 0000000000..e6b9cef4cd --- /dev/null +++ b/configs/pe2201_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_PE2201=y +CONFIG_TEXT_BASE=0x38180000 +CONFIG_SYS_MALLOC_LEN=0x101000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30c1a000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pe2201" +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_PSCI_RESET is not set +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pe2201#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_PHYTIUM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_CMD_BOOTMETH=y diff --git a/include/configs/pe2201.h b/include/configs/pe2201.h new file mode 100644 index 0000000000..80f8f17bcd --- /dev/null +++ b/include/configs/pe2201.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __PE2201_CONFIG_H +#define __PE2201_CONFIG_H + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x74000000 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#endif -- 2.17.1

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[PATCH v4 0/2] *** Add support for phyCORE-AM62x ***
by Wadim Egorov 17 Jan '24

17 Jan '24

v4: - Rebase on current next - Drop schema file overrides from binman v3: https://lists.denx.de/pipermail/u-boot/2023-December/539779.html v2: https://lists.denx.de/pipermail/u-boot/2023-November/538971.html v1: https://lists.denx.de/pipermail/u-boot/2023-October/535750.html Wadim Egorov (2): board: phytec: am62x: Add PHYTEC phyCORE-AM62x SoM doc: board: phytec: Add phyCORE-AM62x arch/arm/dts/Makefile | 4 +- .../arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi | 2190 +++++++++++++++++ arch/arm/dts/k3-am62-phycore-som.dtsi | 324 +++ .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 166 ++ arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts | 266 ++ arch/arm/dts/k3-am625-phycore-som-binman.dtsi | 314 +++ arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts | 119 + arch/arm/mach-k3/am62x/Kconfig | 17 + board/phytec/phycore_am62x/Kconfig | 33 + board/phytec/phycore_am62x/MAINTAINERS | 15 + board/phytec/phycore_am62x/Makefile | 8 + board/phytec/phycore_am62x/board-cfg.yaml | 36 + board/phytec/phycore_am62x/phycore-am62x.c | 59 + board/phytec/phycore_am62x/phycore_am62x.env | 23 + board/phytec/phycore_am62x/pm-cfg.yaml | 12 + board/phytec/phycore_am62x/rm-cfg.yaml | 1088 ++++++++ board/phytec/phycore_am62x/sec-cfg.yaml | 379 +++ configs/phycore_am62x_a53_defconfig | 115 + configs/phycore_am62x_r5_defconfig | 130 + doc/board/phytec/index.rst | 1 + doc/board/phytec/phycore-am62x.rst | 158 ++ doc/board/ti/k3.rst | 1 + include/configs/phycore_am62x.h | 15 + 23 files changed, 5472 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62-phycore-som-ddr4-2gb.dtsi create mode 100644 arch/arm/dts/k3-am62-phycore-som.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am625-phyboard-lyra-rdk.dts create mode 100644 arch/arm/dts/k3-am625-phycore-som-binman.dtsi create mode 100644 arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts create mode 100644 board/phytec/phycore_am62x/Kconfig create mode 100644 board/phytec/phycore_am62x/MAINTAINERS create mode 100644 board/phytec/phycore_am62x/Makefile create mode 100644 board/phytec/phycore_am62x/board-cfg.yaml create mode 100644 board/phytec/phycore_am62x/phycore-am62x.c create mode 100644 board/phytec/phycore_am62x/phycore_am62x.env create mode 100644 board/phytec/phycore_am62x/pm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/rm-cfg.yaml create mode 100644 board/phytec/phycore_am62x/sec-cfg.yaml create mode 100644 configs/phycore_am62x_a53_defconfig create mode 100644 configs/phycore_am62x_r5_defconfig create mode 100644 doc/board/phytec/phycore-am62x.rst create mode 100644 include/configs/phycore_am62x.h -- 2.34.1

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[PATCH] test/py: mdio: Add tests for mdio command
by Love Kumar 17 Jan '24

17 Jan '24

Add below test cases for mdio commands: mdio_list - To list MDIO buses mdio_read - To read PHY's register at <devad>.<reg> mdio_write - To write PHY's register at <devad>.<reg> Signed-off-by: Love Kumar <love.kumar(a)amd.com> --- test/py/tests/test_mdio.py | 79 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 test/py/tests/test_mdio.py diff --git a/test/py/tests/test_mdio.py b/test/py/tests/test_mdio.py new file mode 100644 index 000000000000..89711e70b559 --- /dev/null +++ b/test/py/tests/test_mdio.py @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0 +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +import pytest +import re + +""" +Note: This test relies on boardenv_* containing configuration values to define +the PHY device info including the device name, address, register address/value +and write data value. This test will be automatically skipped without this. + +For example: + +# Setup env__mdio_util_test to set the PHY address, device names, register +# address, register address value, and write data value to test mdio commands. +# Test will be skipped if env_mdio_util_test is not set +env__mdio_util_test = { + "eth0": {"phy_addr": 0xc, "device_name": "TI DP83867", "reg": 0, + "reg_val": 0x1000, "write_val": 0x100}, + "eth1": {"phy_addr": 0xa0, "device_name": "TI DP83867", "reg": 1, + "reg_val": 0x2000, "write_val": 0x100}, +} +""" + +def get_mdio_test_env(u_boot_console): + f = u_boot_console.config.env.get("env__mdio_util_test", None) + if not f or len(f) == 0: + pytest.skip("No PHY device to test!") + else: + return f + +(a)pytest.mark.buildconfigspec("cmd_mii") +(a)pytest.mark.buildconfigspec("phylib") +def test_mdio_list(u_boot_console): + f = get_mdio_test_env(u_boot_console) + output = u_boot_console.run_command("mdio list") + for dev, val in f.items(): + phy_addr = val.get("phy_addr") + dev_name = val.get("device_name") + + assert f"{phy_addr:x} -" in output + assert dev_name in output + +(a)pytest.mark.buildconfigspec("cmd_mii") +(a)pytest.mark.buildconfigspec("phylib") +def test_mdio_read(u_boot_console): + f = get_mdio_test_env(u_boot_console) + output = u_boot_console.run_command("mdio list") + for dev, val in f.items(): + phy_addr = hex(val.get("phy_addr")) + dev_name = val.get("device_name") + reg = hex(val.get("reg")) + reg_val = hex(val.get("reg_val")) + + output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}") + assert f"PHY at address {int(phy_addr, 16):x}:" in output + assert f"{int(reg, 16):x} - {reg_val}" in output + +(a)pytest.mark.buildconfigspec("cmd_mii") +(a)pytest.mark.buildconfigspec("phylib") +def test_mdio_write(u_boot_console): + f = get_mdio_test_env(u_boot_console) + output = u_boot_console.run_command("mdio list") + for dev, val in f.items(): + phy_addr = hex(val.get("phy_addr")) + dev_name = val.get("device_name") + reg = hex(val.get("reg")) + reg_val = hex(val.get("reg_val")) + wr_val = hex(val.get("write_val")) + + u_boot_console.run_command(f"mdio write {phy_addr} {reg} {wr_val}") + output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}") + assert f"PHY at address {int(phy_addr, 16):x}:" in output + assert f"{int(reg, 16):x} - {wr_val}" in output + + u_boot_console.run_command(f"mdio write {phy_addr} {reg} {reg_val}") + output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}") + assert f"PHY at address {int(phy_addr, 16):x}:" in output + assert f"{int(reg, 16):x} - {reg_val}" in output -- 2.25.1

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[PATCH next v2 0/6] rockchip: rk3588: add support for detecting U-Boot proper boot medium
by Quentin Schulz 17 Jan '24

17 Jan '24

It is possible to boot U-Boot proper from a different storage medium than the one used by the BOOTROM to load the SPL. This information is stored in the u-boot,spl-boot-device Device Tree property and is accessible from U-Boot proper so that it has knowledge at runtime where it was loaded from. This is already supported on rk3399 and px30 but with duplicated code, so this patch series also factor out all of this into spl-boot-order of Rockchip platforms, which makes it drastically easier to add support to other SoCs, just a simple array needing to be added to the appropriate SoC file. Let's add support for this feature for rk3588 the same way it was done for px30 and rk3399. While at it, let's do some cleanups for Rockchip platforms. Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- Changes in v2: - add factoring into spl-boot-order - rework rk3588 support to use the factored out function - add global data ptr cleanup - remove rk3128 main SoC file (useless content) - Link to v1: https://lore.kernel.org/r/20230502-rk3588-spl-boot-dev-v1-1-071722a85d2d@th… --- Quentin Schulz (6): rockchip: rk3399: simplify logic for getting SPL boot medium DT node rockchip: px30: simplify logic for getting SPL boot medium DT node rockchip: factor out spl_perform_fixups into common spl-boot-order rockchip: rk3588: insert u-boot,spl-boot-device into U-Boot device tree rockchip: remove unused global data ptr rockchip: rk3128: remove noop file arch/arm/mach-rockchip/board.c | 3 -- arch/arm/mach-rockchip/px30/px30.c | 50 +++--------------------------- arch/arm/mach-rockchip/rk3128/Makefile | 1 - arch/arm/mach-rockchip/rk3128/rk3128.c | 16 ---------- arch/arm/mach-rockchip/rk3308/rk3308.c | 3 -- arch/arm/mach-rockchip/rk3328/rk3328.c | 3 -- arch/arm/mach-rockchip/rk3368/rk3368.c | 3 -- arch/arm/mach-rockchip/rk3399/rk3399.c | 55 +++------------------------------ arch/arm/mach-rockchip/rk3588/rk3588.c | 10 ++++-- arch/arm/mach-rockchip/spl-boot-order.c | 49 +++++++++++++++++++++++++++++ 10 files changed, 66 insertions(+), 127 deletions(-) --- base-commit: e17d174773e9ba9447596708e702b7382e47a6cf change-id: 20230502-rk3588-spl-boot-dev-efa2777cc21b Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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